See discussions, stats, and author profiles for this publication at: https://www.researchgate.

net/publication/364327932

Journal of VLSI circuits and systems

Article · January 2023

DOI: 10.31838/jvcs/05.02.10

CITATIONS READS

0 159

2 authors:

Ch Pakkiraiah R. V. S. Satyanarayana
Sri Venkateswara University SVU College Of Engineering
10 PUBLICATIONS 20 CITATIONS 34 PUBLICATIONS 81 CITATIONS

SEE PROFILE SEE PROFILE

Some of the authors of this publication are also working on these related projects:

High Speed Full Adder View project

All content following this page was uploaded by Ch Pakkiraiah on 14 October 2022.

The user has requested enhancement of the downloaded file.

 Journal of VLSI Circuits and Systems, ISSN: 2582-1458 Vol. 5, No. 2, 2023 (pp.63-71)

RESEARCH ARTICLE WWW.VLSIJOURNAL.COM

Design and FPGA Realization of Energy

Efficient Reversible Full Adder for Digital
Computing Applications
C. Pakkiraiah , Dr. R.V.S. Satyanarayana2
1

1
Research Scholar, 2Professor, Department of ECE, SVU College of Engineering, S.V.University, Tirupati

KEYWORDS: AbstrAct
Dynamic Power, EDP, Feynman Gate, Arithmetic primitives are necessary in order to conduct computations on
New Gate, Toffoli Gate. large numbers in arithmetic circuit implementations including multiplications, ad-
ditions, subtractions, and divisions. Because of the importance of computations in
ARTICLE HISTORY: the central processing unit, effective design of arithmetic circuit has been part of the
Received 15.07.2022 most important fields of research for design engineers. In order to create low-power
Accepted 22.08.2022 and energy-efficient portable processors for image and digital signal processing,
Published 25.09.2022 as well as cryptography applications, the switching activity factor and cell count
must be reduced. This research focuses on the reversible digital full adder circuit,
DOI: which is a key element in establishing the Energy Delay Product (EDP) for various
https://doi.org/10.31838/jvcs/05.02.10 computer applications. Here, a new reversible binary full adder is designed using the
switching activity concept and the logic decomposition method. The internal blocks
for reversible full adders such as Feynman Gate, Toffoli Gate, and New Gate are
designed first, then a new reversible binary full adder is developed using the
proposed method. In this paper, conventional and proposed reversible full adders
are synthesized using the Xilinx Vivado design suite for the Zynq-7000 family
of device configuration. According to the implementation results, the proposed
reversible full adder circuit consumes less dynamic power dissipation than
the existing method in comparison. Furthermore, a formulae-based evaluation
is conducted on the implementation results to estimate the EDP of the design.
The proposed reversible full adder design can achieve a 32.3% EDP improvement com-
pared to the Proposed Full Adder.

Author’s e-mail: xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx

How to cite this article: Pakkiraiah C, Satyanarayana RVS. Design and FPGA Real-
ization of Energy Efficient Reversible Full Adder for Digital Computing Applications.
Journal of Complementary Research, Vol. 5, No. 2, 2023 (pp. 63-71).

IntroductIon and feedback mechanism in a reversible logic circuit. In,[4]

A survey of the design of logic circuits such as binary
Minimization of dynamic power dissipation is one of the
adder, binary subtractor, binary multiplier, and division
primary objectives of digital logic design. A new innovative
has been conducted. In,[5] a 3×3 reversible universal
approach is explained in[1] to design low power full adder.
In current days, reversible logic has attracted considerable and multifunctional gates using quantum-dot a cellular
interest to design logic circuits. Novel design of full automaton is reported. High-performing processors that
adder using suitable reversible logic gates is presented generate a lot of heat put a realistic limit about how far
in.[2] A FADE, which is novel 4×4 reversible gate logic researchers can enhance the accuracy. Energy consumption
is reported in.[3] Quantum logic circuits are therefore efficiency will indeed gain through reversible computation.
difficult to design without reversible logic concept. Gate count and other logical measures have been used
Reversible combinational logic synthesis is exponentially to estimate the hardware quality of crypto-primitive
more difficult than conventional digital circuit synthesis algorithms is discussed in.[6] A novel design of reversible
since we’re not enabled to use the concept of fan-out Full adder/subtractor with minimum number of cells has

Journal of VLSI circuits and systems, , ISSN 2582-1458 63

 C. Pakkiraiah, et al. : Design and FPGA Realization of Energy Efficient Reversible Full Adder for Digital Computing Applications

is proposed in.[20] The design of novel full adder using

been distinguished in.[7] Reversible computation is needed HNG gate is introduced in.[21] Concerning this subject,
to enhance device accessible yet further. This will allow researchers are working for years to improve designs and
circuit component sizes to be minimized to microscopic have presented a novel model based on reversible circuits
proportions, enabling electronics more accessible. In,[7] to attain minimum delay and dynamic power dissipation.
An QCA based design provides an ultra-efficient full adder Energy consumption is still one of the main key aspects to
is designed using the concept of explicit interaction of concentrate on in modern technology. In,[22] fast reversible
cells is discussed. In,[9] conventional digital circuits using multiplier is proposed with less circuit complexity. The
reversible logic are presented. Although the expense of NXN reversible multiplier using TSG gate is presented in.[23]
embedded system in the coming days may be considerable, The design of a ripple carry adder, BCD adder and carry
in today’s digital revolution, dynamic power and tradeoffs look-ahead adder using TSG gate is reported in.[24] This
are more crucial than circuit manufacturing costs, study, which is a considerable extension of,[1-2] is organized
therefore the necessity for reversible processing cannot as follows: The essential fundamentals demanded for
be neglected. The Design of full adder using reversible the latest research initiatives are given in Section II. The
logic with minimum constant input and garbage output introduction of reversible logic gates is covered in further
is reported in.[10] The design of fault tolerant full adder depth in Section III. The design of reversible full adders is
using parity preserving logic is proposed in.[11] Due to the discussed in Section IV. IN Section V, the simulation and
abrupt switching of input signals in recent VLSI circuit implementation results for reversible gates and full adders
design, dynamic power consumption is exceptionally high. and then performance metrics assessment is described
Conventional Combinatorial Circuits produce heat for each followed by the conclusion.
bit of binary data lost through execution. As a result,
PrelImInArIes
once data is missing, it cannot be restored in almost any
method. In,[12] the design of combinational logic circuits Power dissipation: Static power dissipation of Metal Oxide
using reversible logic with minimum quantum cost is Semiconductor (MOS) is proportional to the supply voltage
discussed. In,[13] a reversible logic concept is introduced to (Vdd) and leakage currents flows in the transistor.
design new full adder to minimize gate count and garbage
(1)
outputs. When studying the manufacturing of reversible
gates, we need circuits with a minimum number of gates Dynamic power dissipation of a MOS device is largely
and transistors. However, many Boolean expressions are the result of the switching activity, capacitive loads,
irreversible. To minimize cell count, quantum cost and operating frequency and supply voltage (Vdd).
garbage outputs an attempt is made on combinational
circuits, reported in.[14] The dynamic power consumption (2)
due to circuit switching activity factor is discussed
in.[15] We must first convert irreversible functions into In today’s technology 80% of power dissipation occurs
reversible functions before fulfilling these functions. because of switching activity factor. In order to reduce
Every transformation technique that turns an irreversible power loss of MOS circuits, it is necessary to minimize the SA
expression of a reversible expression involves data bits that value of digital Very Large-Scale Integration (VLSI) circuits.
have been assumed to be zero. The design of an arithmetic Switching Activity: The generalized expression to
logic unit (ALU) using reversible logic gates is reported estimate the SA of any basic digital logic gate is expressed as
to minimize power dissipation in.[16] The binary full adder
design1 and design2 are reported in.[17] In the field of IC (3)
design, minimum power dissipation design has emerged Where, N indicates the number of inputs
as a promising research area. Low-power digital logic For example, the SA value of single input NOT gate is
design techniques rely on choosing the best components to 1/4, two input basic gates are having a SA value of 3/16,
decelerate automation without affecting system features. and three input basic gates SA value is 7/64. The single,
In,[18] design of an ALU using two programmable reversible two, and three input gates with their SA values are shown
logic gates is presented. In,[19] design of multiplier using in the Fig.1.
reversible logic gate is reported. Researchers should
optimize diverse computations while keeping propagation
latency and dynamic power dissipation low. It can display
great power dissipation and speed, and it is evolving
into more complex designs and styles. The detection of
faults at output of logic circuits using parity preserving Fig. 1: SA values for one, two, and three input logic gates

64 Journal of VLSI circuits and systems, , ISSN 2582-1458

 C. Pakkiraiah, et al. : Design and FPGA Realization of Energy Efficient Reversible Full Adder for Digital Computing Applications

• Cell Count: In this paper, area occupied by digital Reversible gate using conventional and proposed
circuit design is defined based on the number of cells method is shown in Fig.3. In Fig.3, each and every gate
require implementing any combinational circuit. The represented with their switching activity value. The total
total cell count is defined as the summation of all SA value of FG reversible gate is obtained by adding all
individual NOT, AND, OR, and NAND gates used in the individual SA value of logic gates. From Fig. 3, we observed
process of designing digital logic circuits. that the SA value of Conventional FG (CFG) gate is 1.0625
• Figure of Merit: The product of input to output and the total SA value of FG gate using the Proposed (PFG)
propagation delay and the average power consumption method is 0.5625.
has been used as FOM for digital circuits. FOM is used
(9
to measure and compare devices intended for linear
circuit applications. FOM is used to determine the (10)
quality of a digital logic gate.
(4) b. toffolI gAte (tg)
Power Delay Product: The digital circuit designer goal The toffoli gate is a three-way reversible gate, which
is to minimize PDP; in order to get low power at frequency means it accepts three input signals and sends three
operated digital circuits. The PDP measures the energy output signals. The toffoli gate is represented by a Boolean
consumption level of the gate. The PDP stands for the equation as shown below.
dynamic power consumed per switching event. The power
(11)
delay product is amount of energy required to perform the
computation. However, a digital logic design with minimal (12)
PDP may be very slow in performing its computation.
(5) (13)

• Energy Delay Product: Therefore, energy delay The basic symbol of TG[2] reversible gate and its
product is estimated to get on the better performance functional table is shown in Fig. 4. The Fig. 5 and Fig. 6
of the digital logic circuit design. The energy delay shows the internal logic diagram of the conventional and
product of any digital circuit design is described as the proposed TG reversible gate.
product of power delay product and input to output Each gate is illustrated in the Fig. 5 and Fig. 6 with its
propagation delay. switching activity value. By summing all of the individual SA
values of logic gates, the total SA value of the TG reversible
(6) gate is calculated. The SA value of a Conventional TG (CTG)
gate is 1.0156, while the overall SA value of a TG gate
3. reversIble logIc gAtes employing the proposed technique is 0.5156, as shown in
A. Feynman Gate (FG) the Fig. 5 and Fig. 6.
The feynman gate[2] is a 2×2 reversible gate i.e., FG accepts
two input signals and redirects to two output signals.
Boolean equation representation of feynman gate is given
below
(7)

(8)
The basic symbol of FG reversible gate and its functional Fig. 3: (i) Logic diagram of Conventional FG gate (ii)
table is shown in Fig. 2. The internal logic diagram of FG Proposed FG gate

Fig. 2: (i) Symbol of FG (ii) Functional table of FG Fig. 4: (i) Symbol of TG (ii) Functional table of TG

Journal of VLSI circuits and systems, , ISSN 2582-1458 65

 C. Pakkiraiah, et al. : Design and FPGA Realization of Energy Efficient Reversible Full Adder for Digital Computing Applications

Fig. 7: (i) Symbol of NG (ii) Functional table of NG

The basic symbol of NG reversible gate and its functional

table is shown in Fig.7. The internal logic diagram of the NG
Fig. 5: Logic diagram of Conventional TG gate reversible gate using conventional and proposed method is
illustrated in the Fig. 8 and Fig. 9. The switching activity
value of each gate is shown in the Fig. 8 and Fig.9. The
overall SA value of the NG reversible gate is calculated
by adding all of the individual SA values of logic gates. As
indicated in the Fig.8 and Fig.9, the overall SA value of a
Conventional NG (CNG) gate is 2.7812, while the overall SA
value of a NG gate using the proposed technique is 1.0312.

(19)

(20)

Fig. 6: Logic diagram of proposed TG gate 4. the desIgn of reversIble full Adders
The design of full adder is composed of three reversible
(14) gates such as FG, TG, and NG. The two inputs A and B are
passed through NG gate by making third input as zero.
(15) The first output of NF gate is considered as garbage bit,
the other two outputs are passed as input to FG reversible
C. New Gate (NG) [2] gate with Cin bit. The first two outputs of TG reversible
gate are passed as input to FG gate. The second output
The new gate is a three-way reversible gate, indicating it
of FG reversible gate is sum output and the first output
accepts three input signals and produces three outputs.
is considered as garbage output. The output carry bit is
A Boolean equation is used to represent the new gate, as
obtained from third output of TG gate. The block diagram
shown below.
of reversible full adder is illustrated in Fig. 10.
(16) A. The Proposed Reversible Full Adder (PRFA)

(17) The logic diagram of proposed reversible binary full

adder is designed for the use of proposed logic diagrams
(18) of NG, TG, and FG reversible gates. The total SA value

TABLE I: Comparison among reversible gates using

conventional and proposed method
Conventional method Proposed method
Number of Number of
Name of Number of 2-input Total Cell Number of 2-input Total Cell
the Gate NOT Gates Gates Count SA Value NOT Gates Gates Count SA Value
FG 2 3 5 1.0625 0 3 3 0.5625
TG 2 4 6 1.0156 0 4 4 0.5156
NG 7 8 15 2.7812 0 8 8 1.0312

66 Journal of VLSI circuits and systems, , ISSN 2582-1458

 C. Pakkiraiah, et al. : Design and FPGA Realization of Energy Efficient Reversible Full Adder for Digital Computing Applications

method of FG, TG, and NG improved in every aspect such

proposed reversible full adder from Fig.3, Fig.6, and Fig.9 as NOT cell count and switching activity value.
is calculated as follows B. Proposed Full Adder without reversible gates
The Proposed Full Adder [1] is designed based on the
(21)
following Boolean expressions,
According to theoretical analysis, the comparison (22)
among FG, TG, and NG reversible gates is presented in
Table I. From the table1 we can find out the proposed (23)

(24)
The logic diagram of PFA [1] using equations23, 24, and
25 is shown in Fig.11. The total power dissipation consumed
by PFA [1] is 211mW with a delay of 7.106nsec.

5. sImulAtIon results
Functionality of reversible full adder is verified using
Xilinx vivado behavioral simulation. Here, we are showing
simulation results for two test vectors i.e., 110 and 100.

Fig. 8: Logic diagram of Conventional NG gate

Fig. 10: Block diagram of full adder using reversible
gates[2]

Fig. 9: Logic diagram of proposed NG gate Fig. 11: Logic diagram of PFA[1]

Fig. 12: Simulation results of reversible full adder (i) when input=110 (ii) when input=100

Journal of VLSI circuits and systems, , ISSN 2582-1458 67

 C. Pakkiraiah, et al. : Design and FPGA Realization of Energy Efficient Reversible Full Adder for Digital Computing Applications

TABLE II: Comparison among conventional and proposed reversible gates based on implementation results
Conventional method Proposed method
Name of the
Gate (mW) (mW) Delay (nsec) (mW) (mW) Delay (nsec)
FG 121 73 6.486 120 22 6.486
TG 121 105 7.027 120 31 7.027
NG 122 166 7.359 121 61 7.359

TABLE III: Comparison among conventional and proposed reversible gates based on performance metrics
Conventional method Proposed method

Name of the FOM PDP EDP FOM PDP EDP

Gate (mW) (mW) (nJ) (nJ) ( J) (mW) (mW) (nJ) (nJ) ( J)
FG 97 73 0.629 0.473 3.07 71 22 0.460 0.142 0.92
TG 113 105 0.794 0.737 5.18 75.5 31 0.530 0.217 1.52
NG 144 166 1.059 1.221 8.98 91 61 0.669 0.448 3.29

is 226mW, and 151mW using conventional and proposed

method followed by delays of 7.027nsec.
The implementation result of conventional and
proposed NG is shown in Fig.16. From Fig.16 the total
power consumed by NG is 288mW, and 182mW using
conventional and proposed method followed by delays
of 7.357nsec. The comparison among conventional and
proposed reversible logic gates is shown in Table II based
on their implementation results. The comparison among
conventional and proposed reversible logic gates is shown
in Table III based on their performance metrics. The RTL
Fig. 13: Verification of Simulation results on FPGA board diagram of proposed reversible full adder is shown in
when input=110 Fig.17. The implementation results of proposed reversible
full adder are shown in Fig.18. From Fig.18 the total power
For the above two input combinations, the output dissipated by the proposed full adder is 189mW with a
waveforms are shown in Fig.12. The simulation tool delay of 7.203nsec. The overall comparison among FG,
generated outputs are physically verified on FPGA ZYBOZ7. TG, NG, and full adders in terms of static power, dynamic
For this operation, the Verilog code is synthesized and power and delay based on implementation results using
implemented using Xilinx Vivado Zynq 7000 target device conventional and proposed methods is shown in Table II and
XC7Z020clg400 configuration. Table IV. After imposing the formula-based evaluation on
The net list is generated after implementation step. implementation results, it becomes performance metrics
This net list file is dumped into the FPGA board. Here, of designed circuits. In this paper, we concentrated on
we considered input combination at 110; it means W13 the energy delay product of all designs. The energy
switch is ON, P15 is ON and G15 is OFF are operated by delay product of FG, TG, NG, and reversible full adders is
the designer. According to the above input combination improved using the proposed method over the conventional
M15 LED is activated and M14 is not activated which means method.
when input is 110, the sum output is logic 0 and carry out The performance metrics of all designs are presented
is logic 1 shown in Fig.13. The implementation result of in Table III and Table V. From the Table III and Table V,
conventional and proposed FG is shown in Fig.14. From we found that the proposed method improved in terms of
Fig.14 the total power consumed by FG is 194mW, and Figure of Merit, power delay product, and Energy delay
22mW using conventional and proposed method followed product over the conventional method. The performance
by delays of 6.486nsec. The implementation results of metrics of FG, TG, NG, and full adders are evaluated for
TG using conventional and proposed method are shown conventional and proposed reversible gates. The graphical
in Fig.15. From Fig.15 the total power dissipated by TG representation of comparison among improvement in

68 Journal of VLSI circuits and systems, , ISSN 2582-1458

 C. Pakkiraiah, et al. : Design and FPGA Realization of Energy Efficient Reversible Full Adder for Digital Computing Applications

TABLE IV: Comparison between PFA [1] and PRFA based on implementation results

Name of FA (mW) (mW) Delay (nsec)

PFA [1]
121 90 7.106
PRFA 121 68 7.203

Fig. 14: Implementation Results of FG gate using Conventional and Proposed method

Fig. 15: Implementation Results of TG gate using Conventional and Proposed method

Fig. 16: Implementation Results of NG gate using Conventional and Proposed method

Journal of VLSI circuits and systems, , ISSN 2582-1458 69

 C. Pakkiraiah, et al. : Design and FPGA Realization of Energy Efficient Reversible Full Adder for Digital Computing Applications

TABLE V: Comparison between PFA[1] and PRFA based on Performance metrics

Name of FA (mW) (mW) FOM (nJ) PDP (nJ) EDP ( J)

PFA [1] 105.5 90 0.749 0.639 4.54
PRFA 94.5 68 0.671 0.483 3.43

Fig. 17: RTL diagram of Proposed Reversible FA

Fig. 19: Performance improvement among reversible

Fig. 18: Implementation results of Proposed RFA gates and full adder

performance metrics of reversible gates using conventional reduce the power consumption of the reversible binary
and proposed method is shown in Fig.19.The performance full adder. According to FPGA implementation results, the
metrics of proposed reversible full adder are evaluated proposed reversible full adder consumed 10.4% less FOM,
from equation 4, 5, and 6. The comparison between PRFA and 32.3% less energy delay product than the PFA [1]. The
and PFA is shown in Table IV based on their implementation simulation tool generated outputs are physically verified
results. The comparison between PRFA and PFA is shown on FPGA ZYBOZ7 board. As a result, switching activity-
in Table V based on their performance metrics. based hybrid adders can be used in a variety of real- time
applications, such as CPUs, crypto processors, and security
conclusIon systems. The proposed design is flexible enough to work
together with a wide range of digit sizes and input bits.
In this paper, conventional and proposed reversible gates In this work, we only design the logic circuits of the
and full adders are synthesized using the Xilinx Vivado proposed hybrid adder, allowing physical implementation
design suite for the Zynq-7000 family of devices. We and simulation to be discussed later.
present a reversible FG, TG, NG gates with few cells and
lower dynamic power dissipation than existing designs, as references
well as lower EDP. The switching activity idea has been [1] C. Pakkiraiah and D. R. Satyanarayana, “An innovative
implemented for a novel architectural level design that design of low power binary adder based on switching ac-
minimizes switching activity factors to reduce the dynamic tivity,” International Journal of Computing and Digital
Systems, vol. 11, no. 1, pp. 861–871, 2022.
power consumption and EDP of reversible full adders.
[2] H. T. HOI, “Design and analysis of full adders using revers-
The logic decomposition approach was created to further
ible logic.”

70 Journal of VLSI circuits and systems, , ISSN 2582-1458

 C. Pakkiraiah, et al. : Design and FPGA Realization of Energy Efficient Reversible Full Adder for Digital Computing Applications

[3] D. Krishnaveni, N. Kiran, H. Shalini, and M. Geetha Priya, International Conference on Intelligent Systems and Con-
“Reversible fade gate as decoder, encoder and full adder,” trol (ISCO). IEEE, 2016, pp. 1–4.
in Advances in Automation, Signal Processing, Instrumen- [14] H Rohini and S. Rajashekar, “Design of reversible logic
tation, and Control. Springer, 2021, pp. 1323–1331. based basic combinational circuits,” Communications, vol.
[4] A. Banerjee and D. K. Das, “Arithmetic circuits using re- 5, pp. 38–43, 2016.
versible logic: a survey report,” in Advanced Computing [15] S Das, S. Ghosh, P. Dasgupta, and S. Sensarma, “A rule-
and Systems for Security. Springer, 2020, pp. 99–110. based method for minimizing power dissipation by reduc-
[5] S. Ahmed, M. I. Baba, S. M. Bhat, I. Manzoor, N. Nafees, ing switching activity of digital circuits,” 2015.
and S.-B. Ko, “Design of reversible universal and multi- [16] N. Sharma, R. Sachdeva, U. Saraswat, R. Yadav, and G.
functional gate-based 1-bit full adder and full subtractor Kaur, “Power efficient arithmetic logic unit design using
in quantum-dot cellular automata nanocomputing,” Jour- reversible logic,” International Journal of Computer Ap-
nal of Nanophotonics, vol. 14, no. 3, p. 036002, 2020. plications, vol. 128, no. 6, pp. 36–41, 2015.
[6] S Raghuraman, “Efficiency of logic minimization tech- [17] V. P. Singh, S. Dayal, and M. Rai, “Efficient carry skip ad-
niques for cryptographic hardware implementation,” Ph.D. der design using full adder and carry skip block based on
dissertation, Virginia Tech, 2019. [7] F. Salimzadeh and S. reversible logic,” American Journal of Engineering and
R. Heikalabad, “Design of a novel reversible structure for Research, vol. 12, pp. 97–102, 2015.
full adder/subtractor in quantum-dot cellular automata,”
Physica B: Condensed Matter, vol. 556, pp. 163–169, 2019. [18] M Morrison and N. Ranganathan, “Design of a reversible
alu based on novel programmable reversible logic gate
[8] S. M. Bhat and S. Ahmed, “Design of ultra-efficient revers-
structures,” in 2011 IEEE computer society annual sympo-
ible gate based 1-bit full adder in qca with power dissipa-
sium on VLSI. IEEE, 2011, pp. 126–131.
tion analysis,” International Journal of Theoretical Phys-
ics, vol. 58, no. 12, pp. 4042–4063, 2019. [19] H. Bhagyalakshmi and M. Venkatesha, “An improved de-
sign of a multiplier using reversible logic gates,” Interna-
[9] K. Batish, S. Pathak, and R. Gupta, “Comparative anal-
tional journal of engineering science and technology, vol.
ysis for performance evaluation of full adders using re-
2, no. 8, pp. 3838–3845, 2010.
versible logic gates,” in 2018 international conference on
intelligent circuits and systems (ICICS). IEEE, 2018, pp. [20] M Haghparast and K. Navi, “Design of a novel fault tolerant re-
126–132. versible full adder for nanotechnology based systems,” World
Applied Sciences Journal, vol. 3, no. 1, pp. 114–118, 2008.
[10] B. Balaji, M. Aditya, E. Radhamma, V. Reddy, and Y. Na-
resh, “Full adder/subtractor using reversible logic,” Inter- [21] Haghparast, M., & Navi, K. (2008). A novel reversible BCD
national Journal of Pure and Applied Mathematics, vol. adder for nanotechnology based systems.
120, no. 6, pp. 437–446, 2018. [22] M. Haghparast, S. J. Jassbi, K. Navi, and O. Hashemipour,
[11] P. K. Kumar, P. P. Rao, and K. H. Kishore, “Optimal design “Design of a novel reversible multiplier circuit using hng
of reversible parity preserving new full adder/full subtrac- gate in nanotechnology,” in World Appl. Sci. J. Citeseer,
tor,” in 2017 11th International Conference on Intelligent 2008.
Systems and Control (ISCO). IEEE, 2017, pp. 368–373. [23] H Thapliyal and M. Srinivas, “Novel reversible multipli-
[12] G. C. Naguboina and K. Anusudha, “Design and synthesis of er architecture using reversible tsg gate,” arXiv preprint
combinational circuits using reversible decoder in xilinx,” cs/0605004, 2006.
in 2017 International Conference on Computer, Commu- [24] Thapliyal, H., & Srinivas, M. B. (2005, October). A novel
nication and Signal Processing (ICCCSP). IEEE, 2017, pp. reversible TSG gate and its application for designing re-
1–6. versible carry look-ahead and other adder architectures,
[13] M. Aditya, Y. N. Kumar, and M. Vasantha, “Reversible full/ Asia Pacific conference on advances in computer systems
half adder with optimum power dissipation,” in 2016 10th architecture, Springer, Berlin, Heidelberg, pp. 805-817.

Journal of VLSI circuits and systems, , ISSN 2582-1458 71

View publication stats