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    VLSI Presentation Fall 23

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    Pathul02
    This document appears to be a presentation on VLSI Design (CSE-444) given in the Fall 2023 semester. It provides an overview of the course including the teacher's name and details about three students enrolled in the class. The table of contents outlines topics to be covered such as the introduction to MOS, basic MOS structure, fabrication of MOS, and challenges. The body of the presentation goes into further detail on these topics, explaining concepts like the metal-oxide-semiconductor structure, NMOS vs PMOS, cleaning processes, photolithography, etching, and deposition involved in MOS fabrication.

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    VLSI Presentation Fall 23

    Uploaded by

    Pathul02
    12 views26 pages
    This document appears to be a presentation on VLSI Design (CSE-444) given in the Fall 2023 semester. It provides an overview of the course including the teacher's name and details about three students enrolled in the class. The table of contents outlines topics to be covered such as the introduction to MOS, basic MOS structure, fabrication of MOS, and challenges. The body of the presentation goes into further detail on these topics, explaining concepts like the metal-oxide-semiconductor structure, NMOS vs PMOS, cleaning processes, photolithography, etching, and deposition involved in MOS fabrication.

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    VLSI_Presentation_Fall_23

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    This document appears to be a presentation on VLSI Design (CSE-444) given in the Fall 2023 semester. It provides an overview of the course including the teacher's name and details about three students enrolled in the class. The table of contents outlines topics to be covered such as the introduction to MOS, basic MOS structure, fabrication of MOS, and challenges. The body of the presentation goes into further detail on these topics, explaining concepts like the metal-oxide-semiconductor structure, NMOS vs PMOS, cleaning processes, photolithography, etching, and deposition involved in MOS fabrication.

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    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    12 views26 pages

    VLSI Presentation Fall 23

    Uploaded by

    Pathul02
    This document appears to be a presentation on VLSI Design (CSE-444) given in the Fall 2023 semester. It provides an overview of the course including the teacher's name and details about three students enrolled in the class. The table of contents outlines topics to be covered such as the introduction to MOS, basic MOS structure, fabrication of MOS, and challenges. The body of the presentation goes into further detail on these topics, explaining concepts like the metal-oxide-semiconductor structure, NMOS vs PMOS, cleaning processes, photolithography, etching, and deposition involved in MOS fabrication.

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    of 26

    VLSI Design (CSE-444)

    Fall 2023
    Presentation
    Course Teacher: Agnik Saha
    Lecturer, Department of CSE
    R.P Shaha University

    Student Name: Md. Hossain Ahamed


    Student Name: Farhan Hasan Nilok
    Student ID: 20100056
    Student ID: 20100107
    Batch: 18th
    Batch: 18th
    Department: CSE
    Department: CSE

    Student Name: Gazi Fuad Md. Tahsin


    Student Name: Md. Fattan Prodan
    Student ID: 20100064
    Student ID: 20100025
    Batch: 18th
    Batch: 18th
    Department: CSE
    Department: CSE
    Table of Content

    ➢ Introduction of MOS ( Metal Oxide Semiconductor )


    ➢ Basic Structure of MOS
    ➢ Fabrication of MOS
    ➢ Challenges
    ➢ Summery
    ➢ Conclusion
    Introduction of MOS

    In the field of electronics, MOS refers to Metal-Oxide-Semiconductor, which is a


    technology used in the fabrication of integrated circuits (ICs). MOS transistors are a
    fundamental building block in digital electronics, and MOS technology is widely
    used in the production of microprocessors, memory chips, and other digital ICs.
    Basic Structure of MOS
    The Metal-Oxide-Semiconductor (MOS) structure is a fundamental component in the fabrication of integrated
    circuits (ICs) in the field of electronics. It consists of three main layers: the metal, the oxide, and the
    semiconductor. The most common application of the MOS structure is in MOS transistors, which serve as
    essential building blocks in digital integrated circuits. Here is a basic description of the structure:
    Metal (M):The metal layer is typically the top layer in the MOS structures. It serves as the gate electrode of the
    MOS transistors. The metal is often made of materials like aluminum or copper.
    Oxide (O):The oxide layer is the insulating layer sandwiched between the metal gate and the semiconductor.
    Silicon dioxide (SiO2) is the most commonly used material for the oxide layer. The oxide layer insulates the gate
    from the semiconductor, preventing current flow between them.
    Semiconductor (S):The semiconductor layer is typically made of silicone. It is the region beneath the oxide layer
    and is a crucial part of the MOS transistors. The semiconductor can be either p-type or n-type, depending on the
    specific design of the transistor.
    Types of MOS

    In a MOS transistor, there are two main types based on the doping of the
    semiconductor materials:
    NMOS (N-Type MOS): The semiconductor is n-type (negatively doped), and the
    majority carriers are electrons. In an NMOS transistor, a positive voltage applied to
    the metal gate creates an electric field that attracts electrons, allowing current to
    flow between the source and drain terminals.
    PMOS (P-Type MOS):The semiconductor is p-type (positively doped), and the
    majority carriers are holes. In a PMOS transistor, a negative voltage applied to the
    metal gate creates an electric field that attracts holes, allowing current to flow
    between the source and drain terminals.
    Fabrication of MOS

    The fabrication of Metal-Oxide-Semiconductor (MOS) devices is a


    crucial process in the production of integrated circuits (ICs), including
    microprocessors, memory chips, and other digital components. The
    MOS technology is widely used in the semiconductor industry due to its
    scalability, low power consumption, and compatibility with
    complementary metal-oxide-semiconductor (CMOS) technology.
    Semiconductor Substrate
    1. Selection of Semiconductor Substrate
    • Commonly Silicon: Silicon is the predominant choice for semiconductor substrates.
    • Abundant, stable, and well-understood material.
    • High purity and reliability for electronic applications.
    2. Importance of Crystal Orientation
    • Crystalline Structure: Silicon exhibits a crystalline structure. The orientation of the
    crystal lattice is crucial for electronic properties. Determination of Electronic
    • Properties: Different crystal orientations impact electronic behavior.Controlled
    orientation enhances device performance.
    • Miller Indices: Crystal orientation specified using Miller indices. Influence on the
    electrical and mechanical properties of the substrate.
    • Impact on Fabrication:Crystal orientation affects etching, deposition, and other
    fabrication processes.Considerations for optimizing device characteristics.
    Cleaning Process
    1. Thorough Cleaning Steps Initial
    Surface Preparation:
    • Wafer undergoes initial cleaning to remove particles, organic residues, and other
    contaminants.
    • Essential for creating a pristine surface for subsequent processing.
    Chemical Cleaning:
    • Immersion in chemical baths with specific cleaning agents.
    • Removes organic and inorganic residues on the wafer surface.
    Rinsing Steps:
    • Multiple rinsing steps with high-purity water to eliminate remaining cleaning agents.
    • Ensures a residue-free surface.
    Cleaning Process
    2. Removal of Contaminants and Impurities
    Contaminant Sources:
    • Sources include handling, atmospheric exposure, and residues from previous processing
    steps.
    • Contaminants can adversely affect device performance and reliability.
    Importance of Cleanliness:
    • Cleanliness is paramount in semiconductor manufacturing.
    • Contaminants can interfere with subsequent deposition, etching, and doping processes.
    Cleanroom Environment:
    • Fabrication performed in cleanroom environments with controlled temperature, humidity,
    and air purity.
    • Minimizes airborne particles and contamination.
    Quality Control Measures:
    • Rigorous quality control procedures to verify cleanliness.
    • Monitoring and validation of cleaning processes.
    Fabrication Steps
    • Start with blank wafer
    • Build inverter from the bottom up
    • First step will be to form the n-well
    • Cover wafer with protective layer of SiO2 (oxide)
    • Remove layer where n-well should be built
    • Implant or diffuse n dopants into exposed wafer
    • Strip off SiO2

    p substrate
    Oxidation
    • Grow SiO2 on top of Si wafer
    • 900 – 1200 C with H2O or O2 in oxidation furnace

    SiO2

    p substrate
    Photolithography

    Exposure Processes
    Photoresist
    • Used for lithography .
    • Lithography is a process used to transfer a pattern to layer on the chip. Similar to Printing Process
    • Spin on photoresist (about 1 mm thickness)
    • Photoresist is a light-sensitive organic polymer
    • Positive Photoresist: Softens where exposed to light
    • Negative Photoresist: Harden where exposed to light, Not used in practice generally

    Photoresist
    SiO2

    p substrate
    Lithography
    • Expose photoresist through n-well mask
    • Strip off exposed photoresist

    Photoresist
    SiO2

    p substrate
    Etch
    Cluster Tool Etch
    Configuration Chambers

    Wafers Transfer
    Chamber

    Loadlock

    RIE Chamber Gas Inlet


    Die-electric Etch
    Wafer
    Transfer
    Plasma Etch Chamber
    RF Power

    Exhaust
    Etch
    • Etch oxide with hydrofluoric acid (HF)
    • Seeps through skin and eats bone; nasty stuff!!!
    • Only attacks oxide where resist has been exposed

    Photoresist
    SiO2

    p substrate
    Ion Implantation
    Focus Beam trap and Neutral beam and
    gate plate beam path gated

    phosphorus
    (-) ions photoresist mask

    field oxide
    n-w ell p- epi
    p-channel transistor
    p+ substrate
    Neutral beam trap Y - axis X - axis Wafer in wafer
    and beam gate scanner scanner process chamber
    Strip Oxide
    • Strip off the remaining oxide using HF
    • Back to bare wafer with n-well
    • Subsequent steps involve similar series of steps

    n well
    p substrate
    Polysilicon
    • Deposit very thin layer of gate oxide
    • < 20 Å (6-7 atomic layers)
    • Chemical Vapor Deposition (CVD) of silicon layer
    • Place wafer in furnace with Silane gas (SiH4)
    • Forms many small crystals called polysilicon
    • Heavily doped to be good conductor

    Polysilicon
    Thin gate oxide

    n well
    p substrate
    Polysilicon Patterning
    • Use same lithography process to pattern polysilicon

    Polysilicon

    Polysilicon
    Thin gate oxide

    n well
    p substrate
    Self-Aligned Process
    • Use oxide and masking to expose where n+ dopants should be diffused or
    implanted
    • N-diffusion forms nMOS source, drain, and n-well contact

    n well
    p substrate
    Metalization
    • Sputter on aluminum over whole wafer
    • Pattern to remove excess metal, leaving wires

    Metal

    Metal
    Thick field oxide
    p+ n+ n+ p+ p+ n+

    n well
    p substrate
    Die Cut and Assembly

    Good chips are attached


    to a lead frame package.
    Challenges in MOS Fabrication
    1. Miniaturization Challenges
    • Features Size Reduction
    • Lithography Challenges
    • Quantum Effect

    2. Power Consumption Challenges


    • Leakage Current
    • Heat Dissipation
    • Dynamic Power
    Summary

    Metal-oxide-semiconductor (MOS) fabrication is a process used to


    manufacture MOS transistors, which are fundamental building blocks
    of integrated circuits (ICs) such as microprocessors, memory chips, and
    other electronic devices.
    Conclusion 😵‍💫

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