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Introduction to Hardware
Description Languages – HDLs
Verilog Code for the Full Adder

xi yi
ci 00 01 11 10
0 1 1
ci x i y i c

i + 1
si
1 1 1
0 0 0 0 0
0 0 1 0 1 si = x i yi ci
0 1 0 0 1
0 1 1 1 0 xi yi
1 0 0 0 1
ci 00 01 11 10
1 0 1 1 0
1 1 0 1 0 0 1
1 1 1 1 1
1 1 1 1
Verilog for a Full-Adder
(a) Truth table
c = xy +xc +yc i+1 i i i i i i

• Schematic of the full-adder: (b) Karnaugh maps

xxi
yyi ssi
Cinci

Cout
ci + 1

(c) Circuit
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Verilog Code for the Full-Adder – Style 1

• Switching gears, we turn now back to Verilog
• We have introduced hierarchical/structural and functional
Verilog code already
• The one below uses Verilog gate level primitives

Figure 3.18. Verilog code for the full-adder using gate level primitives.
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Verilog Code for the Full-Adder – Style 2

• Verilog allows the combination of similar
statements into one, as shown below for the
three AND gates

Figure 3.19. Another version of Verilog code from Figure 3.18.

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Verilog Code for the Full-Adder – Style 3

• Using
functional
expressions
• The XOR
function is
denoted by
‘^’
• ç RTL
Viewer
Figure 3.20. Verilog code for the full-adder using continuous assignment.
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Verilog Code for the Full-Adder – Style 4

• The previous
two
continuous
assignment
statements
can also be
combined

Figure 3.21. Another version of Verilog code from Figure 3.20.

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Verification using Testbenches

• Verification = is the process used to demonstrate the
correctness of the design
• Verification requires planning è need to develop a
verification plan
• A testbench = is a VHDL program that applies a
predetermined stimulus to a design entity during
simulation
– A testbench can also verify the output values produced by
the design entity
– A testbench is basically a stimulus-response system
– A testbench is only being used for verification
– A testbench IS NOT and CANNOT be synthesized into a
real circuit
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Verification using Testbenches

• The design entity being verified is usually called
the unit under test (UUT)
• This is in fact a term carried over from the process
of a manufactured product testing, which we’ll
discuss later in the semester
• A manufactured system is being tested
• A design is being verified to determine whether it
meets its specifications or not
• Other terms: device under test (DUT), design
under verification (DUV), module under test (MUV)
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The Structure of a Testbench

• A testbench contains/is also a design entity
• A testbench completely encloses the UUT and
simulates the environment in which the design
will operate; it is therefore completely self-
contained, i.e. it contains no inputs or outputs
• The relationship between the testbench and the
UUT is illustrated below:
Testbench
x_tb
s s_tb
Stimulus y_tb x UUT Response
y Cout_tb
Generator Cin_tb Full-Adder Monitor
Cin Cout
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The circuit

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And the Verification Plan

X Y Cin S Cout
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
• For large circuits it might be not possible nor
feasible to verify and subsequently test all input
combinations, i.e. perform exhaustive verification
• The verification plan sets also the foundation for the
test plan of the manufactured circuit – to be
discussed later in the semester
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A Verilog Testbench for the full adder

• Cin_tb, x_tb,
and y_tb
have to store
values è
registered
• S_tb and
Cout_tb are
internal
signals of
type wire
• A testbench
has no
input/output
ports!
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A Verilog Testbench for the full adder

• The initial is a
procedural block
• All statements
inside a
procedural block
are executed
sequentially
• Unlike the always
block (to be
covered later),
the initial block is
executed only
once
• Verilog starts all
initial statements
at time 0.

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A Verilog Testbench for the full adder

• The value after
the ‘#’ sign
indicates for
how many
simulation
steps to wait
before checking
the value of
s_tb and
Cout_tb
• The default
ModelSim-
Altera
simulation step
is 1 ps è
20000 means in
fact 20 ns
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A Verilog Testbench for the full adder

• Special
commands
are called
system tasks
and they all
begin with
the symbol
‘$’
• Note: ‘$’ is
also used to
indicate
system
functions
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And here’s the entire code testbench code

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Running the simulator

• Simulator = Mentor-Graphics Modelsim for Altera
Quartus = similar to all others; differences in menus
and for complex systems synthesis efficiency
• Transcript window = command prompt and text
based feedback to user
• Simulation waveform window = timing diagram
• Library window = code sources representing
components
• Sim and Objects windows = allow the selection of
additional internal signals to be viewed in the
simulation waveform window
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Transcript window

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Library and Sim windows

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Objects window
• Allows one to select more internal signals to be
stored and viewed in the simulation waveform
window

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Simulation Waveform window

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Design “Bug”
• Let’s ee what happens if there is a design “bug”
or error;
• We voluntarily insert the latter as a typo: the
third AND gate becomes a NAND gate;
• The circuit that is synthesized is a perfectly valid
circuit, except for the fact that it doesn’t
implement the required function;
• The synthesis tool will not reply with an error,
BUT the testbench should!

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The synthesis feedback …

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… and the simulator feedback

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