Pic16F688 Data Sheet: 14-Pin Flash-Based, 8-Bit Cmos Microcontrollers With Nanowatt Technology

PIC16F688
Data Sheet
14-Pin Flash-Based, 8-Bit
CMOS Microcontrollers with
nanoWatt Technology
© 2009 Microchip Technology Inc. DS41203E

Note the following details of the code protection feature on Microchip devices:
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headquarters, design and wafer fabrication facilities in Chandler and
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are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
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and manufacture of development systems is ISO 9001:2000 certified.
DS41203E-page ii © 2009 Microchip Technology Inc.

PIC16F688
14-Pin Flash-Based, 8-Bit CMOS Microcontrollers with nanoWatt Technology
High-Performance RISC CPU: Low-Power Features:

• Only 35 Instructions to Learn: • Standby Current:
- All single-cycle instructions except branches - 50 nA @ 2.0V, typical
• Operating Speed: • Operating Current:
- DC – 20 MHz oscillator/clock input - 11 μA @ 32 kHz, 2.0V, typical
- DC – 200 ns instruction cycle - 220 μA @ 4 MHz, 2.0V, typical
• Interrupt Capability • Watchdog Timer Current:
• 8-level Deep Hardware Stack - 1 μA @ 2.0V, typical
• Direct, Indirect and Relative Addressing modes
Peripheral Features:
Special Microcontroller Features:
• 12 I/O Pins with Individual Direction Control:
• Precision Internal Oscillator: - High-current source/sink for direct LED drive
- Factory calibrated to ±1% - Interrupt-on-change pin
- Software selectable frequency range of - Individually programmable weak pull-ups
8 MHz to 125 kHz
- Ultra Low-Power Wake-up
- Software tunable
- Two-Speed Start-Up mode • Analog Comparator module with:
- Crystal fail detect for critical applications - Two analog comparators
- Clock mode switching during operation for - Programmable On-chip Voltage Reference
power savings (CVREF) module (% of VDD)
• Power-Saving Sleep mode - Comparator inputs and outputs externally
• Wide Operating Voltage Range (2.0V-5.5V) accessible
• Industrial and Extended Temperature Range • A/D Converter:
• Power-on Reset (POR) - 10-bit resolution and 8 channels
• Power-up Timer (PWRT) and Oscillator Start-up • Timer0: 8-bit Timer/Counter with 8-bit
Timer (OST) Programmable Prescaler
• Brown-out Reset (BOR) with Software Control • Enhanced Timer1:
Option - 16-bit timer/counter with prescaler
• Enhanced Low-Current Watchdog Timer (WDT) - External Timer1 Gate (count enable)
with on-chip oscillator (software selectable nomi- - Option to use OSC1 and OSC2 in LP mode as
nal 268 seconds with full prescaler) with software Timer1 oscillator if INTOSC mode selected
enable
• Enhanced USART Module:
• Multiplexed Master Clear with Weak Pull-up or
- Supports RS-485, RS-232, LIN 2.0/2.1 and
Input Only Pin
J2602
• Programmable Code Protection
- Auto-Baud Detect
• High-Endurance Flash/EEPROM Cell:
- Auto-wake-up on Start bit
- 100,000 write Flash endurance
• In-Circuit Serial Programming™ (ICSP™) via two
- 1,000,000 write EEPROM endurance
pins
- Flash/Data EEPROM retention: > 40 years
© 2009 Microchip Technology Inc. DS41203E-page 1

PIC16F688
Program
Data Memory
Memory 10-bit A/D Timers
Device I/O Comparators
Flash SRAM EEPROM (ch) 8/16-bit
(words) (bytes) (bytes)
PIC16F688 4096 256 256 12 8 2 1/1
Pin Diagram (PDIP, SOIC, TSSOP)
14-pin PDIP, SOIC, TSSOP
VDD 1 14 VSS
RA5/T1CKI/OSC1/CLKIN 2 13 RA0/AN0/C1IN+/ICSPDAT/ULPWU
RA4/AN3/T1G/OSC2/CLKOUT 3 RA1/AN1/C1IN-/VREF/ICSPCLK
PIC16F688
12
RA3/MCLR/VPP 4 11 RA2/AN2/T0CKI/INT/C1OUT
RC5/RX/DT 5 10 RC0/AN4/C2IN+
RC4/C2OUT/TX/CK 6 9 RC1/AN5/C2IN-
RC3/AN7 7 8 RC2/AN6
TABLE 1: PIC16F688 14-PIN SUMMARY (PDIP, SOIC, TSSOP)

I/O Pin Analog Comparators Timers EUSART Interrupt Pull-up Basic
RA0 13 AN0/ULPWU C1IN+ — — IOC Y ICSPDAT
RA1 12 AN1 C1IN- — — IOC Y VREF/ICSPCLK
RA2 11 AN2 C1OUT T0CKI — IOC/INT Y —
RA3 4 — — — — IOC Y(1) MCLR/VPP
RA4 3 AN3 — T1G — IOC Y OSC2/CLKOUT
RA5 2 — — T1CKI — IOC Y OSC1/CLKIN
RC0 10 AN4 C2IN+ — — — — —
RC1 9 AN5 C2IN- — — — — —
RC2 8 AN6 — — — — — —
RC3 7 AN7 — — — — — —
RC4 6 — C2OUT — TX/CK — — —
RC5 5 — — — RX/DT — — —
— 1 — — — — — — VDD
— 14 — — — — — — VSS
Note 1: Pull-up activated only with external MCLR configuration.
DS41203E-page 2 © 2009 Microchip Technology Inc.

PIC16F688
Pin Diagram (QFN)
16-pin QFN
VDD
VSS
NC
NC
13
15
14
16
RA5/T1CKI/OSC1/CLKIN 1 12 RA0/AN0/C1IN+/ICSPDAT/ULPWU
RA4/AN3/T1G/OSC2/CLKOUT 2 11 RA1/AN1/C1IN-/VREF/ICSPCLK
PIC16F688
RA3/MCLR/VPP 3 10 RA2/AN2/T0CKI/INT/C1OUT
RC5/RX/DT 4 9 RC0/AN4/C2IN+
5
6
7
8
RC3/AN7
RC2/AN6
RC4/C2OUT/TX/CK
RC1/AN5/C2IN-
TABLE 2: PIC16F688 16-PIN SUMMARY (QFN)

I/O Pin Analog Comparators Timers EUSART Interrupt Pull-up Basic
RA0 12 AN0/ULPWU C1IN+ — — IOC Y ICSPDAT
RA1 11 AN1 C1IN- — — IOC Y VREF/ICSPCLK
RA2 10 AN2 C1OUT T0CKI — IOC/INT Y —
RA3 3 — — — — IOC Y(1) MCLR/VPP
RA4 2 AN3 — T1G — IOC Y OSC2/CLKOUT
RA5 1 — — T1CKI — IOC Y OSC1/CLKIN
RC0 9 AN4 C2IN+ — — — — —
RC1 8 AN5 C2IN- — — — — —
RC2 7 AN6 — — — — — —
RC3 6 AN7 — — — — — —
RC4 5 — C2OUT — TX/CK — — —
RC5 4 — — — RX/DT — — —
— 16 — — — — — — VDD
— 13 — — — — — — VSS
— 14 — — — — — — NC
— 15 — — — — — — NC
Note 1: Pull-up activated only with external MCLR configuration.

PIC16F688
Table of Contents
1.0 Device Overview ......................................................................................................................................................................... 5
2.0 Memory Organization .................................................................................................................................................................. 7
3.0 Clock Sources ........................................................................................................................................................................... 21
4.0 I/O Ports .................................................................................................................................................................................... 33
5.0 Timer0 Module .......................................................................................................................................................................... 45
6.0 Timer1 Module with Gate Control.............................................................................................................................................. 49
7.0 Comparator Module................................................................................................................................................................... 55
8.0 Analog-to-Digital Converter (A/D) Module ................................................................................................................................. 65
9.0 Data EEPROM and Flash Program Memory Control ................................................................................................................ 77
10.0 Enhanced Universal Asynchronous Receiver Transmitter (EUSART) ...................................................................................... 83
11.0 Special Features of the CPU ................................................................................................................................................... 109
12.0 Instruction Set Summary ......................................................................................................................................................... 129
13.0 Development Support .............................................................................................................................................................. 139
14.0 Electrical Specifications........................................................................................................................................................... 143
15.0 DC and AC Characteristics Graphs and Tables ...................................................................................................................... 163
16.0 Packaging Information............................................................................................................................................................. 185
Appendix A: Data Sheet Revision History......................................................................................................................................... 193
Appendix B: Migrating from other PIC® Devices............................................................................................................................... 193
Index ................................................................................................................................................................................................. 195
On-line Support ................................................................................................................................................................................. 199
Systems Information and Upgrade Hot Line ..................................................................................................................................... 199
Reader Response ............................................................................................................................................................................. 200
Product Identification System............................................................................................................................................................ 201
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PIC16F688
1.0 DEVICE OVERVIEW
The PIC16F688 is covered by this data sheet. It is
available in 14-pin PDIP, SOIC, TSSOP and QFN
packages. Figure 1-1 shows a block diagram of the
PIC16F688 device. Table 1-1 shows the pinout
description.
FIGURE 1-1: PIC16F688 BLOCK DIAGRAM
INT
Configuration
13 8 PORTA
Data Bus
Program Counter
Flash RA0
4k x 14 RA1
Program RA2
RAM
Memory 8-Level Stack 256 bytes RA3
(13 bit) File RA4
Registers
RA5
Program
14
Bus RAM Addr 9
Addr MUX
Instruction Reg
PORTC
Direct Addr 7 Indirect
8 Addr RC0
RC1
FSR Reg
RC2
STATUS Reg RC3

8 RC4
RC5
3
Power-up MUX
Timer
Instruction Oscillator
Decode & Start-up Timer ALU
Control
Power-on
Reset 8
Timing Watchdog
OSC1/CLKIN Generation W Reg
Timer
Brown-out
OSC2/CLKOUT
Reset
Internal
Oscillator
Block
RX/DT TX/CK
T1G VDD VSS
MCLR
T1CKI
Timer0 Timer1 EUSART

T0CKI
2
Analog-to-Digital Converter Analog Comparators EEDAT
and Reference 256 bytes
8
DATA
EEPROM
EEADDR
VREF AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 C1IN- C1IN+ C1OUT C2IN- C2IN+ C2OUT

PIC16F688
TABLE 1-1: PIC16F688 PINOUT DESCRIPTION
Input Output
Name Function Description
Type Type
RA0/AN0/C1IN+/ICSPDAT/ULPWU RA0 TTL CMOS PORTA I/O w/prog pull-up and interrupt-on-change
AN0 AN — A/D Channel 0 input
C1IN+ AN — Comparator 1 input
ICSPDAT TTL CMOS Serial Programming Data I/O
ULPWU AN — Ultra Low-Power Wake-up input
RA1/AN1/C1IN-/VREF/ICSPCLK RA1 TTL CMOS PORTA I/O w/prog pull-up and interrupt-on-change
C1IN- AN — Comparator 1 input
VREF AN — External Voltage Reference for A/D
ICSPCLK ST — Serial Programming Clock
RA2/AN2/T0CKI/INT/C1OUT RA2 ST CMOS PORTA I/O w/prog pull-up and interrupt-on-change
T0CKI ST — Timer0 clock input
INT ST — External Interrupt
C1OUT — CMOS Comparator 1 output
RA3/MCLR/VPP RA3 TTL — PORTA input with interrupt-on-change
MCLR ST — Master Clear w/internal pull-up
VPP HV — Programming voltage
RA4/AN3/T1G/OSC2/CLKOUT RA4 TTL CMOS PORTA I/O w/prog pull-up and interrupt-on-change
T1G ST — Timer1 gate
OSC2 — XTAL Crystal/Resonator
CLKOUT — CMOS FOSC/4 output
RA5/T1CKI/OSC1/CLKIN RA5 TTL CMOS PORTA I/O w/prog pull-up and interrupt-on-change
T1CKI ST — Timer1 clock
OSC1 XTAL — Crystal/Resonator
CLKIN ST — External clock input/RC oscillator connection
RC0/AN4/C2IN+ RC0 TTL CMOS PORTC I/O
C2IN+ AN Comparator 2 input
RC1/AN5/C2IN- RC1 TTL CMOS PORTC I/O
C2IN- AN Comparator 2 input
RC2/AN6 RC2 TTL CMOS PORTC I/O
RC3/AN7 RC3 TTL CMOS PORTC I/O
RC4/C2OUT/TX/CK RC4 TTL CMOS PORTC I/O
C2OUT — CMOS Comparator 2 output
TX — CMOS USART asynchronous output
CK ST CMOS USART asynchronous clock
RC5/RX/DT RC5 TTL CMOS Port C I/O
RX ST CMOS USART asynchronous input
DT ST CMOS USART asynchronous data
VSS VSS Power — Ground reference
VDD VDD Power — Positive supply
Legend: AN = Analog input or output CMOS = CMOS compatible input or output OC = Open collector output
TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels
HV = High Voltage XTAL = Crystal

PIC16F688
2.0 MEMORY ORGANIZATION 2.2 Data Memory Organization
The data memory is partitioned into multiple banks,
2.1 Program Memory Organization which contain the General Purpose Registers (GPR)
The PIC16F688 has a 13-bit program counter capable and the Special Function Registers (SFR). Bits RP0
of addressing a 4K x 14 program memory space. Only and RP1 are bank select bits.
the first 4K x 14 (0000h-01FFF) for the PIC16F688 is RP1 RP0
physically implemented. Accessing a location above 0 0 → Bank 0 is selected
these boundaries will cause a wrap-around within the
first 4K x 14 space. The Reset vector is at 0000h and 0 1 → Bank 1 is selected
the interrupt vector is at 0004h (see Figure 2-1). 1 0 → Bank 2 is selected
1 1 → Bank 3 is selected
FIGURE 2-1: PROGRAM MEMORY MAP
Each bank extends up to 7Fh (128 bytes). The lower
AND STACK FOR THE
locations of each bank are reserved for the Special
PIC16F688
Function Registers. Above the Special Function Regis-
PC<12:0> ters are the General Purpose Registers, implemented
as static RAM. All implemented banks contain Special
CALL, RETURN 13
RETFIE, RETLW
Function Registers. Some frequently used Special
Function Registers from one bank are mirrored in
another bank for code reduction and quicker access.
Stack Level 1
Stack Level 2
2.2.1 GENERAL PURPOSE REGISTER
FILE
Stack Level 8 The register file is organized as 256 x 8 in the
PIC16F688. Each register is accessed, either directly
Reset Vector 0000h or indirectly, through the File Select Register (FSR)
(see Section 2.4 “Indirect Addressing, INDF and
FSR Registers”).
Interrupt Vector 0004h

2.2.2 SPECIAL FUNCTION REGISTERS
0005h The Special Function Registers are registers used by
the CPU and peripheral functions for controlling the
On-chip Program desired operation of the device (see Tables 2-1, 2-2,
Memory 2-3 and 2-4). These registers are static RAM.
01FFh
The special registers can be classified into two sets:
02000h core and peripheral. The Special Function Registers
Wraps to 0000h-07FFh associated with the “core” are described in this section.
Those related to the operation of the peripheral
1FFFh features are described in the section of that peripheral
feature.

PIC16F688
FIGURE 2-2: PIC16F688 SPECIAL FUNCTION REGISTERS
File File File File
Address Address Address Address
Indirect addr. (1) 00h Indirect addr. (1) 80h Indirect addr. (1) 100h Indirect addr. (1) 180h
TMR0 01h OPTION_REG 81h TMR0 101h OPTION_REG 181h
PCL 02h PCL 82h PCL 102h PCL 182h
STATUS 03h STATUS 83h STATUS 103h STATUS 183h
FSR 04h FSR 84h FSR 104h FSR 184h
PORTA 05h TRISA 85h PORTA 105h TRISA 185h
06h 86h 106h 186h
PORTC 07h TRISC 87h PORTC 107h TRISC 187h
08h 88h 108h 188h
09h 89h 109h 189h
PCLATH 0Ah PCLATH 8Ah PCLATH 10Ah PCLATH 18Ah
INTCON 0Bh INTCON 8Bh INTCON 10Bh INTCON 18Bh
PIR1 0Ch PIE1 8Ch 10Ch 18Ch
0Dh 8Dh 10Dh 18Dh
TMR1L 0Eh PCON 8Eh 10Eh 18Eh
TMR1H 0Fh OSCCON 8Fh 10Fh 18Fh
T1CON 10h OSCTUNE 90h 110h 190h
BAUDCTL 11h ANSEL 91h 111h 191h
SPBRGH 12h 92h 112h 192h
SPBRG 13h 93h 113h 193h
RCREG 14h 94h 114h 194h
TXREG 15h WPUA 95h 115h 195h
TXSTA 16h IOCA 96h 116h 196h
RCSTA 17h EEDATH 97h 117h 197h
WDTCON 18h EEADRH 98h 118h 198h
CMCON0 19h VRCON 99h 119h 199h
CMCON1 1Ah EEDAT 9Ah 11Ah 19Ah
1Bh EEADR 9Bh 11Bh 19Bh
1Ch EECON1 9Ch 11Ch 19Ch
1Dh EECON2(1) 9Dh 11Dh 19Dh
ADRESH 1Eh ADRESL 9Eh 11Eh 19Eh
ADCON0 1Fh ADCON1 9Fh 11Fh 19Fh
20h A0h 120h 1A0h
General General
General Purpose Purpose
Purpose Register Register
Register
80 Bytes 80 Bytes
96 Bytes EFh 16Fh 1EFh
accesses F0h accesses 170h accesses 1F0h
7Fh Bank 0 FFh Bank 0 17Fh Bank 0 1FFh
Bank 0 Bank 1 Bank 2 Bank 3
Unimplemented data memory locations, read as ‘0’.

Note 1: Not a physical register.

PIC16F688
TABLE 2-1: PIC16F688 SPECIAL REGISTERS SUMMARY BANK 0
Value on
Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page
POR/BOR
Bank 0
00h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx 20, 117
01h TMR0 Timer0 Module’s register xxxx xxxx 45, 117
02h PCL Program Counter’s (PC) Least Significant Byte 0000 0000 19, 117
03h STATUS IRP RP1 RP0 TO PD Z DC C 0001 1xxx 13, 117
04h FSR Indirect Data Memory Address Pointer xxxx xxxx 20, 117
05h PORTA — — RA5 RA4 RA3 RA2 RA1 RA0 --x0 x000 33, 117
06h — Unimplemented — —
07h PORTC — — RC5 RC4 RC3 RC2 RC1 RC0 --xx 0000 42, 117
0Ah PCLATH — — — Write Buffer for upper 5 bits of Program Counter ---0 0000 19, 117
0Bh INTCON GIE PEIE T0IE INTE RAIE T0IF INTF RAIF(2) 0000 000x 15, 117
0Ch PIR1 EEIF ADIF RCIF C2IF C1IF OSFIF TXIF TMR1IF 0000 0000 17, 117
0Dh — Unimplemented — —
0Eh TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 xxxx xxxx 48, 117
0Fh TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 xxxx xxxx 48, 117
10h T1CON T1GINV TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0000 0000 51, 117
11h BAUDCTL ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 01-0 0-00 94, 117
12h SPBRGH USART Baud Rate High Generator 0000 0000 95, 117
13h SPBRG USART Baud Rate Generator 0000 0000 95, 117
14h RCREG USART Receive Register 0000 0000 87, 117
15h TXREG USART Transmit Register 0000 0000 87, 117
16h TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 92, 117
17h RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 93, 117
18h WDTCON — — — WDTPS3 WDTPS2 WDTPS1 WDTPS0 SWDTEN ---0 1000 124, 117
19h CMCON0 C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 0000 0000 61, 117
1Ah CMCON1 — — — — — — T1GSS C2SYNC ---- --10 62, 117
1Bh — Unimplemented — —
1Ch — Unimplemented — —
1Eh ADRESH Most Significant 8 bits of the left shifted A/D result or 2 bits of right shifted result xxxx xxxx 72, 117
1Fh ADCON0 ADFM VCFG — CHS2 CHS1 CHS0 GO/DONE ADON 00-0 0000 71, 117
Legend: – = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented
Note 1: Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation.
2: MCLR and WDT Reset does not affect the previous value data latch. The RAIF bit will be cleared upon Reset but will set again if the
mismatched exists.

PIC16F688
TABLE 2-2: PIC16F688 SPECIAL FUNCTION REGISTERS SUMMARY BANK 1
Value on
POR/BOR
Bank 1
81h OPTION_REG RAPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 14, 117
85h TRISA — — TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 --11 1111 33, 117
87h TRISC — — TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 --11 1111 42, 117
8Ch PIE1 EEIE ADIE RCIE C2IE C1IE OSFIE TXIE TMR1IE 0000 0000 16, 117
8Eh PCON — — ULPWUE SBOREN — — POR BOR --01 --qq 18, 117
8Fh OSCCON — IRCF2 IRCF1 IRCF0 OSTS HTS LTS SCS -110 x000 22, 118
90h OSCTUNE — — — TUN4 TUN3 TUN2 TUN1 TUN0 ---0 0000 26, 118
91h ANSEL ANS7 ANS6 ANS5 ANS4 ANS3 ANS2 ANS1 ANS0 1111 1111 34, 118
95h WPUA(2) — — WPUA5 WPUA4 — WPUA2 WPUA1 WPUA0 --11 -111 35, 118
96h IOCA — — IOCA5 IOCA4 IOCA3 IOCA2 IOCA1 IOCA0 --00 0000 35, 118
97h EEDATH — — EEDATH5 EEDATH4 EEDATH3 EEDATH2 EEDATH1 EEDATH0 --00 0000 78, 118
98h EEADRH — — — — EEADRH3 EEADRH2 EEADRH1 EEADRH0 ---- 0000 78, 118
99h VRCON VREN — VRR — VR3 VR2 VR1 VR0 0-0- 0000 63, 118
9Ah EEDAT EEDAT7 EEDAT6 EEDAT5 EEDAT4 EEDAT3 EEDAT2 EEDAT1 EEDAT0 0000 0000 78, 118
9Bh EEADR EEADR7 EEADR6 EEADR5 EEADR4 EEADR3 EEADR2 EEADR1 EEADR0 0000 0000 78, 118
9Ch EECON1 EEPGD — — — WRERR WREN WR RD x--- x000 79, 118
9Dh EECON2 EEPROM Control 2 Register (not a physical register) ---- ---- 77, 118
9Eh ADRESL Least Significant 2 bits of the left shifted result or 8 bits of the right shifted result xxxx xxxx 72, 118
9Fh ADCON1 — ADCS2 ADCS1 ADCS0 — — — — -000 ---- 71, 118
2: RA3 pull-up is enabled when pin is configured as MCLR in the Configuration Word register.
mismatched exists.

PIC16F688
TABLE 2-3: PIC16F688 SPECIAL REGISTERS SUMMARY BANK 2
Value on
POR/BOR
Bank 2
101h TMR0 Timer0 Module’s register xxxx xxxx 45, 117
105h PORTA — — RA5 RA4 RA3 RA2 RA1 RA0 --x0 x000 33, 117
107h PORTC — — RC5 RC4 RC3 RC2 RC1 RC0 --xx 0000 42, 117
10Eh — Unimplemented — —
10Fh — Unimplemented — —
11Ah — Unimplemented — —
mismatched exists.

PIC16F688
TABLE 2-4: PIC16F688 SPECIAL FUNCTION REGISTERS SUMMARY BANK 3
Value on
POR/BOR
Bank 3
181h OPTION_REG RAPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 14, 117
185h TRISA — — TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 --11 1111 33, 117
187h TRISC — — TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 --11 1111 42, 117
mismatched exists.

PIC16F688
2.2.2.1 STATUS Register For example, CLRF STATUS will clear the upper three
bits and set the Z bit. This leaves the STATUS register
The STATUS register, shown in Register 2-1, contains:
as ‘000u u1uu’ (where u = unchanged).
• the arithmetic status of the ALU
It is recommended, therefore, that only BCF, BSF,
• the Reset status SWAPF and MOVWF instructions are used to alter the
• the bank select bits for data memory (SRAM) STATUS register, because these instructions do not
The STATUS register can be the destination for any affect any Status bits. For other instructions not
instruction, like any other register. If the STATUS affecting any Status bits (see Section 12.0
register is the destination for an instruction that affects “Instruction Set Summary”).
the Z, DC or C bits, then the write to these three bits is Note 1: The C and DC bits operate as a Borrow
disabled. These bits are set or cleared according to the and Digit Borrow out bit, respectively, in
device logic. Furthermore, the TO and PD bits are not subtraction.
writable. Therefore, the result of an instruction with the
STATUS register as destination may be different than
intended.
REGISTER 2-1: STATUS: STATUS REGISTER
R/W-0 R/W-0 R/W-0 R-1 R-1 R/W-x R/W-x R/W-x
IRP RP1 RP0 TO PD Z DC(1) C(1)
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 IRP: Register Bank Select bit (used for indirect addressing)
1 = Bank 2, 3 (100h-1FFh)
0 = Bank 0, 1 (00h-FFh)
bit 6-5 RP<1:0>: Register Bank Select bits (used for direct addressing)
00 = Bank 0 (00h-7Fh)
01 = Bank 1 (80h-FFh)
10 = Bank 2 (100h-17Fh)
11 = Bank 3 (180h-1FFh)
bit 4 TO: Time-out bit
1 = After power-up, CLRWDT instruction or SLEEP instruction
0 = A WDT time-out occurred
bit 3 PD: Power-down bit
1 = After power-up or by the CLRWDT instruction
0 = By execution of the SLEEP instruction
bit 2 Z: Zero bit
1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero
bit 1 DC: Digit Carry/Borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions)(1)
1 = A carry-out from the 4th low-order bit of the result occurred
0 = No carry-out from the 4th low-order bit of the result
bit 0 C: Carry/Borrow bit(1) (ADDWF, ADDLW, SUBLW, SUBWF instructions)(1)
1 = A carry-out from the Most Significant bit of the result occurred
0 = No carry-out from the Most Significant bit of the result occurred
Note 1: For Borrow, the polarity is reversed. A subtraction is executed by adding the two’s complement of the second operand.
For rotate (RRF, RLF) instructions, this bit is loaded with either the high-order or low-order bit of the source register.

PIC16F688
2.2.2.2 OPTION Register
Note: To achieve a 1:1 prescaler assignment for
The OPTION register is a readable and writable
Timer0, assign the prescaler to the WDT
register, which contains various control bits to
by setting PSA bit of the OPTION register
configure:
to ‘1’. See Section 5.1.3 “Software
• Timer0/WDT prescaler Programmable Prescaler”.
• External RA2/INT interrupt
• Timer0
• Weak pull-ups on PORTA
REGISTER 2-2: OPTION_REG: OPTION REGISTER

R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
RAPU INTEDG T0CS T0SE PSA PS2 PS1 PS0
bit 7 bit 0
Legend:
bit 7 RAPU: PORTA Pull-up Enable bit

1 = PORTA pull-ups are disabled
0 = PORTA pull-ups are enabled by individual PORT latch values
bit 6 INTEDG: Interrupt Edge Select bit
1 = Interrupt on rising edge of RA2/INT pin
0 = Interrupt on falling edge of RA2/INT pin
bit 5 T0CS: Timer0 Clock Source Select bit
1 = Transition on RA2/T0CKI pin
0 = Internal instruction cycle clock (FOSC/4)
bit 4 T0SE: Timer0 Source Edge Select bit
1 = Increment on high-to-low transition on RA2/T0CKI pin
0 = Increment on low-to-high transition on RA2/T0CKI pin
bit 3 PSA: Prescaler Assignment bit
1 = Prescaler is assigned to the WDT
0 = Prescaler is assigned to the Timer0 module
bit 2-0 PS<2:0>: Prescaler Rate Select bits
Bit Value Timer0 Rate WDT Rate
000 1:2 1:1

001 1:4 1:2
010 1:8 1:4
011 1 : 16 1:8
100 1 : 32 1 : 16
101 1 : 64 1 : 32
110 1 : 128 1 : 64
111 1 : 256 1 : 128

PIC16F688
2.2.2.3 INTCON Register
Note: Interrupt flag bits are set when an interrupt
The INTCON register is a readable and writable
condition occurs, regardless of the state of
register, which contains the various enable and flag bits
its corresponding enable bit or the global
for TMR0 register overflow, PORTA change and
enable bit, GIE of the INTCON register.
external RA2/INT pin interrupts.
User software should ensure the appropri-
ate interrupt flag bits are clear prior to
enabling an interrupt.
REGISTER 2-3: INTCON: INTERRUPT CONTROL REGISTER

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-x
GIE PEIE T0IE INTE RAIE T0IF INTF RAIF
bit 7 bit 0
Legend:
bit 7 GIE: Global Interrupt Enable bit

1 = Enables all unmasked interrupts
0 = Disables all interrupts
bit 6 PEIE: Peripheral Interrupt Enable bit
1 = Enables all unmasked peripheral interrupts
0 = Disables all peripheral interrupts
bit 5 T0IE: Timer0 Overflow Interrupt Enable bit
1 = Enables the Timer0 interrupt
0 = Disables the Timer0 interrupt
bit 4 INTE: RA2/INT External Interrupt Enable bit
1 = Enables the RA2/INT external interrupt
0 = Disables the RA2/INT external interrupt
bit 3 RAIE: PORTA Change Interrupt Enable bit(1)
1 = Enables the PORTA change interrupt
0 = Disables the PORTA change interrupt
bit 2 T0IF: Timer0 Overflow Interrupt Flag bit(2)
1 = Timer0 register has overflowed (must be cleared in software)
0 = Timer0 register did not overflow
bit 1 INTF: RA2/INT External Interrupt Flag bit
1 = The RA2/INT external interrupt occurred (must be cleared in software)
0 = The RA2/INT external interrupt did not occur
bit 0 RAIF: PORTA Change Interrupt Flag bit
1 = When at least one of the PORTA <5:0> pins changed state (must be cleared in software)
0 = None of the PORTA <5:0> pins have changed state
Note 1: IOCA register must also be enabled.

2: T0IF bit is set when TMR0 rolls over. TMR0 is unchanged on Reset and should be initialized before
clearing T0IF bit.

PIC16F688
2.2.2.4 PIE1 Register
The PIE1 register contains the interrupt enable bits, as
Note: Bit PEIE of the INTCON register must be
shown in Register 2-4.
set to enable any peripheral interrupt.
REGISTER 2-4: PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1

EEIE ADIE RCIE C2IE C1IE OSFIE TXIE TMR1IE
bit 7 bit 0
Legend:
bit 7 EEIE: EE Write Complete Interrupt Enable bit

1 = Enables the EE write complete interrupt
0 = Disables the EE write complete interrupt
bit 6 ADIE: A/D Converter (ADC) Interrupt Enable bit
1 = Enables the ADC interrupt
0 = Disables the ADC interrupt
bit 5 RCIE: EUSART Receive Interrupt Enable bit
1 = Enables the EUSART receive interrupt
0 = Disables the EUSART receive interrupt
bit 4 C2IE: Comparator 2 Interrupt Enable bit
1 = Enables the Comparator C2 interrupt
0 = Disables the Comparator C2 interrupt
bit 3 C1IE: Comparator 1 Interrupt Enable bit
1 = Enables the Comparator C1 interrupt
0 = Disables the Comparator C1 interrupt
bit 2 OSFIE: Oscillator Fail Interrupt Enable bit
1 = Enables the oscillator fail interrupt
0 = Disables the oscillator fail interrupt
bit 1 TXIE: EUSART Transmit Interrupt Enable bit
1 = Enables the EUSART transmit interrupt
0 = Disables the EUSART transmit interrupt
bit 0 TMR1IE: Timer1 Overflow Interrupt Enable bit
1 = Enables the Timer1 overflow interrupt
0 = Disables the Timer1 overflow interrupt

PIC16F688
2.2.2.5 PIR1 Register
The PIR1 register contains the interrupt flag bits, as Note: Interrupt flag bits are set when an interrupt
shown in Register 2-5. condition occurs, regardless of the state of
its corresponding enable bit or the global
enable bit, GIE bit of the INTCON register.
User software should ensure the appropri-
ate interrupt flag bits are clear prior to
enabling an interrupt.
REGISTER 2-5: PIR1: PERIPHERAL INTERRUPT REQUEST REGISTER 1

R/W-0 R/W-0 R-0 R/W-0 R/W-0 R/W-0 R-0 R/W-0
EEIF ADIF RCIF C2IF C1IF OSFIF TXIF TMR1IF
bit 7 bit 0
Legend:
bit 7 EEIF: EEPROM Write Operation Interrupt Flag bit

1 = The write operation completed (must be cleared in software)
0 = The write operation has not completed or has not been started
bit 6 ADIF: A/D Converter Interrupt Flag bit
1 = A/D conversion complete (must be cleared in software)
0 = A/D conversion has not completed or has not been started
bit 5 RCIF: EUSART Receive Interrupt Flag bit
1 = The EUSART receive buffer is full (cleared by reading RCREG)
0 = The EUSART receive buffer is not full
bit 4 C2IF: Comparator C2 Interrupt Flag bit
1 = Comparator output (C2OUT bit) has changed (must be cleared in software)
0 = Comparator output (C2OUT bit) has not changed
bit 3 C1IF: Comparator C1 Interrupt Flag bit
1 = Comparator output (C1OUT bit) has changed (must be cleared in software)
0 = Comparator output (C1OUT bit) has not changed
bit 2 OSFIF: Oscillator Fail Interrupt Flag bit
1 = System oscillator failed, clock input has changed to INTOSC (must be cleared in software)
0 = System clock operating
bit 1 TXIF: EUSART Transmit Interrupt Flag bit
1 = The EUSART transmit buffer is empty (cleared by writing to TXREG)
0 = The EUSART transmit buffer is full
bit 0 TMR1IF: Timer1 Overflow Interrupt Flag bit
1 = The TMR1 register overflowed (must be cleared in software)
0 = The TMR1 register did not overflow

PIC16F688
2.2.2.6 PCON Register
The Power Control (PCON) register (see Register 2-6)
contains flag bits to differentiate between a:
• Power-on Reset (POR)
• Brown-out Reset (BOR)
• Watchdog Timer Reset (WDT)
• External MCLR Reset
The PCON register also controls the Ultra Low-Power
Wake-up and software enable of the BOR.
REGISTER 2-6: PCON: POWER CONTROL REGISTER

U-0 U-0 R/W-0 R/W-1 U-0 U-0 R/W-0 R/W-x
— — ULPWUE SBOREN(1) — — POR BOR
bit 7 bit 0
Legend:
bit 7-6 Unimplemented: Read as ‘0’

bit 5 ULPWUE: Ultra Low-Power Wake-up Enable bit
1 = Ultra low-power wake-up enabled
0 = Ultra low-power wake-up disabled
bit 4 SBOREN: Software BOR Enable bit(1)
1 = BOR enabled
0 = BOR disabled
bit 1 POR: Power-on Reset Status bit
1 = No Power-on Reset occurred
0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)
bit 0 BOR: Brown-out Reset Status bit
1 = No Brown-out Reset occurred
0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs)
Note 1: BOREN<1:0> = 01 in the Configuration Word register for this bit to control the BOR.

PIC16F688
2.3 PCL and PCLATH 2.3.2 STACK
The Program Counter (PC) is 13 bits wide. The low byte The PIC16F688 family has an 8-level x 13-bit wide
comes from the PCL register, which is a readable and hardware stack (see Figure 2-1). The stack space is
writable register. The high byte (PC<12:8>) is not not part of either program or data space and the Stack
directly readable or writable and comes from PCLATH. Pointer is not readable or writable. The PC is PUSHed
On any Reset, the PC is cleared. Figure 2-3 shows the onto the stack when a CALL instruction is executed or
two situations for the loading of the PC. The upper an interrupt causes a branch. The stack is POPed in
example in Figure 2-3 shows how the PC is loaded on a the event of a RETURN, RETLW or a RETFIE
write to PCL (PCLATH<4:0> → PCH). The lower exam- instruction execution. PCLATH is not affected by a
ple in Figure 2-3 shows how the PC is loaded during a PUSH or POP operation.
CALL or GOTO instruction (PCLATH<4:3> → PCH). The stack operates as a circular buffer. This means that
after the stack has been PUSHed eight times, the ninth
FIGURE 2-3: LOADING OF PC IN push overwrites the value that was stored from the first
DIFFERENT SITUATIONS push. The tenth push overwrites the second push (and
so on).
PCH PCL
Instruction with Note 1: There are no Status bits to indicate Stack
12 8 7 0 PCL as
PC Destination Overflow or Stack Underflow conditions.
PCLATH<4:0> 8 2: There are no instructions/mnemonics

5 ALU Result called PUSH or POP. These are actions
that occur from the execution of the
PCLATH CALL, RETURN, RETLW and RETFIE
instructions or the vectoring to an
PCH PCL interrupt address.
12 11 10 8 7 0
PC GOTO, CALL
PCLATH<4:3> 11
2 OPCODE<10:0>
PCLATH
2.3.1 COMPUTED GOTO

A computed GOTO is accomplished by adding an offset
to the program counter (ADDWF PCL). When
performing a table read using a computed GOTO
method, care should be exercised if the table location
crosses a PCL memory boundary (each 256-byte
block). Refer to the Application Note AN556,
“Implementing a Table Read” (DS00556).

PIC16F688
2.4 Indirect Addressing, INDF and A simple program to clear RAM location 20h-2Fh using
FSR Registers indirect addressing is shown in Example 2-1.
The INDF register is not a physical register. Addressing EXAMPLE 2-1: INDIRECT ADDRESSING
the INDF register will cause indirect addressing.
MOVLW 0x20 ;initialize pointer
Indirect addressing is possible by using the INDF MOVWF FSR ;to RAM
register. Any instruction using the INDF register NEXT CLRF INDF ;clear INDF register
actually accesses data pointed to by the File Select INCF FSR ;inc pointer
Register (FSR). Reading INDF itself indirectly will BTFSS FSR,4 ;all done?
produce 00h. Writing to the INDF register indirectly GOTO NEXT ;no clear next
CONTINUE ;yes continue
results in a no operation (although Status bits may be
affected). An effective 9-bit address is obtained by
concatenating the 8-bit FSR register and the IRP bit of
the STATUS register, as shown in Figure 2-4.
FIGURE 2-4: DIRECT/INDIRECT ADDRESSING PIC16F688
Direct Addressing Indirect Addressing
RP1 RP0 6 From Opcode 0 IRP 7 File Select Register 0
Bank Select Location Select Bank Select Location Select

00 01 10 11
00h 180h
Data
Memory
7Fh 1FFh
Bank 0 Bank 1 Bank 2 Bank 3
Note: For memory map detail, see Figure 2-2.

PIC16F688
3.0 OSCILLATOR MODULE (WITH The oscillator module can be configured in one of eight
clock modes.
FAIL-SAFE CLOCK MONITOR)
1. EC – External clock with I/O on OSC2/CLKOUT.
3.1 Overview 2. LP – 32 kHz Low-Power Crystal mode.
3. XT – Medium Gain Crystal or Ceramic
The oscillator module has a wide variety of clock Resonator Oscillator mode.
sources and selection features that allow it to be used
4. HS – High Gain Crystal or Ceramic Resonator
in a wide range of applications while maximizing perfor-
mode.
mance and minimizing power consumption. Figure 3-1
illustrates a block diagram of the oscillator module. 5. RC – External Resistor-Capacitor (RC) with
FOSC/4 output on OSC2/CLKOUT.
Clock sources can be configured from external
6. RCIO – External Resistor-Capacitor (RC) with
oscillators, quartz crystal resonators, ceramic resonators
I/O on OSC2/CLKOUT.
and Resistor-Capacitor (RC) circuits. In addition, the
system clock source can be configured from one of two 7. INTOSC – Internal oscillator with FOSC/4 output
internal oscillators, with a choice of speeds selectable via on OSC2 and I/O on OSC1/CLKIN.
software. Additional clock features include: 8. INTOSCIO – Internal oscillator with I/O on
OSC1/CLKIN and OSC2/CLKOUT.
• Selectable system clock source between external
or internal via software. Clock source modes are configured by the FOSC<2:0>
• Two-Speed Start-Up mode, which minimizes bits in the Configuration Word register (CONFIG). The
latency between external oscillator start-up and internal clock can be generated from two internal
code execution. oscillators. The HFINTOSC is a calibrated high-
frequency oscillator. The LFINTOSC is an uncalibrated
• Fail-Safe Clock Monitor (FSCM) designed to
low-frequency oscillator.
detect a failure of the external clock source (LP,
XT, HS, EC or RC modes) and switch
automatically to the internal oscillator.
FIGURE 3-1: PIC® MCU CLOCK SOURCE BLOCK DIAGRAM
FOSC<2:0>
(Configuration Word Register)
External Oscillator SCS<0>
(OSCCON Register)
OSC2
Sleep
LP, XT, HS, RC, RCIO, EC
OSC1
MUX
IRCF<2:0>
(OSCCON Register) System Clock
(CPU and Peripherals)
8 MHz
111 INTOSC
Internal Oscillator 4 MHz
110
2 MHz
101
Postscaler
1 MHz
MUX
HFINTOSC 100
500 kHz
8 MHz 011
250 kHz
010
125 kHz
001
LFINTOSC 31 kHz
000
31 kHz
Power-up Timer (PWRT)

Watchdog Timer (WDT)
Fail-Safe Clock Monitor (FSCM)

PIC16F688
3.2 Oscillator Control
The Oscillator Control (OSCCON) register (Figure 3-1)
controls the system clock and frequency selection
options. The OSCCON register contains the following
bits:
• Frequency selection bits (IRCF)
• Frequency Status bits (HTS, LTS)
• System clock control bits (OSTS, SCS)
REGISTER 3-1: OSCCON: OSCILLATOR CONTROL REGISTER

U-0 R/W-1 R/W-1 R/W-0 R-1 R-0 R-0 R/W-0
— IRCF2 IRCF1 IRCF0 OSTS(1) HTS LTS SCS
bit 7 bit 0
Legend:
bit 7 Unimplemented: Read as ‘0’

bit 6-4 IRCF<2:0>: Internal Oscillator Frequency Select bits
111 = 8 MHz
110 = 4 MHz (default)
101 = 2 MHz
100 = 1 MHz
011 = 500 kHz
010 = 250 kHz
001 = 125 kHz
000 = 31 kHz (LFINTOSC)
bit 3 OSTS: Oscillator Start-up Time-out Status bit(1)
1 = Device is running from the external clock defined by FOSC<2:0> of the Configuration Word
0 = Device is running from the internal oscillator (HFINTOSC or LFINTOSC)
bit 2 HTS: HFINTOSC Status bit (High Frequency – 8 MHz to 125 kHz)
1 = HFINTOSC is stable
0 = HFINTOSC is not stable
bit 1 LTS: LFINTOSC Stable bit (Low Frequency – 31 kHz)
1 = LFINTOSC is stable
0 = LFINTOSC is not stable
bit 0 SCS: System Clock Select bit
1 = Internal oscillator is used for system clock
0 = Clock source defined by FOSC<2:0> of the Configuration Word
Note 1: Bit resets to ‘0’ with Two-Speed Start-up and LP, XT or HS selected as the Oscillator mode or Fail-Safe
mode is enabled.

PIC16F688
3.3 Clock Source Modes 3.4 External Clock Modes
Clock source modes can be classified as external or 3.4.1 OSCILLATOR START-UP TIMER (OST)
internal.
If the oscillator module is configured for LP, XT or HS
• External Clock modes rely on external circuitry for modes, the Oscillator Start-up Timer (OST) counts
the clock source. Examples are: oscillator mod- 1024 oscillations from OSC1. This occurs following a
ules (EC mode), quartz crystal resonators or Power-on Reset (POR) and when the Power-up Timer
ceramic resonators (LP, XT and HS modes) and (PWRT) has expired (if configured), or a wake-up from
Resistor-Capacitor (RC) mode circuits. Sleep. During this time, the program counter does not
• Internal clock sources are contained internally increment and program execution is suspended. The
within the oscillator module. The oscillator module OST ensures that the oscillator circuit, using a quartz
has two internal oscillators: the 8 MHz High- crystal resonator or ceramic resonator, has started and
Frequency Internal Oscillator (HFINTOSC) and is providing a stable system clock to the oscillator
the 31 kHz Low-Frequency Internal Oscillator module. When switching between clock sources, a
(LFINTOSC). delay is required to allow the new clock to stabilize.
The system clock can be selected between external or These oscillator delays are shown in Table 3-1.
internal clock sources via the System Clock Select In order to minimize latency between external oscillator
(SCS) bit of the OSCCON register. See Section 3.6 start-up and code execution, the Two-Speed Clock
“Clock Switching” for additional information. Start-up mode can be selected (see Section 3.7 “Two-
Speed Clock Start-up Mode”).
TABLE 3-1: OSCILLATOR DELAY EXAMPLES

Switch From Switch To Frequency Oscillator Delay
LFINTOSC 31 kHz
Sleep/POR Oscillator Warm-Up Delay (TWARM)
HFINTOSC 125 kHz to 8 MHz
Sleep/POR EC, RC DC – 20 MHz 2 instruction cycles
LFINTOSC (31 kHz) EC, RC DC – 20 MHz 1 cycle of each
Sleep/POR LP, XT, HS 32 kHz to 20 MHz 1024 Clock Cycles (OST)
LFINTOSC (31 kHz) HFINTOSC 125 kHz to 8 MHz 1 μs (approx.)
3.4.2 EC MODE FIGURE 3-2: EXTERNAL CLOCK (EC)

The External Clock (EC) mode allows an externally MODE OPERATION
generated logic level as the system clock source. When
operating in this mode, an external clock source is Clock from OSC1/CLKIN
connected to the OSC1 input and the OSC2 is available Ext. System
for general purpose I/O. Figure 3-2 shows the pin PIC® MCU
connections for EC mode.
I/O OSC2/CLKOUT(1)
The Oscillator Start-up Timer (OST) is disabled when
EC mode is selected. Therefore, there is no delay in
operation after a Power-on Reset (POR) or wake-up Note 1: Alternate pin functions are listed in
from Sleep. Because the PIC® MCU design is fully Section 1.0 “Device Overview”.
static, stopping the external clock input will have the
effect of halting the device while leaving all data intact.
Upon restarting the external clock, the device will
resume operation as if no time had elapsed.

PIC16F688
3.4.3 LP, XT, HS MODES
Note 1: Quartz crystal characteristics vary according
The LP, XT and HS modes support the use of quartz to type, package and manufacturer. The
crystal resonators or ceramic resonators connected to user should consult the manufacturer data
OSC1 and OSC2 (Figure 3-3). The mode selects a low, sheets for specifications and recommended
medium or high gain setting of the internal inverter- application.
amplifier to support various resonator types and speed.
2: Always verify oscillator performance over
LP Oscillator mode selects the lowest gain setting of the VDD and temperature range that is
the internal inverter-amplifier. LP mode current expected for the application.
consumption is the least of the three modes. This mode
3: For oscillator design assistance, reference
is best suited to drive resonators with a low drive level
the following Microchip Applications Notes:
specification, for example, tuning fork type crystals.
This mode is designed to drive only 32.768 kHz tuning • AN826, “Crystal Oscillator Basics and
fork type crystals (watch crystals). Crystal Selection for rfPIC® and PIC®
Devices” (DS00826)
XT Oscillator mode selects the intermediate gain
setting of the internal inverter-amplifier. XT mode • AN849, “Basic PIC® Oscillator Design”
current consumption is the medium of the three modes. (DS00849)
This mode is best suited to drive resonators with a • AN943, “Practical PIC® Oscillator
medium drive level specification. Analysis and Design” (DS00943)
HS Oscillator mode selects the highest gain setting of the • AN949, “Making Your Oscillator Work”
internal inverter-amplifier. HS mode current consumption (DS00949)
is the highest of the three modes. This mode is best
suited for resonators that require a high drive setting. FIGURE 3-4: CERAMIC RESONATOR
OPERATION
Figure 3-3 and Figure 3-4 show typical circuits for
(XT OR HS MODE)
quartz crystal and ceramic resonators, respectively.
FIGURE 3-3: QUARTZ CRYSTAL PIC® MCU
OPERATION (LP, XT OR
OSC1/CLKIN
HS MODE)
C1 To Internal
Logic
PIC® MCU
RP(3) RF(2) Sleep
OSC1/CLKIN
C1 To Internal
Logic OSC2/CLKOUT
C2 Ceramic RS(1)
Quartz Resonator
RF(2) Sleep
Crystal
Note 1: A series resistor (RS) may be required for
ceramic resonators with low drive level.
OSC2/CLKOUT
C2 RS(1) 2: The value of RF varies with the Oscillator mode
selected (typically between 2 MΩ to 10 MΩ).
Note 1: A series resistor (RS) may be required for 3: An additional parallel feedback resistor (RP)
quartz crystals with low drive level. may be required for proper ceramic resonator
2: The value of RF varies with the Oscillator mode operation.
selected (typically between 2 MΩ to 10 MΩ).

PIC16F688
3.4.4 EXTERNAL RC MODES 3.5 Internal Clock Modes
The external Resistor-Capacitor (RC) modes support The oscillator module has two independent, internal
the use of an external RC circuit. This allows the oscillators that can be configured or selected as the
designer maximum flexibility in frequency choice while system clock source.
keeping costs to a minimum when clock accuracy is not
required. There are two modes: RC and RCIO. 1. The HFINTOSC (High-Frequency Internal
Oscillator) is factory calibrated and operates at
In RC mode, the RC circuit connects to OSC1. OSC2/ 8 MHz. The frequency of the HFINTOSC can be
CLKOUT outputs the RC oscillator frequency divided user-adjusted via software using the OSCTUNE
by 4. This signal may be used to provide a clock for register (Register 3-2).
external circuitry, synchronization, calibration, test or
2. The LFINTOSC (Low-Frequency Internal
other application requirements. Figure 3-5 shows the
Oscillator) is uncalibrated and operates at 31 kHz.
external RC mode connections.
The system clock speed can be selected via software
FIGURE 3-5: EXTERNAL RC MODES using the Internal Oscillator Frequency Select bits
IRCF<2:0> of the OSCCON register.
VDD The system clock can be selected between external or
PIC® MCU
internal clock sources via the System Clock Selection
REXT (SCS) bit of the OSCCON register. See Section 3.6
OSC1/CLKIN Internal “Clock Switching” for more information.
Clock
CEXT 3.5.1 INTOSC AND INTOSCIO MODES
The INTOSC and INTOSCIO modes configure the
VSS
internal oscillators as the system clock source when
FOSC/4 or OSC2/CLKOUT(1) the device is programmed using the oscillator selection
I/O(2) or the FOSC<2:0> bits in the Configuration Word
register (CONFIG). See Section 11.0 “Special
Features of the CPU” for more information.
Recommended values: 10 kΩ ≤ REXT ≤ 100 kΩ, <3V
3 kΩ ≤ REXT ≤ 100 kΩ, 3-5V In INTOSC mode, OSC1/CLKIN is available for general
CEXT > 20 pF, 2-5V purpose I/O. OSC2/CLKOUT outputs the selected
Note 1: Alternate pin functions are listed in
internal oscillator frequency divided by 4. The CLKOUT
Section 1.0 “Device Overview”. signal may be used to provide a clock for external
2: Output depends upon RC or RCIO clock mode. circuitry, synchronization, calibration, test or other
application requirements.
In RCIO mode, the RC circuit is connected to OSC1. In INTOSCIO mode, OSC1/CLKIN and OSC2/CLKOUT
OSC2 becomes an additional general purpose I/O pin. are available for general purpose I/O.
The RC oscillator frequency is a function of the supply
voltage, the resistor (REXT) and capacitor (CEXT) values 3.5.2 HFINTOSC
and the operating temperature. Other factors affecting The High-Frequency Internal Oscillator (HFINTOSC) is
the oscillator frequency are: a factory calibrated 8 MHz internal clock source. The
• threshold voltage variation frequency of the HFINTOSC can be altered via
• component tolerances software using the OSCTUNE register (Register 3-2).
• packaging variations in capacitance The output of the HFINTOSC connects to a postscaler
The user also needs to take into account variation due and multiplexer (see Figure 3-1). One of seven
to tolerance of external RC components used. frequencies can be selected via software using the
IRCF<2:0> bits of the OSCCON register. See
Section 3.5.4 “Frequency Select Bits (IRCF)” for
more information.
The HFINTOSC is enabled by selecting any frequency
between 8 MHz and 125 kHz by setting the IRCF<2:0>
bits of the OSCCON register ≠ 000. Then, set the
System Clock Source (SCS) bit of the OSCCON
register to ‘1’ or enable Two-Speed Start-up by setting
the IESO bit in the Configuration Word register
(CONFIG) to ‘1’.
The HF Internal Oscillator (HTS) bit of the OSCCON
register indicates whether the HFINTOSC is stable or not.

PIC16F688
3.5.2.1 OSCTUNE Register When the OSCTUNE register is modified, the
HFINTOSC frequency will begin shifting to the new
The HFINTOSC is factory calibrated but can be
frequency. Code execution continues during this shift.
adjusted in software by writing to the OSCTUNE
There is no indication that the shift has occurred.
register (Register 3-2).
OSCTUNE does not affect the LFINTOSC frequency.
The default value of the OSCTUNE register is ‘0’. The
Operation of features that depend on the LFINTOSC
value is a 5-bit two’s complement number.
clock source frequency, such as the Power-up Timer
(PWRT), Watchdog Timer (WDT), Fail-Safe Clock
Monitor (FSCM) and peripherals, are not affected by the
change in frequency.
REGISTER 3-2: OSCTUNE: OSCILLATOR TUNING REGISTER

U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — — TUN4 TUN3 TUN2 TUN1 TUN0
bit 7 bit 0
Legend:

bit 4-0 TUN<4:0>: Frequency Tuning bits
01111 = Maximum frequency
01110 =
•
•
•
00001 =
00000 = Oscillator module is running at the calibrated frequency.
11111 =
•
•
•
10000 = Minimum frequency

PIC16F688
3.5.3 LFINTOSC 3.5.5 HF AND LF INTOSC CLOCK
The Low-Frequency Internal Oscillator (LFINTOSC) is SWITCH TIMING
an uncalibrated 31 kHz internal clock source. When switching between the LFINTOSC and the
The output of the LFINTOSC connects to a postscaler HFINTOSC, the new oscillator may already be shut
and multiplexer (see Figure 3-1). Select 31 kHz, via down to save power (see Figure 3-6). If this is the case,
software, using the IRCF<2:0> bits of the OSCCON there is a delay after the IRCF<2:0> bits of the
register. See Section 3.5.4 “Frequency Select Bits OSCCON register are modified before the frequency
(IRCF)” for more information. The LFINTOSC is also the selection takes place. The LTS and HTS bits of the
frequency for the Power-up Timer (PWRT), Watchdog OSCCON register will reflect the current active status
Timer (WDT) and Fail-Safe Clock Monitor (FSCM). of the LFINTOSC and HFINTOSC oscillators. The
timing of a frequency selection is as follows:
The LFINTOSC is enabled by selecting 31 kHz
(IRCF<2:0> bits of the OSCCON register = 000) as the 1. IRCF<2:0> bits of the OSCCON register are
system clock source (SCS bit of the OSCCON modified.
register = 1), or when any of the following are enabled: 2. If the new clock is shut down, a clock start-up
delay is started.
• Two-Speed Start-up IESO bit of the Configuration
Word register = 1 and IRCF<2:0> bits of the 3. Clock switch circuitry waits for a falling edge of
OSCCON register = 000 the current clock.
• Power-up Timer (PWRT) 4. CLKOUT is held low and the clock switch
circuitry waits for a rising edge in the new clock.
• Watchdog Timer (WDT)
5. CLKOUT is now connected with the new clock.
• Fail-Safe Clock Monitor (FSCM)
LTS and HTS bits of the OSCCON register are
The LF Internal Oscillator (LTS) bit of the OSCCON updated as required.
register indicates whether the LFINTOSC is stable or 6. Clock switch is complete.
not.
See Figure 3-1 for more details.
3.5.4 FREQUENCY SELECT BITS (IRCF) If the internal oscillator speed selected is between
The output of the 8 MHz HFINTOSC and 31 kHz 8 MHz and 125 kHz, there is no start-up delay before
LFINTOSC connects to a postscaler and multiplexer the new frequency is selected. This is because the old
(see Figure 3-1). The Internal Oscillator Frequency and new frequencies are derived from the HFINTOSC
Select bits IRCF<2:0> of the OSCCON register select via the postscaler and multiplexer.
the frequency output of the internal oscillators. One of Start-up delay specifications are located in the
eight frequencies can be selected via software: Section 14.0 “Electrical Specifications”, under the
• 8 MHz AC Specifications (Oscillator Module).
• 4 MHz (Default after Reset)
• 2 MHz
• 1 MHz
• 500 kHz
• 250 kHz
• 125 kHz
• 31 kHz (LFINTOSC)
Note: Following any Reset, the IRCF<2:0> bits of
the OSCCON register are set to ‘110’ and
the frequency selection is set to 4 MHz.
The user can modify the IRCF bits to
select a different frequency.

PIC16F688
FIGURE 3-6: INTERNAL OSCILLATOR SWITCH TIMING
HF LF(1)
HFINTOSC LFINTOSC (FSCM and WDT disabled)
HFINTOSC
Start-up Time 2-cycle Sync Running
LFINTOSC
IRCF <2:0> ≠0 =0
System Clock
Note 1: When going from LF to HF.
HFINTOSC LFINTOSC (Either FSCM or WDT enabled)
HFINTOSC
2-cycle Sync Running
LFINTOSC
IRCF <2:0> ≠0 =0
System Clock
LFINTOSC HFINTOSC
LFINTOSC turns off unless WDT or FSCM is enabled
LFINTOSC
Start-up Time 2-cycle Sync Running
HFINTOSC
IRCF <2:0> =0 ≠0
System Clock

PIC16F688
3.6 Clock Switching When the oscillator module is configured for LP, XT or
HS modes, the Oscillator Start-up Timer (OST) is
The system clock source can be switched between enabled (see Section 3.4.1 “Oscillator Start-up Timer
external and internal clock sources via software using (OST)”). The OST will suspend program execution until
the System Clock Select (SCS) bit of the OSCCON 1024 oscillations are counted. Two-Speed Start-up
register. mode minimizes the delay in code execution by
operating from the internal oscillator as the OST is
3.6.1 SYSTEM CLOCK SELECT (SCS) BIT
counting. When the OST count reaches 1024 and the
The System Clock Select (SCS) bit of the OSCCON OSTS bit of the OSCCON register is set, program
register selects the system clock source that is used for execution switches to the external oscillator.
the CPU and peripherals.
• When the SCS bit of the OSCCON register = 0, 3.7.1 TWO-SPEED START-UP MODE
the system clock source is determined by CONFIGURATION
configuration of the FOSC<2:0> bits in the Two-Speed Start-up mode is configured by the
Configuration Word register (CONFIG). following settings:
• When the SCS bit of the OSCCON register = 1, • IESO (of the Configuration Word register) = 1;
the system clock source is chosen by the internal Internal/External Switchover bit (Two-Speed Start-
oscillator frequency selected by the IRCF<2:0> up mode enabled).
bits of the OSCCON register. After a Reset, the
• SCS (of the OSCCON register) = 0.
SCS bit of the OSCCON register is always
cleared. • FOSC<2:0> bits in the Configuration Word
register (CONFIG) configured for LP, XT or HS
Note: Any automatic clock switch, which may mode.
occur from Two-Speed Start-up or Fail-Safe
Clock Monitor, does not update the SCS bit Two-Speed Start-up mode is entered after:
of the OSCCON register. The user can • Power-on Reset (POR) and, if enabled, after
monitor the OSTS bit of the OSCCON Power-up Timer (PWRT) has expired, or
register to determine the current system • Wake-up from Sleep.
clock source.
If the external clock oscillator is configured to be
anything other than LP, XT or HS mode, then Two-
3.6.2 OSCILLATOR START-UP TIME-OUT
Speed Start-up is disabled. This is because the external
STATUS (OSTS) BIT
clock oscillator does not require any stabilization time
The Oscillator Start-up Time-out Status (OSTS) bit of after POR or an exit from Sleep.
the OSCCON register indicates whether the system
clock is running from the external clock source, as 3.7.2 TWO-SPEED START-UP
defined by the FOSC<2:0> bits in the Configuration SEQUENCE
Word register (CONFIG), or from the internal clock
1. Wake-up from Power-on Reset or Sleep.
source. In particular, OSTS indicates that the Oscillator
Start-up Timer (OST) has timed out for LP, XT or HS 2. Instructions begin execution by the internal
modes. oscillator at the frequency set in the IRCF<2:0>
bits of the OSCCON register.
3.7 Two-Speed Clock Start-up Mode 3. OST enabled to count 1024 clock cycles.
4. OST timed out, wait for falling edge of the
Two-Speed Start-up mode provides additional power internal oscillator.
savings by minimizing the latency between external 5. OSTS is set.
oscillator start-up and code execution. In applications
6. System clock held low until the next falling edge
that make heavy use of the Sleep mode, Two-Speed
of new clock (LP, XT or HS mode).
Start-up will remove the external oscillator start-up
time from the time spent awake and can reduce the 7. System clock is switched to external clock
overall power consumption of the device. source.
This mode allows the application to wake-up from

Sleep, perform a few instructions using the INTOSC
as the clock source and go back to Sleep without
waiting for the primary oscillator to become stable.
Note: Executing a SLEEP instruction will abort
the oscillator start-up time and will cause
the OSTS bit of the OSCCON register to
remain clear.

PIC16F688
3.7.3 CHECKING TWO-SPEED CLOCK
STATUS
Checking the state of the OSTS bit of the OSCCON
register will confirm if the microcontroller is running
from the external clock source, as defined by the
FOSC<2:0> bits in the Configuration Word register
(CONFIG), or the internal oscillator.
FIGURE 3-7: TWO-SPEED START-UP
HFINTOSC
TOST
OSC1 0 1 1022 1023
OSC2
Program Counter PC - N PC PC + 1
System Clock

PIC16F688
3.8 Fail-Safe Clock Monitor 3.8.3 FAIL-SAFE CONDITION CLEARING
The Fail-Safe Clock Monitor (FSCM) allows the device The Fail-Safe condition is cleared after a Reset,
to continue operating should the external oscillator fail. executing a SLEEP instruction or toggling the SCS bit
The FSCM can detect oscillator failure any time after of the OSCCON register. When the SCS bit is toggled,
the Oscillator Start-up Timer (OST) has expired. The the OST is restarted. While the OST is running, the
FSCM is enabled by setting the FCMEN bit in the device continues to operate from the INTOSC selected
Configuration Word register (CONFIG). The FSCM is in OSCCON. When the OST times out, the Fail-Safe
applicable to all external oscillator modes (LP, XT, HS, condition is cleared and the device will be operating
EC, RC and RCIO). from the external clock source. The Fail-Safe condition
must be cleared before the OSFIF flag can be cleared.
FIGURE 3-8: FSCM BLOCK DIAGRAM
3.8.4 RESET OR WAKE-UP FROM SLEEP
Clock Monitor The FSCM is designed to detect an oscillator failure
Latch after the Oscillator Start-up Timer (OST) has expired.
External
S Q The OST is used after waking up from Sleep and after
Clock
any type of Reset. The OST is not used with the EC or
RC Clock modes so that the FSCM will be active as
LFINTOSC soon as the Reset or wake-up has completed. When
÷ 64 R Q
Oscillator the FSCM is enabled, the Two-Speed Start-up is also
enabled. Therefore, the device will always be executing
31 kHz 488 Hz code while the OST is operating.
(~32 μs) (~2 ms)
Note: Due to the wide range of oscillator start-up
Sample Clock Clock times, the Fail-Safe circuit is not active
Failure during oscillator start-up (i.e., after exiting
Detected Reset or Sleep). After an appropriate
amount of time, the user should check the
OSTS bit of the OSCCON register to verify
3.8.1 FAIL-SAFE DETECTION the oscillator start-up and that the system
The FSCM module detects a failed oscillator by clock switchover has successfully
comparing the external oscillator to the FSCM sample completed.
clock. The sample clock is generated by dividing the
LFINTOSC by 64. See Figure 3-8. Inside the fail
detector block is a latch. The external clock sets the
latch on each falling edge of the external clock. The
sample clock clears the latch on each rising edge of the
sample clock. A failure is detected when an entire half-
cycle of the sample clock elapses before the primary
clock goes low.
3.8.2 FAIL-SAFE OPERATION

When the external clock fails, the FSCM switches the
device clock to an internal clock source and sets the bit
flag OSFIF of the PIR2 register. Setting this flag will
generate an interrupt if the OSFIE bit of the PIE2
register is also set. The device firmware can then take
steps to mitigate the problems that may arise from a
failed clock. The system clock will continue to be
sourced from the internal clock source until the device
firmware successfully restarts the external oscillator
and switches back to external operation.
The internal clock source chosen by the FSCM is
determined by the IRCF<2:0> bits of the OSCCON
register. This allows the internal oscillator to be
configured before a failure occurs.

PIC16F688
FIGURE 3-9: FSCM TIMING DIAGRAM
Sample Clock
System Oscillator
Clock Failure
Output
Clock Monitor Output

(Q)
Failure
Detected
OSCFIF
Test Test Test
Note: The system clock is normally at a much higher frequency than the sample clock. The relative frequencies in
this example have been chosen for clarity.
TABLE 3-2: SUMMARY OF REGISTERS ASSOCIATED WITH CLOCK SOURCES

Value on
Value on
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other
POR, BOR
Resets(1)
CONFIG(2) CPD CP MCLRE PWRTE WDTE FOSC2 FOSC1 FOSC0 — —

INTCON GIE PEIE T0IE INTE RAIE T0IF INTF RAIF 0000 000x 0000 000x
OSCCON — IRCF2 IRCF1 IRCF0 OSTS HTS LTS SCS -110 x000 -110 x000
OSCTUNE — — — TUN4 TUN3 TUN2 TUN1 TUN0 ---0 0000 ---u uuuu
PIE1 EEIE ADIE RCIE C2IE C1IE OSFIE TXIE TMR1IE 0000 0000 0000 0000
PIR1 EEIF ADIF RCIF C2IF C1IF OSFIF TXIF TMR1IF 0000 0000 0000 0000
Legend: x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by oscillators.
2: See Configuration Word register (CONFIG) for operation of all register bits.

PIC16F688
4.0 I/O PORTS Therefore, a write to a port implies that the port pins are
read, this value is modified and then written to the
There are as many as twelve general purpose I/O pins PORT data latch. RA3 reads ‘0’ when MCLRE = 1.
available. Depending on which peripherals are enabled,
The TRISA register controls the direction of the
some or all of the pins may not be available as general
PORTA pins, even when they are being used as
purpose I/O. In general, when a peripheral is enabled,
analog inputs. The user must ensure the bits in the
the associated pin may not be used as a general
TRISA register are maintained set when using them as
purpose I/O pin.
analog inputs. I/O pins configured as analog input
always read ‘0’.
4.1 PORTA and the TRISA Registers
Note: The ANSEL and CMCON0 registers must
PORTA is a 6-bit wide, bidirectional port. The be initialized to configure an analog
corresponding data direction register is TRISA. Setting channel as a digital input. Pins configured
a TRISA bit (= 1) will make the corresponding PORTA as analog inputs will read ‘0’.
pin an input (i.e., put the corresponding output driver in
a High-Impedance mode). Clearing a TRISA bit (= 0)
EXAMPLE 4-1: INITIALIZING PORTA
will make the corresponding PORTA pin an output (i.e.,
BANKSEL PORTA ;
put the contents of the output latch on the selected pin).
CLRF PORTA ;Init PORTA
The exception is RA3, which is input only and its TRISA MOVLW 07h ;Set RA<2:0> to
bit will always read as ‘1’. Example 4-1 shows how to MOVWF CMCON0 ;digital I/O
initialize PORTA. BANKSEL ANSEL ;
Reading the PORTA register reads the status of the CLRF ANSEL ;digital I/O
MOVLW 0Ch ;Set RA<3:2> as inputs
pins, whereas writing to it will write to the PORT latch.
MOVWF TRISA ;and set RA<5:4,1:0>
All write operations are read-modify-write operations.
;as outputs
REGISTER 4-1: PORTA: PORTA REGISTER

U-0 U-0 R/W-x R/W-0 R-x R/W-0 R/W-0 R/W-0
— — RA5 RA4 RA3 RA2 RA1 RA0
bit 7 bit 0
Legend:

bit 5-0 RA<5:0>: PORTA I/O Pin bit
1 = Port pin is > VIH
0 = Port pin is < VIL
REGISTER 4-2: TRISA: PORTA TRI-STATE REGISTER

U-0 U-0 R/W-1 R/W-1 R-1 R/W-1 R/W-1 R/W-1
— — TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0
bit 7 bit 0
Legend:

bit 5-0 TRISA<5:0>: PORTA Tri-State Control bits
1 = PORTA pin configured as an input (tri-stated)
0 = PORTA pin configured as an output
Note 1: TRISA<3> always reads ‘1’.
2: TRISA<5:4> always reads ‘1’ in XT, HS and LP Oscillator modes.

PIC16F688
4.2 Additional Pin Functions 4.2.3 INTERRUPT-ON-CHANGE
Every PORTA pin on the PIC16F688 has an interrupt- Each of the PORTA pins is individually configurable as
on-change option and a weak pull-up option. PORTA an interrupt-on-change pin. Control bits IOCAx enable
also provides an Ultra Low-Power Wake-up option. The or disable the interrupt function for each pin. Refer to
next three sections describe these functions. Register 4-5. The interrupt-on-change is disabled on a
Power-on Reset.
4.2.1 ANSEL REGISTER For enabled interrupt-on-change pins, the values are
The ANSEL register is used to configure the Input compared with the old value latched on the last read of
mode of an I/O pin to analog. Refer to Register 4-3. PORTA. The ‘mismatch’ outputs of the last read are
Setting the appropriate ANSEL bit high will cause all OR’d together to set the PORTA Change Interrupt Flag
digital reads on the pin to be read as ‘0’ and allow bit (RAIF) in the INTCON register.
analog functions on the pin to operate correctly. This interrupt can wake the device from Sleep. The user,
The state of the ANSEL bits has no affect on digital in the Interrupt Service Routine, clears the interrupt by:
output functions. A pin with TRIS clear and ANSEL set a) Any read or write of PORTA. This will end the
will still operate as a digital output, but the Input mode mismatch condition, then
will be analog. This can cause unexpected behavior b) Clear the flag bit RAIF.
when executing read-modify-write instructions on the
affected port. A mismatch condition will continue to set flag bit RAIF.
Reading PORTA will end the mismatch condition and
4.2.2 WEAK PULL-UPS allow flag bit RAIF to be cleared. The latch holding the
last read value is not affected by a MCLR nor BOR
Each of the PORTA pins, except RA3, has an
Reset. After these Resets, the RAIF flag will continue
individually configurable internal weak pull-up. Control
to be set if a mismatch is present.
bits WPUAx enable or disable each pull-up. Refer to
Register 4-4. Each weak pull-up is automatically turned Note: If a change on the I/O pin should occur
off when the port pin is configured as an output. The when the read operation is being executed
pull-ups are disabled on a Power-on Reset by the (start of the Q2 cycle), then the RAIF
RAPU bit of the OPTION register. A weak pull-up is interrupt flag may not get set.
automatically enabled for RA3 when configured as
MCLR and disabled when RA3 is an I/O. There is no
software control of the MCLR pull-up.
REGISTER 4-3: ANSEL: ANALOG SELECT REGISTER

ANS7 ANS6 ANS5 ANS4 ANS3 ANS2 ANS1 ANS0
bit 7 bit 0
Legend:
bit 7-0 ANS<7:0>: Analog Select bits

Analog select between analog or digital function on pins AN<7:0>, respectively.
1 = Analog input. Pin is assigned as analog input(1).
0 = Digital I/O. Pin is assigned to port or special function.
Note 1: Setting a pin to an analog input automatically disables the digital input circuitry, weak pull-ups and
interrupt-on-change, if available. The corresponding TRIS bit must be set to Input mode in order to allow
external control of the voltage on the pin.

PIC16F688
REGISTER 4-4: WPUA: WEAK PULL-UP PORTA REGISTER

U-0 U-0 R/W-1 R/W-1 U-0 R/W-1 R/W-1 R/W-1
— — WPUA5 WPUA4 — WPUA2 WPUA1 WPUA0
bit 7 bit 0
Legend:

bit 5-4 WPUA<5:4>: Weak Pull-up Control bits
1 = Pull-up enabled
0 = Pull-up disabled
bit 2-0 WPUA<2:0>: Weak Pull-up Control bits
1 = Pull-up enabled
0 = Pull-up disabled
Note 1: Global RAPU must be enabled for individual pull-ups to be enabled.

2: The weak pull-up device is automatically disabled if the pin is in Output mode (TRISA = 0).
3: The RA3 pull-up is enabled when configured as MCLR and disabled as an I/O in the Configuration Word.
4: WPUA<5:4> always reads ‘1’ in XT, HS and LP OSC modes.
REGISTER 4-5: IOCA: INTERRUPT-ON-CHANGE PORTA REGISTER

U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — IOCA5 IOCA4 IOCA3 IOCA2 IOCA1 IOCA0
bit 7 bit 0
Legend:

bit 5-0 IOCA<5:0>: Interrupt-on-change PORTA Control bits
1 = Interrupt-on-change enabled
0 = Interrupt-on-change disabled
Note 1: Global Interrupt Enable (GIE) must be enabled for individual interrupts to be recognized.
2: IOCA<5:4> always reads ‘1’ in XT, HS and LP OSC modes.

PIC16F688
4.2.4 ULTRA LOW-POWER WAKE-UP EXAMPLE 4-2: ULTRA LOW-POWER
The Ultra Low-Power Wake-up (ULPWU) on RA0 WAKE-UP INITIALIZATION
allows a slow falling voltage to generate an interrupt- BANKSEL PORTA ;
on-change on RA0 without excess current consump- BSF PORTA,0 ;Set RA0 data latch
tion. The mode is selected by setting the ULPWUE bit MOVLW H’7’ ;Turn off
of the PCON register. This enables a small current sink MOVWF CMCON0 ; comparators
which can be used to discharge a capacitor on RA0. BANKSEL ANSEL ;
BCF ANSEL,0 ;RA0 to digital I/O
To use this feature, the RA0 pin is configured to output BANKSEL TRISA ;
‘1’ to charge the capacitor, interrupt-on-change for RA0 BCF TRISA,0 ;Output high to
is enabled, and RA0 is configured as an input. The CALL CapDelay ; charge capacitor
ULPWUE bit is set to begin the discharge and a SLEEP BSF PCON,ULPWUE ;Enable ULP Wake-up
instruction is performed. When the voltage on RA0 BSF IOCA,0 ;Select RA0 IOC
drops below VIL, an interrupt will be generated which BSF TRISA,0 ;RA0 to input
MOVLW B’10001000’ ;Enable interrupt
will cause the device to wake-up. Depending on the
MOVWF INTCON ; and clear flag
state of the GIE bit of the INTCON register, the device
SLEEP ;Wait for IOC
will either jump to the interrupt vector (0004h) or NOP ;
execute the next instruction when the interrupt event
occurs. See Section 4.2.3 “INTERRUPT-ON-
CHANGE” and Section 11.3.3 “PORTA Interrupt” for
more information.
This feature provides a low-power technique for
periodically waking up the device from Sleep. The
time-out is dependent on the discharge time of the RC
circuit on RA0. See Example 4-2 for initializing the
Ultra Low-Power Wake-up module.
The series resistor provides overcurrent protection for
the RA0 pin and can allow for software calibration of the
time-out. (see Figure 4-1). A timer can be used to
measure the charge time and discharge time of the
capacitor. The charge time can then be adjusted to
provide the desired interrupt delay. This technique will
compensate for the affects of temperature, voltage and
component accuracy. The Ultra Low-Power Wake-up
peripheral can also be configured as a simple
programmable low voltage detect or temperature sensor.
Note: For more information, refer to Application
Note AN879, “Using the Microchip Ultra
Low-Power Wake-up Module”
(DS00879).

PIC16F688
4.2.5 PIN DESCRIPTIONS AND 4.2.5.1 RA0/AN0/C1IN+/ICSPDAT/ULPWU
DIAGRAMS Figure 4-1 shows the diagram for this pin. The RA0 pin
Each PORTA pin is multiplexed with other functions. is configurable to function as one of the following:
The pins and their combined functions are briefly • a general purpose I/O
described here. For specific information about individ-
• an analog input for the A/D
ual functions such as the comparator or the A/D, refer
to the appropriate section in this data sheet. • an analog input to the comparator
• an analog input to the Ultra Low-Power Wake-up
• In-Circuit Serial Programming™ data
FIGURE 4-1: BLOCK DIAGRAM OF RA0

Analog(1)
Input Mode
VDD
Data Bus
D Q Weak
WR CK Q
WPUDA RAPU
RD
WPUDA VDD
D Q
WR CK Q I/O PIN
PORTA
VSS
-
+ VT
D Q
WR CK Q
TRISA IULP
0 1
RD
TRISA Analog(1) Vss
Input Mode
ULPWUE
RD
PORTA
D Q
CK Q Q D
WR
IOCA
EN Q3
RD
IOCA Q D
EN
Interrupt-on-
Change
RD PORTA
To Comparator
To A/D Converter
Note 1: Comparator mode and ANSEL determines analog Input mode.

PIC16F688
4.2.5.2 RA1/AN1/C1IN-/VREF/ICSPCLK 4.2.5.3 RA2/AN2/T0CKI/INT/C1OUT
Figure 4-2 shows the diagram for this pin. The RA1 pin Figure 4-3 shows the diagram for this pin. The RA2 pin
is configurable to function as one of the following: is configurable to function as one of the following:
• a general purpose I/O • a general purpose I/O
• an analog input for the A/D • an analog input for the A/D
• an analog input to the comparator • the clock input for Timer0
• a voltage reference input for the A/D • an external edge triggered interrupt
• In-Circuit Serial Programming™ clock • a digital output from the comparator
FIGURE 4-2: BLOCK DIAGRAM OF RA1 FIGURE 4-3: BLOCK DIAGRAM OF RA2
Analog(1) Analog(1)
Data Bus Input Mode Data Bus Input Mode
D Q D Q VDD
VDD
WR WR CK
CK Q Q Weak
WPUA Weak WPUA
RD RAPU RD RAPU
WPUA WPUA
C1OUT
Enable
VDD VDD
D Q D Q
WR CK Q WR CK
PORTA Q C1OUT 1
PORTA
0 I/O pin
I/O pin
D Q D Q
WR CK Q WR CK
TRISA VSS TRISA Q VSS
(1)
Analog Analog(1)
RD Input Mode RD Input Mode
TRISA TRISA
RD RD
PORTA PORTA
D Q D Q
WR CK Q Q D Q D
WR CK Q
IOCA IOCA
EN Q3 EN Q3
RD RD
IOCA Q D IOCA Q D
EN EN
Interrupt-on- Interrupt-on-
change change
RD PORTA RD PORTA
To Comparator
To Timer0
To A/D Converter
To INT
To A/D Converter
Note 1: Comparator mode and ANSEL determines analog
Input mode.
Note 1: Analog Input mode is based upon ANSEL.

PIC16F688
4.2.5.4 RA3/MCLR/VPP 4.2.5.5 RA4/AN3/T1G/OSC2/CLKOUT
Figure 4-4 shows the diagram for this pin. The RA3 pin Figure 4-5 shows the diagram for this pin. The RA4 pin
is configurable to function as one of the following: is configurable to function as one of the following:
• a general purpose input • a general purpose I/O
• as Master Clear Reset with weak pull-up • an analog input for the A/D
• a Timer1 gate input
FIGURE 4-4: BLOCK DIAGRAM OF RA3 • a crystal/resonator connection
• a clock output
VDD
MCLRE Weak FIGURE 4-5: BLOCK DIAGRAM OF RA4
Data Bus MCLRE Analog(3)

Reset Input Input Mode
CLK(1)
pin Data Bus Modes
RD VSS D Q
TRISA VDD
MCLRE VSS WR CK
RD WPUA Q Weak
PORTA
D Q RAPU
RD
Q D WPUA
WR CK Oscillator
Q Circuit
IOCA
Q3 OSC1
EN
CLKOUT VDD
RD Enable
IOCA Q D
Fosc/4 1
D Q
EN
Interrupt-on- 0 I/O pin
change WR CK
PORTA Q
CLKOUT
RD PORTA Enable
VSS
D Q
INTOSC/
WR CK RC/EC(2)
TRISA Q
CLKOUT
RD Enable
TRISA Analog(3)
Input Mode
RD
PORTA
D Q
CK Q D
WR Q
IOCA
EN Q3
RD
IOCA Q D
EN
Interrupt-on-
change
RD PORTA
To T1G
To A/D Converter
Note 1: CLK modes are XT, HS, LP, LPTMR1 and CLKOUT
Enable.
2: With CLKOUT option.
3: Analog Input mode is ANSEL.

PIC16F688
4.2.5.6 RA5/T1CKI/OSC1/CLKIN FIGURE 4-6: BLOCK DIAGRAM OF RA5
Figure 4-6 shows the diagram for this pin. The RA5 pin INTOSC
is configurable to function as one of the following: Mode
TMR1LPEN(1)
• a general purpose I/O Data Bus
D Q VDD
• a Timer1 clock input
WR CK Weak
• a crystal/resonator connection WPUA Q
• a clock input RAPU

RD
WPUA
Oscillator
Circuit
OSC2 VDD
D Q
WR CK
PORTA Q
D Q I/O pin
WR CK
TRISA Q VSS
INTOSC
RD Mode
TRISA
RD
(2)
PORTA
D Q
CK Q D
WR Q
IOCA
EN Q3
RD
IOCA
Q D
EN
Interrupt-on-
change
RD PORTA
To Timer1 or CLKGEN
Note 1: Timer1 LP oscillator enabled.

2: When using Timer1 with LP oscillator, the
Schmitt Trigger is bypassed.

PIC16F688
TABLE 4-1: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
Value on
Value on
POR, BOR
Resets
ANSEL ANS7 ANS6 ANS5 ANS4 ANS3 ANS2 ANS1 ANS0 1111 1111 1111 1111
CMCON0 C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 0000 0000 0000 0000
PCON — — ULPWUE SBOREN — — POR BOR --01 --qq --0u --uu
IOCA — — IOCA5 IOCA4 IOCA3 IOCA2 IOCA1 IOCA0 --00 0000 --00 0000
OPTION_REG RAPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111
PORTA — — RA5 RA4 RA3 RA2 RA1 RA0 --x0 x000 --x0 x000
TRISA — — TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 --11 1111 --11 1111
WPUA — — WPUA5 WPUA4 — WPUA2 WPUA1 WPUA0 --11 -111 --11 -111
Legend: x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by PORTA.

PIC16F688
4.3 PORTC EXAMPLE 4-3: INITIALIZING PORTC
BANKSEL PORTC ;
PORTC is a general purpose I/O port consisting of 6
CLRF PORTC ;Init PORTC
bidirectional pins. The pins can be configured for either
MOVLW 07h ;Set RC<4,1:0> to
digital I/O or analog input to A/D converter or compara- MOVWF CMCON0 ;digital I/O
tor. For specific information about individual functions BANKSEL ANSEL ;
such as the EUSART or the A/D converter, refer to the CLRF ANSEL ;digital I/O
appropriate section in this data sheet. MOVLW 0Ch ;Set RC<3:2> as inputs
MOVWF TRISC ;and set RC<5:4,1:0>
Note: The ANSEL and CMCON0 registers must ;as outputs
be initialized to configure an analog
channel as a digital input. Pins configured
as analog inputs will read ‘0’.
REGISTER 4-6: PORTC: PORTC REGISTER

U-0 U-0 R/W-x R/W-x R/W-0 R/W-0 R/W-0 R/W-0
— — RC5 RC4 RC3 RC2 RC1 RC0
bit 7 bit 0
Legend:

bit 5-0 RC<5:0>: PORTC I/O Pin bit
1 = PORTC pin is > VIH
0 = PORTC pin is < VIL
REGISTER 4-7: TRISC: PORTC TRI-STATE REGISTER

U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
— — TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0
bit 7 bit 0
Legend:

bit 5-0 TRISC<5:0>: PORTC Tri-State Control bits
1 = PORTC pin configured as an input (tri-stated)
0 = PORTC pin configured as an output

PIC16F688
4.3.1 RC0/AN4/C2IN+ 4.3.3 RC2/AN6
Figure 4-7 shows the diagram for this pin. The RC0 is Figure 4-8 shows the diagram for this pin. The RC2 is
configurable to function as one of the following: configurable to function as one of the following:
• an analog input for the A/D Converter • an analog input for the A/D Converter
• an analog input to the comparator
4.3.4 RC3/AN7
4.3.2 RC1/AN5/C2IN- Figure 4-8 shows the diagram for this pin. The RC3 is
Figure 4-7 shows the diagram for this pin. The RC1 is configurable to function as one of the following:
configurable to function as one of the following: • a general purpose I/O
• a general purpose I/O • an analog input for the A/D Converter
• an analog input for the A/D Converter
• an analog input to the comparator FIGURE 4-8: BLOCK DIAGRAM OF RC2
AND RC3
FIGURE 4-7: BLOCK DIAGRAM OF RC0 Data Bus
AND RC1
Data Bus VDD
D Q
WR CK
VDD PORTC Q
D Q
WR CK I/O Pin
PORTC Q
D Q
WR CK
I/O Pin Q
TRISC VSS
D Q Analog Input
WR Mode(1)
CK RD
TRISC Q VSS TRISC
Analog Input
Mode(1) RD
RD
TRISC PORTC
To A/D Converter
RD
PORTC
To Comparators Note 1: Analog Input mode comes from ANSEL.
To A/D Converter
Note 1: Analog Input mode is based upon Comparator mode

and ANSEL.

PIC16F688
4.3.5 RC4/C2OUT/TX/CK 4.3.6 RC5/RX/DT
Figure 4-9 shows the diagram for this pin. The RC4 is The RC5 is configurable to function as one of the
configurable to function as one of the following: following:
• a digital output from the comparator • a digital I/O for the EUSART
• a digital I/O for the EUSART
FIGURE 4-10: BLOCK DIAGRAM OF RC5
FIGURE 4-9: BLOCK DIAGRAM OF RC4 PIN
Data Bus
USART Select(1) EUSART Out
C2OUT EN Enable
VDD
D Q
WR CK
VDD PORTC Q EUSART 1
EUSART DT Out
TX/CLKOUT 0 0 I/O Pin
Data Bus 0
C2OUT 1 D Q
1
WR CK
D Q I/O Pin Q VSS
TRISC
WR CK Q
PORTC VSS RD
TRISC
D Q RD
WR PORTC
CK Q
TRISC
To EUSART RX/DT In
RD
TRISC
RD
PORTC
To EUSART CLK Input
Note 1: USART Select signals selects between port

data and peripheral output.
TABLE 4-2: SUMMARY OF REGISTERS ASSOCIATED WITH PORTC

Value on
Value on
POR, BOR
Resets
PORTC — — RC5 RC4 RC3 RC2 RC1 RC0 --xx 0000 --xx 0000
TRISC — — TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 --11 1111 --11 1111
Legend: x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by PORTC.

PIC16F688
5.0 TIMER0 MODULE 5.1 Timer0 Operation
The Timer0 module is an 8-bit timer/counter with the When used as a timer, the Timer0 module can be used
following features: as either an 8-bit timer or an 8-bit counter.
• 8-bit timer/counter register (TMR0)
5.1.1 8-BIT TIMER MODE
• 8-bit prescaler (shared with Watchdog Timer)
When used as a timer, the Timer0 module will
• Programmable internal or external clock source
increment every instruction cycle (without prescaler).
• Programmable external clock edge selection Timer mode is selected by clearing the T0CS bit of the
• Interrupt on overflow OPTION register to ‘0’.
Figure 5-1 is a block diagram of the Timer0 module. When TMR0 is written, the increment is inhibited for
two instruction cycles immediately following the write.
Note: The value written to the TMR0 register can
be adjusted, in order to account for the two
instruction cycle delay when TMR0 is
written.
5.1.2 8-BIT COUNTER MODE

When used as a counter, the Timer0 module will
increment on every rising or falling edge of the T0CKI
pin. The incrementing edge is determined by the T0SE
bit of the OPTION register. Counter mode is selected by
setting the T0CS bit of the OPTION register to ‘1’.
FIGURE 5-1: BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER
FOSC/4
Data Bus
0
8
1
Sync
1 2 Tcy TMR0
T0CKI 0
pin 0
T0SE T0CS Set Flag bit T0IF
8-bit
on Overflow
Prescaler PSA
1
8
WDTE PSA
SWDTEN
PS<2:0> 1
WDT
16-bit Time-out
Prescaler 0
16
31 kHz Watchdog
INTOSC Timer PSA
WDTPS<3:0>
Note 1: T0SE, T0CS, PSA, PS<2:0> are bits in the OPTION register.
2: SWDTEN and WDTPS<3:0> are bits in the WDTCON register.
3: WDTE bit is in the Configuration Word register.

PIC16F688
5.1.3 SOFTWARE PROGRAMMABLE When changing the prescaler assignment from the
PRESCALER WDT to the Timer0 module, the following instruction
sequence must be executed (see Example 5-2).
A single software programmable prescaler is available
for use with either Timer0 or the Watchdog Timer
(WDT), but not both simultaneously. The prescaler EXAMPLE 5-2: CHANGING PRESCALER
assignment is controlled by the PSA bit of the OPTION (WDT → TIMER0)
register. To assign the prescaler to Timer0, the PSA bit CLRWDT ;Clear WDT and
must be cleared to a ‘0’. ;prescaler
BANKSEL OPTION_REG ;
There are 8 prescaler options for the Timer0 module MOVLW b’11110000’ ;Mask TMR0 select and
ranging from 1:2 to 1:256. The prescale values are ANDWF OPTION_REG,W ;prescaler bits
selectable via the PS<2:0> bits of the OPTION register. IORLW b’00000011’ ;Set prescale to 1:16
In order to have a 1:1 prescaler value for the Timer0 MOVWF OPTION_REG ;
module, the prescaler must be assigned to the WDT
module.
5.1.4 TIMER0 INTERRUPT
The prescaler is not readable or writable. When
assigned to the Timer0 module, all instructions writing to Timer0 will generate an interrupt when the TMR0
the TMR0 register will clear the prescaler. register overflows from FFh to 00h. The T0IF interrupt
flag bit of the INTCON register is set every time the
When the prescaler is assigned to WDT, a CLRWDT TMR0 register overflows, regardless of whether or not
instruction will clear the prescaler along with the WDT. the Timer0 interrupt is enabled. The T0IF bit must be
cleared in software. The Timer0 interrupt enable is the
5.1.3.1 Switching Prescaler Between T0IE bit of the INTCON register.
Timer0 and WDT Modules
Note: The Timer0 interrupt cannot wake the
As a result of having the prescaler assigned to either
processor from Sleep since the timer is
Timer0 or the WDT, it is possible to generate an
frozen during Sleep.
unintended device Reset when switching prescaler
values. When changing the prescaler assignment from
5.1.5 USING TIMER0 WITH AN
Timer0 to the WDT module, the instruction sequence
EXTERNAL CLOCK
shown in Example 5-1, must be executed.
When Timer0 is in Counter mode, the synchronization
EXAMPLE 5-1: CHANGING PRESCALER of the T0CKI input and the Timer0 register is accom-
(TIMER0 → WDT) plished by sampling the prescaler output on the Q2 and
Q4 cycles of the internal phase clocks. Therefore, the
BANKSEL TMR0 ; high and low periods of the external clock source must
CLRWDT ;Clear WDT
meet the timing requirements as shown in
CLRF TMR0 ;Clear TMR0 and
Section 14.0 “Electrical Specifications”.
;prescaler
BANKSEL OPTION_REG ;
BSF OPTION_REG,PSA ;Select WDT
CLRWDT ;
;
MOVLW b’11111000’ ;Mask prescaler
ANDWF OPTION_REG,W ;bits
IORLW b’00000101’ ;Set WDT prescaler
MOVWF OPTION_REG ;to 1:32

PIC16F688
REGISTER 5-1: OPTION_REG: OPTION REGISTER

RAPU INTEDG T0CS T0SE PSA PS2 PS1 PS0
bit 7 bit 0
Legend:
bit 7 RAPU: PORTA Pull-up Enable bit

1 = PORTA pull-ups are disabled
0 = PORTA pull-ups are enabled by individual PORT latch values
bit 6 INTEDG: Interrupt Edge Select bit
1 = Interrupt on rising edge of INT pin
0 = Interrupt on falling edge of INT pin
bit 5 T0CS: TMR0 Clock Source Select bit
1 = Transition on T0CKI pin
0 = Internal instruction cycle clock (FOSC/4)
bit 4 T0SE: TMR0 Source Edge Select bit
1 = Increment on high-to-low transition on T0CKI pin
0 = Increment on low-to-high transition on T0CKI pin
bit 3 PSA: Prescaler Assignment bit
1 = Prescaler is assigned to the WDT
0 = Prescaler is assigned to the Timer0 module
bit 2-0 PS<2:0>: Prescaler Rate Select bits
BIT VALUE TMR0 RATE WDT RATE
000 1:2 1:1

001 1:4 1:2
010 1:8 1:4
011 1 : 16 1:8
100 1 : 32 1 : 16
101 1 : 64 1 : 32
110 1 : 128 1 : 64
111 1 : 256 1 : 128
Note 1: A dedicated 16-bit WDT postscaler is available. See Section 11.5 “Watchdog Timer (WDT)” for more
information.
TABLE 5-1: SUMMARY OF REGISTERS ASSOCIATED WITH TIMER0

Value on
Value on
POR, BOR
Resets
TMR0 Timer0 Module Register xxxx xxxx uuuu uuuu
Legend: – = Unimplemented locations, read as ‘0’, u = unchanged, x = unknown. Shaded cells are not used by the
Timer0 module.

PIC16F688
6.0 TIMER1 MODULE WITH GATE 6.1 Timer1 Operation
CONTROL The Timer1 module is a 16-bit incrementing counter
The Timer1 module is a 16-bit timer/counter with the which is accessed through the TMR1H:TMR1L register
following features: pair. Writes to TMR1H or TMR1L directly update the
counter.
• 16-bit timer/counter register pair (TMR1H:TMR1L)
When used with an internal clock source, the module is
• Programmable internal or external clock source
a timer. When used with an external clock source, the
• 3-bit prescaler module can be used as either a timer or counter.
• Optional LP oscillator
• Synchronous or asynchronous operation 6.2 Clock Source Selection
• Timer1 gate (count enable) via comparator or
The TMR1CS bit of the T1CON register is used to select
T1G pin
the clock source. When TMR1CS = 0, the clock source
• Interrupt on overflow is FOSC/4. When TMR1CS = 1, the clock source is
• Wake-up on overflow (external clock, supplied externally.
Asynchronous mode only)
Clock Source TMR1CS Clock Source
Figure 6-1 is a block diagram of the Timer1 module.
FOSC/4 0 FOSC/4
T1CKI pin 1 T1CKI pin
FIGURE 6-1: TIMER1 BLOCK DIAGRAM
TMR1GE
T1GINV
TMR1ON
Set flag bit
TMR1IF on To C2 Comparator Module
Overflow Timer1 Clock
TMR1(2)
Synchronized
EN 0 clock input
TMR1H TMR1L
1
Oscillator
(1) T1SYNC
OSC1/T1CKI 1
Prescaler Synchronize(3)
FOSC/4 1, 2, 4, 8 det
Internal 0
OSC2/T1G Clock 2
T1CKPS<1:0>
TMR1CS
1
INTOSC
Without CLKOUT
C2OUT 0
T1OSCEN
T1GSS
Note 1: ST Buffer is low power type when using LP oscillator, or high speed type when using T1CKI.
2: Timer1 register increments on rising edge.
3: Synchronize does not operate while in Sleep.

PIC16F688
6.2.1 INTERNAL CLOCK SOURCE 6.5 Timer1 Operation in
When the internal clock source is selected the Asynchronous Counter Mode
TMR1H:TMR1L register pair will increment on multiples
If control bit T1SYNC of the T1CON register is set, the
of TCY as determined by the Timer1 prescaler.
external clock input is not synchronized. The timer
continues to increment asynchronous to the internal
6.2.2 EXTERNAL CLOCK SOURCE
phase clocks. The timer will continue to run during
When the external clock source is selected, the Timer1 Sleep and can generate an interrupt on overflow,
module may work as a timer or a counter. which will wake-up the processor. However, special
When counting, Timer1 is incremented on the rising precautions in software are needed to read/write the
edge of the external clock input T1CKI. In addition, the timer (see Section 6.5.1 “Reading and Writing
Counter mode clock can be synchronized to the Timer1 in Asynchronous Counter Mode”).
microcontroller system clock or run asynchronously. Note: When switching from synchronous to
If an external clock oscillator is needed (and the asynchronous operation, it is possible to
microcontroller is using the INTOSC without CLKOUT), skip an increment. When switching from
Timer1 can use the LP oscillator as a clock source. asynchronous to synchronous operation,
it is possible to produce a single spurious
Note: In Counter mode, a falling edge must be
increment.
registered by the counter prior to the first
incrementing rising edge.
6.5.1 READING AND WRITING TIMER1 IN
ASYNCHRONOUS COUNTER
6.3 Timer1 Prescaler MODE
Timer1 has four prescaler options allowing 1, 2, 4 or 8 Reading TMR1H or TMR1L while the timer is running
divisions of the clock input. The T1CKPS bits of the from an external asynchronous clock will ensure a valid
T1CON register control the prescale counter. The read (taken care of in hardware). However, the user
prescale counter is not directly readable or writable; should keep in mind that reading the 16-bit timer in two
however, the prescaler counter is cleared upon a write to 8-bit values itself, poses certain problems, since the
TMR1H or TMR1L. timer may overflow between the reads.
For writes, it is recommended that the user simply stop
6.4 Timer1 Oscillator the timer and write the desired values. A write
A low-power 32.768 kHz crystal oscillator is built-in contention may occur by writing to the timer registers,
between pins OSC1 (input) and OSC2 (amplifier while the register is incrementing. This may produce an
output). The oscillator is enabled by setting the unpredictable value in the TMR1H:TTMR1L register
T1OSCEN control bit of the T1CON register. The pair.
oscillator will continue to run during Sleep.
6.6 Timer1 Gate
The Timer1 oscillator is shared with the system LP
oscillator. Thus, Timer1 can use this mode only when Timer1 gate source is software configurable to be the
the primary system clock is derived from the internal T1G pin or the output of Comparator 2. This allows the
oscillator or when in LP oscillator mode. The user must device to directly time external events using T1G or
provide a software time delay to ensure proper oscilla- analog events using Comparator 2. See the CMCON1
tor start-up. register (Register 7-2) for selecting the Timer1 gate
TRISA5 and TRISA4 bits are set when the Timer1 source. This feature can simplify the software for a
oscillator is enabled. RA5 and RA4 bits read as ‘0’ and Delta-Sigma A/D converter and many other applications.
TRISA5 and TRISA4 bits read as ‘1’. For more information on Delta-Sigma A/D converters,
see the Microchip web site (www.microchip.com).
Note: The oscillator requires a start-up and
stabilization time before use. Thus, Note: TMR1GE bit of the T1CON register must
T1OSCEN should be set and a suitable be set to use either T1G or C2OUT as the
delay observed prior to enabling Timer1. Timer1 gate source. See Register 7-2 for
more information on selecting the Timer1
gate source.
Timer1 gate can be inverted using the T1GINV bit of
the T1CON register, whether it originates from the T1G
pin or Comparator 2 output. This configures Timer1 to
measure either the active-high or active-low time
between events.

PIC16F688
6.7 Timer1 Interrupt 6.8 Timer1 Operation During Sleep
The Timer1 register pair (TMR1H:TMR1L) increments Timer1 can only operate during Sleep when setup in
to FFFFh and rolls over to 0000h. When Timer1 rolls Asynchronous Counter mode. In this mode, an external
over, the Timer1 interrupt flag bit of the PIR1 register is crystal or clock source can be used to increment the
set. To enable the interrupt on rollover, you must set counter. To set up the timer to wake the device:
these bits: • TMR1ON bit of the T1CON register must be set
• Timer1 interrupt enable bit of the PIE1 register • TMR1IE bit of the PIE1 register must be set
• PEIE bit of the INTCON register • PEIE bit of the INTCON register must be set
• GIE bit of the INTCON register The device will wake-up on an overflow and execute
The interrupt is cleared by clearing the TMR1IF bit in the next instruction. If the GIE bit of the INTCON
the Interrupt Service Routine. register is set, the device will call the Interrupt Service
Routine (0004h).
Note: The TMR1H:TTMR1L register pair and the
TMR1IF bit should be cleared before
enabling interrupts.
FIGURE 6-2: TIMER1 INCREMENTING EDGE
T1CKI = 1
when TMR1
Enabled
T1CKI = 0
when TMR1
Enabled
Note 1: Arrows indicate counter increments.

2: In Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge of
the clock.

PIC16F688
6.9 Timer1 Control Register
The Timer1 Control register (T1CON), shown in
Register 6-1, is used to control Timer1 and select the
various features of the Timer1 module.
REGISTER 6-1: T1CON: TIMER 1 CONTROL REGISTER

(1) (2)
T1GINV TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON
bit 7 bit 0
Legend:
bit 7 T1GINV: Timer1 Gate Invert bit(1)

1 = Timer1 gate is active high (Timer1 counts when gate is high)
0 = Timer1 gate is active low (Timer1 counts when gate is low)
bit 6 TMR1GE: Timer1 Gate Enable bit(2)
If TMR1ON = 0:
This bit is ignored
If TMR1ON = 1:
1 = Timer1 is on if Timer1 gate is active
0 = Timer1 is on
bit 5-4 T1CKPS<1:0>: Timer1 Input Clock Prescale Select bits
11 = 1:8 Prescale Value
bit 3 T1OSCEN: LP Oscillator Enable Control bit
If INTOSC without CLKOUT oscillator is active:
1 = LP oscillator is enabled for Timer1 clock
0 = LP oscillator is off
Else:
This bit is ignored. LP oscillator is disabled.
bit 2 T1SYNC: Timer1 External Clock Input Synchronization Control bit
TMR1CS = 1:
1 = Do not synchronize external clock input
0 = Synchronize external clock input
TMR1CS = 0:
This bit is ignored. Timer1 uses the internal clock
bit 1 TMR1CS: Timer1 Clock Source Select bit
1 = External clock from T1CKI pin (on the rising edge)
0 = Internal clock (FOSC/4)
bit 0 TMR1ON: Timer1 On bit
1 = Enables Timer1
0 = Stops Timer1
Note 1: T1GINV bit inverts the Timer1 gate logic, regardless of source.
2: TMR1GE bit must be set to use either T1G pin or C2OUT, as selected by the T1GSS bit of the CM2CON1
register, as a Timer1 gate source.

PIC16F688
TABLE 6-1: SUMMARY OF REGISTERS ASSOCIATED WITH TIMER1
Value on
Value on
POR, BOR
Resets
CMCON1 — — — — — — T1GSS C2SYNC ---- --10 00-- --10
TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu
TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu
T1CON T1GINV TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0000 0000 uuuu uuuu
Legend: x = unknown, u = unchanged, – = unimplemented, read as ‘0’. Shaded cells are not used by the Timer1 module.

PIC16F688
7.0 COMPARATOR MODULE 7.1 Comparator Overview
Comparators are used to interface analog circuits to a A comparator is shown in Figure 7-1 along with the
digital circuit by comparing two analog voltages and relationship between the analog input levels and the
providing a digital indication of their relative magnitudes. digital output. When the analog voltage at VIN+ is less
The comparators are very useful mixed signal building than the analog voltage at VIN-, the output of the
blocks because they provide analog functionality comparator is a digital low level. When the analog
independent of the program execution. The analog voltage at VIN+ is greater than the analog voltage at
comparator module includes the following features: VIN-, the output of the comparator is a digital high level.
• Dual comparators
FIGURE 7-1: SINGLE COMPARATOR
• Multiple comparator configurations
• Comparator outputs are available internally/exter-
nally VIN+ +
• Programmable output polarity Output
VIN- –
• Interrupt-on-change
• Wake-up from Sleep
• Timer1 gate (count enable)
• Output synchronization to Timer1 clock input
VIN-
• Programmable voltage reference VIN+
Note: Only Comparator C2 can be linked to
Timer1.
Output
Note: The black areas of the output of the

comparator represents the uncertainty
due to input offsets and response time.
This device contains two comparators as shown in

Figure 7-2 and Figure 7-3. The comparators are not
independently configurable.

PIC16F688
FIGURE 7-2: COMPARATOR C1 OUTPUT BLOCK DIAGRAM
MULTIPLEX
C1INV
Port Pins
To C1OUT pin
C1
To Data Bus
D Q
Q1
EN RD CMCON0
Set C1IF bit

D Q
Q3*RD CMCON0
EN
CL
Reset
Note 1: Q1 and Q3 are phases of the four-phase system clock (FOSC).

2: Q1 is held high during Sleep mode.
FIGURE 7-3: COMPARATOR C2 OUTPUT BLOCK DIAGRAM
C2SYNC
To Timer1 Gate
MULTIPLEX
C2INV
Port Pins
0
C2 To C2OUT pin
D Q 1
Timer1
clock source(1)
To Data Bus
D Q
Q1
EN RD CMCON0
Set C2IF bit

D Q
Q3*RD CMCON0
EN
CL
Reset
Note 1: Comparator output is latched on falling edge of Timer1 clock source.

2: Q1 and Q3 are phases of the four-phase system clock (FOSC).
3: Q1 is held high during Sleep mode.

PIC16F688
7.1.1 ANALOG INPUT CONNECTION
CONSIDERATIONS Note 1: When reading a PORT register, all pins
A simplified circuit for an analog input is shown in configured as analog inputs will read as a
Figure 7-4. Since the analog input pins share their ‘0’. Pins configured as digital inputs will
connection with a digital input, they have reverse convert as an analog input, according to
biased ESD protection diodes to VDD and VSS. The the input specification.
analog input, therefore, must be between VSS and VDD. 2: Analog levels on any pin defined as a
If the input voltage deviates from this range by more digital input, may cause the input buffer to
than 0.6V in either direction, one of the diodes is consume more current than is specified.
forward biased and a latch-up may occur.
A maximum source impedance of 10 kΩ is recommended
for the analog sources. Also, any external component
connected to an analog input pin, such as a capacitor or
a Zener diode, should have very little leakage current to
minimize inaccuracies introduced.
FIGURE 7-4: ANALOG INPUT MODEL

VDD
VT ≈ 0.6V RIC
Rs < 10K
To ADC Input
AIN
CPIN ILEAKAGE
VA
5 pF VT ≈ 0.6V ±500 nA
Vss
Legend: CPIN = Input Capacitance

ILEAKAGE = Leakage Current at the pin due to various junctions
RIC = Interconnect Resistance
RS = Source Impedance
VA = Analog Voltage
VT = Threshold Voltage

PIC16F688
7.2 Comparator Configuration
There are eight modes of operation for the comparator.
The CM<2:0> bits of the CMCON0 register are used to
select these modes as shown in Figure 7-5. I/O lines
change as a function of the mode and are designated
as follows:
• Analog function (A): digital input buffer is disabled
• Digital function (D): comparator digital output,
overrides port function
• Normal port function (I/O): independent of
comparator
The port pins denoted as “A” will read as a ‘0’
regardless of the state of the I/O pin or the I/O control
TRIS bit. Pins used as analog inputs should also have
the corresponding TRIS bit set to ‘1’ to disable the
digital output driver. Pins denoted as “D” should have
the corresponding TRIS bit set to ‘0’ to enable the
digital output driver.
Note: Comparator interrupts should be disabled

during a Comparator mode change to
prevent unintended interrupts.

PIC16F688
FIGURE 7-5: COMPARATOR I/O OPERATING MODES
Comparators Reset (POR Default Value) Two Independent Comparators
CM<2:0> = 000 CM<2:0> = 100
C1IN-
A VIN- C1IN- A VIN-
VIN+ C1 Off(1) VIN+ C1 C1OUT
C1IN+ A C1IN+ A
A VIN- C2IN-
A VIN-
C2IN-
(1) C2 C2OUT
VIN+ C2 Off A VIN+
C2IN+ A C2IN+
Three Inputs Multiplexed to Two Comparators One Independent Comparator

CM<2:0> = 001 CM<2:0> = 101
A
C1IN-
I/O VIN-
C1IN- CIS = 0 VIN-
A CIS = 1 I/O VIN+ C1 Off(1)
C1IN+ C1 C1OUT C1IN+
VIN+
C2IN-
A VIN- A VIN-
C2IN-
A VIN+ C2 C2OUT A VIN+ C2 C2OUT
C2IN+ C2IN+
Four Inputs Multiplexed to Two Comparators Two Common Reference Comparators with Outputs
CM<2:0> = 010 CM<2:0> = 110
A
C1IN-
A VIN-
C1IN- CIS = 0 VIN-
A CIS = 1 VIN+ C1 C1OUT
C1IN+ C1 C1OUT
VIN+
C1OUT(pin) D
A
C2IN- CIS = 0 VIN-
C2IN-
A VIN-
C2IN+ A CIS = 1 C2OUT
VIN+ C2 A VIN+ C2 C2OUT
C2IN+
C2OUT(pin) D
From CVREF Module
Two Common Reference Comparators Comparators Off (Lowest Power)

CM<2:0> = 011 CM<2:0> = 111
C1IN-
A VIN- I/O VIN-
C1IN-
I/O VIN+ C1 C1OUT C1 Off(1)
C1IN+ C1IN+ I/O
VIN+
C2IN-
A VIN- I/O VIN-
C2IN-
A VIN+ C2 C2OUT I/O VIN+ C2 Off(1)
C2IN+ C2IN+
Legend: A = Analog Input, ports always reads ‘0’ CIS = Comparator Input Switch (CMCON0<3>)
I/O = Normal port I/O D = Comparator Digital Output
Note 1: Reads as ‘0’, unless CxINV = 1.

PIC16F688
7.3 Comparator Control
The CMCON0 register (Register 7-1) provides access
to the following comparator features:
• Mode selection
• Output state
• Output polarity
• Input switch
7.3.1 COMPARATOR OUTPUT STATE

Each comparator state can always be read internally
via the associated CxOUT bit of the CMCON0 register.
The comparator outputs are directed to the CxOUT
pins when CM<2:0> = 110. When this mode is
selected, the TRIS bits for the associated CxOUT pins
must be cleared to enable the output drivers.
7.3.2 COMPARATOR OUTPUT POLARITY

Inverting the output of a comparator is functionally
equivalent to swapping the comparator inputs. The
polarity of a comparator output can be inverted by set-
ting the CxINV bits of the CMCON0 register. Clearing
CxINV results in a non-inverted output. A complete
table showing the output state versus input conditions
and the polarity bit is shown in Table 7-1.
TABLE 7-1: OUTPUT STATE VS. INPUT

CONDITIONS
Input Conditions CxINV CxOUT
VIN- > VIN+ 0 0
VIN- < VIN+ 0 1
VIN- > VIN+ 1 1
VIN- < VIN+ 1 0
Note: CxOUT refers to both the register bit and
output pin.

PIC16F688
7.3.3 COMPARATOR INPUT SWITCH 7.5 Comparator Interrupt Operation
The inverting input of the comparators may be switched The comparator interrupt flag is set whenever there is
between two analog pins in the following modes: a change in the output value of the comparator.
• CM<2:0> = 001 (Comparator C1 only) Changes are recognized by means of a mismatch
• CM<2:0> = 010 (Comparators C1 and C2) circuit which consists of two latches and an exclusive-
or gate (see Figure 7-2 and Figure 7-3). One latch is
In the above modes, both pins remain in analog mode updated with the comparator output level when the
regardless of which pin is selected as the input. The CIS CMCON0 register is read. This latch retains the value
bit of the CMCON0 register controls the comparator until the next read of the CMCON0 register or the
input switch. occurrence of a Reset. The other latch of the mismatch
circuit is updated on every Q1 system clock. A
7.4 Comparator Response Time mismatch condition will occur when a comparator
output change is clocked through the second latch on
The comparator output is indeterminate for a period of
the Q1 clock cycle. The mismatch condition will persist,
time after the change of an input source or the selection
holding the CxIF bit of the PIR1 register true, until either
of a new reference voltage. This period is referred to as
the CMCON0 register is read or the comparator output
the response time. The response time of the
returns to the previous state.
comparator differs from the settling time of the voltage
reference. Therefore, both of these times must be Note: A write operation to the CMCON0 register
considered when determining the total response time will also clear the mismatch condition
to a comparator input change. See the Comparator and because all writes include a read
Voltage Reference specifications in Section 14.0 operation at the beginning of the write
“Electrical Specifications” for more details. cycle.
Software will need to maintain information about the
status of the comparator output to determine the actual
change that has occurred.
The CxIF bit of the PIR1 register is the comparator
interrupt flag. This bit must be reset in software by
clearing it to ‘0’. Since it is also possible to write a ‘1’ to
this register, a simulated interrupt may be initiated.
The CxIE bit of the PIE1 register and the PEIE and GIE
bits of the INTCON register must all be set to enable
comparator interrupts. If any of these bits are cleared,
the interrupt is not enabled, although the CxIF bit of the
PIR1 register will still be set if an interrupt condition
occurs.
The user, in the Interrupt Service Routine, can clear the
interrupt in the following manner:
a) Any read or write of CMCON0. This will end the
mismatch condition. See Figures 7-6 and 7-7
b) Clear the CxIF interrupt flag.
A persistent mismatch condition will preclude clearing
the CxIF interrupt flag. Reading CMCON0 will end the
mismatch condition and allow the CxIF bit to be
cleared.

PIC16F688
FIGURE 7-6: COMPARATOR 7.6 Operation During Sleep
INTERRUPT TIMING W/O
The comparator, if enabled before entering Sleep mode,
CMCON0 READ
remains active during Sleep. The additional current
Q1 consumed by the comparator is shown separately in
Q3 Section 14.0 “Electrical Specifications”. If the
CIN+ TRT comparator is not used to wake the device, power
COUT consumption can be minimized while in Sleep mode by
Set CMIF (level)
turning off the comparator. The comparator is turned off
by selecting mode CM<2:0> = 000 or CM<2:0> = 111
CMIF
of the CMCON0 register.
reset by software
A change to the comparator output can wake-up the
device from Sleep. To enable the comparator to wake
FIGURE 7-7: COMPARATOR the device from Sleep, the CxIE bit of the PIE1 register
INTERRUPT TIMING WITH and the PEIE bit of the INTCON register must be set.
CMCON0 READ The instruction following the Sleep instruction always
executes following a wake from Sleep. If the GIE bit of
Q1
the INTCON register is also set, the device will then
Q3 execute the Interrupt Service Routine.
CIN+ TRT
COUT 7.7 Effects of a Reset
Set CMIF (level)
A device Reset forces the CMCON0 and CMCON1
CMIF
registers to their Reset states. This forces the
cleared by CMCON0 read reset by software
comparator module to be in the Comparator Reset
mode (CM<2:0> = 000). Thus, all comparator inputs
are analog inputs with the comparator disabled to
consume the smallest current possible.
Note 1: If a change in the CM1CON0 register
(CxOUT) occurs when a read operation is
being executed (start of the Q2 cycle),
then the CxIF Interrupt Flag bit of the
PIR1 register may not get set.
2: When either comparator is first enabled,
bias circuitry in the comparator module
may cause an invalid output from the
comparator until the bias circuitry is stable.
Allow about 1 μs for bias settling then clear
the mismatch condition and interrupt flags
before enabling comparator interrupts.

PIC16F688
REGISTER 7-1: CMCON0: COMPARATOR CONFIGURATION REGISTER

R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0
bit 7 bit 0
Legend:
bit 7 C2OUT: Comparator 2 Output bit

When C2INV = 0:
1 = C2 VIN+ > C2 VIN-
0 = C2 VIN+ < C2 VIN-
When C2INV = 1:
1 = C2 VIN+ < C2 VIN-
0 = C2 VIN+ > C2 VIN-
bit 6 C1OUT: Comparator 1 Output bit
When C1INV = 0:
1 = C1 VIN+ > C1 VIN-
0 = C1 VIN+ < C1 VIN-
When C1INV = 1:
1 = C1 VIN+ < C1 VIN-
0 = C1 VIN+ > C1 VIN-
bit 5 C2INV: Comparator 2 Output Inversion bit
1 = C2 output inverted
0 = C2 output not inverted
bit 4 C1INV: Comparator 1 Output Inversion bit
1 = C1 Output inverted
0 = C1 Output not inverted
bit 3 CIS: Comparator Input Switch bit
When CM<2:0> = 010:
1 = C1IN+ connects to C1 VIN-
C2IN+ connects to C2 VIN-
0 = C1IN- connects to C1 VIN-
C2IN- connects to C2 VIN-
When CM<2:0> = 001:
1 = C1IN+ connects to C1 VIN-
0 = C1IN- connects to C1 VIN-
bit 2-0 CM<2:0>: Comparator Mode bits (See Figure 7-5)
000 = Comparators off. CxIN pins are configured as analog
001 = Three inputs multiplexed to two comparators
010 = Four inputs multiplexed to two comparators
011 = Two common reference comparators
100 = Two independent comparators
101 = One independent comparator
110 = Two common reference comparators with outputs
111 = Comparators off. CxIN pins are configured as digital I/O

PIC16F688
7.8 Comparator C2 Gating Timer1 7.9 Synchronizing Comparator C2
This feature can be used to time the duration or interval
Output to Timer1
of analog events. Clearing the T1GSS bit of the The output of Comparator C2 can be synchronized with
CMCON1 register will enable Timer1 to increment Timer1 by setting the C2SYNC bit of the CMCON1
based on the output of Comparator C2. This requires register. When enabled, the comparator output is
that Timer1 is on and gating is enabled. See latched on the falling edge of the Timer1 clock source.
Section 6.0 “Timer1 Module with Gate Control” for If a prescaler is used with Timer1, the comparator
details. output is latched after the prescaling function. To
It is recommended to synchronize Comparator C2 with prevent a race condition, the comparator output is
Timer1 by setting the C2SYNC bit when the comparator latched on the falling edge of the Timer1 clock source
is used as the Timer1 gate source. This ensures Timer1 and Timer1 increments on the rising edge of its clock
does not miss an increment if the comparator changes source. Reference the comparator block diagrams
during an increment. (Figure 7-2 and Figure 7-3) and the Timer1 Block
Diagram (Figure 6-1) for more information.
REGISTER 7-2: CMCON1: COMPARATOR CONFIGURATION REGISTER

U-0 U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-0
— — — — — — T1GSS C2SYNC
bit 7 bit 0
Legend:

bit 1 T1GSS: Timer1 Gate Source Select bit(1)
1 = Timer1 gate source is T1G pin (pin should be configured as digital input)
0 = Timer1 gate source is Comparator C2 output
bit 0 C2SYNC: Comparator C2 Output Synchronization bit(2)
1 = Output is synchronized with falling edge of Timer1 clock
0 = Output is asynchronous
Note 1: Refer to Section 6.6 “Timer1 Gate”.

2: Refer to Figure 7-3.

PIC16F688
7.10 Comparator Voltage Reference EQUATION 7-1: CVREF OUTPUT VOLTAGE
The Comparator Voltage Reference module provides V RR = 1 (low range):
an internally generated voltage reference for the CVREF = (VR<3:0>/24) × V DD
comparators. The following features are available: V RR = 0 (high range):
• Independent from Comparator operation CV REF = (VDD/4) + (VR<3:0> × VDD/32)
• Two 16-level voltage ranges
• Output clamped to VSS The full range of VSS to VDD cannot be realized due to
the construction of the module. See Figure 7-8.
• Ratiometric with VDD
The VRCON register (Figure 7-3) controls the Voltage 7.10.3 OUTPUT CLAMPED TO VSS
Reference module shown in Figure 7-8.
The CVREF output voltage can be set to Vss with no
power consumption by configuring VRCON as follows:
7.10.1 INDEPENDENT OPERATION
• VREN = 0
The comparator voltage reference is independent of
the comparator configuration. Setting the VREN bit of • VRR = 1
the VRCON register will enable the voltage reference. • VR<3:0> = 0000
This allows the comparator to detect a zero-crossing
7.10.2 OUTPUT VOLTAGE SELECTION while not consuming additional CVREF module current.
The CVREF voltage reference has 2 ranges with 16
voltage levels in each range. Range selection is 7.10.4 OUTPUT RATIOMETRIC TO VDD
controlled by the VRR bit of the VRCON register. The The comparator voltage reference is VDD derived and
16 levels are set with the VR<3:0> bits of the VRCON therefore, the CVREF output changes with fluctuations in
register. VDD. The tested absolute accuracy of the Comparator
The CVREF output voltage is determined by the Voltage Reference can be found in Section 14.0
following equations: “Electrical Specifications”.
REGISTER 7-3: VRCON: VOLTAGE REFERENCE CONTROL REGISTER

R/W-0 U-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
VREN — VRR — VR3 VR2 VR1 VR0
bit 7 bit 0
Legend:
bit 7 VREN: CVREF Enable bit

1 = CVREF circuit powered on
0 = CVREF circuit powered down, no IDD drain and CVREF = VSS.
bit 5 VRR: CVREF Range Selection bit
1 = Low range
0 = High range
bit 3-0 VR<3:0>: CVREF Value Selection bits (0 ≤ VR<3:0> ≤ 15)
When VRR = 1: CVREF = (VR<3:0>/24) * VDD
When VRR = 0: CVREF = VDD/4 + (VR<3:0>/32) * VDD

PIC16F688
FIGURE 7-8: COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM
16 Stages
8R R R R R
VDD
8R VRR
16-1 Analog
MUX
VREN
15
CVREF to 14
Comparator 2
Input 1
0
VR<3:0>(1)
VREN
VR<3:0> = 0000
VRR
Note 1: Care should be taken to ensure VREF remains

within the comparator common mode input
range. See Section 14.0 “Electrical Specifica-
tions” for more detail.
TABLE 7-2: SUMMARY OF REGISTERS ASSOCIATED WITH THE COMPARATOR AND

VOLTAGE REFERENCE MODULES
Value on
Value on
POR, BOR
Resets
CMCON1 — — — — — — T1GSS C2SYNC ---- --10 ---- --10
VRCON VREN — VRR — VR3 VR2 VR1 VR0 0-0- 0000 0-0- 0000
Legend: x = unknown, u = unchanged, – = unimplemented, read as ‘0’. Shaded cells are not used for comparator.

PIC16F688
8.0 ANALOG-TO-DIGITAL
CONVERTER (ADC) MODULE
The Analog-to-Digital Converter (ADC) allows
conversion of an analog input signal to a 10-bit binary
representation of that signal. This device uses analog
inputs, which are multiplexed into a single sample and
hold circuit. The output of the sample and hold is
connected to the input of the converter. The converter
generates a 10-bit binary result via successive
approximation and stores the conversion result into the
ADC result registers (ADRESL and ADRESH).
The ADC voltage reference is software selectable to
either VDD or a voltage applied to the external reference
pins.
The ADC can generate an interrupt upon completion of
a conversion. This interrupt can be used to wake-up the
device from Sleep.
Figure 8-1 shows the block diagram of the ADC.
FIGURE 8-1: ADC BLOCK DIAGRAM
VDD
VCFG = 0
VREF VCFG = 1
RA0/AN0 000
RA1/AN1/VREF 001
A/D
RA2/AN2 010
011 GO/DONE 10
RA4/AN3
RC0/AN4 100
0 = Left Justify
RC1/AN5 101 ADFM
1 = Right Justify
RC2/AN6 110 ADON 10
RC3/AN7 111
VSS ADRESH ADRESL
CHS

PIC16F688
8.1 ADC Configuration For correct conversion, the appropriate TAD specification
must be met. See A/D conversion requirements in
When configuring and using the ADC the following Section 14.0 “Electrical Specifications” for more
functions must be considered: information. Table 8-1 gives examples of appropriate
• Port configuration ADC clock selections.
• Channel selection Note: Unless using the FRC, any changes in the
• ADC voltage reference selection system clock frequency will change the
• ADC conversion clock source ADC clock frequency, which may
• Interrupt control adversely affect the ADC result.
• Results formatting
8.1.1 PORT CONFIGURATION

The ADC can be used to convert both analog and digital
signals. When converting analog signals, the I/O pin
should be configured for analog by setting the associated
TRIS and ANSEL bits. See the corresponding Port
section for more information.
Note: Analog voltages on any pin that is defined
as a digital input may cause the input
buffer to conduct excess current.
8.1.2 CHANNEL SELECTION

The CHS bits of the ADCON0 register determine which
channel is connected to the sample and hold circuit.
When changing channels, a delay is required before
starting the next conversion. Refer to Section 8.2
“ADC Operation” for more information.
8.1.3 ADC VOLTAGE REFERENCE

The VCFG bit of the ADCON0 register provides control
of the positive voltage reference. The positive voltage
reference can be either VDD or an external voltage
source. The negative voltage reference is always
connected to the ground reference.
8.1.4 CONVERSION CLOCK

The source of the conversion clock is software
selectable via the ADCS bits of the ADCON1 register.
There are seven possible clock options:
• FOSC/2
• FOSC/4
• FOSC/8
• FOSC/16
• FOSC/32
• FOSC/64
• FRC (dedicated internal oscillator)
The time to complete one bit conversion is defined as
TAD. One full 10-bit conversion requires 11 TAD periods
as shown in Figure 8-3.

PIC16F688
TABLE 8-1: ADC CLOCK PERIOD (TAD) VS. DEVICE OPERATING FREQUENCIES (VDD > 3.0V)
ADC Clock Period (TAD) Device Frequency (FOSC)
ADC Clock Source ADCS<2:0> 20 MHz 8 MHz 4 MHz 1 MHz

FOSC/2 000 100 ns (2)
250 ns (2)
500 ns (2)
2.0 μs
FOSC/4 100 200 ns(2) 500 ns(2) 1.0 μs(2) 4.0 μs
FOSC/8 001 400 ns (2)
1.0 μs (2)
2.0 μs 8.0 μs(3)
FOSC/16 101 800 ns (2)
2.0 μs 4.0 μs 16.0 μs(3)
FOSC/32 010 1.6 μs 4.0 μs 8.0 μs(3) 32.0 μs(3)
FOSC/64 110 3.2 μs 8.0 μs (3)
16.0 μs (3)
64.0 μs(3)
FRC x11 2-6 μs(1,4) 2-6 μs(1,4) 2-6 μs(1,4) 2-6 μs(1,4)
Legend: Shaded cells are outside of recommended range.
Note 1: The FRC source has a typical TAD time of 4 μs for VDD > 3.0V.
2: These values violate the minimum required TAD time.
3: For faster conversion times, the selection of another clock source is recommended.
4: When the device frequency is greater than 1 MHz, the FRC clock source is only recommended if the
conversion will be performed during Sleep.
FIGURE 8-2: ANALOG-TO-DIGITAL CONVERSION TAD CYCLES
TCY to TAD TAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 TAD8 TAD9 TAD10 TAD11
b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
Conversion Starts
Holding Capacitor is Disconnected from Analog Input (typically 100 ns)
Set GO/DONE bit

ADRESH and ADRESL registers are loaded,
GO bit is cleared,
ADIF bit is set,
Holding capacitor is connected to analog input

PIC16F688
8.1.5 INTERRUPTS 8.1.6 RESULT FORMATTING
The ADC module allows for the ability to generate an The 10-bit A/D Conversion result can be supplied in
interrupt upon completion of an Analog-to-Digital two formats, left justified or right justified. The ADFM bit
Conversion. The ADC interrupt flag is the ADIF bit in of the ADCON0 register controls the output format.
the PIR1 register. The ADC interrupt enable is the ADIE Figure 8-4 shows the two output formats.
bit in the PIE1 register. The ADIF bit must be cleared in
software.
Note: The ADIF bit is set at the completion of
every conversion, regardless of whether
or not the ADC interrupt is enabled.
This interrupt can be generated while the device is
operating or while in Sleep. If the device is in Sleep, the
interrupt will wake-up the device. Upon waking from
Sleep, the next instruction following the SLEEP
instruction is always executed. If the user is attempting
to wake-up from Sleep and resume in-line code
execution, the global interrupt must be disabled. If the
global interrupt is enabled, execution will switch to the
Interrupt Service Routine.
Please see Section 8.1.5 “Interrupts” for more
information.
FIGURE 8-3: 10-BIT A/D CONVERSION RESULT FORMAT
ADRESH ADRESL
(ADFM = 0) MSB LSB
bit 7 bit 0 bit 7 bit 0
10-bit A/D Result Unimplemented: Read as ‘0’
(ADFM = 1) MSB LSB

bit 7 bit 0 bit 7 bit 0
Unimplemented: Read as ‘0’ 10-bit A/D Result

PIC16F688
8.2 ADC Operation 8.2.5 A/D CONVERSION PROCEDURE
This is an example procedure for using the ADC to
8.2.1 STARTING A CONVERSION perform an Analog-to-Digital Conversion:
To enable the ADC module, the ADON bit of the 1. Configure Port:
ADCON0 register must be set to a ‘1’. Setting the GO/
• Disable pin output driver (See TRIS register)
DONE bit of the ADCON0 register to a ‘1’ will start the
Analog-to-Digital Conversion. • Configure pin as analog
2. Configure the ADC module:
Note: The GO/DONE bit should not be set in the
• Select ADC conversion clock
same instruction that turns on the ADC.
Refer to Section 8.2.5 “A/D Conversion • Configure voltage reference
Procedure”. • Select ADC input channel
• Select result format
8.2.2 COMPLETION OF A CONVERSION • Turn on ADC module
When the conversion is complete, the ADC module will: 3. Configure ADC interrupt (optional):
• Clear the GO/DONE bit • Clear ADC interrupt flag
• Set the ADIF flag bit • Enable ADC interrupt
• Update the ADRESH:ADRESL registers with new • Enable peripheral interrupt
conversion result • Enable global interrupt(1)
4. Wait the required acquisition time(2).
8.2.3 TERMINATING A CONVERSION
5. Start conversion by setting the GO/DONE bit.
If a conversion must be terminated before completion, 6. Wait for ADC conversion to complete by one of
the GO/DONE bit can be cleared in software. The the following:
ADRESH:ADRESL registers will not be updated with
• Polling the GO/DONE bit
the partially complete Analog-to-Digital Conversion
sample. Instead, the ADRESH:ADRESL register pair • Waiting for the ADC interrupt (interrupts
will retain the value of the previous conversion. Addi- enabled)
tionally, a 2 TAD delay is required before another acqui- 7. Read ADC Result
sition can be initiated. Following this delay, an input 8. Clear the ADC interrupt flag (required if interrupt
acquisition is automatically started on the selected is enabled).
channel.
Note: A device Reset forces all registers to their
Note 1: The global interrupt can be disabled if the
Reset state. Thus, the ADC module is
user is attempting to wake-up from Sleep
turned off and any pending conversion is
and resume in-line code execution.
terminated.
2: See Section 8.3 “A/D Acquisition
8.2.4 ADC OPERATION DURING SLEEP Requirements”.
The ADC module can operate during Sleep. This
requires the ADC clock source to be set to the FRC
option. When the FRC clock source is selected, the
ADC waits one additional instruction before starting the
conversion. This allows the SLEEP instruction to be
executed, which can reduce system noise during the
conversion. If the ADC interrupt is enabled, the device
will wake-up from Sleep when the conversion
completes. If the ADC interrupt is disabled, the ADC
module is turned off after the conversion completes,
although the ADON bit remains set.
When the ADC clock source is something other than
FRC, a SLEEP instruction causes the present conver-
sion to be aborted and the ADC module is turned off,
although the ADON bit remains set.

PIC16F688
EXAMPLE 8-1: A/D CONVERSION
;This code block configures the ADC
;for polling, Vdd reference, Frc clock
;and AN0 input.
;
;Conversion start & polling for completion
; are included.
;
BANKSEL ADCON1 ;
MOVLW B’01110000’ ;ADC Frc clock
MOVWF ADCON1 ;
BANKSEL TRISA ;
BSF TRISA,0 ;Set RA0 to input
BANKSEL ANSEL ;
BSF ANSEL,0 ;Set RA0 to analog
BANKSEL ADCON0 ;
MOVLW B’10000001’ ;Right justify,
MOVWF ADCON0 ;Vdd Vref, AN0, On
CALL SampleTime ;Acquisiton delay
BSF ADCON0,GO ;Start conversion
BTFSC ADCON0,GO ;Is conversion done?
GOTO $-1 ;No, test again
BANKSEL ADRESH ;
MOVF ADRESH,W ;Read upper 2 bits
MOVWF RESULTHI ;store in GPR space
BANKSEL ADRESL ;
MOVF ADRESL,W ;Read lower 8 bits
MOVWF RESULTLO ;Store in GPR space

PIC16F688
8.2.6 ADC REGISTER DEFINITIONS
The following registers are used to control the operation of the ADC.
REGISTER 8-1: ADCON0: A/D CONTROL REGISTER 0

R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
ADFM VCFG — CHS2 CHS1 CHS0 GO/DONE ADON
bit 7 bit 0
Legend:
bit 7 ADFM: A/D Conversion Result Format Select bit

1 = Right justified
0 = Left justified
bit 6 VCFG: Voltage Reference bit
1 = VREF pin
0 = VDD
bit 4-2 CHS<2:0>: Analog Channel Select bits
000 = AN0
001 = AN1
010 = AN2
011 = AN3
100 = AN4
101 = AN5
110 = AN6
111 = AN7
bit 1 GO/DONE: A/D Conversion Status bit
1 = A/D Conversion cycle in progress. Setting this bit starts an A/D Conversion cycle.
This bit is automatically cleared by hardware when the A/D Conversion has completed.
0 = A/D Conversion completed/not in progress
bit 0 ADON: ADC Enable bit
1 = ADC is enabled
0 = ADC is disabled and consumes no operating current
REGISTER 8-2: ADCON1: A/D CONTROL REGISTER 1

U-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0
— ADCS2 ADCS1 ADCS0 — — — —
bit 7 bit 0
Legend:

bit 6-4 ADCS<2:0>: A/D Conversion Clock Select bits
000 = FOSC/2
001 = FOSC/8
010 = FOSC/32
x11 = FRC (clock derived from a dedicated internal oscillator = 500 kHz max)
100 = FOSC/4
101 = FOSC/16
110 = FOSC/64

PIC16F688
REGISTER 8-3: ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM = 0

R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
ADRES9 ADRES8 ADRES7 ADRES6 ADRES5 ADRES4 ADRES3 ADRES2
bit 7 bit 0
Legend:
bit 7-0 ADRES<9:2>: ADC Result Register bits

Upper 8 bits of 10-bit conversion result
REGISTER 8-4: ADRESL: ADC RESULT REGISTER LOW (ADRESL) ADFM = 0

ADRES1 ADRES0 — — — — — —
bit 7 bit 0
Legend:

Lower 2 bits of 10-bit conversion result
bit 5-0 Reserved: Do not use.
REGISTER 8-5: ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM = 1

— — — — — — ADRES9 ADRES8
bit 7 bit 0
Legend:
bit 7-2 Reserved: Do not use.

Upper 2 bits of 10-bit conversion result
REGISTER 8-6: ADRESL: ADC RESULT REGISTER LOW (ADRESL) ADFM = 1

ADRES7 ADRES6 ADRES5 ADRES4 ADRES3 ADRES2 ADRES1 ADRES0
bit 7 bit 0
Legend:

Lower 8 bits of 10-bit conversion result

PIC16F688
8.3 A/D Acquisition Requirements can be started. To calculate the minimum acquisition
time, Equation 8-1 may be used. This equation
For the ADC to meet its specified accuracy, the charge assumes that 1/2 LSb error is used (1024 steps for the
holding capacitor (CHOLD) must be allowed to fully ADC). The 1/2 LSb error is the maximum error allowed
charge to the input channel voltage level. The Analog for the ADC to meet its specified resolution.
Input model is shown in Figure 8-4. The source
impedance (RS) and the internal sampling switch (RSS)
impedance directly affect the time required to charge the
capacitor CHOLD. The sampling switch (RSS) impedance
varies over the device voltage (VDD), see Figure 8-4.
The maximum recommended impedance for analog
sources is 10 kΩ. As the source impedance is
decreased, the acquisition time may be decreased.
After the analog input channel is selected (or changed),
an A/D acquisition must be done before the conversion
EQUATION 8-1: ACQUISITION TIME EXAMPLE
Assumptions: Temperature = 50°C and external impedance of 10k Ω 5.0V V DD
T ACQ = Amplifier Settling Time + Hold Capacitor Charging Time + Temperature Coefficient
= T AMP + T C + T COFF
= 2µs + T C + [ ( Temperature - 25°C ) ( 0.05µs/°C ) ]
The value for TC can be approximated with the following equations:
1
V AP PLIE D ⎛⎝ 1 – ------------⎞⎠ = V CHOLD ;[1] VCHOLD charged to within 1/2 lsb
2047
–TC
⎛ ----------⎞
RC ;[2] VCHOLD charge response to VAPPLIED
V AP P LI ED ⎜ 1 – e ⎟ = V CHOLD
⎝ ⎠
– Tc
⎛ ---------⎞
1
V AP P LIED ⎜ 1 – e ⎟ = V A P PLIE D ⎛⎝ 1 – ------------⎞⎠
RC
;combining [1] and [2]
⎝ ⎠ 2047
Solving for TC:
T C = – C HOLD ( R IC + R SS + R S ) ln(1/2047)
= – 10pF ( 1k Ω + 7k Ω + 10k Ω ) ln(0.0004885)
= 1.37 µs
Therefore:
T ACQ = 2ΜS + 1.37 ΜS + [ ( 50°C- 25°C ) ( 0.05ΜS /°C ) ]
= 4.67 ΜS
Note 1: The reference voltage (VREF) has no effect on the equation, since it cancels itself out.
2: The charge holding capacitor (CHOLD) is not discharged after each conversion.
3: The maximum recommended impedance for analog sources is 10 kΩ. This is required to meet the pin
leakage specification.

PIC16F688
FIGURE 8-4: ANALOG INPUT MODEL
VDD
Sampling
Switch
VT = 0.6V
Rs ANx RIC ≤ 1k SS Rss
VA CPIN I LEAKAGE
VT = 0.6V CHOLD = 10 pF
5 pF ± 500 nA
VSS/VREF-
6V
5V RSS
Legend: CPIN = Input Capacitance VDD 4V
VT = Threshold Voltage 3V
I LEAKAGE = Leakage current at the pin due to 2V
various junctions
RIC = Interconnect Resistance 5 6 7 8 9 10 11
SS = Sampling Switch Sampling Switch
CHOLD = Sample/Hold Capacitance (kΩ)
FIGURE 8-5: ADC TRANSFER FUNCTION
Full-Scale Range
3FFh
3FEh
3FDh
3FCh
ADC Output Code
1 LSB ideal
3FBh
Full-Scale
004h Transition
003h
002h
001h
000h Analog Input Voltage
1 LSB ideal
VSS/VREF- Zero-Scale VDD/VREF+

Transition

PIC16F688
TABLE 8-2: SUMMARY OF ASSOCIATED ADC REGISTERS
Value on
Value on
POR, BOR
Resets
ADCON0 ADFM VCFG — CHS2 CHS1 CHS0 GO/DONE ADON 00-0 0000 00-0 0000
ADCON1 — ADCS2 ADCS1 ADCS0 — — — — -000 ---- -000 ----
ADRESH A/D Result Register High Byte xxxx xxxx uuuu uuuu
ADRESL A/D Result Register Low Byte xxxx xxxx uuuu uuuu
Legend: x = unknown, u = unchanged, — = unimplemented read as ‘0’. Shaded cells are not used for ADC module.

PIC16F688
NOTES:

PIC16F688
9.0 DATA EEPROM AND FLASH 9.1 EEADR and EEADRH Registers
PROGRAM MEMORY The EEADR and EEADRH registers can address up to
CONTROL a maximum of 256 bytes of data EEPROM or up to a
maximum of 4K words of program EEPROM.
Data EEPROM memory is readable and writable and
the Flash program memory is readable during normal When selecting a program address value, the MSB of
operation (full VDD range). These memories are not the address is written to the EEADRH register and the
directly mapped in the register file space. Instead, they LSB is written to the EEADR register. When selecting a
are indirectly addressed through the Special Function data address value, only the LSB of the address is
Registers. There are six SFRs used to access these written to the EEADR register.
memories:
9.1.1 EECON1 AND EECON2 REGISTERS
• EECON1
EECON1 is the control register for EE memory
• EECON2
accesses.
• EEDAT
Control bit EEPGD determines if the access will be a
• EEDATH
program or data memory access. When clear, as it is
• EEADR when reset, any subsequent operations will operate on
• EEADRH the data memory. When set, any subsequent
When interfacing the data memory block, EEDAT holds operations will operate on the program memory.
the 8-bit data for read/write, and EEADR holds the Program memory can only be read.
address of the EE data location being accessed. This Control bits RD and WR initiate read and write,
device has 256 bytes of data EEPROM with an address respectively. These bits cannot be cleared, only set, in
range from 0h to 0FFh. software. They are cleared in hardware at completion
When interfacing the program memory block, the of the read or write operation. The inability to clear the
EEDAT and EEDATH registers form a 2-byte word that WR bit in software prevents the accidental, premature
holds the 14-bit data for read/write, and the EEADR termination of a write operation.
and EEADRH registers form a 2-byte word that holds The WREN bit, when set, will allow a write operation to
the 12-bit address of the EEPROM location being data EEPROM. On power-up, the WREN bit is clear.
accessed. This device has 4K words of program The WRERR bit is set when a write operation is inter-
EEPROM with an address range from 0h to 0FFFh. rupted by a MCLR or a WDT Time-out Reset during
The program memory allows one word reads. normal operation. In these situations, following Reset,
The EEPROM data memory allows byte read and write. the user can check the WRERR bit and rewrite the
A byte write automatically erases the location and location. The data and address will be unchanged in
writes the new data (erase before write). the EEDAT and EEADR registers.
The write time is controlled by an on-chip timer. The Interrupt flag bit EEIF of the PIR1 register is set when
write/erase voltages are generated by an on-chip write is complete. It must be cleared in the software.
charge pump rated to operate over the voltage range of EECON2 is not a physical register. Reading EECON2
the device for byte or word operations. will read all ‘0’s. The EECON2 register is used
When the device is code-protected, the CPU may exclusively in the data EEPROM write sequence.
continue to read and write the data EEPROM memory
and read the program memory. When code-protected,
the device programmer can no longer access data or
program memory.

PIC16F688
REGISTER 9-1: EEDAT: EEPROM DATA REGISTER

EEDAT7 EEDAT6 EEDAT5 EEDAT4 EEDAT3 EEDAT2 EEDAT1 EEDAT0
bit 7 bit 0
Legend:
bit 7-0 EEDATn: Byte Value to Write to or Read from Data EEPROM bits
REGISTER 9-2: EEADR: EEPROM ADDRESS REGISTER

EEADR7 EEADR6 EEADR5 EEADR4 EEADR3 EEADR2 EEADR1 EEADR0
bit 7 bit 0
Legend:
bit 7-0 EEADR<7:0>: 8 Least Significant Address bits for EEPROM Read/Write Operation(1) or Read from program memory
REGISTER 9-3: EEDATH: EEPROM DATA HIGH BYTE REGISTER

U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — EEDATH5 EEDATH4 EEDATH3 EEDATH2 EEDATH1 EEDATH0
bit 7 bit 0
Legend:

bit 5-0 EEDATH<5:0>: 6 Most Significant Data bits from program memory
REGISTER 9-4: EEADRH: EEPROM ADDRESS HIGH BYTE REGISTER

U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
— — — — EEADRH3 EEADRH2 EEADRH1 EEADRH0
bit 7 bit 0
Legend:

bit 3-0 EEADRH<3:0>: Specifies the 4 Most Significant Address bits or high bits for program memory reads

PIC16F688
REGISTER 9-5: EECON1: EEPROM CONTROL REGISTER

R/W-x U-0 U-0 U-0 R/W-x R/W-0 R/S-0 R/S-0
EEPGD — — — WRERR WREN WR RD
bit 7 bit 0
Legend:
S = Bit can only be set
bit 7 EEPGD: Program/Data EEPROM Select bit

1 = Accesses program memory
0 = Accesses data memory
bit 3 WRERR: EEPROM Error Flag bit
1 = A write operation is prematurely terminated (any MCLR Reset, any WDT Reset during
normal operation or BOR Reset)
0 = The write operation completed
bit 2 WREN: EEPROM Write Enable bit
1 = Allows write cycles
0 = Inhibits write to the data EEPROM
bit 1 WR: Write Control bit
EEPGD = 1:
This bit is ignored
EEPGD = 0:
1 = Initiates a write cycle (The bit is cleared by hardware once write is complete. The WR bit can only
be set, not cleared, in software.)
0 = Write cycle to the data EEPROM is complete
bit 0 RD: Read Control bit
1 = Initiates a memory read (the RD is cleared in hardware and can only be set, not cleared, in
software.)
0 = Does not initiate a memory read

PIC16F688
9.1.2 READING THE DATA EEPROM 9.1.3 WRITING TO THE DATA EEPROM
MEMORY MEMORY
To read a data memory location, the user must write To write an EEPROM data location, the user must first
the address to the EEADR register, clear the EEPGD write the address to the EEADR register and the data
control bit of the EECON1 register, and then set control to the EEDAT register. Then the user must follow a
bit RD of the EECON1 register. The data is available in specific sequence to initiate the write for each byte.
the very next cycle, in the EEDAT register; therefore, it The write will not initiate if the above sequence is not
can be read in the next instruction. EEDAT will hold this followed exactly (write 55h to EECON2, write AAh to
value until another read or until it is written to by the EECON2, then set WR bit) for each byte. Interrupts
user (during a write operation). should be disabled during this code segment.
Additionally, the WREN bit in EECON1 must be set to
EXAMPLE 9-1: DATA EEPROM READ
enable write. This mechanism prevents accidental
BANKSEL EEADR ; writes to data EEPROM due to errant (unexpected)
MOVLW DATA_EE_ADDR ;
code execution (i.e., lost programs). The user should
MOVWF EEADR ;Data Memory
keep the WREN bit clear at all times, except when
;Address to read
BCF EECON1, EEPGD ;Point to DATA updating EEPROM. The WREN bit is not cleared
;memory by hardware.
BSF EECON1, RD ;EE Read After a write sequence has been initiated, clearing the
MOVF EEDAT, W ;W = EEDAT WREN bit will not affect this write cycle. The WR bit will
be inhibited from being set unless the WREN bit is set.
At the completion of the write cycle, the WR bit is
cleared in hardware and the EE Write Complete
Interrupt Flag bit (EEIF) is set. The user can either
enable this interrupt or poll this bit. EEIF must be
cleared by software.
EXAMPLE 9-2: DATA EEPROM WRITE

BANKSEL EEADR ;
MOVLW DATA_EE_ADDR ;
MOVWF EEADR ;Data Memory Address to write
MOVLW DATA_EE_DATA ;
MOVWF EEDAT ;Data Memory Value to write
BANKSEL EECON1 ;
BCF EECON1, EEPGD ;Point to DATA memory
BSF EECON1, WREN ;Enable writes
BCF INTCON, GIE ;Disable INTs.

BTFSC INTCON, GIE ;SEE AN576
GOTO $-2
MOVLW 55h ;
Sequence
MOVWF EECON2 ;Write 55h

Required
MOVLW AAh ;
MOVWF EECON2 ;Write AAh
BSF EECON1, WR ;Set WR bit to begin write
BSF INTCON, GIE ;Enable INTs.
SLEEP ;Wait for interrupt to signal write complete

BCF EECON1, WREN ;Disable writes

PIC16F688
9.1.4 READING THE FLASH PROGRAM EEDAT and EEDATH registers will hold this value until
MEMORY another read or until it is written to by the user (during
a write operation).
To read a program memory location, the user must
write two bytes of the address to the EEADR and Note 1: The two instructions following a program
EEADRH registers, set the EEPGD control bit of the memory read are required to be NOP’s.
EECON1 register, and then set control bit RD of the This prevents the user from executing a
EECON1 register. Once the read control bit is set, the two-cycle instruction on the next
program memory Flash controller will use the second instruction after the RD bit is set.
instruction cycle to read the data. This causes the sec- 2: If the WR bit is set when EEPGD = 1, it
ond instruction immediately following the “BSF will be immediately reset to ‘0’ and no
EECON1,RD” instruction to be ignored. The data is
operation will take place.
available in the very next cycle, in the EEDAT and
EEDATH registers; therefore, it can be read as two
bytes in the following instructions.
EXAMPLE 9-3: FLASH PROGRAM READ

BANKSEL EEADR ;
MOVLW MS_PROG_EE_ADDR ;
MOVWF EEADRH ;MS Byte of Program Address to read
MOVLW LS_PROG_EE_ADDR ;
MOVWF EEADR ;LS Byte of Program Address to read
BANKSEL EECON1 ;
BSF EECON1, EEPGD ;Point to PROGRAM memory
BSF EECON1, RD ;EE Read
Sequence
Required
;
;First instruction after BSF EECON1,RD executes normally
NOP
NOP ;Any instructions here are ignored as program
;memory is read in second cycle after BSF EECON1,RD
;
BANKSEL EEDAT ;
MOVF EEDAT, W ;W = LS Byte of Program Memory
MOVWF LOWPMBYTE ;
MOVF EEDATH, W ;W = MS Byte of Program EEDAT
MOVWF HIGHPMBYTE ;
BCF STATUS, RP1 ;Bank 0

PIC16F688
FIGURE 9-1: FLASH PROGRAM MEMORY READ CYCLE EXECUTION
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Flash ADDR PC PC + 1 EEADRH,EEADR PC +3

PC+3 PC + 4 PC + 5
Flash Data INSTR (PC) INSTR (PC + 1) EEDATH,EEDAT INSTR (PC + 3) INSTR (PC + 4)
INSTR(PC - 1) BSF EECON1,RD INSTR(PC + 1) Forced NOP INSTR(PC + 3) INSTR(PC + 4)

executed here executed here executed here executed here executed here executed here
RD bit
EEDATH
EEDAT
Register
EERHLT
TABLE 9-1: SUMMARY OF REGISTERS ASSOCIATED WITH DATA EEPROM

Value on
Value on
POR, BOR
Resets
EECON1 EEPGD — — — WRERR WREN WR RD x--- x000 0--- q000

EECON2 EEPROM Control Register 2 (not a physical register) ---- ---- ---- ----
EEADR EEADR7 EEADR6 EEADR5 EEADR4 EEADR3 EEADR2 EEADR1 EEADR0 0000 0000 0000 0000
EEADRH — — — — EEADRH3 EEADRH2 EEADRH1 EEADRH0 ---- 0000 ---- 0000
EEDAT EEDAT7 EEDAT6 EEDAT5 EEDAT4 EEDAT3 EEDAT2 EEDAT1 EEDAT0 0000 0000 0000 0000
EEDATH — — EEDATH5 EEDATH4 EEDATH3 EEDATH2 EEDATH1 EEDATH0 --00 0000 --00 0000
INTCON GIE PEIE T0IE INTE RABIE T0IF INTF RABIF 0000 000x 0000 000x
Legend: x = unknown, u = unchanged, — = unimplemented read as ‘0’, q = value depends upon condition.
Shaded cells are not used by data EEPROM module.

PIC16F688
10.0 ENHANCED UNIVERSAL The EUSART module includes the following capabilities:
SYNCHRONOUS • Full-duplex asynchronous transmit and receive
ASYNCHRONOUS RECEIVER • Two-character input buffer
TRANSMITTER (EUSART) • One-character output buffer
• Programmable 8-bit or 9-bit character length
The Enhanced Universal Synchronous Asynchronous
• Address detection in 9-bit mode
Receiver Transmitter (EUSART) module is a serial I/O
communications peripheral. It contains all the clock • Input buffer overrun error detection
generators, shift registers and data buffers necessary • Received character framing error detection
to perform an input or output serial data transfer • Half-duplex synchronous master
independent of device program execution. The • Half-duplex synchronous slave
EUSART, also known as a Serial Communications • Programmable clock polarity in synchronous
Interface (SCI), can be configured as a full-duplex modes
asynchronous system or half-duplex synchronous
system. Full-Duplex mode is useful for The EUSART module implements the following
communications with peripheral systems, such as CRT additional features, making it ideally suited for use in
terminals and personal computers. Half-Duplex Local Interconnect Network (LIN) bus systems:
Synchronous mode is intended for communications • Automatic detection and calibration of the baud rate
with peripheral devices, such as A/D or D/A integrated • Wake-up on Break reception
circuits, serial EEPROMs or other microcontrollers.
• 13-bit Break character transmit
These devices typically do not have internal clocks for
baud rate generation and require the external clock Block diagrams of the EUSART transmitter and
signal provided by a master synchronous device. receiver are shown in Figure 10-1 and Figure 10-2.
FIGURE 10-1: EUSART TRANSMIT BLOCK DIAGRAM

Data Bus
TXIE
Interrupt
TXREG Register TXIF
8
MSb LSb TX/CK pin
(8) 0 Pin Buffer
• • • and Control
Transmit Shift Register (TSR)
TXEN
TRMT SPEN
Baud Rate Generator FOSC
÷n
TX9
BRG16 n
+1 Multiplier x4 x16 x64
TX9D
SYNC 1 X 0 0 0
SPBRGH SPBRG BRGH X 1 1 0 0
BRG16 X 1 0 1 0

PIC16F688
FIGURE 10-2: EUSART RECEIVE BLOCK DIAGRAM
SPEN CREN OERR RCIDL
RX/DT pin MSb RSR Register LSb

Pin Buffer Data
and Control Recovery
Stop (8) 7 ••• 1 0 START
Baud Rate Generator FOSC RX9

÷n
BRG16
+1 n
Multiplier x4 x16 x64
SYNC 1 X 0 0 0
SPBRGH SPBRG BRGH X 1 1 0 0 FIFO
FERR RX9D RCREG Register
BRG16 X 1 0 1 0
8
Data Bus
RCIF Interrupt
RCIE
The operation of the EUSART module is controlled

through three registers:
• Transmit Status and Control (TXSTA)
• Receive Status and Control (RCSTA)
• Baud Rate Control (BAUDCTL)
These registers are detailed in Register 10-1,
Register 10-2 and Register 10-3, respectively.

PIC16F688
10.1 EUSART Asynchronous Mode
The EUSART transmits and receives data using the Note 1: When the SPEN bit is set, the RX/DT I/O
standard non-return-to-zero (NRZ) format. NRZ is pin is automatically configured as an input,
implemented with two levels: a VOH mark state which regardless of the state of the corresponding
represents a ‘1’ data bit, and a VOL space state which TRIS bit and whether or not the EUSART
represents a ‘0’ data bit. NRZ refers to the fact that receiver is enabled. The RX/DT pin data
consecutively transmitted data bits of the same value can be read via a normal PORT read but
stay at the output level of that bit without returning to a PORT latch data output is precluded.
neutral level between each bit transmission. An NRZ 2: The TXIF transmitter interrupt flag is set
transmission port idles in the mark state. Each character when the TXEN enable bit is set.
transmission consists of one Start bit followed by eight
or nine data bits and is always terminated by one or 10.1.1.2 Transmitting Data
more Stop bits. The Start bit is always a space and the
A transmission is initiated by writing a character to the
Stop bits are always marks. The most common data
TXREG register. If this is the first character, or the
format is 8 bits. Each transmitted bit persists for a period
previous character has been completely flushed from
of 1/(Baud Rate). An on-chip dedicated 8-bit/16-bit Baud
the TSR, the data in the TXREG is immediately
Rate Generator is used to derive standard baud rate
transferred to the TSR register. If the TSR still contains
frequencies from the system oscillator. See Table 10-5
all or part of a previous character, the new character
for examples of baud rate configurations.
data is held in the TXREG until the Stop bit of the
The EUSART transmits and receives the LSb first. The previous character has been transmitted. The pending
EUSART’s transmitter and receiver are functionally character in the TXREG is then transferred to the TSR
independent, but share the same data format and baud in one TCY immediately following the Stop bit
rate. Parity is not supported by the hardware, but can transmission. The transmission of the Start bit, data bits
be implemented in software and stored as the ninth and Stop bit sequence commences immediately
data bit. following the transfer of the data to the TSR from the
TXREG.
10.1.1 EUSART ASYNCHRONOUS
TRANSMITTER 10.1.1.3 Transmit Interrupt Flag
The EUSART transmitter block diagram is shown in The TXIF interrupt flag bit of the PIR1 register is set
Figure 10-1. The heart of the transmitter is the serial whenever the EUSART transmitter is enabled and no
Transmit Shift Register (TSR), which is not directly character is being held for transmission in the TXREG.
accessible by software. The TSR obtains its data from In other words, the TXIF bit is only clear when the TSR
the transmit buffer, which is the TXREG register. is busy with a character and a new character has been
queued for transmission in the TXREG. The TXIF flag
10.1.1.1 Enabling the Transmitter bit is not cleared immediately upon writing TXREG.
The EUSART transmitter is enabled for asynchronous TXIF becomes valid in the second instruction cycle
operations by configuring the following three control following the write execution. Polling TXIF immediately
bits: following the TXREG write will return invalid results. The
TXIF bit is read-only, it cannot be set or cleared by
• TXEN = 1 software.
• SYNC = 0
The TXIF interrupt can be enabled by setting the TXIE
• SPEN = 1 interrupt enable bit of the PIE1 register. However, the
All other EUSART control bits are assumed to be in TXIF flag bit will be set whenever the TXREG is empty,
their default state. regardless of the state of TXIE enable bit.
Setting the TXEN bit of the TXSTA register enables the To use interrupts when transmitting data, set the TXIE
transmitter circuitry of the EUSART. Clearing the SYNC bit only when there is more data to send. Clear the
bit of the TXSTA register configures the EUSART for TXIE interrupt enable bit upon writing the last character
asynchronous operation. Setting the SPEN bit of the of the transmission to the TXREG.
RCSTA register enables the EUSART and
automatically configures the TX/CK I/O pin as an output.
If the TX/CK pin is shared with an analog peripheral the
analog I/O function must be disabled by clearing the
corresponding ANSEL bit.

PIC16F688
10.1.1.4 TSR Status 10.1.1.6 Asynchronous Transmission Set-up:
The TRMT bit of the TXSTA register indicates the 1. Initialize the SPBRGH, SPBRG register pair and
status of the TSR register. This is a read-only bit. The the BRGH and BRG16 bits to achieve the desired
TRMT bit is set when the TSR register is empty and is baud rate (see Section 10.3 “EUSART Baud
cleared when a character is transferred to the TSR Rate Generator (BRG)”).
register from the TXREG. The TRMT bit remains clear 2. Enable the asynchronous serial port by clearing
until all bits have been shifted out of the TSR register. the SYNC bit and setting the SPEN bit.
No interrupt logic is tied to this bit, so the user has to 3. If 9-bit transmission is desired, set the TX9 con-
poll this bit to determine the TSR status. trol bit. A set ninth data bit will indicate that the 8
Note: The TSR register is not mapped in data Least Significant data bits are an address when
memory, so it is not available to the user. the receiver is set for address detection.
4. Enable the transmission by setting the TXEN
10.1.1.5 Transmitting 9-Bit Characters control bit. This will cause the TXIF interrupt bit
The EUSART supports 9-bit character transmissions. to be set.
When the TX9 bit of the TXSTA register is set the 5. If interrupts are desired, set the TXIE interrupt
EUSART will shift 9 bits out for each character transmit- enable bit. An interrupt will occur immediately
ted. The TX9D bit of the TXSTA register is the ninth, provided that the GIE and PEIE bits of the INT-
and Most Significant, data bit. When transmitting 9-bit CON register are also set.
data, the TX9D data bit must be written before writing 6. If 9-bit transmission is selected, the ninth bit
the 8 Least Significant bits into the TXREG. All nine bits should be loaded into the TX9D data bit.
of data will be transferred to the TSR shift register 7. Load 8-bit data into the TXREG register. This
immediately after the TXREG is written. will start the transmission.
A special 9-bit Address mode is available for use with
multiple receivers. See Section 10.1.2.7 “Address
Detection” for more information on the Address mode.
FIGURE 10-3: ASYNCHRONOUS TRANSMISSION
Write to TXREG
Word 1
BRG Output
(Shift Clock)
RC4/C2OUT/TX/CK
pin Start bit bit 0 bit 1 bit 7/8 Stop bit
Word 1
TXIF bit
(Transmit Buffer 1 TCY
Reg. Empty Flag)
Word 1
TRMT bit Transmit Shift Reg
(Transmit Shift
Reg. Empty Flag)
FIGURE 10-4: ASYNCHRONOUS TRANSMISSION (BACK-TO-BACK)
Write to TXREG
Word 1 Word 2
BRG Output
(Shift Clock)
RC4/C2OUT/TX/CK
pin Start bit bit 0 bit 1 bit 7/8 Stop bit Start bit bit 0
TXIF bit 1 TCY Word 1 Word 2
(Interrupt Reg. Flag)
1 TCY
TRMT bit Word 1 Word 2
(Transmit Shift Transmit Shift Reg.
Reg. Empty Flag) Transmit Shift Reg.
Note: This timing diagram shows two consecutive transmissions.

PIC16F688
TABLE 10-1: REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION
Value on
Value on
POR, BOR
Resets
BAUDCTL ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 01-0 0-00 01-0 0-00
RCREG EUSART Receive Data Register 0000 0000 0000 0000
RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x
SPBRG BRG7 BRG6 BRG5 BRG4 BRG3 BRG2 BRG1 BRG0 0000 0000 0000 0000
SPBRGH BRG15 BRG14 BRG13 BRG12 BRG11 BRG10 BRG9 BRG8 0000 0000 0000 0000
TXREG EUSART Transmit Data Register 0000 0000 0000 0000
TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 0000 0010
Legend: x = unknown, – = unimplemented read as ‘0’. Shaded cells are not used for Asynchronous Transmission.

PIC16F688
10.1.2 EUSART ASYNCHRONOUS 10.1.2.2 Receiving Data
RECEIVER The receiver data recovery circuit initiates character
The Asynchronous mode would typically be used in reception on the falling edge of the first bit. The first bit,
RS-232 systems. The receiver block diagram is shown also known as the Start bit, is always a zero. The data
in Figure 10-2. The data is received on the RX/DT pin recovery circuit counts one-half bit time to the center of
and drives the data recovery block. The data recovery the Start bit and verifies that the bit is still a zero. If it is
block is actually a high-speed shifter operating at 16 not a zero then the data recovery circuit aborts
times the baud rate, whereas the serial Receive Shift character reception, without generating an error, and
Register (RSR) operates at the bit rate. When all 8 or 9 resumes looking for the falling edge of the Start bit. If
bits of the character have been shifted in, they are the Start bit zero verification succeeds then the data
immediately transferred to a two character First-In- recovery circuit counts a full bit time to the center of the
First-Out (FIFO) memory. The FIFO buffering allows next bit. The bit is then sampled by a majority detect
reception of two complete characters and the start of a circuit and the resulting ‘0’ or ‘1’ is shifted into the RSR.
third character before software must start servicing the This repeats until all data bits have been sampled and
EUSART receiver. The FIFO and RSR registers are not shifted into the RSR. One final bit time is measured and
directly accessible by software. Access to the received the level sampled. This is the Stop bit, which is always
data is via the RCREG register. a ‘1’. If the data recovery circuit samples a ‘0’ in the
Stop bit position then a framing error is set for this
10.1.2.1 Enabling the Receiver character, otherwise the framing error is cleared for this
The EUSART receiver is enabled for asynchronous character. See Section 10.1.2.4 “Receive Framing
operation by configuring the following three control bits: Error” for more information on framing errors.
• CREN = 1 Immediately after all data bits and the Stop bit have
been received, the character in the RSR is transferred
• SYNC = 0
to the EUSART receive FIFO and the RCIF interrupt
• SPEN = 1 flag bit of the PIR1 register is set. The top character in
All other EUSART control bits are assumed to be in the FIFO is transferred out of the FIFO by reading the
their default state. RCREG register.
Setting the CREN bit of the RCSTA register enables the Note: If the receive FIFO is overrun, no additional
receiver circuitry of the EUSART. Clearing the SYNC bit characters will be received until the overrun
of the TXSTA register configures the EUSART for condition is cleared. See Section 10.1.2.5
asynchronous operation. Setting the SPEN bit of the “Receive Overrun Error” for more
RCSTA register enables the EUSART and information on overrun errors.
automatically configures the RX/DT I/O pin as an input.
If the RX/DT pin is shared with an analog peripheral the 10.1.2.3 Receive Interrupts
analog I/O function must be disabled by clearing the The RCIF interrupt flag bit of the PIR1 register is set
corresponding ANSEL bit. whenever the EUSART receiver is enabled and there is
Note: When the SPEN bit is set the TX/CK I/O an unread character in the receive FIFO. The RCIF
pin is automatically configured as an interrupt flag bit is read-only, it cannot be set or cleared
output, regardless of the state of the by software.
corresponding TRIS bit and whether or not RCIF interrupts are enabled by setting the following
the EUSART transmitter is enabled. The bits:
PORT latch is disconnected from the
• RCIE interrupt enable bit of the PIE1 register
output driver so it is not possible to use the
TX/CK pin as a general purpose output. • PEIE peripheral interrupt enable bit of the INT-
CON register
• GIE global interrupt enable bit of the INTCON
register
The RCIF interrupt flag bit will be set when there is an
unread character in the FIFO, regardless of the state of
interrupt enable bits.

PIC16F688
10.1.2.4 Receive Framing Error 10.1.2.7 Address Detection
Each character in the receive FIFO buffer has a A special Address Detection mode is available for use
corresponding framing error Status bit. A framing error when multiple receivers share the same transmission
indicates that a Stop bit was not seen at the expected line, such as in RS-485 systems. Address detection is
time. The framing error status is accessed via the enabled by setting the ADDEN bit of the RCSTA
FERR bit of the RCSTA register. The FERR bit register.
represents the status of the top unread character in the Address detection requires 9-bit character reception.
receive FIFO. Therefore, the FERR bit must be read When address detection is enabled, only characters
before reading the RCREG. with the ninth data bit set will be transferred to the
The FERR bit is read-only and only applies to the top receive FIFO buffer, thereby setting the RCIF interrupt
unread character in the receive FIFO. A framing error bit. All other characters will be ignored.
(FERR = 1) does not preclude reception of additional Upon receiving an address character, user software
characters. It is not necessary to clear the FERR bit. determines if the address matches its own. Upon
Reading the next character from the FIFO buffer will address match, user software must disable address
advance the FIFO to the next character and the next detection by clearing the ADDEN bit before the next
corresponding framing error. Stop bit occurs. When user software detects the end of
The FERR bit can be forced clear by clearing the SPEN the message, determined by the message protocol
bit of the RCSTA register which resets the EUSART. used, software places the receiver back into the
Clearing the CREN bit of the RCSTA register does not Address Detection mode by setting the ADDEN bit.
affect the FERR bit. A framing error by itself does not
generate an interrupt.
Note: If all receive characters in the receive
FIFO have framing errors, repeated reads
of the RCREG will not clear the FERR bit.
10.1.2.5 Receive Overrun Error

The receive FIFO buffer can hold two characters. An
overrun error will be generated If a third character, in its
entirety, is received before the FIFO is accessed. When
this happens the OERR bit of the RCSTA register is
set. The characters already in the FIFO buffer can be
read but no additional characters will be received until
the error is cleared. The error must be cleared by either
clearing the CREN bit of the RCSTA register or by
resetting the EUSART by clearing the SPEN bit of the
RCSTA register.
10.1.2.6 Receiving 9-bit Characters

The EUSART supports 9-bit character reception. When
the RX9 bit of the RCSTA register is set the EUSART
will shift 9 bits into the RSR for each character
received. The RX9D bit of the RCSTA register is the
ninth and Most Significant data bit of the top unread
character in the receive FIFO. When reading 9-bit data
from the receive FIFO buffer, the RX9D data bit must
be read before reading the 8 Least Significant bits from
the RCREG.

PIC16F688
10.1.2.8 Asynchronous Reception Set-up: 10.1.2.9 9-bit Address Detection Mode Set-up
1. Initialize the SPBRGH, SPBRG register pair and This mode would typically be used in RS-485 systems.
the BRGH and BRG16 bits to achieve the To set up an Asynchronous Reception with Address
desired baud rate (see Section 10.3 “EUSART Detect Enable:
Baud Rate Generator (BRG)”). 1. Initialize the SPBRGH, SPBRG register pair and
2. Enable the serial port by setting the SPEN bit. the BRGH and BRG16 bits to achieve the
The SYNC bit must be clear for asynchronous desired baud rate (see Section 10.3 “EUSART
operation. Baud Rate Generator (BRG)”).
3. If interrupts are desired, set the RCIE interrupt 2. Enable the serial port by setting the SPEN bit.
enable bit and set the GIE and PEIE bits of the The SYNC bit must be clear for asynchronous
INTCON register. operation.
4. If 9-bit reception is desired, set the RX9 bit. 3. If interrupts are desired, set the RCIE interrupt
5. Enable reception by setting the CREN bit. enable bit and set the GIE and PEIE bits of the
6. The RCIF interrupt flag bit will be set when a INTCON register.
character is transferred from the RSR to the 4. Enable 9-bit reception by setting the RX9 bit.
receive buffer. An interrupt will be generated if 5. Enable address detection by setting the ADDEN
the RCIE interrupt enable bit was also set. bit.
7. Read the RCSTA register to get the error flags 6. Enable reception by setting the CREN bit.
and, if 9-bit data reception is enabled, the ninth 7. The RCIF interrupt flag bit will be set when a
data bit. character with the ninth bit set is transferred
8. Get the received 8 Least Significant data bits from the RSR to the receive buffer. An interrupt
from the receive buffer by reading the RCREG will be generated if the RCIE interrupt enable bit
register. was also set.
9. If an overrun occurred, clear the OERR flag by 8. Read the RCSTA register to get the error flags.
clearing the CREN receiver enable bit. The ninth data bit will always be set.
9. Get the received 8 Least Significant data bits
from the receive buffer by reading the RCREG
register. Software determines if this is the
device’s address.
10. If an overrun occurred, clear the OERR flag by
clearing the CREN receiver enable bit.
11. If the device has been addressed, clear the
ADDEN bit to allow all received data into the
receive buffer and generate interrupts.
FIGURE 10-5: ASYNCHRONOUS RECEPTION

Start Start Start
RX/DT pin bit bit 0 bit 1 bit 7/8 Stop bit bit 0 bit 7/8 Stop bit bit 7/8 Stop
bit bit bit
Rcv Shift
Reg
Rcv Buffer Reg
Word 1 Word 2
RCREG RCREG
RCIDL
Read Rcv
Buffer Reg
RCREG
RCIF
(Interrupt Flag)
OERR bit
CREN
Note: This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word,
causing the OERR (overrun) bit to be set.

PIC16F688
TABLE 10-2: REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
Value on
Value on
POR, BOR
Resets
Legend: x = unknown, – = unimplemented read as ‘0’. Shaded cells are not used for Asynchronous Reception.

PIC16F688
10.2 Clock Accuracy with The first (preferred) method uses the OSCTUNE
Asynchronous Operation register to adjust the INTOSC output. Adjusting the
value in the OSCTUNE register allows for fine resolution
The factory calibrates the internal oscillator block changes to the system clock source. See Section 3.5
output (INTOSC). However, the INTOSC frequency “Internal Clock Modes” for more information.
may drift as VDD or temperature changes, and this
The other method adjusts the value in the Baud Rate
directly affects the asynchronous baud rate. Two
Generator. This can be done automatically with the
methods may be used to adjust the baud rate clock, but
Auto-Baud Detect feature (see Section 10.3.1 “Auto-
both require a reference clock source of some kind.
Baud Detect”). There may not be fine enough
resolution when adjusting the Baud Rate Generator to
compensate for a gradual change in the peripheral
clock frequency.
REGISTER 10-1: TXSTA: TRANSMIT STATUS AND CONTROL REGISTER

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-1 R/W-0
CSRC TX9 TXEN(1) SYNC SENDB BRGH TRMT TX9D
bit 7 bit 0
Legend:
bit 7 CSRC: Clock Source Select bit

Asynchronous mode:
Don’t care
Synchronous mode:
1 = Master mode (clock generated internally from BRG)
0 = Slave mode (clock from external source)
bit 6 TX9: 9-bit Transmit Enable bit
1 = Selects 9-bit transmission
0 = Selects 8-bit transmission
bit 5 TXEN: Transmit Enable bit(1)
1 = Transmit enabled
0 = Transmit disabled
bit 4 SYNC: EUSART Mode Select bit
1 = Synchronous mode
0 = Asynchronous mode
bit 3 SENDB: Send Break Character bit
Asynchronous mode:
1 = Send Sync Break on next transmission (cleared by hardware upon completion)
0 = Sync Break transmission completed
Synchronous mode:
Don’t care
bit 2 BRGH: High Baud Rate Select bit
Asynchronous mode:
1 = High speed
0 = Low speed
Synchronous mode:
Unused in this mode
bit 1 TRMT: Transmit Shift Register Status bit
1 = TSR empty
0 = TSR full
bit 0 TX9D: Ninth bit of Transmit Data
Can be address/data bit or a parity bit.
Note 1: SREN/CREN overrides TXEN in Sync mode.

PIC16F688
REGISTER 10-2: RCSTA: RECEIVE STATUS AND CONTROL REGISTER(1)

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-0 R-x
SPEN RX9 SREN CREN ADDEN FERR OERR RX9D
bit 7 bit 0
Legend:
bit 7 SPEN: Serial Port Enable bit

1 = Serial port enabled (configures RX/DT and TX/CK pins as serial port pins)
0 = Serial port disabled (held in Reset)
bit 6 RX9: 9-bit Receive Enable bit
1 = Selects 9-bit reception
0 = Selects 8-bit reception
bit 5 SREN: Single Receive Enable bit
Asynchronous mode:
Don’t care
Synchronous mode – Master:
1 = Enables single receive
0 = Disables single receive
This bit is cleared after reception is complete.
Synchronous mode – Slave
Don’t care
bit 4 CREN: Continuous Receive Enable bit
Asynchronous mode:
1 = Enables receiver
0 = Disables receiver
Synchronous mode:
1 = Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN)
0 = Disables continuous receive
bit 3 ADDEN: Address Detect Enable bit
Asynchronous mode 9-bit (RX9 = 1):
1 = Enables address detection, enable interrupt and load the receive buffer when RSR<8> is set
0 = Disables address detection, all bytes are received and ninth bit can be used as parity bit
Asynchronous mode 8-bit (RX9 = 0):
Don’t care
bit 2 FERR: Framing Error bit
1 = Framing error (can be updated by reading RCREG register and receive next valid byte)
0 = No framing error
bit 1 OERR: Overrun Error bit
1 = Overrun error (can be cleared by clearing bit CREN)
0 = No overrun error
bit 0 RX9D: Ninth bit of Received Data
This can be address/data bit or a parity bit and must be calculated by user firmware.

PIC16F688
REGISTER 10-3: BAUDCTL: BAUD RATE CONTROL REGISTER

R-0 R-1 U-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0
ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN
bit 7 bit 0
Legend:
bit 7 ABDOVF: Auto-Baud Detect Overflow bit

Asynchronous mode:
1 = Auto-baud timer overflowed
0 = Auto-baud timer did not overflow
Synchronous mode:
Don’t care
bit 6 RCIDL: Receive Idle Flag bit
Asynchronous mode:
1 = Receiver is Idle
0 = Start bit has been received and the receiver is receiving
Synchronous mode:
Don’t care
bit 4 SCKP: Synchronous Clock Polarity Select bit
Asynchronous mode:
1 = Transmit inverted data to the RB7/TX/CK pin
0 = Transmit non-inverted data to the RB7/TX/CK pin
Synchronous mode:
1 = Data is clocked on rising edge of the clock
0 = Data is clocked on falling edge of the clock
bit 3 BRG16: 16-bit Baud Rate Generator bit
1 = 16-bit Baud Rate Generator is used
0 = 8-bit Baud Rate Generator is used
bit 1 WUE: Wake-up Enable bit
Asynchronous mode:
1 = Receiver is waiting for a falling edge. No character will be received byte RCIF will be set. WUE will
automatically clear after RCIF is set.
0 = Receiver is operating normally
Synchronous mode:
Don’t care
bit 0 ABDEN: Auto-Baud Detect Enable bit
Asynchronous mode:
1 = Auto-Baud Detect mode is enabled (clears when auto-baud is complete)
0 = Auto-Baud Detect mode is disabled
Synchronous mode:
Don’t care

PIC16F688
10.3 EUSART Baud Rate Generator If the system clock is changed during an active receive
(BRG) operation, a receive error or data loss may result. To
avoid this problem, check the status of the RCIDL bit to
The Baud Rate Generator (BRG) is an 8-bit or 16-bit make sure that the receive operation is Idle before
timer that is dedicated to the support of both the changing the system clock.
asynchronous and synchronous EUSART operation.
By default, the BRG operates in 8-bit mode. Setting the EXAMPLE 10-1: CALCULATING BAUD
BRG16 bit of the BAUDCTL register selects 16-bit RATE ERROR
mode.
For a device with FOSC of 16 MHz, desired baud rate
The SPBRGH, SPBRG register pair determines the of 9600, Asynchronous mode, 8-bit BRG:
period of the free running baud rate timer. In
F OS C
Asynchronous mode the multiplier of the baud rate Desired Baud Rate = ---------------------------------------------------------------------
64 ( [SPBRGH:SPBRG] + 1 )
period is determined by both the BRGH bit of the TXSTA
register and the BRG16 bit of the BAUDCTL register. In Solving for SPBRGH:SPBRG:
Synchronous mode, the BRGH bit is ignored.
FOSC
---------------------------------------------
Table 10-3 contains the formulas for determining the Desired Baud Rate
X = --------------------------------------------- – 1
baud rate. Example 10-1 provides a sample calculation 64
for determining the baud rate and baud rate error. 16000000
------------------------
Typical baud rates and error values for various 9600
= ------------------------ – 1
asynchronous modes have been computed for your 64
convenience and are shown in Table 10-3. It may be = [ 25.042 ] = 25
advantageous to use the high baud rate (BRGH = 1),
or the 16-bit BRG (BRG16 = 1) to reduce the baud rate 16000000
Calculated Baud Rate = ---------------------------
64 ( 25 + 1 )
error. The 16-bit BRG mode is used to achieve slow
baud rates for fast oscillator frequencies. = 9615
Writing a new value to the SPBRGH, SPBRG register
Calc. Baud Rate – Desired Baud Rate
pair causes the BRG timer to be reset (or cleared). This Error = --------------------------------------------------------------------------------------------
Desired Baud Rate
ensures that the BRG does not wait for a timer overflow
before outputting the new baud rate. ( 9615 – 9600 )
= ---------------------------------- = 0.16%
9600
TABLE 10-3: BAUD RATE FORMULAS

Configuration Bits
BRG/EUSART Mode Baud Rate Formula
SYNC BRG16 BRGH
0 0 0 8-bit/Asynchronous FOSC/[64 (n+1)]

0 0 1 8-bit/Asynchronous
FOSC/[16 (n+1)]
1 0 x 8-bit/Synchronous FOSC/[4 (n+1)]
1 1 x 16-bit/Synchronous
Legend: x = Don’t care, n = value of SPBRGH, SPBRG register pair
TABLE 10-4: REGISTERS ASSOCIATED WITH THE BAUD RATE GENERATOR

Value on
Value on
POR, BOR
Resets
Legend: x = unknown, – = unimplemented read as ‘0’. Shaded cells are not used for the Baud Rate Generator.

PIC16F688
TABLE 10-5: BAUD RATES FOR ASYNCHRONOUS MODES

SYNC = 0, BRGH = 0, BRG16 = 0
FOSC = 20.000 MHz FOSC = 18.432 MHz FOSC = 11.0592 MHz FOSC = 8.000 MHz
BAUD
RATE SPBRG SPBRG SPBRG SPBRG
Actual % Actual % Actual % Actual %
value value value value
Rate Error Rate Error Rate Error Rate Error
(decimal) (decimal) (decimal) (decimal)
300 — — — — — — — — — — — —
1200 1221 1.73 255 1200 0.00 239 1200 0.00 143 1202 0.16 103
2400 2404 0.16 129 2400 0.00 119 2400 0.00 71 2404 0.16 51
9600 9470 -1.36 32 9600 0.00 29 9600 0.00 17 9615 0.16 12
10417 10417 0.00 29 10286 -1.26 27 10165 -2.42 16 10417 0.00 11
19.2k 19.53k 1.73 15 19.20k 0.00 14 19.20k 0.00 8 — — —
57.6k — — — 57.60k 0.00 7 57.60k 0.00 2 — — —
115.2k — — — — — — — — — — — —
SYNC = 0, BRGH = 0, BRG16 = 0
BAUD FOSC = 4.000 MHz FOSC = 3.6864 MHz FOSC = 2.000 MHz FOSC = 1.000 MHz
300 300 0.16 207 300 0.00 191 300 0.16 103 300 0.16 51
1200 1202 0.16 51 1200 0.00 47 1202 0.16 25 1202 0.16 12
2400 2404 0.16 25 2400 0.00 23 2404 0.16 12 — — —
9600 — — — 9600 0.00 5 — — — — — —
10417 10417 0.00 5 — — — 10417 0.00 2 — — —
19.2k — — — 19.20k 0.00 2 — — — — — —
57.6k — — — 57.60k 0.00 0 — — — — — —
115.2k — — — — — — — — — — — —
SYNC = 0, BRGH = 1, BRG16 = 0
300 — — — — — — — — — — — —
1200 — — — — — — — — — — — —
2400 — — — — — — — — — 2404 0.16 207
9600 9615 0.16 129 9600 0.00 119 9600 0.00 71 9615 0.16 51
10417 10417 0.00 119 10378 -0.37 110 10473 0.53 65 10417 0.00 47
19.2k 19.23k 0.16 64 19.20k 0.00 59 19.20k 0.00 35 19231 0.16 25
57.6k 56.82k -1.36 21 57.60k 0.00 19 57.60k 0.00 11 55556 -3.55 8
115.2k 113.64k -1.36 10 115.2k 0.00 9 115.2k 0.00 5 — — —

PIC16F688
TABLE 10-5: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED)
SYNC = 0, BRGH = 1, BRG16 = 0
300 — — — — — — — — — 300 0.16 207
1200 1202 0.16 207 1200 0.00 191 1202 0.16 103 1202 0.16 51
2400 2404 0.16 103 2400 0.00 95 2404 0.16 51 2404 0.16 25
9600 9615 0.16 25 9600 0.00 23 9615 0.16 12 — — —
10417 10417 0.00 23 10473 0.53 21 10417 0.00 11 10417 0.00 5
19.2k 19.23k 0.16 12 19.2k 0.00 11 — — — — — —
57.6k — — — 57.60k 0.00 3 — — — — — —
115.2k — — — 115.2k 0.00 1 — — — — — —
SYNC = 0, BRGH = 0, BRG16 = 1
300 300.0 -0.01 4166 300.0 0.00 3839 300.0 0.00 2303 299.9 -0.02 1666
1200 1200 -0.03 1041 1200 0.00 959 1200 0.00 575 1199 -0.08 416
2400 2399 -0.03 520 2400 0.00 479 2400 0.00 287 2404 0.16 207
9600 9615 0.16 129 9600 0.00 119 9600 0.00 71 9615 0.16 51
10417 10417 0.00 119 10378 -0.37 110 10473 0.53 65 10417 0.00 47
19.2k 19.23k 0.16 64 19.20k 0.00 59 19.20k 0.00 35 19.23k 0.16 25
57.6k 56.818 -1.36 21 57.60k 0.00 19 57.60k 0.00 11 55556 -3.55 8
115.2k 113.636 -1.36 10 115.2k 0.00 9 115.2k 0.00 5 — — —
SYNC = 0, BRGH = 0, BRG16 = 1
300 300.1 0.04 832 300.0 0.00 767 299.8 -0.108 416 300.5 0.16 207
1200 1202 0.16 207 1200 0.00 191 1202 0.16 103 1202 0.16 51
2400 2404 0.16 103 2400 0.00 95 2404 0.16 51 2404 0.16 25
9600 9615 0.16 25 9600 0.00 23 9615 0.16 12 — — —
10417 10417 0.00 23 10473 0.53 21 10417 0.00 11 10417 0.00 5
19.2k 19.23k 0.16 12 19.20k 0.00 11 — — — — — —
57.6k — — — 57.60k 0.00 3 — — — — — —
115.2k — — — 115.2k 0.00 1 — — — — — —

PIC16F688
TABLE 10-5: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED)
SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1
300 300.0 0.00 16665 300.0 0.00 15359 300.0 0.00 9215 300.0 0.00 6666
1200 1200 -0.01 4166 1200 0.00 3839 1200 0.00 2303 1200 -0.02 1666
2400 2400 0.02 2082 2400 0.00 1919 2400 0.00 1151 2401 0.04 832
9600 9597 -0.03 520 9600 0.00 479 9600 0.00 287 9615 0.16 207
10417 10417 0.00 479 10425 0.08 441 10433 0.16 264 10417 0 191
19.2k 19.23k 0.16 259 19.20k 0.00 239 19.20k 0.00 143 19.23k 0.16 103
57.6k 57.47k -0.22 86 57.60k 0.00 79 57.60k 0.00 47 57.14k -0.79 34
115.2k 116.3k 0.94 42 115.2k 0.00 39 115.2k 0.00 23 117.6k 2.12 16
SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1
300 300.0 0.01 3332 300.0 0.00 3071 299.9 -0.02 1666 300.1 0.04 832
1200 1200 0.04 832 1200 0.00 767 1199 -0.08 416 1202 0.16 207
2400 2398 0.08 416 2400 0.00 383 2404 0.16 207 2404 0.16 103
9600 9615 0.16 103 9600 0.00 95 9615 0.16 51 9615 0.16 25
10417 10417 0.00 95 10473 0.53 87 10417 0.00 47 10417 0.00 23
19.2k 19.23k 0.16 51 19.20k 0.00 47 19.23k 0.16 25 19.23k 0.16 12
57.6k 58.82k 2.12 16 57.60k 0.00 15 55.56k -3.55 8 — — —
115.2k 111.1k -3.55 8 115.2k 0.00 7 — — — — — —

PIC16F688
10.3.1 AUTO-BAUD DETECT and SPBRG registers are clocked at 1/8th the BRG
base clock rate. The resulting byte measurement is the
The EUSART module supports automatic detection
average bit time when clocked at full speed.
and calibration of the baud rate.
Note 1: If the WUE bit is set with the ABDEN bit,
In the Auto-Baud Detect (ABD) mode, the clock to the
auto-baud detection will occur on the byte
BRG is reversed. Rather than the BRG clocking the
following the Break character (see
incoming RX signal, the RX signal is timing the BRG.
Section 10.3.3 “Auto-Wake-up on
The Baud Rate Generator is used to time the period of
Break”).
a received 55h (ASCII “U”) which is the Sync character
for the LIN bus. The unique feature of this character is 2: It is up to the user to determine that the
that it has five rising edges including the Stop bit edge. incoming character baud rate is within the
range of the selected BRG clock source.
Setting the ABDEN bit of the BAUDCTL register starts
Some combinations of oscillator frequency
the auto-boot sequence (Figure 10-6). While the ABD
and EUSART baud rates are not possible
sequence takes place, the EUSART state machine is
due to bit error rates. Overall system timing
held in Idle. On the first rising edge of the receive line,
and communication baud rates must be
after the Start bit, the SPBRG begins counting up using
taken into consideration when using the
the BRG counter clock as shown in Table 10-6. The
Auto-Baud Detect feature.
fifth rising edge will occur on the RX pin at the end of
the eighth bit period. At that time, an accumulated 3: During the auto-baud process, the auto-
value totaling the proper BRG period is left in baud counter starts counting at 1. Upon
SPBRGH, SPBRG register pair, the ABDEN bit is completion of the auto-baud sequence, to
automatically cleared and the RCIF interrupt flag is set. achieve maximum accuracy, subtract 1
The value in the RCREG needs to be read to clear the from the SPBRGH:SPBRG register pair.
RCIF interrupt. RCREG content should be discarded.
When calibrating for modes that do not use the TABLE 10-6: BRG COUNTER CLOCK RATES
SPBRGH register the user can verify that the SPBRG BRG Base BRG ABD
register did not overflow by checking for 00h in the BRG16 BRGH
Clock Clock
SPBRGH register.
The BRG auto-baud clock is determined by the BRG16 0 0 FOSC/64 FOSC/512
and BRGH bits as shown in Table 10-6. During ABD, 0 1 FOSC/16 FOSC/128
both the SPBRGH and SPBRG registers are used as a
1 0 FOSC/16 FOSC/128
16-bit counter, independent of the BRG16 bit setting.
While calibrating the baud rate period, the SPBRGH 1 1 FOSC/4 FOSC/32
Note: During the ABD sequence, SPBRG and
SPBRGH registers are both used as a 16-bit
counter, independent of BRG16 setting.
FIGURE 10-6: AUTOMATIC BAUD RATE CALCULATION
BRG Value XXXXh 0000h 001Ch
Edge #1 Edge #2 Edge #3 Edge #4 Edge #5

RX pin Start bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 Stop bit
BRG Clock
Set by User Auto Cleared

ABDEN bit
RCIDL
RCIF bit
(Interrupt)
Read
RCREG
SPBRG XXh 1Ch
SPBRGH XXh 00h
Note 1: The ABD sequence requires the EUSART module to be configured in Asynchronous mode.

PIC16F688
10.3.2 AUTO-BAUD OVERFLOW The WUE bit is automatically cleared by the low-to-high
transition on the RX line at the end of the Break. This
During the course of automatic baud detection, the
signals to the user that the Break event is over. At this
ABDOVF bit of the BAUDCTL register will be set if the
point, the EUSART module is in Idle mode waiting to
baud rate counter overflows before the fifth rising edge
receive the next character.
is detected on the RX pin. The ABDOVF bit indicates
that the counter has exceeded the maximum count that
10.3.3.1 Special Considerations
can fit in the 16 bits of the SPBRGH:SPBRG register
pair. After the ABDOVF has been set, the counter con- Break Character
tinues to count until the fifth rising edge is detected on To avoid character errors or character fragments
the RX pin. Upon detecting the fifth RX edge, the hard- during a wake-up event, the wake-up character must
ware will set the RCIF interrupt flag and clear the be all zeros.
ABDEN bit of the BAUDCTL register. The RCIF flag
When the wake-up is enabled the function works
can be subsequently cleared by reading the RCREG.
independent of the low time on the data stream. If the
The ABDOVF flag can be cleared by software directly.
WUE bit is set and a valid non-zero character is
To terminate the auto-baud process before the RCIF received, the low time from the Start bit to the first rising
flag is set, clear the ABDEN bit then clear the ABDOVF edge will be interpreted as the wake-up event. The
bit. The ABDOVF bit will remain set if the ABDEN bit is remaining bits in the character will be received as a
not cleared first. fragmented character and subsequent characters can
result in framing or overrun errors.
10.3.3 AUTO-WAKE-UP ON BREAK
Therefore, the initial character in the transmission must
During Sleep mode, all clocks to the EUSART are be all ‘0’s. This must be 10 or more bit times, 13-bit
suspended. Because of this, the Baud Rate Generator times recommended for LIN bus, or any number of bit
is inactive and a proper character reception cannot be times for standard RS-232 devices.
performed. The Auto-Wake-up feature allows the
controller to wake-up due to activity on the RX/DT line. Oscillator Start-up Time
This feature is available only in Asynchronous mode. Oscillator start-up time must be considered, especially
The Auto-Wake-up feature is enabled by setting the in applications using oscillators with longer start-up
WUE bit of the BAUDCTL register. Once set, the normal intervals (i.e., LP, XT or HS mode). The Sync Break (or
receive sequence on RX/DT is disabled, and the wake-up signal) character must be of sufficient length,
EUSART remains in an Idle state, monitoring for a wake- and be followed by a sufficient interval, to allow enough
up event independent of the CPU mode. A wake-up time for the selected oscillator to start and provide
event consists of a high-to-low transition on the RX/DT proper initialization of the EUSART.
line. (This coincides with the start of a Sync Break or a WUE Bit
wake-up signal character for the LIN protocol.) The wake-up event causes a receive interrupt by
The EUSART module generates an RCIF interrupt setting the RCIF bit. The WUE bit is cleared in
coincident with the wake-up event. The interrupt is hardware by a rising edge on RX/DT. The interrupt
generated synchronously to the Q clocks in normal CPU condition is then cleared in software by reading the
operating modes (Figure 10-7), and asynchronously if RCREG register and discarding its contents.
the device is in Sleep mode (Figure 10-8). The interrupt To ensure that no actual data is lost, check the RCIDL.
condition is cleared by reading the RCREG register.
FIGURE 10-7: AUTO-WAKE-UP BIT (WUE) TIMING DURING NORMAL OPERATION

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
Bit set by user Auto Cleared
WUE bit
RX/DT Line
RCIF
Cleared due to User Read of RCREG
Note 1: The EUSART remains in Idle while the WUE bit is set.

PIC16F688
FIGURE 10-8: AUTO-WAKE-UP BIT (WUE) TIMINGS DURING SLEEP
Q1Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4

OSC1
Bit Set by User Auto Cleared
WUE bit
RX/DT Line Note 1
RCIF
Cleared due to User Read of RCREG
Sleep Command Executed Sleep Ends
Note 1: If the wake-up event requires long oscillator warm-up time, the automatic clearing of the WUE bit can occur while the stposc signal is
still active. This sequence should not depend on the presence of Q clocks.
2: The EUSART remains in Idle while the WUE bit is set.
10.3.4 BREAK CHARACTER SEQUENCE 10.3.5 RECEIVING A BREAK CHARACTER

The EUSART module has the capability of sending the The Enhanced EUSART module can receive a Break
special Break character sequences that are required by character in two ways.
the LIN bus standard. A Break character consists of a The first method to detect a Break character uses the
Start bit, followed by 12 ‘0’ bits and a Stop bit. FERR bit of the RCSTA register and the Received data
To send a Break character, set the SENDB and TXEN as indicated by RCREG. The Baud Rate Generator is
bits of the TXSTA register. The Break character trans- assumed to have been initialized to the expected baud
mission is then initiated by a write to the TXREG. The rate.
value of data written to TXREG will be ignored and all A Break character has been received when;
‘0’s will be transmitted.
• RCIF bit is set
The SENDB bit is automatically reset by hardware after
• FERR bit is set
the corresponding Stop bit is sent. This allows the user
to preload the transmit FIFO with the next transmit byte • RCREG = 00h
following the Break character (typically, the Sync The second method uses the Auto-Wake-up feature
character in the LIN specification). described in Section 10.3.3 “Auto-Wake-up on
The TRMT bit of the TXSTA register indicates when the Break”. By enabling this feature, the EUSART will
transmit operation is active or Idle, just as it does during sample the next two transitions on RX/DT, cause an
normal transmission. See Figure 10-9 for the timing of RCIF interrupt, and receive the next data byte followed
the Break character sequence. by another interrupt.
Note that following a Break character, the user will
10.3.4.1 Break and Sync Transmit Sequence typically want to enable the Auto-Baud Detect feature.
The following sequence will start a message frame For both methods, the user can set the ABDEN bit of
header made up of a Break, followed by an auto-baud the BAUDCTL register before placing the EUSART in
Sync byte. This sequence is typical of a LIN bus Sleep mode.
master.
1. Configure the EUSART for the desired mode.
2. Set the TXEN and SENDB bits to enable the
Break sequence.
3. Load the TXREG with a dummy character to
initiate transmission (the value is ignored).
4. Write ‘55h’ to TXREG to load the Sync character
into the transmit FIFO buffer.
5. After the Break has been sent, the SENDB bit is
reset by hardware and the Sync character is
then transmitted.
When the TXREG becomes empty, as indicated by the
TXIF, the next data byte can be written to TXREG.

PIC16F688
FIGURE 10-9: SEND BREAK CHARACTER SEQUENCE
Write to TXREG
Dummy Write
BRG Output
(Shift Clock)
TX (pin) Start bit bit 0 bit 1 bit 11 Stop bit

Break
TXIF bit
(Transmit
interrupt Flag)
TRMT bit
(Transmit Shift
Reg. Empty Flag)
SENDB Sampled Here Auto Cleared
SENDB
(send Break
control bit)

PIC16F688
10.4 EUSART Synchronous Mode the clock Idle state as high. When the SCKP bit is set,
the data changes on the falling edge of each clock.
Synchronous serial communications are typically used Clearing the SCKP bit sets the Idle state as low. When
in systems with a single master and one or more the SCKP bit is cleared, the data changes on the rising
slaves. The master device contains the necessary edge of each clock.
circuitry for baud rate generation and supplies the clock
for all devices in the system. Slave devices can take 10.4.1.3 Synchronous Master Transmission
advantage of the master clock by eliminating the
Data is transferred out of the device on the RX/DT pin.
internal clock generation circuitry.
The RX/DT and TX/CK pin output drivers are automat-
There are two signal lines in Synchronous mode: a ically enabled when the EUSART is configured for
bidirectional data line and a clock line. Slaves use the synchronous master transmit operation.
external clock supplied by the master to shift the serial
A transmission is initiated by writing a character to the
data into and out of their respective receive and trans-
TXREG register. If the TSR still contains all or part of a
mit shift registers. Since the data line is bidirectional,
previous character, the new character data is held in
synchronous operation is half-duplex only. Half-duplex
the TXREG until the last bit of the previous character
refers to the fact that master and slave devices can
has been transmitted. If this is the first character, or the
receive and transmit data but not both simultaneously.
previous character has been completely flushed from
The EUSART can operate as either a master or slave
the TSR, the data in the TXREG is immediately trans-
device.
ferred to the TSR. The transmission of the character
Start and Stop bits are not used in synchronous commences immediately following the transfer of the
transmissions. data to the TSR from the TXREG.
Each data bit changes on the leading edge of the
10.4.1 SYNCHRONOUS MASTER MODE
master clock and remains valid until the subsequent
The following bits are used to configure the EUSART leading clock edge.
for Synchronous Master operation:
Note: The TSR register is not mapped in data
• SYNC = 1 memory, so it is not available to the user.
• CSRC = 1
• SREN = 0 (for transmit); SREN = 1 (for receive) 10.4.1.4 Synchronous Master Transmission
• CREN = 0 (for transmit); CREN = 1 (for receive) Set-up:
• SPEN = 1 1. Initialize the SPBRGH, SPBRG register pair and
the BRGH and BRG16 bits to achieve the
Setting the SYNC bit of the TXSTA register configures
desired baud rate (see Section 10.3 “EUSART
the device for synchronous operation. Setting the CSRC
Baud Rate Generator (BRG)”).
bit of the TXSTA register configures the device as a
master. Clearing the SREN and CREN bits of the RCSTA 2. Enable the synchronous master serial port by
register ensures that the device is in the Transmit mode, setting bits SYNC, SPEN and CSRC.
otherwise the device will be configured to receive. Setting 3. Disable Receive mode by clearing bits SREN
the SPEN bit of the RCSTA register enables the and CREN.
EUSART. If the RX/DT or TX/CK pins are shared with an 4. Enable Transmit mode by setting the TXEN bit.
analog peripheral the analog I/O functions must be 5. If 9-bit transmission is desired, set the TX9 bit.
disabled by clearing the corresponding ANSEL bits.
6. If interrupts are desired, set the TXIE, GIE and
10.4.1.1 Master Clock PEIE interrupt enable bits.
7. If 9-bit transmission is selected, the ninth bit
Synchronous data transfers use a separate clock line,
should be loaded in the TX9D bit.
which is synchronous with the data. A device
configured as a master transmits the clock on the TX/ 8. Start transmission by loading data to the
CK line. The TX/CK pin is automatically configured as TXREG register.
an output when the EUSART is configured for
synchronous transmit operation. Serial data bits
change on the leading edge to ensure they are valid at
the trailing edge of each clock. One clock cycle is
generated for each data bit. Only as many clock cycles
are generated as there are data bits.
10.4.1.2 Clock Polarity

A clock polarity option is provided for Microwire
compatibility. Clock polarity is selected with the SCKP
bit of the BAUDCTL register. Setting the SCKP bit sets

PIC16F688
FIGURE 10-10: SYNCHRONOUS TRANSMISSION
RX/DT
pin bit 0 bit 1 bit 2 bit 7 bit 0 bit 1 bit 7
Word 1 Word 2
TX/CK pin
(SCKP = 0)
TX/CK pin
(SCKP = 1)
Write to
TXREG Reg Write Word 1 Write Word 2
TXIF bit
(Interrupt Flag)
TRMT bit
‘1’ ‘1’
TXEN bit
Note: Sync Master mode, SPBRG = 0, continuous transmission of two 8-bit words.
FIGURE 10-11: SYNCHRONOUS TRANSMISSION (THROUGH TXEN)
RX/DT pin bit 0 bit 1 bit 2 bit 6 bit 7
TX/CK pin
Write to
TXREG reg
TXIF bit
TRMT bit
TXEN bit
TABLE 10-7: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION

Value on
Value on
POR, BOR
Resets
Legend: x = unknown, – = unimplemented read as ‘0’. Shaded cells are not used for Synchronous Master Transmission.

PIC16F688
10.4.1.5 Synchronous Master Reception 10.4.1.8 Synchronous Master Reception Set-
Data is received at the RX/DT pin. The RX/DT and TX/ up:
CK pin output drivers are automatically disabled when 1. Initialize the SPBRGH, SPBRG register pair for
the EUSART is configured for synchronous master the appropriate baud rate. Set or clear the
receive operation. BRGH and BRG16 bits, as required, to achieve
In Synchronous mode, reception is enabled by setting the desired baud rate.
either the Single Receive Enable bit (SREN of the 2. Enable the synchronous master serial port by
RCSTA register) or the Continuous Receive Enable bit setting bits SYNC, SPEN and CSRC.
(CREN of the RCSTA register). 3. Ensure bits CREN and SREN are clear.
When SREN is set and CREN is clear, only as many 4. If using interrupts, set the GIE and PEIE bits of
clock cycles are generated as there are data bits in a the INTCON register and set RCIE.
single character. The SREN bit is automatically cleared 5. If 9-bit reception is desired, set bit RX9.
at the completion of one character. When CREN is set, 6. Start reception by setting the SREN bit or for
clocks are continuously generated until CREN is continuous reception, set the CREN bit.
cleared. If CREN is cleared in the middle of a character
7. Interrupt flag bit RCIF will be set when reception
the CK clock stops immediately and the partial charac-
of a character is complete. An interrupt will be
ter is discarded. If SREN and CREN are both set, then
generated if the enable bit RCIE was set.
SREN is cleared at the completion of the first character
and CREN takes precedence. 8. Read the RCSTA register to get the ninth bit (if
enabled) and determine if any error occurred
To initiate reception, set either SREN or CREN. Data is during reception.
sampled at the RX/DT pin on the trailing edge of the
9. Read the 8-bit received data by reading the
TX/CK clock pin and is shifted into the Receive Shift
RCREG register.
Register (RSR). When a complete character is
received into the RSR, the RCIF bit is set and the char- 10. If an overrun error occurs, clear the error by
acter is automatically transferred to the two character either clearing the CREN bit of the RCSTA
receive FIFO. The Least Significant eight bits of the top register or by clearing the SPEN bit which resets
character in the receive FIFO are available in RCREG. the EUSART.
The RCIF bit remains set as long as there are un-read
characters in the receive FIFO.
10.4.1.6 Receive Overrun Error

The receive FIFO buffer can hold two characters. An
overrun error will be generated if a third character, in its
entirety, is received before RCREG is read to access
the FIFO. When this happens the OERR bit of the
RCSTA register is set. Previous data in the FIFO will
not be overwritten. The two characters in the FIFO
buffer can be read, however, no additional characters
will be received until the error is cleared. The OERR bit
can only be cleared by clearing the overrun condition.
If the overrun error occurred when the SREN bit is set
and CREN is clear then the error is cleared by reading
RCREG. If the overrun occurred when the CREN bit is
set then the error condition is cleared by either clearing
the CREN bit of the RCSTA register or by clearing the
SPEN bit which resets the EUSART.
10.4.1.7 Receiving 9-bit Characters

The EUSART supports 9-bit character reception. When
the RX9 bit of the RCSTA register is set the EUSART
will shift 9-bits into the RSR for each character
received. The RX9D bit of the RCSTA register is the
ninth, and Most Significant, data bit of the top unread
character in the receive FIFO. When reading 9-bit data
from the receive FIFO buffer, the RX9D data bit must
be read before reading the 8 Least Significant bits from
the RCREG.

PIC16F688
FIGURE 10-12: SYNCHRONOUS RECEPTION (MASTER MODE, SREN)
RX/DT
pin bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7
TX/CK pin
(SCKP = 0)
TX/CK pin
(SCKP = 1)
Write to
bit SREN
SREN bit
CREN bit ‘0’ ‘0’
RCIF bit
(Interrupt)
Read
RXREG
Note: Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRGH = 0.
TABLE 10-8: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION

Value on
Value on
POR, BOR
Resets
Legend: x = unknown, – = unimplemented read as ‘0’. Shaded cells are not used for Synchronous Master Reception.

PIC16F688
10.4.2 SYNCHRONOUS SLAVE MODE If two words are written to the TXREG and then the
SLEEP instruction is executed, the following will occur:
The following bits are used to configure the EUSART
for Synchronous slave operation: 1. The first character will immediately transfer to
the TSR register and transmit.
• SYNC = 1
2. The second word will remain in TXREG register.
• CSRC = 0
3. The TXIF bit will not be set.
• SREN = 0 (for transmit); SREN = 1 (for receive)
4. After the first character has been shifted out of
• CREN = 0 (for transmit); CREN = 1 (for receive)
TSR, the TXREG register will transfer the second
• SPEN = 1 character to the TSR and the TXIF bit will now be
Setting the SYNC bit of the TXSTA register configures set.
the device for synchronous operation. Clearing the 5. If the PEIE and TXIE bits are set, the interrupt
CSRC bit of the TXSTA register configures the device as will wake the device from Sleep and execute the
a slave. Clearing the SREN and CREN bits of the RCSTA next instruction. If the GIE bit is also set, the
register ensures that the device is in the Transmit mode, program will call the Interrupt Service Routine.
otherwise the device will be configured to receive. Setting
the SPEN bit of the RCSTA register enables the 10.4.2.2 Synchronous Slave Transmission
EUSART. If the RX/DT or TX/CK pins are shared with an Set-up:
analog peripheral the analog I/O functions must be
1. Set the SYNC and SPEN bits and clear the
disabled by clearing the corresponding ANSEL bits.
CSRC bit.
10.4.2.1 EUSART Synchronous Slave 2. Clear the CREN and SREN bits.
Transmit 3. If using interrupts, ensure that the GIE and PEIE
bits of the INTCON register are set and set the
The operation of the Synchronous Master and Slave
TXIE bit.
modes are identical (see Section 10.4.1.3
“Synchronous Master Transmission”), except in the 4. If 9-bit transmission is desired, set the TX9 bit.
case of the Sleep mode. 5. Enable transmission by setting the TXEN bit.
6. If 9-bit transmission is selected, insert the Most
Significant bit into the TX9D bit.
7. Start transmission by writing the Least
Significant 8 bits to the TXREG register.
TABLE 10-9: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION

Value on
Value on
POR, BOR
Resets
Legend: x = unknown, – = unimplemented read as ‘0’. Shaded cells are not used for Synchronous Slave Transmission.

PIC16F688
10.4.2.3 EUSART Synchronous Slave 10.4.2.4 Synchronous Slave Reception Set-
Reception up:
The operation of the Synchronous Master and Slave 1. Set the SYNC and SPEN bits and clear the
modes is identical (Section 10.4.1.5 “Synchronous CSRC bit.
Master Reception”), with the following exceptions: 2. If using interrupts, ensure that the GIE and PEIE
• Sleep bits of the INTCON register are set and set the
• CREN bit is always set, therefore the receiver is RCIE bit.
never Idle 3. If 9-bit reception is desired, set the RX9 bit.
• SREN bit, which is a “don’t care” in Slave mode 4. Set the CREN bit to enable reception.
A character may be received while in Sleep mode by 5. The RCIF bit will be set when reception is
setting the CREN bit prior to entering Sleep. Once the complete. An interrupt will be generated if the
word is received, the RSR register will transfer the data RCIE bit was set.
to the RCREG register. If the RCIE enable bit is set, the 6. If 9-bit mode is enabled, retrieve the Most
interrupt generated will wake the device from Sleep Significant bit from the RX9D bit of the RCSTA
and execute the next instruction. If the GIE bit is also register.
set, the program will branch to the interrupt vector. 7. Retrieve the 8 Least Significant bits from the
receive FIFO by reading the RCREG register.
8. If an overrun error occurs, clear the error by
either clearing the CREN bit of the RCSTA
register or by clearing the SPEN bit which resets
the EUSART.
TABLE 10-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION

Value on
Value on
POR, BOR
Resets
Legend: x = unknown, – = unimplemented read as ‘0’. Shaded cells are not used for Synchronous Slave Reception.

PIC16F688
11.0 SPECIAL FEATURES OF THE The PIC16F688 has two timers that offer necessary
delays on power-up. One is the Oscillator Start-up
CPU Timer (OST), intended to keep the chip in Reset until
The PIC16F688 has a host of features intended to the crystal oscillator is stable. The other is the
maximize system reliability, minimize cost through Power-up Timer (PWRT), which provides a fixed
elimination of external components, provide delay of 64 ms (nominal) on power-up only, designed
power-saving features and offer code protection. to keep the part in Reset while the power supply
stabilizes. There is also circuitry to reset the device if
These features are:
a brown-out occurs, which can use the Power-up
• Reset Timer to provide at least a 64 ms Reset. With these
- Power-on Reset (POR) three functions-on-chip, most applications need no
- Power-up Timer (PWRT) external Reset circuitry.
- Oscillator Start-up Timer (OST) The Sleep mode is designed to offer a very low-current
- Brown-out Reset (BOR) Power-Down mode. The user can wake-up from Sleep
• Interrupts through:
• Watchdog Timer (WDT) • External Reset
• Oscillator Selection • Watchdog Timer Wake-up
• Sleep • An interrupt
• Code Protection Several oscillator options are also made available to
• ID Locations allow the part to fit the application. The INTOSC option
• In-Circuit Serial Programming™ saves system cost while the LP crystal option saves
power. A set of Configuration bits are used to select
various options (see Register 11-1).

PIC16F688
11.1 Configuration Bits
The Configuration bits can be programmed (read as
‘0’), or left unprogrammed (read as ‘1’) to select various
device configurations as shown in Register 11-1.
These bits are mapped in program memory location
2007h.
Note: Address 2007h is beyond the user program

memory space. It belongs to the special
configuration memory space
(2000h-3FFFh), which can be accessed
only during programming. See
“PIC12F6XX/16F6XX Memory Program-
ming Specification” (DS41204) for more
information.

PIC16F688
REGISTER 11-1: CONFIG: CONFIGURATION WORD REGISTER
Reserved Reserved Reserved Reserved FCMEN IESO BOREN1(1) BOREN0(1)

bit 15 bit 8
CPD(2) CP(3) MCLRE(4) PWRTE WDTE FOSC2 FOSC1 FOSC0

bit 7 bit 0
Legend:
R = Readable bit W = Writable bit P = Programmable’ U = Unimplemented bit, read
as ‘0’
bit 15-12 Reserved: Reserved bits. Do Not Use.

bit 11 FCMEN: Fail-Safe Clock Monitor Enabled bit
1 = Fail-Safe Clock Monitor is enabled
0 = Fail-Safe Clock Monitor is disabled
bit 10 IESO: Internal External Switchover bit
1 = Internal External Switchover mode is enabled
0 = Internal External Switchover mode is disabled
bit 9-8 BOREN<1:0>: Brown-out Reset Selection bits(1)
11 = BOR enabled
10 = BOR enabled during operation and disabled in Sleep
01 = BOR controlled by SBOREN bit of the PCON register
00 = BOR disabled
bit 7 CPD: Data Code Protection bit(2)
1 = Data memory code protection is disabled
0 = Data memory code protection is enabled
bit 6 CP: Code Protection bit(2)
1 = Program memory code protection is disabled
0 = Program memory code protection is enabled
bit 5 MCLRE: MCLR Pin Function Select bit(3)
1 = MCLR pin function is MCLR
0 = MCLR pin function is digital input, MCLR internally tied to VDD
bit 4 PWRTE: Power-up Timer Enable bit
1 = PWRT disabled
0 = PWRT enabled
bit 3 WDTE: Watchdog Timer Enable bit
1 = WDT enabled
0 = WDT disabled
bit 2-0 FOSC<2:0>: Oscillator Selection bits
111 = EXTRC oscillator: External RC on RA5/OSC1/CLKIN, CLKOUT function on RA4/OSC2/CLKOUT pin
110 = EXTRCIO oscillator: External RC on RA5/OSC1/CLKIN, I/O function on RA4/OSC2/CLKOUT pin
101 = INTOSC oscillator: CLKOUT function on RA4/OSC2/CLKOUT pin, I/O function on
RA5/OSC1/CLKIN
100 = INTOSCIO oscillator: I/O function on RA4/OSC2/CLKOUT pin, I/O function on
RA5/OSC1/CLKIN
011 = EC: I/O function on RA4/OSC2/CLKOUT pin, CLKIN on RA5/OSC1/CLKIN
010 = HS oscillator: High-speed crystal/resonator on RA4/OSC2/CLKOUT and RA5/OSC1/CLKIN
001 = XT oscillator: Crystal/resonator on RA4/OSC2/CLKOUT and RA5/OSC1/CLKIN
000 = LP oscillator: Low-power crystal on RA4/OSC2/CLKOUT and RA5/OSC1/CLKIN
Note 1: Enabling Brown-out Reset does not automatically enable Power-up Timer.
2: The entire data EEPROM will be erased when the code protection is turned off.
3: The entire program memory will be erased when the code protection is turned off.
4: When MCLR is asserted in INTOSC or RC mode, the internal clock oscillator is disabled.

PIC16F688
11.2 Reset They are not affected by a WDT wake-up since this is
viewed as the resumption of normal operation. TO and
The PIC16F688 differentiates between various kinds of PD bits are set or cleared differently in different Reset
Reset: situations, as indicated in Table 11-2. These bits are
a) Power-on Reset (POR) used in software to determine the nature of the Reset.
b) WDT Reset during normal operation See Table 11-4 for a full description of Reset states of
c) WDT Reset during Sleep all registers.
d) MCLR Reset during normal operation A simplified block diagram of the On-Chip Reset Circuit
e) MCLR Reset during Sleep is shown in Figure 11-1.
f) Brown-out Reset (BOR) The MCLR Reset path has a noise filter to detect and
ignore small pulses. See Section 14.0 “Electrical
Some registers are not affected in any Reset condition;
Specifications” for pulse width specifications.
their status is unknown on POR and unchanged in any
other Reset. Most other registers are reset to a “Reset
state” on:
• Power-on Reset
• MCLR Reset
• MCLR Reset during Sleep
• WDT Reset
• Brown-out Reset (BOR)
FIGURE 11-1: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
External
Reset
MCLR/VPP pin
Sleep
WDT WDT
Module Time-out
Reset
VDD Rise
Detect
Power-on Reset
VDD
Brown-out(1)
Reset BOREN
SBOREN S
OST/PWRT
OST
Chip_Reset
10-bit Ripple Counter R Q
OSC1/
CLKI pin
PWRT
LFINTOSC 11-bit Ripple Counter
Enable PWRT
Enable OST
Note 1: Refer to the Configuration Word register (Register 11-1).

PIC16F688
11.2.1 POWER-ON RESET FIGURE 11-2: RECOMMENDED MCLR
The on-chip POR circuit holds the chip in Reset until CIRCUIT
VDD has reached a high enough level for proper
VDD
operation. To take advantage of the POR, simply PIC16F688
connect the MCLR pin through a resistor to VDD. This R1
will eliminate external RC components usually needed 1 kΩ (or greater)
to create Power-on Reset. A maximum rise time for
VDD is required. See Section 14.0 “Electrical Specifi- MCLR
cations” for details. If the BOR is enabled, the maxi-
mum rise time specification does not apply. The BOR C1
circuitry will keep the device in Reset until VDD reaches 0.1 μF
VBOD (see Section 11.2.4 “Brown-Out Reset (optional, not critical)
(BOR)”).
Note: The POR circuit does not produce an
internal Reset when VDD declines. To
11.2.3 POWER-UP TIMER (PWRT)
re-enable the POR, VDD must reach Vss
for a minimum of 100 μs. The Power-up Timer provides a fixed 64 ms (nominal)
time-out on power-up only, from POR or Brown-out
When the device starts normal operation (exits the
Reset. The Power-up Timer operates from the 31 kHz
Reset condition), device operating parameters (i.e.,
LFINTOSC oscillator. For more information, see
voltage, frequency, temperature, etc.) must be met to
Section 3.5 “Internal Clock Modes”. The chip is kept
ensure operation. If these conditions are not met, the
in Reset as long as PWRT is active. The PWRT delay
device must be held in Reset until the operating
allows the VDD to rise to an acceptable level. A Config-
conditions are met.
uration bit, PWRTE, can disable (if set) or enable (if
For additional information, refer to Application Note cleared or programmed) the Power-up Timer. The
AN607, “Power-up Trouble Shooting” (DS00607). Power-up Timer should be enabled when Brown-out
Reset is enabled, although it is not required.
11.2.2 MCLR
The Power-up Timer delay will vary from chip-to-chip
PIC16F688 has a noise filter in the MCLR Reset path. and vary due to:
The filter will detect and ignore small pulses.
• VDD variation
It should be noted that a WDT Reset does not drive • Temperature variation
MCLR pin low.
• Process variation
The behavior of the ESD protection on the MCLR pin
See DC parameters for details (Section 14.0
has been altered from early devices of this family.
“Electrical Specifications”).
Voltages applied to the pin that exceed its specification
can result in both MCLR Resets and excessive current Note: Voltage spikes below VSS at the MCLR
beyond the device specification during the ESD event. pin, inducing currents greater than 80 mA,
For this reason, Microchip recommends that the MCLR may cause latch-up. Thus, a series resis-
pin no longer be tied directly to VDD. The use of an RC tor of 50-100 Ω should be used when
network, as shown in Figure 11-2, is suggested. applying a “low” level to the MCLR pin,
An internal MCLR option is enabled by clearing the rather than pulling this pin directly to VSS.
MCLRE bit in the Configuration Word register. When
MCLRE = 0, the Reset signal to the chip is generated
internally. When the MCLRE = 1, the RA3/MCLR pin
becomes an external Reset input. In this mode, the
RA3/MCLR pin has a weak pull-up to VDD.

PIC16F688
11.2.4 BROWN-OUT RESET (BOR) This will occur regardless of VDD slew rate. A Reset is
not insured to occur if VDD falls below VBOD for less
The BOREN0 and BOREN1 bits in the Configuration
than parameter (TBOD).
Word register selects one of four BOR modes. Two
modes have been added to allow software or hardware On any Reset (Power-on, Brown-out Reset, Watchdog
control of the BOR enable. When BOREN<1:0> = 01, Timer, etc.), the chip will remain in Reset until VDD rises
the SBOREN bit of the PCON register enables/disables above VBOD (see Figure 11-3). The Power-up Timer
the BOR, allowing it to be controlled in software. By will now be invoked, if enabled and will keep the chip in
selecting BOREN<1:0>, the BOR is automatically Reset an additional 64 ms.
disabled in Sleep to conserve power and enabled on
Note: The Power-up Timer is enabled by the
wake-up. In this mode, the SBOREN bit is disabled.
PWRTE bit in the Configuration Word
See Register 11-1 for the Configuration Word
register.
definition.
If VDD drops below VBOD while the Power-up Timer is
If VDD falls below VBOD for greater than parameter
running, the chip will go back into a Brown-out Reset
(TBOD) (see Section 14.0 “Electrical Specifica-
and the Power-up Timer will be re-initialized. Once VDD
tions”), the Brown-out situation will reset the device.
rises above VBOD, the Power-up Timer will execute a
64 ms Reset.
FIGURE 11-3: BROWN-OUT SITUATIONS
VDD
VBOD
Internal
Reset 64 ms(1)
VDD
VBOD
Internal < 64 ms
Reset 64 ms(1)
VDD
VBOD
Internal
Reset 64 ms(1)
Note 1: 64 ms delay only if PWRTE bit is programmed to ‘0’.

PIC16F688
11.2.5 TIME-OUT SEQUENCE 11.2.6 POWER CONTROL (PCON)
On power-up, the time-out sequence is as follows: first, REGISTER
PWRT time-out is invoked after POR has expired, then The Power Control (PCON) register (address 8Eh) has
OST is activated after the PWRT time-out has expired. two Status bits to indicate what type of Reset that last
The total time-out will vary based on oscillator configu- occurred.
ration and PWRTE bit status. For example, in EC mode
Bit 0 is BOR (Brown-out). BOR is unknown on
with PWRTE bit erased (PWRT disabled), there will be
Power-on Reset. It must then be set by the user and
no time-out at all. Figure 11.2.1, Figure 11-5 and
checked on subsequent Resets to see if BOR = 0,
Figure 11-6 depict time-out sequences. The device can
indicating that a Brown-out has occurred. The BOR
execute code from the INTOSC while OST is active by
Status bit is a “don’t care” and is not necessarily
enabling Two-Speed Start-up or Fail-Safe Monitor (see
predictable if the brown-out circuit is disabled
Section 3.7.2 “Two-Speed Start-up Sequence” and
(BOREN<1:0> = 00 in the Configuration Word
Section 3.8 “Fail-Safe Clock Monitor”).
register).
Since the time-outs occur from the POR pulse, if MCLR
Bit 1 is POR (Power-on Reset). It is a ‘0’ on Power-on
is kept low long enough, the time-outs will expire. Then,
Reset and unaffected otherwise. The user must write a
bringing MCLR high will begin execution immediately
‘1’ to this bit following a Power-on Reset. On a
(see Figure 11-5). This is useful for testing purposes or
subsequent Reset, if POR is ‘0’, it will indicate that a
to synchronize more than one PIC16F688 device
Power-on Reset has occurred (i.e., VDD may have
operating in parallel.
gone too low).
Table 11-5 shows the Reset conditions for some
For more information, see Section 4.2.4 “Ultra
special registers, while Table 11-4 shows the Reset
Low-Power Wake-up” and Section 11.2.4
conditions for all the registers.
“Brown-Out Reset (BOR)”.
TABLE 11-1: TIME-OUT IN VARIOUS SITUATIONS

Power-up Brown-out Reset
Wake-up
Oscillator Configuration
from Sleep
PWRTE = 0 PWRTE = 1 PWRTE = 0 PWRTE = 1
XT, HS, LP TPWRT + 1024 1024 • TOSC TPWRT + 1024 1024 • TOSC 1024 • TOSC
• TOSC • TOSC
RC, EC, INTOSC TPWRT — TPWRT — —
TABLE 11-2: PCON BITS AND THEIR SIGNIFICANCE

POR BOR TO PD Condition
0 u 1 1 Power-on Reset
1 0 1 1 Brown-out Reset
u u 0 u WDT Reset
u u 0 0 WDT Wake-up
u u u u MCLR Reset during normal operation
u u 1 0 MCLR Reset during Sleep

Legend: u = unchanged, x = unknown
TABLE 11-3: SUMMARY OF REGISTERS ASSOCIATED WITH BROWN-OUT RESET

Value on
Value on
Name Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other
POR, BOR
Resets(1)
CONFIG(2) BOREN1 BOREN0 CPD CP MCLRE PWRTE WDTE FOSC2 FOSC1 FOSC0 — —
PCON — — ULPWUE SBOREN — — POR BOR --01 --qq --0u --uu
STATUS IRP RP1 RP0 TO PD Z DC C 0001 1xxx 000q quuu
Legend: u = unchanged, x = unknown, – = unimplemented bit, reads as ‘0’, q = value depends on condition. Shaded cells are not used by BOR.
2: See Configuration Word register (Register 11-1) for operation of all register bits.

PIC16F688
FIGURE 11-4: TIME-OUT SEQUENCE ON POWER-UP (DELAYED MCLR)
VDD
MCLR
Internal POR
TPWRT
PWRT Time-out TOST
OST Time-out
Internal Reset
FIGURE 11-5: TIME-OUT SEQUENCE ON POWER-UP (DELAYED MCLR)
VDD
MCLR
Internal POR
TPWRT
PWRT Time-out TOST
OST Time-out
Internal Reset
FIGURE 11-6: TIME-OUT SEQUENCE ON POWER-UP (MCLR WITH VDD)
VDD
MCLR
Internal POR
TPWRT
PWRT Time-out TOST
OST Time-out
Internal Reset

PIC16F688
TABLE 11-4: INITIALIZATION CONDITION FOR REGISTERS
Wake-up from Sleep
MCLR Reset
Power-on through Interrupt
Register Address WDT Reset
Reset Wake-up from Sleep
Brown-out Reset(1)
through WDT Time-out
W — xxxx xxxx uuuu uuuu uuuu uuuu
INDF 00h/80h/100h/180h xxxx xxxx uuuu uuuu uuuu uuuu
TMR0 01h/101h xxxx xxxx uuuu uuuu uuuu uuuu
PCL 02h/82h/102h/182h 0000 0000 0000 0000 PC + 1(3)
STATUS 03h/83h/103h/183h 0001 1xxx 000q quuu(4) uuuq quuu(4)
FSR 04h/84h/104h/184h xxxx xxxx uuuu uuuu uuuu uuuu
PORTA 05h/105h --x0 x000 --00 0000 --uu uuuu
PORTC 07h/107h --xx 0000 --00 0000 --uu uuuu
PCLATH 0Ah/8Ah/10Ah/18Ah ---0 0000 ---0 0000 ---u uuuu
INTCON 0Bh/8Bh/10Bh/18Bh 0000 000x 0000 000x uuuu uuuu(2)
PIR1 0Ch 0000 0000 0000 0000 uuuu uuuu(2)
TMR1L 0Eh xxxx xxxx uuuu uuuu uuuu uuuu
TMR1H 0Fh xxxx xxxx uuuu uuuu uuuu uuuu
T1CON 10h 0000 0000 uuuu uuuu -uuu uuuu
BAUDCTL 11h 01-0 0-00 01-0 0-00 uu-u u-uu
SPBRGH 12h -000 0000 -000 0000 -uuu uuuu
SPBRG 13h 0000 0000 0000 0000 uuuu uuuu
RCREG 14h 0000 0000 0000 0000 uuuu uuuu
TXREG 15h 0000 0000 0000 0000 uuuu uuuu
TXSTA 16h 0000 0010 0000 0010 uuuu uuuu
RCSTA 17h 000x 000x 000x 000x uuuu uuuu
WDTCON 18h ---0 1000 ---0 1000 ---u uuuu
CMCON0 19h 0000 0000 0000 0000 uuuu uuuu
CMCON1 1Ah ---- --10 ---- --10 ---- --uu
ADRESH 1Eh xxxx xxxx uuuu uuuu uuuu uuuu
ADCON0 1Fh 00-0 0000 00-0 0000 uu-u uuuu
OPTION_REG 81h/181h 1111 1111 1111 1111 uuuu uuuu
TRISA 85h/185h --11 1111 --11 1111 --uu uuuu
TRISC 87h/187h --11 1111 --11 1111 --uu uuuu
PIE1 8Ch 0000 0000 0000 0000 uuuu uuuu
PCON 8Eh --01 --0x --0u --uu(1,5) --uu --uu
Legend: u = unchanged, x = unknown, – = unimplemented bit, reads as ‘0’, q = value depends on condition.
Note 1: If VDD goes too low, Power-on Reset will be activated and registers will be affected differently.
2: One or more bits in INTCON and/or PIR1 will be affected (to cause wake-up).
3: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt
vector (0004h).
4: See Table 11-5 for Reset value for specific condition.
5: If Reset was due to brown-out, then bit 0 = 0. All other Resets will cause bit 0 = u.

PIC16F688
TABLE 11-4: INITIALIZATION CONDITION FOR REGISTERS (CONTINUED)
• MCLR Reset • Wake-up from Sleep
Power-on • WDT Reset through interrupt
Register Address
Reset • Brown-out Reset(1) • Wake-up from Sleep
through WDT time-out
OSCCON 8Fh -110 q000 -110 q000 -uuu uuuu
OSCTUNE 90h ---0 0000 ---u uuuu ---u uuuu
ANSEL 91h 1111 1111 1111 1111 uuuu uuuu
WPUA 95h --11 -111 --11 -111 uuuu uuuu
IOCA 96h --00 0000 --00 0000 --uu uuuu
EEDATH 97h --00 0000 --00 0000 --uu uuuu
EEADRH 98h ---- 0000 ---- 0000 ---- uuuu
VRCON 99h 0-0- 0000 0-0- 0000 u-u- uuuu
EEDAT 9Ah 0000 0000 0000 0000 uuuu uuuu
EEADR 9Bh 0000 0000 0000 0000 uuuu uuuu
EECON1 9Ch x--- x000 u--- q000 u--- uuuu
EECON2 9Dh ---- ---- ---- ---- ---- ----
ADRESL 9Eh xxxx xxxx uuuu uuuu uuuu uuuu
ADCON1 9Fh -000 ---- -000 ---- -uuu ----
Legend: u = unchanged, x = unknown, – = unimplemented bit, reads as ‘0’, q = value depends on condition.
Note 1: If VDD goes too low, Power-on Reset will be activated and registers will be affected differently.
2: One or more bits in INTCON and/or PIR1 will be affected (to cause wake-up).
3: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt
vector (0004h).
4: See Table 11-5 for Reset value for specific condition.
5: If Reset was due to brown-out, then bit 0 = 0. All other Resets will cause bit 0 = u.
TABLE 11-5: INITIALIZATION CONDITION FOR SPECIAL REGISTERS

Program Status PCON
Condition
Counter Register Register
Power-on Reset 000h 0001 1xxx --01 --0x
MCLR Reset during normal operation 000h 000u uuuu --0u --uu
MCLR Reset during Sleep 000h 0001 0uuu --0u --uu
WDT Reset 000h 0000 uuuu --0u --uu
WDT Wake-up PC + 1 uuu0 0uuu --uu --uu
Brown-out Reset 000h 0001 1uuu --01 --10
(1)
Interrupt Wake-up from Sleep PC + 1 uuu1 0uuu --uu --uu
Legend: u = unchanged, x = unknown, – = unimplemented bit, reads as ‘0’.
Note 1: When the wake-up is due to an interrupt and Global Interrupt Enable bit, GIE, is set, the PC is loaded with
the interrupt vector (0004h) after execution of PC + 1.

PIC16F688
11.3 Interrupts For external interrupt events, such as the INT pin or
PORTA change interrupt, the interrupt latency will be
The PIC16F688 has multiple sources of interrupt: three or four instruction cycles. The exact latency
• External Interrupt RA2/INT depends upon when the interrupt event occurs (see
• TMR0 Overflow Interrupt Figure 11-8). The latency is the same for one or
two-cycle instructions. Once in the Interrupt Service
• PORTA Change Interrupts
Routine, the source(s) of the interrupt can be
• 2 Comparator Interrupts determined by polling the interrupt flag bits. The
• A/D Interrupt interrupt flag bit(s) must be cleared in software before
• Timer1 Overflow Interrupt re-enabling interrupts to avoid multiple interrupt
• EEPROM Data Write Interrupt requests.
• Fail-Safe Clock Monitor Interrupt Note 1: Individual interrupt flag bits are set,
• EUSART Receive and Transmit interrupts regardless of the status of their
corresponding mask bit or the GIE bit.
The Interrupt Control (INTCON) register and Peripheral
Interrupt Request 1 (PIR1) register record individual 2: When an instruction that clears the GIE
interrupt requests in flag bits. The INTCON register bit is executed, any interrupts that were
also has individual and global interrupt enable bits. pending for execution in the next cycle
are ignored. The interrupts, which were
A Global Interrupt Enable bit, GIE bit of the INTCON
ignored, are still pending to be serviced
register, enables (if set) all unmasked interrupts, or dis-
when the GIE bit is set again.
ables (if cleared) all interrupts. Individual interrupts can
be disabled through their corresponding enable bits in For additional information on Timer1, A/D or data
the INTCON register and PIE1 register. GIE is cleared EEPROM modules, refer to the respective peripheral
on Reset. section.
The Return from Interrupt instruction, RETFIE, exits
the interrupt routine, as well as sets the GIE bit, which
re-enables unmasked interrupts.
The following interrupt flags are contained in the
INTCON register:
• INT Pin Interrupt
• PORTA Change Interrupt
• TMR0 Overflow Interrupt
The peripheral interrupt flags are contained in the
special register, PIR1. The corresponding interrupt
enable bit is contained in special register, PIE1.
The following interrupt flags are contained in the PIR1
register:
• EEPROM Data Write Interrupt
• A/D Interrupt
• EUSART Receive and Transmit Interrupts
• 2 Comparator Interrupts
• Timer1 Overflow Interrupt
• Fail-Safe Clock Monitor Interrupt
When an interrupt is serviced:
• The GIE is cleared to disable any further interrupt.
• The return address is pushed onto the stack.
• The PC is loaded with 0004h.

PIC16F688
11.3.1 RA2/INT INTERRUPT 11.3.2 TIMER0 INTERRUPT
External interrupt on RA2/INT pin is edge-triggered; An overflow (FFh → 00h) in the TMR0 register will set
either rising if the INTEDG bit of the OPTION register is the T0IF of the INTCON register bit. The interrupt can
set, or falling if the INTEDG bit is clear. When a valid be enabled/disabled by setting/clearing T0IE bit of the
edge appears on the RA2/INT pin, the INTF bit of the INTCON register. See Section 5.0 “Timer0 Module”
INTCON register is set. This interrupt can be disabled for operation of the Timer0 module.
by clearing the INTE control bit of the INTCON register.
The INTF bit must be cleared in software in the Inter- 11.3.3 PORTA INTERRUPT
rupt Service Routine before re-enabling this interrupt. An input change on PORTA change sets the RAIF bit
The RA2/INT interrupt can wake-up the processor from of the INTCON register. The interrupt can be
Sleep if the INTE bit was set prior to going into Sleep. enabled/disabled by setting/clearing the RAIE bit of the
The status of the GIE bit decides whether or not the INTCON register. Plus, individual pins can be
processor branches to the interrupt vector following configured through the IOCA register.
wake-up (0004h). See Section 11.6 “Power-Down
Mode (Sleep)” for details on Sleep and Figure 11-10 Note: If a change on the I/O pin should occur
for timing of wake-up from Sleep through RA2/INT when the read operation is being executed
interrupt. (start of the Q2 cycle), then the RAIF
interrupt flag may not get set.
Note: The ANSEL (91h) and CMCON0 (19h)
registers must be initialized to configure
an analog channel as a digital input. Pins
configured as analog inputs will read ‘0’.
FIGURE 11-7: INTERRUPT LOGIC
IOC-RA0
IOCA0
IOC-RA1
IOCA1
IOC-RA2
IOCA2
IOC-RA3
IOCA3
IOC-RA4
IOCA4
IOC-RA5
IOCA5
T0IF Wake-up (If in Sleep mode)

TXIF T0IE
TXIE
INTF
INTE Interrupt to CPU
TMR1IF RAIF
TMR1IE
RAIE
C1IF
C1IE PEIE
C2IF GIE
C2IE
ADIF
ADIE
EEIF
EEIE
OSFIF
OSFIE
RCIF
RCIE

PIC16F688
FIGURE 11-8: INT PIN INTERRUPT TIMING
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
CLKOUT (3)
(4)
INT pin
(1)
(1)
INTF Flag (5) Interrupt Latency (2)
(INTCON<1>)
GIE bit
(INTCON<7>)
Instruction Flow
PC PC PC + 1 PC + 1 0004h 0005h
Instruction
Fetched Inst (PC) Inst (PC + 1) — Inst (0004h) Inst (0005h)
Instruction Dummy Cycle Dummy Cycle Inst (0004h)

Executed Inst (PC - 1) Inst (PC)
Note 1: INTF flag is sampled here (every Q1).

2: Asynchronous interrupt latency = 3-4 TCY. Synchronous latency = 3 TCY, where TCY = instruction cycle time.
Latency is the same whether Inst (PC) is a single cycle or a two-cycle instruction.
3: CLKOUT is available only in INTOSC and RC Oscillator modes.
4: For minimum width of INT pulse, refer to AC specifications in Section 14.0 “Electrical Specifications”.
5: INTF is enabled to be set any time during the Q4-Q1 cycles.
TABLE 11-6: SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPTS

Value on
Value on
POR, BOR
Resets
Legend: x = unknown, u = unchanged, — = unimplemented read as ‘0’, q = value depends upon condition.
Shaded cells are not used by the Interrupt module.

PIC16F688
11.4 Context Saving During Interrupts
During an interrupt, only the return PC value is saved
on the stack. Typically, users may wish to save key
registers during an interrupt (e.g., W and Status
registers). This must be implemented in software.
Since the lower 16 bytes of all banks are common in the
PIC16F688 (see Figure 2-2), temporary holding
registers, W_TEMP and STATUS_TEMP, should be
placed in here. These 16 locations do not require
banking and therefore, make it easier to context save
and restore. The same code shown in Example 11-1
can be used to:
• Store the W register
• Store the Status register
• Execute the ISR code
• Restore the Status (and Bank Select Bit register)
• Restore the W register
Note: The PIC16F688 normally does not require

saving the PCLATH. However, if
computed GOTO’s are used in the ISR and
the main code, the PCLATH must be
saved and restored in the ISR.
EXAMPLE 11-1: SAVING STATUS AND W REGISTERS IN RAM

MOVWF W_TEMP ;Copy W to TEMP register
SWAPF STATUS,W ;Swap status to be saved into W
;Swaps are used because they do not affect the status bits
MOVWF STATUS_TEMP ;Save status to bank zero STATUS_TEMP register
:
:(ISR) ;Insert user code here
:
SWAPF STATUS_TEMP,W ;Swap STATUS_TEMP register into W
;(sets bank to original state)
MOVWF STATUS ;Move W into STATUS register
SWAPF W_TEMP,F ;Swap W_TEMP
SWAPF W_TEMP,W ;Swap W_TEMP into W

PIC16F688
11.5 Watchdog Timer (WDT) A new prescaler has been added to the path between
the INTRC and the multiplexers used to select the path
The WDT has the following features: for the WDT. This prescaler is 16 bits and can be
• Operates from the LFINTOSC (31 kHz) programmed to divide the INTRC by 32 to 65536,
• Contains a 16-bit prescaler giving the WDT a nominal range of 1 ms to 268s.
• Shares an 8-bit prescaler with Timer0
11.5.2 WDT CONTROL
• Time-out period is from 1 ms to 268 seconds
The WDTE bit is located in the Configuration Word
• Configuration bit and software controlled
register. When set, the WDT runs continuously.
WDT is cleared under certain conditions described in
When the WDTE bit in the Configuration Word register
Table 11-7.
is set, the SWDTEN bit of the WDTCON register has no
effect. If WDTE is clear, then the SWDTEN bit can be
11.5.1 WDT OSCILLATOR
used to enable and disable the WDT. Setting the bit will
The WDT derives its time base from the 31 kHz enable it and clearing the bit will disable it.
LFINTOSC. The LTS bit does not reflect that the
The PSA and PS<2:0> bits of the OPTION register
LFINTOSC is enabled.
have the same function as in previous versions of the
The value of WDTCON is ‘---0 1000’ on all Resets. PIC16F688 family of microcontrollers. See Section 5.0
This gives a nominal time base of 16 ms, which is “Timer0 Module” for more information.
compatible with the time base generated with previous
PIC16F688 microcontroller versions.
Note: When the Oscillator Start-up Timer (OST)
is invoked, the WDT is held in Reset,
because the WDT Ripple Counter is used
by the OST to perform the oscillator delay
count. When the OST count has expired,
the WDT will begin counting (if enabled).
FIGURE 11-9: WATCHDOG TIMER BLOCK DIAGRAM

From TMR0 Clock Source 0
Prescaler(1)
1
16-bit WDT Prescaler
PSA
PS<2:0>
31 kHz
WDTPS<3:0> To TMR0
LFINTOSC Clock
0 1
PSA
WDTE from Configuration Word Register

SWDTEN from WDTCON
WDT Time-out
Note 1: This is the shared Timer0/WDT prescaler. See Section 5.1.3 “Software Programmable Prescaler” for more information.
TABLE 11-7: WDT STATUS

Conditions WDT
WDTE = 0
CLRWDT Command
Cleared
Oscillator Fail Detected
Exit Sleep + System Clock = T1OSC, EXTRC, INTRC, EXTCLK
Exit Sleep + System Clock = XT, HS, LP Cleared until the end of OST

PIC16F688
REGISTER 11-2: WDTCON: WATCHDOG TIMER CONTROL REGISTER

U-0 U-0 U-0 R/W-0 R/W-1 R/W-0 R/W-0 R/W-0
— — — WDTPS3 WDTPS2 WDTPS1 WDTPS0 SWDTEN
bit 7 bit 0
Legend:

bit 4-1 WDTPS<3:0>: Watchdog Timer Period Select bits
Bit Value = Prescale Rate
0000 = 1:32
0001 = 1:64
0010 = 1:128
0011 = 1:256
0100 = 1:512 (Reset value)
0101 = 1:1024
0110 = 1:2048
0111 = 1:4096
1000 = 1:8192
1001 = 1:16384
1010 = 1:32768
1011 = 1:65536
1100 = Reserved
1101 = Reserved
1110 = Reserved
1111 = Reserved
bit 0 SWDTEN: Software Enable or Disable the Watchdog Timer(1)
1 = WDT is turned on
0 = WDT is turned off (Reset value)
Note 1: If WDTE Configuration bit = 1, then WDT is always enabled, irrespective of this control bit. If WDTE
Configuration bit = 0, then it is possible to turn WDT on/off with this control bit.
TABLE 11-8: SUMMARY OF REGISTERS ASSOCIATED WITH WATCHDOG TIMER

Value on
Value on
POR, BOR
Resets
WDTCON — — — WDTPS3 WDTPS2 WSTPS1 WDTPS0 SWDTEN ---0 1000 ---0 1000
CONFIG CPD CP MCLRE PWRTE WDTE FOSC2 FOSC1 FOSC0 — —
Legend: Shaded cells are not used by the Watchdog Timer.
Note 1: See Register 11.0 for operation of all Configuration Word register bits.

PIC16F688
11.6 Power-Down Mode (Sleep) Other peripherals cannot generate interrupts since
during Sleep, no on-chip clocks are present.
The Power-down mode is entered by executing a
SLEEP instruction. When the SLEEP instruction is being executed, the next
instruction (PC + 1) is prefetched. For the device to
If the Watchdog Timer is enabled: wake-up through an interrupt event, the corresponding
• WDT will be cleared but keeps running. interrupt enable bit must be set (enabled). Wake-up is
• PD bit in the Status register is cleared. regardless of the state of the GIE bit. If the GIE bit is
clear (disabled), the device continues execution at the
• TO bit is set.
instruction after the SLEEP instruction. If the GIE bit is
• Oscillator driver is turned off. set (enabled), the device executes the instruction after
• I/O ports maintain the status they had before SLEEP the SLEEP instruction, then branches to the interrupt
was executed (driving high, low or high-impedance). address (0004h). In cases where the execution of the
For lowest current consumption in this mode, all I/O instruction following SLEEP is not desirable, the user
pins should be either at VDD or VSS, with no external should have a NOP after the SLEEP instruction.
circuitry drawing current from the I/O pin, and the Note: If the global interrupts are disabled (GIE is
comparators and CVREF should be disabled. I/O pins cleared), but any interrupt source has both
that are high-impedance inputs should be pulled high its interrupt enable bit and the correspond-
or low externally to avoid switching currents caused by ing interrupt flag bits set, the device will
floating inputs. The T0CKI input should also be at VDD immediately wake-up from Sleep. The
or VSS for lowest current consumption. The SLEEP instruction is completely executed.
contribution from on-chip pull-ups on PORTA should be
considered. The WDT is cleared when the device wakes up from
Sleep, regardless of the source of wake-up.
The MCLR pin must be at a logic high level.
Note: It should be noted that a Reset generated 11.6.2 WAKE-UP USING INTERRUPTS
by a WDT time-out does not drive MCLR When global interrupts are disabled (GIE cleared) and
pin low. any interrupt source has both its interrupt enable bit
and interrupt flag bit set, one of the following will occur:
11.6.1 WAKE-UP FROM SLEEP
• If the interrupt occurs before the execution of a
The device can wake-up from Sleep through one of the SLEEP instruction, the SLEEP instruction will
following events: complete as a NOP. Therefore, the WDT and WDT
1. External Reset input on MCLR pin. prescaler and postscaler (if enabled) will not be
2. Watchdog Timer wake-up (if WDT was cleared, the TO bit will not be set and the PD bit
enabled). will not be cleared.
3. Interrupt from RA2/INT pin, PORTA change or a • If the interrupt occurs during or after the
peripheral interrupt. execution of a SLEEP instruction, the device will
immediately wake-up from Sleep. The SLEEP
The first event will cause a device Reset. The two latter instruction will be completely executed before the
events are considered a continuation of program wake-up. Therefore, the WDT and WDT prescaler
execution. The TO and PD bits in the Status register and postscaler (if enabled) will be cleared, the TO
can be used to determine the cause of device Reset. bit will be set and the PD bit will be cleared.
The PD bit, which is set on power-up, is cleared when
Sleep is invoked. TO bit is cleared if WDT wake-up Even if the flag bits were checked before executing a
occurred. SLEEP instruction, it may be possible for flag bits to
become set before the SLEEP instruction completes.
The following peripheral interrupts can wake the device To determine whether a SLEEP instruction executed,
from Sleep: test the PD bit. If the PD bit is set, the SLEEP instruction
1. Timer1 interrupt. Timer1 must be operating as was executed as a NOP.
an asynchronous counter. To ensure that the WDT is cleared, a CLRWDT instruction
2. A/D conversion (when A/D clock source is FRC). should be executed before a SLEEP instruction.
3. EEPROM write operation completion.
4. Comparator output changes state.
5. Interrupt-on-change.
6. External Interrupt from INT pin.
7. EUSART Receive Interrupt.
8. ULPWU Interrupt.

PIC16F688
FIGURE 11-10: WAKE-UP FROM SLEEP THROUGH INTERRUPT
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
CLKOUT(4) TOST(2)
INT pin
INTF flag
(INTCON<1>) Interrupt Latency (3)
GIE bit
(INTCON<7>) Processor in
Sleep
Instruction Flow
PC PC PC + 1 PC + 2 PC + 2 PC + 2 0004h 0005h
Instruction Inst(PC + 1) Inst(PC + 2) Inst(0004h) Inst(0005h)
Fetched Inst(PC) = Sleep
Instruction Sleep Inst(PC + 1) Dummy Cycle Dummy Cycle
Executed Inst(PC - 1) Inst(0004h)
Note 1: XT, HS or LP Oscillator mode assumed.

2: TOST = 1024 TOSC (drawing not to scale). This delay does not apply to EC and RC Oscillator modes.
3: GIE = 1 assumed. In this case after wake-up, the processor jumps to 0004h. If GIE = 0, execution will continue in-line.
4: CLKOUT is not available in XT, HS, LP or EC Oscillator modes, but shown here for timing reference.
11.7 Code Protection

If the code protection bit(s) have not been
programmed, the on-chip program memory can be
read out using ICSP for verification purposes.
Note: The entire data EEPROM and Flash
program memory will be erased when the
code protection is turned off. See the
“PIC12F6XX/16F6XX Memory Program-
ming Specification” (DS41204) for more
information.
11.8 ID Locations
Four memory locations (2000h-2003h) are designated
as ID locations where the user can store checksum or
other code identification numbers. These locations are
not accessible during normal execution but are
readable and writable during Program/Verify mode.
Only the Least Significant 7 bits of the ID locations are
used.

PIC16F688
11.9 In-Circuit Serial Programming 11.10 In-Circuit Debugger
This allows customers to manufacture boards with Since in-circuit debugging requires access to the data
unprogrammed devices and then program the and MCLR pins, MPLAB® ICD 2 development with an
microcontroller just before shipping the product. This 14-pin device is not practical. A special 20-pin
also allows the most recent firmware or a custom PIC16F688 ICD device is used with MPLAB ICD 2 to
firmware to be programmed. provide separate clock, data and MCLR pins and frees
The device is placed into a Program/Verify mode by all normally available pins to the user.
holding the RA0 and RA1 pins low, while raising the A special debugging adapter allows the ICD device to
MCLR (VPP) pin from VIL to VIHH. See the be used in place of a PIC16F688 device. The
“PIC12F6XX/16F6XX Memory Programming debugging adapter is the only source of the ICD device.
Specification” (DS41204) for more information. RA0 When the ICD pin on the PIC16F688 ICD device is held
becomes the programming data and RA1 becomes the low, the In-Circuit Debugger functionality is enabled.
programming clock. Both RA0 and RA1 are Schmitt This function allows simple debugging functions when
Trigger inputs in Program/Verify mode. used with MPLAB ICD 2. When the microcontroller has
A typical In-Circuit Serial Programming connection is this feature enabled, some of the resources are not
shown in Figure 11-11. available for general use. Table 11-9 shows which
features are consumed by the background debugger:
FIGURE 11-11: TYPICAL IN-CIRCUIT
SERIAL PROGRAMMING TABLE 11-9: DEBUGGER RESOURCES
CONNECTION Resource Description
To Normal I/O pins ICDCLK, ICDDATA

Connections Stack 1 level
External
Connector Program Memory Address 0h must be NOP
* PIC16F688
Signals 700h-7FFh
+5V VDD For more information, see “MPLAB® ICD 2 In-Circuit
0V VSS Debugger User’s Guide” (DS51331), available on
Microchip’s web site (www.microchip.com).
VPP MCLR/VPP/RA3
CLK RA1
FIGURE 11-12: 20-PIN ICD PINOUT
Data I/O RA0
20-Pin PDIP
In-Circuit Debug Device
NC 1 20 ICDCLK
ICDMCLR/VPP 2 19 ICDDATA
* * *
PIC16F688 -ICD
VDD 3 18 Vss
RA5 4 17 RA0
To Normal RA4 5 16 RA1
Connections RA3 6 15 RA2
RC5 7 14 RC0
* Isolation devices (as required) RC4 8 13 RC1
RC3 9 12 RC2
ICD 10 11 NC

PIC16F688
NOTES:

PIC16F688
12.0 INSTRUCTION SET SUMMARY TABLE 12-1: OPCODE FIELD
DESCRIPTIONS
The PIC16F688 instruction set is highly orthogonal and
is comprised of three basic categories: Field Description
• Byte-oriented operations f Register file address (0x00 to 0x7F)
• Bit-oriented operations W Working register (accumulator)
• Literal and control operations b Bit address within an 8-bit file register
Each PIC16 instruction is a 14-bit word divided into an k Literal field, constant data or label
opcode, which specifies the instruction type and one or x Don’t care location (= 0 or 1).
more operands, which further specify the operation of The assembler will generate code with x = 0.
the instruction. The formats for each of the categories It is the recommended form of use for
is presented in Figure 12-1, while the various opcode compatibility with all Microchip software tools.
fields are summarized in Table 12-1.
d Destination select; d = 0: store result in W,
Table 12-2 lists the instructions recognized by the d = 1: store result in file register f.
MPASMTM assembler. Default is d = 1.
For byte-oriented instructions, ‘f’ represents a file PC Program Counter
register designator and ‘d’ represents a destination TO Time-out bit
designator. The file register designator specifies which
file register is to be used by the instruction.
C Carry bit
DC Digit carry bit
The destination designator specifies where the result of
the operation is to be placed. If ‘d’ is zero, the result is Z Zero bit
placed in the W register. If ‘d’ is one, the result is placed PD Power-down bit
in the file register specified in the instruction.
For bit-oriented instructions, ‘b’ represents a bit field FIGURE 12-1: GENERAL FORMAT FOR
designator, which selects the bit affected by the INSTRUCTIONS
operation, while ‘f’ represents the address of the file in
which the bit is located. Byte-oriented file register operations
13 8 7 6 0
For literal and control operations, ‘k’ represents an
OPCODE d f (FILE #)
8-bit or 11-bit constant, or literal value.
d = 0 for destination W
One instruction cycle consists of four oscillator periods; d = 1 for destination f
for an oscillator frequency of 4 MHz, this gives a f = 7-bit file register address
nominal instruction execution time of 1 μs. All
instructions are executed within a single instruction Bit-oriented file register operations
cycle, unless a conditional test is true, or the program 13 10 9 7 6 0
counter is changed as a result of an instruction. When OPCODE b (BIT #) f (FILE #)
this occurs, the execution takes two instruction cycles,
with the second cycle executed as a NOP. b = 3-bit bit address
f = 7-bit file register address
All instruction examples use the format ‘0xhh’ to
represent a hexadecimal number, where ‘h’ signifies a
Literal and control operations
hexadecimal digit.
General
12.1 Read-Modify-Write Operations 13 8 7 0

OPCODE k (literal)
Any instruction that specifies a file register as part of
the instruction performs a Read-Modify-Write (R-M-W) k = 8-bit immediate value
operation. The register is read, the data is modified,
and the result is stored according to either the instruc- CALL and GOTO instructions only
tion, or the destination designator ‘d’. A read operation 13 11 10 0
is performed on a register even if the instruction writes OPCODE k (literal)
to that register.
k = 11-bit immediate value
For example, a CLRF PORTA instruction will read
PORTA, clear all the data bits, then write the result
back to PORTA. This example would have the
unintended consequence of clearing the condition that
set the RAIF flag.

PIC16F688
TABLE 12-2: PIC16F684 INSTRUCTION SET
Mnemonic, 14-Bit Opcode Status
Description Cycles Notes
Operands MSb LSb Affected
BYTE-ORIENTED FILE REGISTER OPERATIONS

ADDWF f, d Add W and f 1 00 0111 dfff ffff C, DC, Z 1, 2
ANDWF f, d AND W with f 1 00 0101 dfff ffff Z 1, 2
CLRF f Clear f 1 00 0001 lfff ffff Z 2
CLRW – Clear W 1 00 0001 0xxx xxxx Z
COMF f, d Complement f 1 00 1001 dfff ffff Z 1, 2
DECF f, d Decrement f 1 00 0011 dfff ffff Z 1, 2
DECFSZ f, d Decrement f, Skip if 0 1(2) 00 1011 dfff ffff 1, 2, 3
INCF f, d Increment f 1 00 1010 dfff ffff Z 1, 2
INCFSZ f, d Increment f, Skip if 0 1(2) 00 1111 dfff ffff 1, 2, 3
IORWF f, d Inclusive OR W with f 1 00 0100 dfff ffff Z 1, 2
MOVF f, d Move f 1 00 1000 dfff ffff Z 1, 2
MOVWF f Move W to f 1 00 0000 lfff ffff
NOP – No Operation 1 00 0000 0xx0 0000
RLF f, d Rotate Left f through Carry 1 00 1101 dfff ffff C 1, 2
RRF f, d Rotate Right f through Carry 1 00 1100 dfff ffff C 1, 2
SUBWF f, d Subtract W from f 1 00 0010 dfff ffff C, DC, Z 1, 2
SWAPF f, d Swap nibbles in f 1 00 1110 dfff ffff 1, 2
XORWF f, d Exclusive OR W with f 1 00 0110 dfff ffff Z 1, 2
BIT-ORIENTED FILE REGISTER OPERATIONS
BCF f, b Bit Clear f 1 01 00bb bfff ffff 1, 2
BSF f, b Bit Set f 1 01 01bb bfff ffff 1, 2
BTFSC f, b Bit Test f, Skip if Clear 1 (2) 01 10bb bfff ffff 3
BTFSS f, b Bit Test f, Skip if Set 1 (2) 01 11bb bfff ffff 3
LITERAL AND CONTROL OPERATIONS
ADDLW k Add literal and W 1 11 111x kkkk kkkk C, DC, Z
ANDLW k AND literal with W 1 11 1001 kkkk kkkk Z
CALL k Call Subroutine 2 10 0kkk kkkk kkkk
CLRWDT – Clear Watchdog Timer 1 00 0000 0110 0100 TO, PD
GOTO k Go to address 2 10 1kkk kkkk kkkk
IORLW k Inclusive OR literal with W 1 11 1000 kkkk kkkk Z
MOVLW k Move literal to W 1 11 00xx kkkk kkkk
RETFIE – Return from interrupt 2 00 0000 0000 1001
RETLW k Return with literal in W 2 11 01xx kkkk kkkk
RETURN – Return from Subroutine 2 00 0000 0000 1000
SLEEP – Go into Standby mode 1 00 0000 0110 0011 TO, PD
SUBLW k Subtract W from literal 1 11 110x kkkk kkkk C, DC, Z
XORLW k Exclusive OR literal with W 1 11 1010 kkkk kkkk Z
Note 1: When an I/O register is modified as a function of itself (e.g., MOVF GPIO, 1), the value used will be that value present
on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and is driven low by an external
device, the data will be written back with a ‘0’.
2: If this instruction is executed on the TMR0 register (and where applicable, d = 1), the prescaler will be cleared if
assigned to the Timer0 module.
3: If the Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second
cycle is executed as a NOP.

PIC16F688
12.2 Instruction Descriptions
ADDLW Add literal and W BCF Bit Clear f
Syntax: [ label ] ADDLW k Syntax: [ label ] BCF f,b

Operands: 0 ≤ k ≤ 255 Operands: 0 ≤ f ≤ 127
0≤b≤7
Operation: (W) + k → (W)
Operation: 0 → (f<b>)
Status Affected: C, DC, Z
Status Affected: None
Description: The contents of the W register
are added to the eight-bit literal ‘k’ Description: Bit ‘b’ in register ‘f’ is cleared.
and the result is placed in the
W register.
ADDWF Add W and f BSF Bit Set f
Syntax: [ label ] ADDWF f,d Syntax: [ label ] BSF f,b

Operands: 0 ≤ f ≤ 127 Operands: 0 ≤ f ≤ 127
d ∈ [0,1] 0≤b≤7
Operation: (W) + (f) → (destination) Operation: 1 → (f<b>)
Status Affected: C, DC, Z Status Affected: None
Description: Add the contents of the W register Description: Bit ‘b’ in register ‘f’ is set.
with register ‘f’. If ‘d’ is ‘0’, the
result is stored in the W register. If
‘d’ is ‘1’, the result is stored back
in register ‘f’.
ANDLW AND literal with W BTFSC Bit Test f, Skip if Clear
Syntax: [ label ] ANDLW k Syntax: [ label ] BTFSC f,b

0≤b≤7
Operation: (W) .AND. (k) → (W)
Operation: skip if (f<b>) = 0
Status Affected: Z
Description: The contents of W register are
AND’ed with the eight-bit literal Description: If bit ‘b’ in register ‘f’ is ‘1’, the next
‘k’. The result is placed in the W instruction is executed.
register. If bit ‘b’, in register ‘f’, is ‘0’, the
next instruction is discarded, and
a NOP is executed instead, making
this a two-cycle instruction.
ANDWF AND W with f
Syntax: [ label ] ANDWF f,d
Operands: 0 ≤ f ≤ 127
d ∈ [0,1]
Operation: (W) .AND. (f) → (destination)
Status Affected: Z
Description: AND the W register with register
‘f’. If ‘d’ is ‘0’, the result is stored in
the W register. If ‘d’ is ‘1’, the
result is stored back in register ‘f’.

PIC16F688
BTFSS Bit Test f, Skip if Set CLRWDT Clear Watchdog Timer
Syntax: [ label ] BTFSS f,b Syntax: [ label ] CLRWDT

Operands: 0 ≤ f ≤ 127 Operands: None
0≤b<7 Operation: 00h → WDT
Operation: skip if (f<b>) = 1 0 → WDT prescaler,
1 → TO
1 → PD
Description: If bit ‘b’ in register ‘f’ is ‘0’, the next
Status Affected: TO, PD
instruction is executed.
If bit ‘b’ is ‘1’, then the next Description: CLRWDT instruction resets the
instruction is discarded and a NOP Watchdog Timer. It also resets the
is executed instead, making this a prescaler of the WDT.
two-cycle instruction. Status bits TO and PD are set.
CALL Call Subroutine COMF Complement f

Syntax: [ label ] CALL k Syntax: [ label ] COMF f,d
Operation: (PC)+ 1→ TOS, d ∈ [0,1]
k → PC<10:0>, Operation: (f) → (destination)
(PCLATH<4:3>) → PC<12:11>
Status Affected: Z
Description: The contents of register ‘f’ are
Description: Call Subroutine. First, return complemented. If ‘d’ is ‘0’, the
address (PC + 1) is pushed onto result is stored in W. If ‘d’ is ‘1’,
the stack. The eleven-bit the result is stored back in
immediate address is loaded into register ‘f’.
PC bits <10:0>. The upper bits of
the PC are loaded from PCLATH.
CALL is a two-cycle instruction.
CLRF Clear f DECF Decrement f

Syntax: [ label ] CLRF f Syntax: [ label ] DECF f,d
Operation: 00h → (f) d ∈ [0,1]
1→Z Operation: (f) - 1 → (destination)
Status Affected: Z Status Affected: Z
Description: The contents of register ‘f’ are Description: Decrement register ‘f’. If ‘d’ is ‘0’,
cleared and the Z bit is set. the result is stored in the W
register. If ‘d’ is ‘1’, the result is
stored back in register ‘f’.
CLRW Clear W
Syntax: [ label ] CLRW
Operands: None
Operation: 00h → (W)
1→Z
Status Affected: Z
Description: W register is cleared. Zero bit (Z)
is set.

PIC16F688
DECFSZ Decrement f, Skip if 0 INCFSZ Increment f, Skip if 0

Syntax: [ label ] DECFSZ f,d Syntax: [ label ] INCFSZ f,d
d ∈ [0,1] d ∈ [0,1]
Operation: (f) - 1 → (destination); Operation: (f) + 1 → (destination),
skip if result = 0 skip if result = 0
Status Affected: None Status Affected: None
Description: The contents of register ‘f’ are Description: The contents of register ‘f’ are
decremented. If ‘d’ is ‘0’, the result incremented. If ‘d’ is ‘0’, the result
is placed in the W register. If ‘d’ is is placed in the W register. If ‘d’ is
‘1’, the result is placed back in ‘1’, the result is placed back in
register ‘f’. register ‘f’.
If the result is ‘1’, the next If the result is ‘1’, the next
instruction is executed. If the instruction is executed. If the
result is ‘0’, then a NOP is result is ‘0’, a NOP is executed
executed instead, making it a instead, making it a two-cycle
two-cycle instruction. instruction.
GOTO Unconditional Branch IORLW Inclusive OR literal with W

Syntax: [ label ] GOTO k Syntax: [ label ] IORLW k
Operands: 0 ≤ k ≤ 2047 Operands: 0 ≤ k ≤ 255
Operation: k → PC<10:0> Operation: (W) .OR. k → (W)
PCLATH<4:3> → PC<12:11> Status Affected: Z
Status Affected: None Description: The contents of the W register are
Description: GOTO is an unconditional branch. OR’ed with the eight-bit literal ‘k’.
The eleven-bit immediate value is The result is placed in the
loaded into PC bits <10:0>. The W register.
upper bits of PC are loaded from
PCLATH<4:3>. GOTO is a
two-cycle instruction.
INCF Increment f IORWF Inclusive OR W with f
Syntax: [ label ] INCF f,d Syntax: [ label ] IORWF f,d

d ∈ [0,1] d ∈ [0,1]
Operation: (f) + 1 → (destination) Operation: (W) .OR. (f) → (destination)
Status Affected: Z Status Affected: Z
Description: The contents of register ‘f’ are Description: Inclusive OR the W register with
incremented. If ‘d’ is ‘0’, the result register ‘f’. If ‘d’ is ‘0’, the result is
is placed in the W register. If ‘d’ is placed in the W register. If ‘d’ is
‘1’, the result is placed back in ‘1’, the result is placed back in
register ‘f’. register ‘f’.

PIC16F688
MOVF Move f MOVWF Move W to f

Syntax: [ label ] MOVF f,d Syntax: [ label ] MOVWF f
d ∈ [0,1] Operation: (W) → (f)
Operation: (f) → (dest) Status Affected: None
Status Affected: Z Description: Move data from W register to
Description: The contents of register f is register ‘f’.
moved to a destination dependent Words: 1
upon the status of d. If d = 0,
destination is W register. If d = 1, Cycles: 1
the destination is file register f Example: MOVW OPTION
itself. d = 1 is useful to test a file F
register since status flag Z is Before Instruction
affected. OPTION = 0xFF
Words: 1 W = 0x4F
Cycles: 1 After Instruction
OPTION = 0x4F
Example: MOVF FSR, 0 W = 0x4F
After Instruction
W = value in FSR
register
Z = 1
MOVLW Move literal to W NOP No Operation

Syntax: [ label ] MOVLW k Syntax: [ label ] NOP
Operands: 0 ≤ k ≤ 255 Operands: None
Operation: k → (W) Operation: No operation
Description: The eight-bit literal ‘k’ is loaded into Description: No operation.
W register. The “don’t cares” will Words: 1
assemble as ‘0’s.
Cycles: 1
Words: 1
Example: NOP
Cycles: 1
Example: MOVLW 0x5A
After Instruction
W = 0x5A

PIC16F688
RETFIE Return from Interrupt RETLW Return with literal in W

Syntax: [ label ] RETFIE Syntax: [ label ] RETLW k
Operands: None Operands: 0 ≤ k ≤ 255
Operation: TOS → PC, Operation: k → (W);
1 → GIE TOS → PC
Description: Return from Interrupt. Stack is Description: The W register is loaded with the
POPed and Top-of-Stack (TOS) is eight bit literal ‘k’. The program
loaded in the PC. Interrupts are counter is loaded from the top of
enabled by setting Global the stack (the return address).
Interrupt Enable bit, GIE This is a two-cycle instruction.
(INTCON<7>). This is a two-cycle Words: 1
instruction.
Cycles: 2
Words: 1
Example: CALL TABLE;W contains
Cycles: 2 table
Example: RETFIE ;offset value
TABLE • ;W now has table value
After Interrupt •
PC = TOS •
GIE = 1 ADDWF PC ;W = offset
RETLW k1 ;Begin table
RETLW k2 ;
•
•
•
RETLW kn ; End of table
Before Instruction
W = 0x07
After Instruction
W = value of k8
RETURN Return from Subroutine

Syntax: [ label ] RETURN
Operands: None
Operation: TOS → PC
Description: Return from subroutine. The stack
is POPed and the top of the stack
(TOS) is loaded into the program
counter. This is a two-cycle
instruction.

PIC16F688
RLF Rotate Left f through Carry SLEEP Enter Sleep mode

Syntax: [ label ] RLF f,d Syntax: [ label ] SLEEP
Operands: 0 ≤ f ≤ 127 Operands: None
d ∈ [0,1] Operation: 00h → WDT,
Operation: See description below 0 → WDT prescaler,
Status Affected: C 1 → TO,
0 → PD
Description: The contents of register ‘f’ are
rotated one bit to the left through Status Affected: TO, PD
the Carry flag. If ‘d’ is ‘0’, the Description: The power-down Status bit, PD is
result is placed in the W register. cleared. Time-out Status bit, TO
If ‘d’ is ‘1’, the result is stored is set. Watchdog Timer and its
back in register ‘f’. prescaler are cleared.
C Register f The processor is put into Sleep
mode with the oscillator stopped.
Words: 1
Cycles: 1
Example: RLF REG1,0
Before Instruction
REG1 = 1110 0110
C = 0
After Instruction
REG1 = 1110 0110
W = 1100 1100
C = 1
RRF Rotate Right f through Carry SUBLW Subtract W from literal

Syntax: [ label ] RRF f,d Syntax: [ label ] SUBLW k
Operands: 0 ≤ f ≤ 127 Operands: 0 ≤ k ≤ 255
d ∈ [0,1] Operation: k - (W) → (W)
Operation: See description below Status Affected: C, DC, Z
Status Affected: C Description: The W register is subtracted (2’s
Description: The contents of register ‘f’ are complement method) from the
rotated one bit to the right through eight-bit literal ‘k’. The result is
the Carry flag. If ‘d’ is ‘0’, the placed in the W register.
result is placed in the W register.
If ‘d’ is ‘1’, the result is placed C=0 W>k
back in register ‘f’. C=1 W≤k
C Register f DC = 0 W<3:0> > k<3:0>
DC = 1 W<3:0> ≤ k<3:0>

PIC16F688
SUBWF Subtract W from f XORLW Exclusive OR literal with W

Syntax: [ label ] SUBWF f,d Syntax: [ label ] XORLW k
Operands: 0 ≤ f ≤ 127 Operands: 0 ≤ k ≤ 255
d ∈ [0,1]
Operation: (W) .XOR. k → (W)
Operation: (f) - (W) → (destination)
Status Affected: Z
Status Affected: C, DC, Z
Description: The contents of the W register
Description: Subtract (2’s complement method) are XOR’ed with the eight-bit
W register from register ‘f’. If ‘d’ is literal ‘k’. The result is placed in
‘0’, the result is stored in the W the W register.
register. If ‘d’ is ‘1’, the result is
stored back in register ‘f.
C=0 W>f
C=1 W≤f
DC = 0 W<3:0> > f<3:0>
DC = 1 W<3:0> ≤ f<3:0>
SWAPF Swap Nibbles in f XORWF Exclusive OR W with f

Syntax: [ label ] SWAPF f,d Syntax: [ label ] XORWF f,d
d ∈ [0,1] d ∈ [0,1]
Operation: (f<3:0>) → (destination<7:4>), Operation: (W) .XOR. (f) → (destination)
(f<7:4>) → (destination<3:0>) Status Affected: Z
Status Affected: None Description: Exclusive OR the contents of the
Description: The upper and lower nibbles of W register with register ‘f’. If ‘d’ is
register ‘f’ are exchanged. If ‘d’ is ‘0’, the result is stored in the W
‘0’, the result is placed in the W register. If ‘d’ is ‘1’, the result is
register. If ‘d’ is ‘1’, the result is stored back in register ‘f’.
placed in register ‘f’.

PIC16F688
NOTES:

PIC16F688
13.0 DEVELOPMENT SUPPORT 13.1 MPLAB Integrated Development
Environment Software
The PIC® microcontrollers are supported with a full
range of hardware and software development tools: The MPLAB IDE software brings an ease of software
• Integrated Development Environment development previously unseen in the 8/16-bit micro-
controller market. The MPLAB IDE is a Windows®
- MPLAB® IDE Software
operating system-based application that contains:
• Assemblers/Compilers/Linkers
• A single graphical interface to all debugging tools
- MPASMTM Assembler
- Simulator
- MPLAB C18 and MPLAB C30 C Compilers
- Programmer (sold separately)
- MPLINKTM Object Linker/
MPLIBTM Object Librarian - Emulator (sold separately)
- MPLAB ASM30 Assembler/Linker/Library - In-Circuit Debugger (sold separately)
• Simulators • A full-featured editor with color-coded context
- MPLAB SIM Software Simulator • A multiple project manager
• Emulators • Customizable data windows with direct edit of
contents
- MPLAB ICE 2000 In-Circuit Emulator
• High-level source code debugging
- MPLAB REAL ICE™ In-Circuit Emulator
• Visual device initializer for easy register
• In-Circuit Debugger
initialization
- MPLAB ICD 2
• Mouse over variable inspection
• Device Programmers
• Drag and drop variables from source to watch
- PICSTART® Plus Development Programmer windows
- MPLAB PM3 Device Programmer • Extensive on-line help
- PICkit™ 2 Development Programmer • Integration of select third party tools, such as
• Low-Cost Demonstration and Development HI-TECH Software C Compilers and IAR
Boards and Evaluation Kits C Compilers
The MPLAB IDE allows you to:
• Edit your source files (either assembly or C)
• One touch assemble (or compile) and download
to PIC MCU emulator and simulator tools
(automatically updates all project information)
• Debug using:
- Source files (assembly or C)
- Mixed assembly and C
- Machine code
MPLAB IDE supports multiple debugging tools in a
single development paradigm, from the cost-effective
simulators, through low-cost in-circuit debuggers, to
full-featured emulators. This eliminates the learning
curve when upgrading to tools with increased flexibility
and power.

PIC16F688
13.2 MPASM Assembler 13.5 MPLAB ASM30 Assembler, Linker
The MPASM Assembler is a full-featured, universal
and Librarian
macro assembler for all PIC MCUs. MPLAB ASM30 Assembler produces relocatable
The MPASM Assembler generates relocatable object machine code from symbolic assembly language for
files for the MPLINK Object Linker, Intel® standard HEX dsPIC30F devices. MPLAB C30 C Compiler uses the
files, MAP files to detail memory usage and symbol assembler to produce its object file. The assembler
reference, absolute LST files that contain source lines generates relocatable object files that can then be
and generated machine code and COFF files for archived or linked with other relocatable object files and
debugging. archives to create an executable file. Notable features
of the assembler include:
The MPASM Assembler features include:
• Support for the entire dsPIC30F instruction set
• Integration into MPLAB IDE projects
• Support for fixed-point and floating-point data
• User-defined macros to streamline
assembly code • Command line interface
• Conditional assembly for multi-purpose • Rich directive set
source files • Flexible macro language
• Directives that allow complete control over the • MPLAB IDE compatibility
assembly process
13.6 MPLAB SIM Software Simulator
13.3 MPLAB C18 and MPLAB C30 The MPLAB SIM Software Simulator allows code
C Compilers development in a PC-hosted environment by simulat-
The MPLAB C18 and MPLAB C30 Code Development ing the PIC MCUs and dsPIC® DSCs on an instruction
Systems are complete ANSI C compilers for level. On any given instruction, the data areas can be
Microchip’s PIC18 and PIC24 families of microcon- examined or modified and stimuli can be applied from
trollers and the dsPIC30 and dsPIC33 family of digital a comprehensive stimulus controller. Registers can be
signal controllers. These compilers provide powerful logged to files for further run-time analysis. The trace
integration capabilities, superior code optimization and buffer and logic analyzer display extend the power of
ease of use not found with other compilers. the simulator to record and track program execution,
actions on I/O, most peripherals and internal registers.
For easy source level debugging, the compilers provide
symbol information that is optimized to the MPLAB IDE The MPLAB SIM Software Simulator fully supports
debugger. symbolic debugging using the MPLAB C18 and
MPLAB C30 C Compilers, and the MPASM and
MPLAB ASM30 Assemblers. The software simulator
13.4 MPLINK Object Linker/ offers the flexibility to develop and debug code outside
MPLIB Object Librarian of the hardware laboratory environment, making it an
The MPLINK Object Linker combines relocatable excellent, economical software development tool.
objects created by the MPASM Assembler and the
MPLAB C18 C Compiler. It can link relocatable objects
from precompiled libraries, using directives from a
linker script.
The MPLIB Object Librarian manages the creation and
modification of library files of precompiled code. When
a routine from a library is called from a source file, only
the modules that contain that routine will be linked in
with the application. This allows large libraries to be
used efficiently in many different applications.
The object linker/library features include:
• Efficient linking of single libraries instead of many
smaller files
• Enhanced code maintainability by grouping
related modules together
• Flexible creation of libraries with easy module
listing, replacement, deletion and extraction

PIC16F688
13.7 MPLAB ICE 2000 13.9 MPLAB ICD 2 In-Circuit Debugger
High-Performance Microchip’s In-Circuit Debugger, MPLAB ICD 2, is a
In-Circuit Emulator powerful, low-cost, run-time development tool,
The MPLAB ICE 2000 In-Circuit Emulator is intended connecting to the host PC via an RS-232 or high-speed
to provide the product development engineer with a USB interface. This tool is based on the Flash PIC
complete microcontroller design tool set for PIC MCUs and can be used to develop for these and other
microcontrollers. Software control of the MPLAB ICE PIC MCUs and dsPIC DSCs. The MPLAB ICD 2 utilizes
2000 In-Circuit Emulator is advanced by the MPLAB the in-circuit debugging capability built into the Flash
Integrated Development Environment, which allows devices. This feature, along with Microchip’s In-Circuit
editing, building, downloading and source debugging Serial ProgrammingTM (ICSPTM) protocol, offers cost-
from a single environment. effective, in-circuit Flash debugging from the graphical
user interface of the MPLAB Integrated Development
The MPLAB ICE 2000 is a full-featured emulator Environment. This enables a designer to develop and
system with enhanced trace, trigger and data monitor- debug source code by setting breakpoints, single step-
ing features. Interchangeable processor modules allow ping and watching variables, and CPU status and
the system to be easily reconfigured for emulation of peripheral registers. Running at full speed enables
different processors. The architecture of the MPLAB testing hardware and applications in real time. MPLAB
ICE 2000 In-Circuit Emulator allows expansion to ICD 2 also serves as a development programmer for
support new PIC microcontrollers. selected PIC devices.
The MPLAB ICE 2000 In-Circuit Emulator system has
been designed as a real-time emulation system with 13.10 MPLAB PM3 Device Programmer
advanced features that are typically found on more
expensive development tools. The PC platform and The MPLAB PM3 Device Programmer is a universal,
Microsoft® Windows® 32-bit operating system were CE compliant device programmer with programmable
chosen to best make these features available in a voltage verification at VDDMIN and VDDMAX for
simple, unified application. maximum reliability. It features a large LCD display
(128 x 64) for menus and error messages and a modu-
lar, detachable socket assembly to support various
13.8 MPLAB REAL ICE In-Circuit
package types. The ICSP™ cable assembly is included
Emulator System as a standard item. In Stand-Alone mode, the MPLAB
MPLAB REAL ICE In-Circuit Emulator System is PM3 Device Programmer can read, verify and program
Microchip’s next generation high-speed emulator for PIC devices without a PC connection. It can also set
Microchip Flash DSC and MCU devices. It debugs and code protection in this mode. The MPLAB PM3
programs PIC® Flash MCUs and dsPIC® Flash DSCs connects to the host PC via an RS-232 or USB cable.
with the easy-to-use, powerful graphical user interface of The MPLAB PM3 has high-speed communications and
the MPLAB Integrated Development Environment (IDE), optimized algorithms for quick programming of large
included with each kit. memory devices and incorporates an SD/MMC card for
file storage and secure data applications.
The MPLAB REAL ICE probe is connected to the design
engineer’s PC using a high-speed USB 2.0 interface and
is connected to the target with either a connector
compatible with the popular MPLAB ICD 2 system
(RJ11) or with the new high-speed, noise tolerant, Low-
Voltage Differential Signal (LVDS) interconnection
(CAT5).
MPLAB REAL ICE is field upgradeable through future
firmware downloads in MPLAB IDE. In upcoming
releases of MPLAB IDE, new devices will be supported,
and new features will be added, such as software break-
points and assembly code trace. MPLAB REAL ICE
offers significant advantages over competitive emulators
including low-cost, full-speed emulation, real-time
variable watches, trace analysis, complex breakpoints, a
ruggedized probe interface and long (up to three meters)
interconnection cables.

PIC16F688
13.11 PICSTART Plus Development 13.13 Demonstration, Development and
Programmer Evaluation Boards
The PICSTART Plus Development Programmer is an A wide variety of demonstration, development and
easy-to-use, low-cost, prototype programmer. It evaluation boards for various PIC MCUs and dsPIC
connects to the PC via a COM (RS-232) port. MPLAB DSCs allows quick application development on fully func-
Integrated Development Environment software makes tional systems. Most boards include prototyping areas for
using the programmer simple and efficient. The adding custom circuitry and provide application firmware
PICSTART Plus Development Programmer supports and source code for examination and modification.
most PIC devices in DIP packages up to 40 pins. The boards support a variety of features, including LEDs,
Larger pin count devices, such as the PIC16C92X and temperature sensors, switches, speakers, RS-232
PIC17C76X, may be supported with an adapter socket. interfaces, LCD displays, potentiometers and additional
The PICSTART Plus Development Programmer is CE EEPROM memory.
compliant.
The demonstration and development boards can be
used in teaching environments, for prototyping custom
13.12 PICkit 2 Development Programmer
circuits and for learning about various microcontroller
The PICkit™ 2 Development Programmer is a low-cost applications.
programmer and selected Flash device debugger with In addition to the PICDEM™ and dsPICDEM™ demon-
an easy-to-use interface for programming many of stration/development board series of circuits, Microchip
Microchip’s baseline, mid-range and PIC18F families has a line of evaluation kits and demonstration software
of Flash memory microcontrollers. The PICkit 2 Starter for analog filter design, KEELOQ® security ICs, CAN,
Kit includes a prototyping development board, twelve IrDA®, PowerSmart battery management, SEEVAL®
sequential lessons, software and HI-TECH’s PICC™ evaluation system, Sigma-Delta ADC, flow rate
Lite C compiler, and is designed to help get up to speed sensing, plus many more.
quickly using PIC® microcontrollers. The kit provides
everything needed to program, evaluate and develop Check the Microchip web page (www.microchip.com)
applications using Microchip’s powerful, mid-range for the complete list of demonstration, development
Flash memory family of microcontrollers. and evaluation kits.

PIC16F688
14.0 ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings(†)

Ambient temperature under bias..........................................................................................................-40° to +125°C
Storage temperature ........................................................................................................................ -65°C to +150°C
Voltage on VDD with respect to VSS ................................................................................................... -0.3V to +6.5V
Voltage on MCLR with respect to Vss ............................................................................................... -0.3V to +13.5V
Voltage on all other pins with respect to VSS ........................................................................... -0.3V to (VDD + 0.3V)
Total power dissipation(1) ............................................................................................................................... 800 mW
Maximum current out of VSS pin ...................................................................................................................... 95 mA
Maximum current into VDD pin ......................................................................................................................... 95 mA
Input clamp current, IIK (VI < 0 or VI > VDD)...............................................................................................................± 20 mA
Output clamp current, IOK (Vo < 0 or Vo >VDD).........................................................................................................± 20 mA
Maximum output current sunk by any I/O pin.................................................................................................... 25 mA
Maximum output current sourced by any I/O pin .............................................................................................. 25 mA
Maximum current sunk by PORTA and PORTC (combined) ........................................................................... 90 mA
Maximum current sourced PORTA and PORTC (combined) ........................................................................... 90 mA
Note 1: Power dissipation is calculated as follows: PDIS = VDD x {IDD – ∑ IOH} + ∑ {(VDD – VOH) x IOH} + ∑(VOl x
IOL).
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure above maximum rating conditions for
extended periods may affect device reliability.

PIC16F688
FIGURE 14-1: PIC16F688 VOLTAGE-FREQUENCY GRAPH,
-40°C ≤ TA ≤ +125°C
5.5
5.0
4.5
VDD (V)
4.0
3.5
3.0
2.5
2.0
0 8 10 20
Frequency (MHz)
Note 1: The shaded region indicates the permissible combinations of voltage and frequency.
FIGURE 14-2: HFINTOSC FREQUENCY ACCURACY OVER DEVICE VDD AND TEMPERATURE
125
± 5%
85
Temperature (°C)
± 2%
60
25 ± 1%
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)

PIC16F688
14.1 DC Characteristics: PIC16F688 -I (Industrial)
PIC16F688 -E (Extended)
Standard Operating Conditions (unless otherwise stated)
DC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for industrial
-40°C ≤ TA ≤ +125°C for extended
Param
Sym Characteristic Min Typ† Max Units Conditions
No.
VDD Supply Voltage 2.0 — 5.5 V FOSC < = 8 MHz: HFINTOSC, EC
D001 2.0 — 5.5 V FOSC < = 4 MHz
D001C 3.0 — 5.5 V FOSC < = 10 MHz
D001D 4.5 — 5.5 V FOSC < = 20 MHz
D002* VDR RAM Data Retention 1.5 — — V Device in Sleep mode
Voltage(1)
D003 VPOR VDD Start Voltage to — VSS — V See Section 11.2.1 “Power-On Reset”
ensure internal Power-on for details.
Reset signal
D004* SVDD VDD Rise Rate to ensure 0.05 — — V/ms See Section 11.2.1 “Power-On Reset”
internal Power-on Reset for details.
signal
* These parameters are characterized but not tested.
† Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: This is the limit to which VDD can be lowered in Sleep mode without losing RAM data.

PIC16F688

Param Conditions
Device Characteristics Min Typ† Max Units
No. VDD Note
D010 Supply Current (IDD) (1, 2)
— 16 23 μA 2.0 FOSC = 32 kHz
— 27 38 μA 3.0 LP Oscillator mode
— 47 75 μA 5.0
D011* — 180 250 μA 2.0 FOSC = 1 MHz
— 290 400 μA 3.0 XT Oscillator mode
— 490 650 μA 5.0
D012 — 280 380 μA 2.0 FOSC = 4 MHz
— 480 670 μA 3.0 XT Oscillator mode
— 0.9 1.4 mA 5.0
D013* — 130 220 μA 2.0 FOSC = 1 MHz
— 215 360 μA 3.0 EC Oscillator mode
— 360 520 μA 5.0
D014 — 220 340 μA 2.0 FOSC = 4 MHz
— 375 550 μA 3.0 EC Oscillator mode
— 0.65 1.0 mA 5.0
D015 — 8 20 μA 2.0 FOSC = 31 kHz
— 16 40 μA 3.0 LFINTOSC mode
— 31 65 μA 5.0
D016* — 320 400 μA 2.0 FOSC = 4 MHz
— 490 640 μA 3.0 HFINTOSC mode
— 0.87 1.2 mA 5.0
D017 — 0.5 0.7 mA 2.0 FOSC = 8 MHz
— 0.78 1 mA 3.0 HFINTOSC mode
— 1.43 1.8 mA 5.0
D018 — 340 580 μA 2.0 FOSC = 4 MHz
— 550 950 μA 3.0 EXTRC mode(3)
— 0.92 1.6 mA 5.0
D019 — 2.9 3.7 mA 4.5 FOSC = 20 MHz
— 3.1 3.8 mA 5.0 HS Oscillator mode
Note 1: The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave,
from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O
pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have
an impact on the current consumption.
3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can
be extended by the formula IR = VDD/2REXT (mA) with REXT in kΩ.

PIC16F688
14.3 DC Characteristics: PIC16F688-I (Industrial)

DC CHARACTERISTICS
Operating temperature -40°C ≤ TA ≤ +85°C for industrial
Param Conditions
No. VDD Note
D020 Power-down Base — 0.05 1.2 μA 2.0 WDT, BOR, Comparators, VREF and
Current(IPD)(2) — 0.15 1.5 μA 3.0 T1OSC disabled
— 0.35 1.8 μA 5.0
— 150 500 nA 3.0 -40°C ≤ TA ≤ +25°C
D021 — 1.0 2.2 μA 2.0 WDT Current(1)
— 2.0 4.0 μA 3.0
— 3.0 7.0 μA 5.0
D022 — 42 60 μA 3.0 BOR Current(1)
— 85 122 μA 5.0
D023 — 32 45 μA 2.0 Comparator Current(1), both
— 60 78 μA 3.0 comparators enabled
— 120 160 μA 5.0
D024 — 30 36 μA 2.0 CVREF Current(1) (high range)
— 45 55 μA 3.0
— 75 95 μA 5.0
D025* — 39 47 μA 2.0 CVREF Current(1) (low range)
— 59 72 μA 3.0
— 98 124 μA 5.0
D026 — 4.5 7.0 μA 2.0 T1OSC Current(1), 32.768 kHz
— 5.0 8.0 μA 3.0
— 6.0 12 μA 5.0
D027 — 0.30 1.6 μA 3.0 A/D Current(1), no conversion in
— 0.36 1.9 μA 5.0 progress
Note 1: The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this
peripheral is enabled. The peripheral Δ current can be determined by subtracting the base IDD or IPD
current from this limit. Max values should be used when calculating total current consumption.
2: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is
measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD.

PIC16F688
14.4 DC Characteristics: PIC16F688-E (Extended)

DC CHARACTERISTICS
Operating temperature -40°C ≤ TA ≤ +125°C for extended
Param Conditions
No. VDD Note
D020E Power-down Base — 0.05 9 μA 2.0 WDT, BOR, Comparators, VREF and
Current (IPD)(2) — 0.15 11 μA 3.0 T1OSC disabled
— 0.35 15 μA 5.0
D021E — 1 28 μA 2.0 WDT Current(1)
— 2 30 μA 3.0
— 3 35 μA 5.0
D022E — 42 65 μA 3.0 BOR Current(1)
— 85 127 μA 5.0
D023E — 32 45 μA 2.0 Comparator Current(1), both
— 60 78 μA 3.0 comparators enabled
— 120 160 μA 5.0
D024E — 30 70 μA 2.0 CVREF Current(1) (high range)
— 45 90 μA 3.0
— 75 120 μA 5.0
D025E* — 39 91 μA 2.0 CVREF Current(1) (low range)
— 59 117 μA 3.0
— 98 156 μA 5.0
D026E — 4.5 25 μA 2.0 T1OSC Current(1), 32.768 kHz
— 5 30 μA 3.0
— 6 40 μA 5.0
D027E — 0.30 12 μA 3.0 A/D Current(1), no conversion in
— 0.36 16 μA 5.0 progress
Note 1: The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this
peripheral is enabled. The peripheral Δ current can be determined by subtracting the base IDD or IPD
current from this limit. Max values should be used when calculating total current consumption.
2: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is
measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD.

PIC16F688

Param
No.
VIL Input Low Voltage
I/O Port:
D030 with TTL buffer Vss — 0.8 V 4.5V ≤ VDD ≤ 5.5V
D030A Vss — 0.15 VDD V 2.0V ≤ VDD ≤ 4.5V
D031 with Schmitt Trigger buffer Vss — 0.2 VDD V 2.0V ≤ VDD ≤ 5.5V
(1)
D032 MCLR, OSC1 (RC mode) VSS — 0.2 VDD V
D033 OSC1 (XT and LP modes) VSS — 0.3 V
D033A OSC1 (HS mode) VSS — 0.3 VDD V
VIH Input High Voltage
I/O ports: —
D040 with TTL buffer 2.0 — VDD V 4.5V ≤ VDD ≤ 5.5V
D040A 0.25 VDD + 0.8 — VDD V 2.0V ≤ VDD ≤ 4.5V
D041 with Schmitt Trigger buffer 0.8 VDD — VDD V 2.0V ≤ VDD ≤ 5.5V
D042 MCLR 0.8 VDD — VDD V
D043 OSC1 (XT and LP modes) 1.6 — VDD V
D043A OSC1 (HS mode) 0.7 VDD — VDD V
D043B OSC1 (RC mode) 0.9 VDD — VDD V (Note 1)
(2)
IIL Input Leakage Current
D060 I/O ports — ± 0.1 ±1 μA VSS ≤ VPIN ≤ VDD,
Pin at high-impedance
D061 MCLR(3) — ± 0.1 ±5 μA VSS ≤ VPIN ≤ VDD
D063 OSC1 — ± 0.1 ±5 μA VSS ≤ VPIN ≤ VDD, XT, HS and
LP oscillator configuration
D070* IPUR PORTA Weak Pull-up Current 50 250 400 μA VDD = 5.0V, VPIN = VSS
VOL Output Low Voltage(5)
D080 I/O ports — — 0.6 V IOL = 8.5 mA, VDD = 4.5V (Ind.)
VOH Output High Voltage(5)
D090 I/O ports VDD – 0.7 — — V IOH = -3.0 mA, VDD = 4.5V (Ind.)
† Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended to use an external
clock in RC mode.
2: Negative current is defined as current sourced by the pin.
3: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent
normal operating conditions. Higher leakage current may be measured at different input voltages.
4: See Section 9.0 “Data EEPROM and Flash Program Memory Control” for additional information.
5: Including OSC2 in CLKOUT mode.

PIC16F688
PIC16F688 -E (Extended) (Continued)
Param
No.
D100 IULP Ultra Low-Power Wake-Up — 200 — nA See Application Note AN879,
Current “Using the Microchip Ultra
Low-Power Wake-up Module”
(DS00879)
Capacitive Loading Specs on
Output Pins
D101* COSC2 OSC2 pin — — 15 pF In XT, HS and LP modes when
external clock is used to drive
OSC1
D101A* CIO All I/O pins — — 50 pF
Data EEPROM Memory
D120 ED Byte Endurance 100K 1M — E/W -40°C ≤ TA ≤ +85°C
D120A ED Byte Endurance 10K 100K — E/W +85°C ≤ TA ≤ +125°C
D121 VDRW VDD for Read/Write VMIN — 5.5 V Using EECON1 to read/write
VMIN = Minimum operating
voltage
D122 TDEW Erase/Write Cycle Time — 5 6 ms
D123 TRETD Characteristic Retention 40 — — Year Provided no other specifications
are violated
D124 TREF Number of Total Erase/Write 1M 10M — E/W -40°C ≤ TA ≤ +85°C
Cycles before Refresh(4)
Program Flash Memory
D130 EP Cell Endurance 10K 100K — E/W -40°C ≤ TA ≤ +85°C
D130A ED Cell Endurance 1K 10K — E/W +85°C ≤ TA ≤ +125°C
D131 VPR VDD for Read VMIN — 5.5 V VMIN = Minimum operating
voltage
D132 VPEW VDD for Erase/Write 4.5 — 5.5 V
D133 TPEW Erase/Write cycle time — 2 2.5 ms
D134 TRETD Characteristic Retention 40 — — Year Provided no other specifications
are violated
† Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended to use an external
clock in RC mode.
2: Negative current is defined as current sourced by the pin.
3: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent
normal operating conditions. Higher leakage current may be measured at different input voltages.
4: See Section 9.0 “Data EEPROM and Flash Program Memory Control” for additional information.
5: Including OSC2 in CLKOUT mode.

PIC16F688
14.6 Thermal Considerations
Operating temperature -40°C ≤ TA ≤ +125°C
Param
Sym Characteristic Typ Units Conditions
No.
TH01 θJA Thermal Resistance 69.8 C/W 14-pin PDIP package
Junction to Ambient 85.0 C/W 14-pin SOIC package
100.4 C/W 14-pin TSSOP package
46.3 C/W 16-pin QFN 4x0.9mm package
TH02 θJC Thermal Resistance 32.5 C/W 14-pin PDIP package
Junction to Case 31.0 C/W 14-pin SOIC package
31.7 C/W 14-pin TSSOP package
2.6 C/W 16-pin QFN 4x0.9mm package
TH03 TJ Junction Temperature 150 C For derated power calculations
TH04 PD Power Dissipation — W PD = PINTERNAL + PI/O
TH05 PINTERNAL Internal Power Dissipation — W PINTERNAL = IDD x VDD
(NOTE 1)
TH06 PI/O I/O Power Dissipation — W PI/O = Σ (IOL * VOL) + Σ (IOH * (VDD - VOH))
TH07 PDER Derated Power — W PDER = (TJ - TA)/θJA
(NOTE 2, 3)
Note 1: IDD is current to run the chip alone without driving any load on the output pins.
2: TA = Ambient Temperature.
3: Maximum allowable power dissipation is the lower value of either the absolute maximum total power
dissipation or derated power (PDER).

PIC16F688
14.7 Timing Parameter Symbology
The timing parameter symbols have been created with
one of the following formats:
1. TppS2ppS
2. TppS
T
F Frequency T Time
Lowercase letters (pp) and their meanings:
pp
cc CCP1 osc OSC1
ck CLKOUT rd RD
cs CS rw RD or WR
di SDI sc SCK
do SDO ss SS
dt Data in t0 T0CKI
io I/O PORT t1 T1CKI
mc MCLR wr WR
Uppercase letters and their meanings:
S
F Fall P Period
H High R Rise
I Invalid (High-impedance) V Valid
L Low Z High-impedance
FIGURE 14-3: LOAD CONDITIONS
Load Condition
Pin CL
VSS
Legend: CL = 50 pF for all pins

15 pF for OSC2 output

PIC16F688
14.8 AC Characteristics: PIC16F688 (Industrial, Extended)
FIGURE 14-4: CLOCK TIMING
Q4 Q1 Q2 Q3 Q4 Q1
OSC1/CLKIN
OS02
OS04 OS04
OS03
OSC2/CLKOUT
(LP, XT, HS Modes)
OSC2/CLKOUT
(CLKOUT Mode)
TABLE 14-1: CLOCK OSCILLATOR TIMING REQUIREMENTS

Param
No.
OS01 FOSC External CLKIN Frequency(1) DC — 37 kHz LP Oscillator mode
DC — 4 MHz XT Oscillator mode
DC — 20 MHz HS Oscillator mode
DC — 20 MHz EC Oscillator mode
Oscillator Frequency(1) — 32.768 — kHz LP Oscillator mode
0.1 — 4 MHz XT Oscillator mode
1 — 20 MHz HS Oscillator mode
DC — 4 MHz RC Oscillator mode
OS02 TOSC External CLKIN Period(1) 27 — • μs LP Oscillator mode
250 — • ns XT Oscillator mode
50 — • ns HS Oscillator mode
50 — • ns EC Oscillator mode
Oscillator Period(1) — 30.5 — μs LP Oscillator mode
250 — 10,000 ns XT Oscillator mode
50 — 1,000 ns HS Oscillator mode
250 — — ns RC Oscillator mode
OS03 TCY Instruction Cycle Time(1) 200 TCY DC ns TCY = 4/FOSC
OS04* TosH, External CLKIN High, 2 — — μs LP oscillator
TosL External CLKIN Low 100 — — ns XT oscillator
20 — — ns HS oscillator
OS05* TosR, External CLKIN Rise, 0 — • ns LP oscillator
TosF External CLKIN Fall 0 — • ns XT oscillator
0 — • ns HS oscillator
† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and
are not tested.
Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are
based on characterization data for that particular oscillator type under standard operating conditions with the
device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or
higher than expected current consumption. All devices are tested to operate at “min” values with an external
clock applied to OSC1 pin. When an external clock input is used, the “max” cycle time limit is “DC” (no clock) for
all devices.

PIC16F688
TABLE 14-2: OSCILLATOR PARAMETERS
Operating Temperature -40°C ≤ TA ≤ +125°C
Param Freq
No. Tolerance
OS06 TWARM Internal Oscillator Switch — — — 2 TOSC Slowest clock
when running(3)
OS07 TSC Fail-Safe Sample Clock — — 21 — ms LFINTOSC/64
Period(1)
OS08 HFOSC Internal Calibrated ±1% 7.92 8.0 8.08 MHz VDD = 3.5V, 25°C
HFINTOSC Frequency(2) ±2% 7.84 8.0 8.16 MHz 2.5V ≤ VDD ≤ 5.5V,
0°C ≤ TA ≤ +85°C
±5% 7.60 8.0 8.40 MHz 2.0V ≤ VDD ≤ 5.5V,
-40°C ≤ TA ≤ +85°C (Ind.),
-40°C ≤ TA ≤ +125°C (Ext.)
OS09* LFOSC Internal Uncalibrated — 15 31 45 kHz
LFINTOSC Frequency
OS10* TIOSC HFINTOSC Oscillator — 5.5 12 24 μs VDD = 2.0V, -40°C to +85°C
ST Wake-up from Sleep — 3.5 7 14 μs VDD = 3.0V, -40°C to +85°C
Start-up Time
— 3 6 11 μs VDD = 5.0V, -40°C to +85°C
† Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are
based on characterization data for that particular oscillator type under standard operating conditions with the
device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or
higher than expected current consumption. All devices are tested to operate at “min” values with an external
clock applied to the OSC1 pin. When an external clock input is used, the “max” cycle time limit is “DC” (no clock)
for all devices.
2: To ensure these oscillator frequency tolerances, VDD and VSS must be capacitively decoupled as close to the
device as possible. 0.1 μF and 0.01 μF values in parallel are recommended.
3: By design.

PIC16F688
FIGURE 14-5: CLKOUT AND I/O TIMING
Cycle Write Fetch Read Execute

Q4 Q1 Q2 Q3
FOSC
OS11 OS12
OS20
CLKOUT OS21
OS19 OS16 OS18
OS13 OS17
I/O pin
(Input)
OS15 OS14
I/O pin Old Value New Value
(Output)
OS18, OS19
TABLE 14-3: CLKOUT AND I/O TIMING PARAMETERS

Param
No.
OS11 TOSH2CKL FOSC↑ to CLKOUT↓ (1) — — 70 ns VDD = 5.0V
OS12 TOSH2CKH FOSC↑ to CLKOUT↑ (1) — — 72 ns VDD = 5.0V
OS13 TCKL2IOV CLKOUT↓ to Port out valid(1) — — 20 ns
OS14 TIOV2CKH Port input valid before CLKOUT↑(1) TOSC + 200 ns — — ns
OS15* TOSH2IOV FOSC↑ (Q1 cycle) to Port out valid — 50 70 ns VDD = 5.0V
OS16 TOSH2IOI FOSC↑ (Q2 cycle) to Port input invalid 50 — — ns VDD = 5.0V
(I/O in hold time)
OS17 TIOV2OSH Port input valid to FOSC↑ (Q2 cycle) 20 — — ns
(I/O in setup time)
OS18 TIOR Port output rise time(2) — 15 72 ns VDD = 2.0V
— 10 32 VDD = 5.0V
OS19 TIOF Port output fall time(2) — 28 55 ns VDD = 2.0V
— 15 30 VDD = 5.0V
OS20* TINP INT pin input high or low time 25 — — ns
OS21* TRAP PORTA interrupt-on-change new input TCY — — ns
level time
† Data in “Typ” column is at 5.0V, 25°C unless otherwise stated.
Note 1: Measurements are taken in RC mode where CLKOUT output is 4 x TOSC.
2: Includes OSC2 in CLKOUT mode.

PIC16F688
FIGURE 14-6: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND
POWER-UP TIMER TIMING
VDD
MCLR
30
Internal
POR
33
PWRT
Time-out 32
OSC
Start-Up Time
Internal Reset(1)
Watchdog Timer
Reset(1)
31
34
34
I/O pins
Note 1: Asserted low.
FIGURE 14-7: BROWN-OUT RESET TIMING AND CHARACTERISTICS
VDD
VBOR + VHYST
VBOR
(Device in Brown-out Reset) (Device not in Brown-out Reset)
37
Reset
(due to BOR) 33*
* 64 ms delay only if PWRTE bit in the Configuration Word register is programmed to ‘0’.

PIC16F688
TABLE 14-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER
AND BROWN-OUT RESET PARAMETERS
Param
No.
30 TMCL MCLR Pulse Width (low) 2 — — μs VDD = 5V, -40°C to +85°C

5 — — μs VDD = 5V
31 TWDT Watchdog Timer Time-out 10 16 29 ms VDD = 5V, -40°C to +85°C
Period (No Prescaler) 10 16 31 ms VDD = 5V
32 TOST Oscillation Start-up Timer — 1024 — TOSC (NOTE 3)
Period(1, 2)
33* TPWRT Power-up Timer Period 40 65 140 ms
34* TIOZ I/O High-impedance from — — 2.0 μs
MCLR Low or Watchdog Timer
Reset
35 VBOR Brown-out Reset Voltage 2.0 — 2.2 V (NOTE 4)
36* VHYST Brown-out Reset Hysteresis — 50 — mV
37* TBOR Brown-out Reset Minimum 100 — — μs VDD ≤ VBOR
Detection Period
† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance
Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values
are based on characterization data for that particular oscillator type under standard operating conditions
with the device executing code. Exceeding these specified limits may result in an unstable oscillator oper-
ation and/or higher than expected current consumption. All devices are tested to operate at “min” values
with an external clock applied to the OSC1 pin. When an external clock input is used, the “max” cycle time
limit is “DC” (no clock) for all devices.
2: By design.
3: Period of the slower clock.
4: To ensure these voltage tolerances, VDD and VSS must be capacitively decoupled as close to the device as
possible. 0.1 μF and 0.01 μF values in parallel are recommended.

PIC16F688
FIGURE 14-8: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS
T0CKI
40 41
42
T1CKI
45 46
47 49
TMR0 or
TMR1
TABLE 14-5: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS

Param
No.
40* TT0H T0CKI High Pulse Width No Prescaler 0.5 TCY + 20 — — ns
With Prescaler 10 — — ns
41* TT0L T0CKI Low Pulse Width No Prescaler 0.5 TCY + 20 — — ns
With Prescaler 10 — — ns
42* TT0P T0CKI Period Greater of: — — ns N = prescale value
20 or TCY + 40 (2, 4, ..., 256)
N
45* TT1H T1CKI High Synchronous, No Prescaler 0.5 TCY + 20 — — ns
Time Synchronous, 15 — — ns
with Prescaler
Asynchronous 30 — — ns
46* TT1L T1CKI Low Synchronous, No Prescaler 0.5 TCY + 20 — — ns
Time Synchronous, 15 — — ns
with Prescaler
47* TT1P T1CKI Input Synchronous Greater of: — — ns N = prescale value
Period 30 or TCY + 40 (1, 2, 4, 8)
N
48 FT1 Timer1 Oscillator Input Frequency Range — 32.768 — kHz
(oscillator enabled by setting bit T1OSCEN)
49* TCKEZTMR1 Delay from External Clock Edge to Timer 2 TOSC — 7 TOSC — Timers in Sync
Increment mode
† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.

PIC16F688
TABLE 14-6: COMPARATOR SPECIFICATIONS
Param
Sym Characteristics Min Typ† Max Units Comments
No.
CM01 VOS Input Offset Voltage — ± 5.0 ± 10 mV (VDD - 1.5)/2
CM02 VCM Input Common Mode Voltage 0 — VDD – 1.5 V
CM03* CMRR Common Mode Rejection Ratio +55 — — dB
CM04* TRT Response Time Falling — 150 600 ns (NOTE 1)
Rising — 200 1000 ns
CM05* TMC2COV Comparator Mode Change to — — 10 μs
Output Valid
† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance
Note 1: Response time is measured with one comparator input at (VDD - 1.5)/2 - 100 mV to (VDD - 1.5)/2 + 20 mV.
TABLE 14-7: COMPARATOR VOLTAGE REFERENCE (CVREF) SPECIFICATIONS

Param
Sym Characteristics Min Typ† Max Units Comments
No.
CV01* CLSB Step Size(2) — VDD/24 — V Low Range (VRR = 1)
— VDD/32 — V High Range (VRR = 0)
CV02* CACC Absolute Accuracy — — ± 1/2 LSb Low Range (VRR = 1)
— — ± 1/2 LSb High Range (VRR = 0)
CV03* CR Unit Resistor Value (R) — 2k — Ω
CV04* CST Settling Time(1) — — 10 μs
† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design
guidance only and are not tested.
Note 1: Settling time measured while VRR = 1 and VR<3:0> transitions from ‘0000’ to ‘1111’.
2: See Section 7.10 “Comparator Voltage Reference” for more information.

PIC16F688
TABLE 14-8: PIC16F688 A/D CONVERTER (ADC) CHARACTERISTICS
Param
No.
AD01 NR Resolution — — 10 bits bit
AD02 EIL Integral Error — — ±1 LSb VREF = 5.12V
AD03 EDL Differential Error — — ±1 LSb No missing codes to 10 bits
VREF = 5.12V
AD04 EOFF Offset Error — — ±1 LSb VREF = 5.12V
AD07 EGN Gain Error — — ±1 LSb VREF = 5.12V
AD06 VREF Reference Voltage(1) 2.2 — — V
AD06A 2.7 VDD Absolute minimum to ensure 1 LSb
accuracy
AD07 VAIN Full-Scale Range VSS — VREF V
AD08 ZAIN Recommended — — 10 kΩ
Impedance of Analog
Voltage Source
AD09* IREF VREF Input Current(1) 10 — 1000 μA During VAIN acquisition.
Based on differential of VHOLD to VAIN.
— — 50 μA During A/D conversion cycle.
Note 1: ADC VREF is from external VREF or VDD pin, whichever is selected as reference input.

PIC16F688
TABLE 14-9: PIC16F688 A/D CONVERSION REQUIREMENTS
Param
No.
AD130* TAD A/D Clock Period 1.6 — 9.0 μs TOSC-based, VREF ≥ 3.0V
3.0 — 9.0 μs TOSC-based, VREF full range
A/D Internal RC ADCS<1:0> = 11 (ADRC mode)
Oscillator Period 3.0 6.0 9.0 μs At VDD = 2.5V
1.6 4.0 6.0 μs At VDD = 5.0V
AD131 TCNV Conversion Time — 11 — TAD Set GO/DONE bit to new data in A/D
(not including Result register
Acquisition Time)(1)
AD132* TACQ Acquisition Time 11.5 — μs
AD133* TAMP Amplifier Settling Time — — 5 μs
AD134 TGO Q4 to A/D Clock Start — TOSC/2 — —
— TOSC/2 + TCY — — If the A/D clock source is selected as

RC, a time of TCY is added before the
A/D clock starts. This allows the SLEEP
instruction to be executed.
Note 1: ADRESH and ADRESL registers may be read on the following TCY cycle.
2: See Section 8.3 “A/D Acquisition Requirements” for minimum conditions.

PIC16F688
FIGURE 14-9: PIC16F688 A/D CONVERSION TIMING (NORMAL MODE)
BSF ADCON0, GO
1 TCY
AD134 (TOSC/2(1))
AD131
Q4
AD130
A/D CLK
A/D Data 9 8 7 6 3 2 1 0
ADRES OLD_DATA NEW_DATA
ADIF 1 TCY
GO DONE
Sampling Stopped
Sample AD132
Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the
SLEEP instruction to be executed.
FIGURE 14-10: PIC16F688 A/D CONVERSION TIMING (SLEEP MODE)
BSF ADCON0, GO
AD134 (TOSC/2 + TCY(1)) 1 TCY
AD131
Q4
AD130
A/D CLK
A/D Data 9 8 7 6 3 2 1 0
ADRES OLD_DATA NEW_DATA
ADIF 1 TCY
GO DONE
AD132 Sampling Stopped

Sample
Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the
SLEEP instruction to be executed.

PIC16F688
15.0 DC AND AC CHARACTERISTICS GRAPHS AND TABLES
The graphs and tables provided in this section are for design guidance and are not tested.
In some graphs or tables, the data presented are outside specified operating range (i.e., outside specified VDD
range). This is for information only and devices are ensured to operate properly only within the specified range.
Note: The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein are
not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore, outside the warranted range.
“Typical” represents the mean of the distribution at 25°C. “Maximum” or “minimum” represents
(mean + 3σ) or (mean - 3σ) respectively, where σ is a standard deviation, over each temperature range.
FIGURE 15-1: TYPICAL IDD vs. FOSC OVER VDD (EC MODE)
3.5
Typical: Statistical Mean @25°C

3.0 Maximum: Mean (Worst-case Temp) + 3σ 5.5V
(-40°C to 125°C)
5.0V
2.5
2.0 4.0V
IDD (mA)
1.5
3.0V
1.0
2.0V
0.5
0.0
1 MHz 2 MHz 4 MHz 6 MHz 8 MHz 10 MHz 12 MHz 14 MHz 16 MHz 18 MHz 20 MHz
FOSC

PIC16F688
FIGURE 15-2: MAXIMUM IDD vs. FOSC OVER VDD (EC MODE)
EC Mode
4.0
5.5V
3.5 Maximum: Mean (Worst-case Temp) + 3σ
(-40°C to 125°C)
5.0V
3.0
2.5
4.0V
IDD (mA)
2.0
3.0V
1.5
2.0V
1.0
0.5
0.0
1 MHz 2 MHz 4 MHz 6 MHz 8 MHz 10 MHz 12 MHz 14 MHz 16 MHz 18 MHz 20 MHz
FOSC
FIGURE 15-3: TYPICAL IDD vs. FOSC OVER VDD (HS MODE)
4.0
Typical: Statistical Mean @25°C 5.5V
(-40°C to 125°C)
Temp)+ 5,0V
3.0
4.5V
2.5
IDD (mA)
2.0
1.5
4.0V
1.0 3.5V
3.0V
0.5
0.0
4 MHz 10 MHz 16 MHz 20 MHz
FOSC

PIC16F688
FIGURE 15-4: MAXIMUM IDD vs. FOSC OVER VDD (HS MODE)
5.0
4.5 Typical:
Typical: Statistical
Statistical Mean
Mean @25°C
@25×C
Maximum: 5.5V
Maximum: Mean
Mean (Worst-case
(Worst CaseTemp) + 3σ
4.0 (-40°C
Temp)+to 3 125°C)
5.0V
3.5
4.5V
3.0
IDD (mA)
2.5
2.0
4.0V
1.5
3.5V
3.0V
1.0
0.5
0.0
4 MHz 10 MHz 16 MHz 20 MHz
FOSC
FIGURE 15-5: TYPICAL IDD vs. VDD OVER FOSC (XT MODE)
1200
@25°C
Typical: Statistical Mean @25×C
Maximum: Mean (Worst Case Temp)
(Worst-case Temp) ++ 3σ
1000
800
IDD (uA)
600
4 MHz
400
1 MHz
200
0
2 2.5 3 3.5 4 4.5 5 5.5
VDD (V)

PIC16F688
FIGURE 15-6: MAXIMUM IDD vs. VDD OVER FOSC (XT MODE)
1,800
1,600 Typical: Statistical Mean @25°C

Maximum: Mean (Worst-case Temp) + 3σ
(-40°C to 125°C)
1,400
1,200
1,000
IDD (uA)
800 4 MHz
600
400 1 MHz
200
0
2 2.5 3 3.5 4 4.5 5 5.5
VDD (V)
FIGURE 15-7: TYPICAL IDD vs. VDD OVER FOSC (EXTRC MODE)
1,200
Typical:
Typical:Statistical
StatisticalMean
Mean@25×C
@25°C
Maximum: Mean (Worst Case Temp) +
1,000 3
((-40°C
40×Ct to 125°C)
125×C)
800 4 MHz
IDD (uA)
600
1 MHz
400
200
0
2 2.5 3 3.5 4 4.5 5 5.5
VDD (V)

PIC16F688
FIGURE 15-8: MAXIMUM IDD vs. VDD (EXTRC MODE)
2,000

Maximum:
Maximum:MeanMean(Worst-case
(Worst CaseTemp)
Temp)+ +3s3
(-40×Ctoto125°C)
(-40°C 125×C)
1,600
1,400
4 MHz
1,200
IDD (uA)
1,000
800
1 MHz
600
400
200
0
2 2.5 3 3.5 4 4.5 5 5.5
VDD (V)
FIGURE 15-9: IDD vs. VDD OVER FOSC (LFINTOSC MODE, 31 kHz)
LFINTOSC Mode, 31KHZ
80
70 Maximum: Mean (Worst-case Temp) + 3σ
(-40°C to 125°C)
60
50
Maximum
IDD (μA)
40
30
Typical
20
10
0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)

PIC16F688
FIGURE 15-10: IDD vs. VDD (LP MODE)
90
(-40°C to 125°C)
70
60 32 kHz Maximum
50
IDD (uA)
40
30
32 kHz Typical
20
10
0
2 2.5 3 3.5 4 4.5 5 5.5
VDD (V)
FIGURE 15-11: TYPICAL IDD vs. FOSC OVER VDD (HFINTOSC MODE)
HFINTOSC
1,800
Typical: Statistical Mean @25°C 5.5V
1,600 Maximum: Mean (Worst-case Temp) + 3σ
(-40°C to 125°C)
5.0V
1,400
1,200
4.0V
1,000
IDD (uA)
3.0V
800
600
2.0V
400
200
0
125 kHz 250 kHz 500 kHz 1 MHz 2 MHz 4 MHz 8 MHz
VDD (V)

PIC16F688
FIGURE 15-12: MAXIMUM IDD vs. FOSC OVER VDD (HFINTOSC MODE)
2,500
Typical: Statistical Mean @ 25°C

Maximum: Mean (Worst-case Temp) +3σ
(-40°C to 125°C) 5.5V
2,000
5.0V
1,500
IDD (uA)
4.0V
3.0V
1,000
2.0V
500
0
125 kHz 250 kHz 500 kHz 1 MHz 2 MHz 4 MHz 8 MHz
VDD (V)
FIGURE 15-13: TYPICAL IPD vs. VDD (SLEEP MODE, ALL PERIPHERALS DISABLED)
Typical
(Sleep Mode all Peripherals Disabled)
0.45

0.40
(-40°C to 125°C)
0.35
0.30
0.25
IPD (μA)
0.20
0.15
0.10
0.05
0.0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)

PIC16F688
FIGURE 15-14: MAXIMUM IPD vs. VDD (SLEEP MODE, ALL PERIPHERALS DISABLED)
Maximum
(Sleep Mode all Peripherals Disabled)
18.0
16.0 Maximum: Mean +
Maximum: Mean 3σ
(Worst-case Temp) + 3σ
(-40°C to 125°C)
14.0
Max. 125°C
12.0
10.0
IPD (μA)
8.0
6.0
4.0
Max. 85°C
2.0
0.0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
FIGURE 15-15: COMPARATOR IPD vs. VDD (BOTH COMPARATORS ENABLED)
180
160 Typical: Statistical Mean @25°C

140 (-40°C to 125°C)
120
Maximum
100
IPD (μA)
Typical
80
60
40
20
0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)

PIC16F688
FIGURE 15-16: BOR IPD vs. VDD OVER TEMPERATURE
160

(-40°C to 125°C)
120
100
Maximum
IPD (μA)
80
Typical
60
40
20
0
2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
FIGURE 15-17: TYPICAL WDT IPD vs. VDD (25°C)
3.0
2.5
2.0
IPD (uA)
1.5
1.0
0.5
0.0
2.0V 2.5V 3.0V 3.5V 4.0V 4.5V 5.0V 5.5V
VDD (V)

PIC16F688
FIGURE 15-18: MAXIMUM WDT IPD vs. VDD OVER TEMPERATURE
40.0
35.0
Max. 125°C
30.0
25.0
IPD (uA)
20.0
15.0
10.0
Max. 85°C
5.0
0.0
2.0V 2.5V 3.0V 3.5V 4.0V 4.5V 5.0V 5.5V
VDD (V)
FIGURE 15-19: WDT PERIOD vs. VDD OVER TEMPERATURE
30
Maximum: Mean + 3σ (-40°C to 125°C)
28 Maximum: Mean + 3σ
Max. (125°C)
26
Max. (85°C)
24
22
Time (ms)
20
Typical
18
16
14
Minimum
12
10
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)

PIC16F688
FIGURE 15-20: WDT PERIOD vs. TEMPERATURE
Vdd = 5V
30
28 Maximum: Mean + 3σ
26
Maximum
24
22
Time (ms)
20
Typical
18
16
Minimum
14
12
10
-40°C 25°C 85°C 125°C
Temperature (°C)
FIGURE 15-21: CVREF IPD vs. VDD OVER TEMPERATURE (HIGH RANGE)
High Range
140
Maximum: Mean + 3σ (-40°C to 125°C)
120
100
Max. 125°C
80
IPD (μA)
Max. 85°C
60
Typical
40
20
0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)

PIC16F688
FIGURE 15-22: CVREF IPD vs. VDD OVER TEMPERATURE (LOW RANGE)
180
(-40°C to 125°C)
140
120
Max. 125°C
100
IPD (μA)
Max. 85°C
80
Typical
60
40
20
0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
FIGURE 15-23: VOL vs. IOL OVER TEMPERATURE (VDD = 3.0V)

(VDD = 3V, -40×C TO 125×C)
0.8

0.7 Maximum: Mean + 3σ
Max. 125°C
0.6
0.5 Max. 85°C

VOL (V)
0.4
0.3 Typical 25°C
0.2
Min. -40°C
0.1
0.0
5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0
IOL (mA)

PIC16F688
FIGURE 15-24: VOL vs. IOL OVER TEMPERATURE (VDD = 5.0V)
0.45

0.40 Typical:
Maximum: MeanStatistical
+ 3σ Mean
Maximum: Means + 3
Max. 125°C
0.35
Max. 85°C
0.30
0.25
VOL (V)
Typ. 25°C
0.20
0.15 Min. -40°C
0.10
0.05
0.00
5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0
IOL (mA)
FIGURE 15-25: VOH vs. IOH OVER TEMPERATURE (VDD = 3.0V)
3.5
3.0
Max. -40°C
Typ. 25°C
2.5
Min. 125°C
2.0
VOH (V)
1.5

(-40°C to 125°C)
0.5
0.0
0.0 -0.5 -1.0 -1.5 -2.0 -2.5 -3.0 -3.5 -4.0
IOH (mA)

PIC16F688
FIGURE 15-26: VOH vs. IOH OVER TEMPERATURE
( , (VDD = 5.0V)
)
5.5
5.0
Max. -40°C
Typ. 25°C
4.5
VOH (V)
Min. 125°C
4.0

(-40°C to 125°C)
3.0
0.0 -0.5 -1.0 -1.5 -2.0 -2.5 -3.0 -3.5 -4.0 -4.5 -5.0
IOH (mA)
FIGURE 15-27: TTL INPUT THRESHOLD VIN vs. VDD OVER TEMPERATURE
(TTL Input, -40×C TO 125×C)
1.7

(-40°C to 125°C)
Max. -40°C
1.3
Typ. 25°C
VIN (V)
1.1
Min. 125°C
0.9
0.7
0.5
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)

PIC16F688
FIGURE 15-28: SCHMITT TRIGGER INPUT THRESHOLD VIN vs. VDD OVER TEMPERATURE
(ST Input, -40×C TO 125×C)
4.0
VIH Max. 125°C
(-40°C to 125°C)
VIH Min. -40°C
3.0
2.5
VIN (V)
2.0
VIL Max. -40°C
1.5 VIL Min. 125°C
1.0
0.5
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
FIGURE 15-29: T1OSC IPD vs. VDD OVER TEMPERATURE (32 kHz)
45.0
40.0 Maximum: Mean
Maximum: Mean (Worst-case
(-40×C
+ Temp) + 3σ
3 to 125×C)
(-40°C to 125°C)
35.0
Max. 125°C
30.0
25.0
IPD (mA)
20.0
15.0
Max. 85°C
10.0
5.0
Typ. 25°C
0.0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)

PIC16F688
FIGURE 15-30: COMPARATOR RESPONSE TIME (RISING EDGE)
531 806
1000
900
800 Max. 125°C
700
Response Time (nS)
600 Note: VCM = VDD - 1.5V)/2

V+ input = VCM Max. 85°C
500 V- input = Transition from VCM + 100MV to VCM - 20MV
400
300
200 Typ. 25°C

Min. -40°C
100
0
2.0 2.5 4.0 5.5
VDD (V)
FIGURE 15-31: COMPARATOR RESPONSE TIME (FALLING EDGE)
1000
900
800 Max. 125°C
700
Response Time (nS)
600 Note: VCM = VDD - 1.5V)/2

V+ input = VCM Max. 85°C
500 V- input = Transition from VCM - 100MV to VCM + 20MV
400
300
200 Typ. 25°C

Min. -40°C
100
0
2.0 2.5 4.0 5.5
VDD (V)

PIC16F688
FIGURE 15-32: LFINTOSC FREQUENCY vs. VDD OVER TEMPERATURE (31 kHz)
LFINTOSC 31Khz
45,000
40,000
Max. -40°C
35,000
Typ. 25°C
30,000
Frequency (Hz)
25,000
20,000 Min. 85°C
Min. 125°C
15,000

5,000 (-40°C to 125°C)
0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
FIGURE 15-33: ADC CLOCK PERIOD vs. VDD OVER TEMPERATURE

125°C
(-40°C to 125°C)
6
85°C
Time (μs)
25°C
4
-40°C
0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)

PIC16F688
FIGURE 15-34: TYPICAL HFINTOSC START-UP TIMES vs. VDD OVER TEMPERATURE
16

85°C (-40°C to 125°C)
12
25°C
10
Time (μs)
-40°C
0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
FIGURE 15-35: MAXIMUM HFINTOSC START-UP TIMES vs. VDD OVER TEMPERATURE
-40C to +85C
25

(-40°C to 125°C)
15
Time (μs)
85°C
25°C
10
-40°C
0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)

PIC16F688
FIGURE 15-36: MINIMUM HFINTOSC START-UP TIMES vs. VDD OVER TEMPERATURE
-40C to +85C
10
9
(-40°C to 125°C)
7
85°C
6
Time (μs)
25°C
5
-40°C
4
0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
FIGURE 15-37: TYPICAL HFINTOSC FREQUENCY CHANGE vs. VDD (25°C)
2
Change from Calibration (%)
-1
-2
-3
-4
-5
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)

PIC16F688
FIGURE 15-38: TYPICAL HFINTOSC FREQUENCY CHANGE OVER DEVICE VDD (85°C)
3
-1
-2
-3
-4
-5
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
FIGURE 15-39: TYPICAL HFINTOSC FREQUENCY CHANGE vs. VDD (125°C)
3
-1
-2
-3
-4
-5
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)

PIC16F688
FIGURE 15-40: TYPICAL HFINTOSC FREQUENCY CHANGE vs. VDD (-40°C)
3
-1
-2
-3
-4
-5
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)

PIC16F688
NOTES:

PIC16F688
16.0 PACKAGING INFORMATION
16.1 Package Marking Information
14-Lead PDIP (Skinny DIP) Example
XXXXXXXXXXXXXX PIC16F688
XXXXXXXXXXXXXX -I/P e3
YYWWNNN 0610017
14-Lead SOIC (3.90 mm) Example
XXXXXXXXXXX PIC16C688
XXXXXXXXXXX -I/SL e3
YYWWNNN 0610017
14-Lead TSSOP Example
XXXXXXXX 688/ST e3
YYWW 0610
NNN 017
16-Lead QFN Example
XXXXXX 16F688
XXXXXX -I/ML e3
YWWNNN 610017
Legend: XX...X Customer-specific information

Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code
e3 Pb-free JEDEC designator for Matte Tin (Sn)
* This package is Pb-free. The Pb-free JEDEC designator ( e3 )
can be found on the outer packaging for this package.
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
* Standard PIC® device marking consists of Microchip part number, year code, week code, and traceability
code. For PIC device marking beyond this, certain price adders apply. Please check with your Microchip
Sales Office. For QTP devices, any special marking adders are included in QTP price.

PIC16F688
16.2 Package Details
The following sections give the technical details of the packages.

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%% 255)))& &5 4
NOTE 1
E1
1 2 3
A A2
L c
A1
b1
b e eB
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% 1+
% % < <
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*$%+ % %
, & "-" %!"& "$ % ! "$ % ! %#". "
& "% -/0
1+21 & %#%! ))% !%%
) +01

PIC16F688
14-Lead Plastic Small Outline (SL) – Narrow, 3.90 mm Body [SOIC]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
E1
NOTE 1
1 2 3
e
h
b
α
h
φ c
A A2
A1 L
L1 β
Units MILLMETERS
Dimension Limits MIN NOM MAX
Number of Pins N 14
Pitch e 1.27 BSC
Overall Height A – – 1.75
Molded Package Thickness A2 1.25 – –
Standoff § A1 0.10 – 0.25
Overall Width E 6.00 BSC
Molded Package Width E1 3.90 BSC
Overall Length D 8.65 BSC
Chamfer (optional) h 0.25 – 0.50
Foot Length L 0.40 – 1.27
Footprint L1 1.04 REF
Foot Angle φ 0° – 8°
Lead Thickness c 0.17 – 0.25
Lead Width b 0.31 – 0.51
Mold Draft Angle Top α 5° – 15°
Mold Draft Angle Bottom β 5° – 15°
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. § Significant Characteristic.
3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side.
4. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-065B

PIC16F688
3 % & %! % 4" ) ' % 4 $% %"%
%% 255)))& &5 4

PIC16F688
14-Lead Plastic Thin Shrink Small Outline (ST) – 4.4 mm Body [TSSOP]
E
E1
NOTE 1
1 2
e
b
c φ
A A2
A1 L1 L
Units MILLIMETERS
Number of Pins N 14
Pitch e 0.65 BSC
Overall Height A – – 1.20
Molded Package Thickness A2 0.80 1.00 1.05
Standoff A1 0.05 – 0.15
Molded Package Width E1 4.30 4.40 4.50
Molded Package Length D 4.90 5.00 5.10
Foot Length L 0.45 0.60 0.75
Footprint L1 1.00 REF
Foot Angle φ 0° – 8°
Lead Thickness c 0.09 – 0.20
Lead Width b 0.19 – 0.30
Notes:
2. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side.

PIC16F688

PIC16F688
16-Lead Plastic Quad Flat, No Lead Package (ML) – 4x4x0.9 mm Body [QFN]
D D2
EXPOSED
PAD
E E2
2 2 b
1 1
K
N N
NOTE 1 L
TOP VIEW BOTTOM VIEW
A A3
A1
Units MILLIMETERS
Number of Pins N 16
Pitch e 0.65 BSC
Overall Height A 0.80 0.90 1.00
Standoff A1 0.00 0.02 0.05
Contact Thickness A3 0.20 REF
Exposed Pad Width E2 2.50 2.65 2.80
Overall Length D 4.00 BSC
Exposed Pad Length D2 2.50 2.65 2.80
Contact Width b 0.25 0.30 0.35
Contact Length L 0.30 0.40 0.50
Contact-to-Exposed Pad K 0.20 – –
Notes:
2. Package is saw singulated.

PIC16F688
3 % & %! % 4" ) ' % 4 $% %"%
%% 255)))& &5 4

PIC16F688
APPENDIX A: DATA SHEET APPENDIX B: MIGRATING FROM
REVISION HISTORY OTHER PIC®
DEVICES
Revision A
This discusses some of the issues in migrating from
This is a new data sheet. other PIC devices to the PIC16F6XX family of devices.
Revision B B.1 PIC16F676 to PIC16F688

Rewrites of the Oscillator and Special Features of the TABLE B-1: FEATURE COMPARISON
CPU Sections. General corrections to Figures and
Feature PIC16F676 PIC16F688
formatting.
Max Operating Speed 20 MHz 20 MHz
Revision C Max Program Memory 1024 4K
(Words)
Revised Electrical Section and added Char Data.
Added Golden Chapters. SRAM (Bytes) 64 256
A/D Resolution 10-bit 10-bit
Revision D Data EEPROM (bytes) 128 256
Replaced Package Drawings; Revised Product ID (SL Timers (8/16-bit) 1/1 1/1
Package to 3.90 mm); Replaced PICmicro with PIC; Oscillator Modes 8 8
Replaced Dev. Tool Section. Brown-out Reset Y Y
Internal Pull-ups RA0/1/2/4/5 RA0/1/2/4/5,
Revision E MCLR
Updated Peripheral Features, page 1; Deleted Note 1, Interrupt-on-change RA0/1/2/3 RA0/1/2/3/4/5
page 13; Updated the Typical Info. in Param. OS18, /4/5
Table 14-3; Added sub-section 10.3.2 (Auto-Baud Comparator 1 2
Overflow, page 100) to Chapter 10; Added SOIC,
EUSART N Y
TSSOP, QFN Package Land Patterns.
Ultra Low-Power N Y
Wake-up
Extended WDT N Y
Software Control N Y
Option of WDT/BOR
INTOSC Frequencies 4 MHz 32 kHz -
8 MHz
Clock Switching N Y
Note: This device has been designed to perform

to the parameters of its data sheet. It has
been tested to an electrical specification
designed to determine its conformance
with these parameters. Due to process
differences in the manufacture of this
device, this device may have different
performance characteristics than its earlier
version. These differences may cause this
device to perform differently in your
application than the earlier version of this
device.

PIC16F688
NOTES:

PIC16F688
INDEX
A RA5 Pin ...................................................................... 40
RC0 and RC1 Pins ..................................................... 43
A/D
Specifications.................................................... 160, 161 RC2 and RC3 Pins ..................................................... 43
Absolute Maximum Ratings .............................................. 143 RC4 Pin ...................................................................... 44
RC5 Pin ...................................................................... 44
AC Characteristics
Industrial and Extended ............................................ 153 Resonator Operation .................................................. 24
Load Conditions ........................................................ 152 Timer1 ........................................................................ 48
TMR0/WDT Prescaler ................................................ 45
ADC .................................................................................... 65
Acquisition Requirements ........................................... 73 Watchdog Timer (WDT)............................................ 123
Associated registers.................................................... 75 Break Character (12-bit) Transmit and Receive ............... 101
Brown-out Reset (BOR).................................................... 114
Block Diagram............................................................. 65
Calculating Acquisition Time....................................... 73 Associated ................................................................ 115
Channel Selection....................................................... 66 Specifications ........................................................... 157
Timing and Characteristics ....................................... 156
Configuration............................................................... 66
Configuring Interrupt ................................................... 69 C
Conversion Clock........................................................ 66
C Compilers
Conversion Procedure ................................................ 69
MPLAB C18.............................................................. 140
Internal Sampling Switch (RSS) Impedance................ 73
MPLAB C30.............................................................. 140
Interrupts..................................................................... 68
Clock Accuracy with Asynchronous Operation ................... 92
Operation .................................................................... 69
Clock Sources
Operation During Sleep .............................................. 69
External Modes........................................................... 23
Port Configuration ....................................................... 66
EC ...................................................................... 23
Reference Voltage (VREF)........................................... 66
HS ...................................................................... 24
Result Formatting........................................................ 68
LP ....................................................................... 24
Source Impedance...................................................... 73
OST .................................................................... 23
Starting an A/D Conversion ........................................ 68
RC ...................................................................... 25
ADCON0 Register............................................................... 71
XT ....................................................................... 24
ADCON1 Register............................................................... 71
Internal Modes............................................................ 25
ADRESH Register (ADFM = 0) ........................................... 72
Frequency Selection........................................... 27
ADRESH Register (ADFM = 1) ........................................... 72
HFINTOSC ......................................................... 25
ADRESL Register (ADFM = 0)............................................ 72
INTOSC .............................................................. 25
ADRESL Register (ADFM = 1)............................................ 72
INTOSCIO .......................................................... 25
Analog Front-end (AFE)
LFINTOSC.......................................................... 27
Power-On Reset ....................................................... 113
Clock Switching .................................................................. 29
Analog Input Connection Considerations............................ 55
CMCON0 Register.............................................................. 61
Analog-to-Digital Converter. See ADC
CMCON1 Register.............................................................. 62
ANSEL Register .................................................................. 34
Code Examples
Assembler
A/D Conversion .......................................................... 70
MPASM Assembler................................................... 140
Assigning Prescaler to Timer0.................................... 46
B Assigning Prescaler to WDT....................................... 46
Indirect Addressing..................................................... 20
BAUDCTL Register ............................................................. 94
Block Diagrams Initializing PORTA ...................................................... 33
ADC ............................................................................ 65 Initializing PORTC ...................................................... 42
Saving Status and W Registers in RAM ................... 122
ADC Transfer Function ............................................... 74
Analog Input Model ............................................... 55, 74 Ultra Low-Power Wake-up Initialization...................... 36
Clock Source............................................................... 21 Code Protection ................................................................ 126
Comparator......................................................................... 53
Comparator 1 .............................................................. 54
Comparator 2 .............................................................. 54 C2OUT as T1 Gate..................................................... 62
Comparator Modes ..................................................... 57 Configurations ............................................................ 56
Interrupts .................................................................... 59
Crystal Operation ........................................................ 24
EUSART Receive ....................................................... 84 Operation.............................................................. 53, 58
Operation During Sleep .............................................. 60
EUSART Transmit ...................................................... 83
External RC Mode....................................................... 25 Response Time .......................................................... 59
Fail-Safe Clock Monitor (FSCM) ................................. 31 Synchronizing COUT w/Timer1 .................................. 62
Comparator Module
In-Circuit Serial Programming Connections.............. 127
Interrupt Logic ........................................................... 120 Associated registers ................................................... 64
MCLR Circuit............................................................. 113 Comparator Voltage Reference (CVREF)............................ 63
Effects of a Reset ....................................................... 60
On-Chip Reset Circuit ............................................... 112
PIC16F688.................................................................... 5 Response Time .......................................................... 59
RA1 Pins ..................................................................... 38 Specifications ........................................................... 159
Comparators
RA2 Pin....................................................................... 38
RA3 Pin....................................................................... 39 C2OUT as T1 Gate..................................................... 49
RA4 Pin....................................................................... 39 Effects of a Reset ....................................................... 60

PIC16F688
Specifications ............................................................ 159 Transmission .................................................... 107
CONFIG Register.............................................................. 111
Configuration Bits.............................................................. 110 F
CPU Features ................................................................... 109 Fail-Safe Clock Monitor ...................................................... 31
Customer Change Notification Service ............................. 199 Fail-Safe Condition Clearing....................................... 31
Customer Notification Service........................................... 199 Fail-Safe Detection ..................................................... 31
Customer Support ............................................................. 199 Fail-Safe Operation..................................................... 31
Reset or Wake-up from Sleep .................................... 31
D Firmware Instructions ....................................................... 129
Data EEPROM Memory ...................................................... 77 Flash Program Memory ...................................................... 77
Associated Registers .................................................. 82 Fuses. See Configuration Bits
Reading....................................................................... 80
Writing ......................................................................... 80 G
Data Memory......................................................................... 7 General Purpose Register File ............................................. 7
DC and AC Characteristics
Graphs and Tables ................................................... 163
I
DC Characteristics I/O Ports.............................................................................. 33
Extended and Industrial ............................................ 149 ID Locations...................................................................... 126
Industrial and Extended ............................................ 145 In-Circuit Debugger........................................................... 127
Development Support ....................................................... 139 In-Circuit Serial Programming (ICSP)............................... 127
Device Overview ................................................................... 5 Indirect Addressing, INDF and FSR Registers ................... 20
Instruction Format............................................................. 129
E Instruction Set................................................................... 129
EEADR Register ................................................................. 78 ADDLW..................................................................... 131
EEADR Registers................................................................ 77 ADDWF..................................................................... 131
EEADRH Registers ............................................................. 77 ANDLW..................................................................... 131
EECON1 Register ......................................................... 77, 79 ANDWF..................................................................... 131
EECON2 Register ............................................................... 77 MOVF ....................................................................... 134
EEDAT Register.................................................................. 78 BCF .......................................................................... 131
EEDATH Register ............................................................... 78 BSF........................................................................... 131
Electrical Specifications .................................................... 143 BTFSC ...................................................................... 131
Enhanced Universal Synchronous Asynchronous BTFSS ...................................................................... 132
Receiver Transmitter (EUSART)................................. 83 CALL......................................................................... 132
Errata .................................................................................... 4 CLRF ........................................................................ 132
EUSART.............................................................................. 83 CLRW ....................................................................... 132
Associated Registers CLRWDT .................................................................. 132
Baud Rate Generator.......................................... 95 COMF ....................................................................... 132
Asynchronous Mode ................................................... 85 DECF ........................................................................ 132
12-bit Break Transmit and Receive................... 101 DECFSZ ................................................................... 133
Associated Registers GOTO ....................................................................... 133
Receive ....................................................... 91 INCF ......................................................................... 133
Transmit ...................................................... 87 INCFSZ..................................................................... 133
Auto-Baud Overflow.......................................... 100 IORLW ...................................................................... 133
Auto-Wake-up on Break.................................... 100 IORWF...................................................................... 133
Baud Rate Generator (BRG)............................... 95 MOVLW .................................................................... 134
Clock Accuracy ................................................... 92 MOVWF .................................................................... 134
Receiver.............................................................. 88 NOP .......................................................................... 134
Setting up 9-bit Mode with Address Detect......... 90 RETFIE ..................................................................... 135
Transmitter.......................................................... 85 RETLW ..................................................................... 135
Baud Rate Generator (BRG) RETURN................................................................... 135
Auto Baud Rate Detect ....................................... 99 RLF ........................................................................... 136
Baud Rate Error, Calculating .............................. 95 RRF .......................................................................... 136
Baud Rates, Asynchronous Modes..................... 96 SLEEP ...................................................................... 136
Formulas ............................................................. 95 SUBLW ..................................................................... 136
High Baud Rate Select (BRGH Bit)..................... 95 SUBWF..................................................................... 137
Synchronous Master Mode ............................... 103, 107 SWAPF ..................................................................... 137
Associated Registers XORLW .................................................................... 137
Receive ..................................................... 106 XORWF .................................................................... 137
Transmit .................................................... 104 Summary Table ........................................................ 130
Reception.......................................................... 105 INTCON Register................................................................ 15
Transmission..................................................... 103 Internal Oscillator Block
Synchronous Slave Mode INTOSC
Associated Registers Specifications ........................................... 154, 155
Receive ..................................................... 108 Internal Sampling Switch (RSS) Impedance........................ 73
Transmit .................................................... 107 Internet Address ............................................................... 199
Reception.......................................................... 108 Interrupts........................................................................... 119

PIC16F688
ADC ............................................................................ 69 ANSEL Register ................................................. 34
Associated Registers ................................................ 121 Interrupt-on-Change ........................................... 34
Comparator ................................................................. 59 Ultra Low-Power Wake-up............................ 34, 36
Context Saving.......................................................... 122 Weak Pull-up ...................................................... 34
Interrupt-on-Change.................................................... 34 Associated registers ................................................... 41
PORTA Interrupt-on-Change .................................... 120 Pin Descriptions and Diagrams .................................. 37
RA2/INT .................................................................... 120 RA0............................................................................. 37
Timer0....................................................................... 120 RA1............................................................................. 38
TMR1 .......................................................................... 50 RA2............................................................................. 38
INTOSC Specifications ............................................. 154, 155 RA4............................................................................. 39
IOCA Register ..................................................................... 35 RA5............................................................................. 40
Specifications ........................................................... 155
L PORTA Register ................................................................. 33
Load Conditions ................................................................ 152 PORTC ............................................................................... 42
Associated registers ................................................... 44
M PA/PB/PC/PD.See Enhanced Universal Asynchronous
MCLR ................................................................................ 113 Receiver Transmitter (EUSART) ........................ 42
Internal ...................................................................... 113 Specifications ........................................................... 155
.............................................................................................. 7 PORTC Register................................................................. 42
Data .............................................................................. 7 Power-Down Mode (Sleep)............................................... 125
Program ........................................................................ 7 Power-up Timer (PWRT) .................................................. 113
.......................................... 199, 193, 140, 141, 139, 141, 140 Specifications ........................................................... 157
Precision Internal Oscillator Parameters .......................... 155
O
Prescaler
OPCODE Field Descriptions ............................................. 129 Shared WDT/Timer0................................................... 46
OPTION Register ................................................................ 14 Switching Prescaler Assignment ................................ 46
OPTION_REG Register ...................................................... 47 Program Memory .................................................................. 7
OSCCON Register ........................................................ 10, 22 Map and Stack.............................................................. 7
Oscillator Programming, Device Instructions.................................... 129
Associated registers.............................................. 32, 52
Oscillator Module ................................................................ 21 R
EC ............................................................................... 21 RA3/MCLR/VPP .................................................................. 39
HFINTOSC.................................................................. 21 RCREG............................................................................... 90
HS ............................................................................... 21 RCSTA Register ................................................................. 93
INTOSC ...................................................................... 21 Reader Response............................................................. 200
INTOSCIO................................................................... 21 Read-Modify-Write Operations ......................................... 129
LFINTOSC .................................................................. 21 Register
LP................................................................................ 21 RCREG Register ........................................................ 99
RC............................................................................... 21 Registers
RCIO ........................................................................... 21 ADCON0 (ADC Control 0) .......................................... 71
XT ............................................................................... 21 ADCON1 (ADC Control 1) .......................................... 71
Oscillator Parameters ....................................................... 154 ADRESH (ADC Result High) with ADFM = 0) ............ 72
Oscillator Specifications .................................................... 153 ADRESH (ADC Result High) with ADFM = 1) ............ 72
Oscillator Start-up Timer (OST) ADRESL (ADC Result Low) with ADFM = 0).............. 72
Specifications............................................................ 157 ADRESL (ADC Result Low) with ADFM = 1).............. 72
Oscillator Switching ANSEL (Analog Select) .............................................. 34
Fail-Safe Clock Monitor............................................... 31 BAUDCTL (Baud Rate Control).................................. 94
Two-Speed Clock Start-up.......................................... 29 CMCON0 (Comparator Control 0) .............................. 61
OSCTUNE Register ............................................................ 26 CMCON1 (Comparator Control 1) .............................. 62
CONFIG (Configuration Word) ................................. 111
P
EEADR (EEPROM Address) ...................................... 78
Packaging ......................................................................... 185 EECON1 (EEPROM Control 1) .................................. 79
Marking ..................................................................... 185 EEDAT (EEPROM Data) ............................................ 78
PDIP Details.............................................................. 186 EEDATH (EEPROM Data High Byte) ......................... 78
PCL and PCLATH ............................................................... 19 INTCON (Interrupt Control) ........................................ 15
Computed GOTO........................................................ 19 IOCA (Interrupt-on-Change PORTA).......................... 35
Stack ........................................................................... 19 OPTION_REG (OPTION)........................................... 14
PCON Register ........................................................... 18, 115 OPTION_REG (Option) .............................................. 47
PICSTART Plus Development Programmer ..................... 142 OSCCON (Oscillator Control)..................................... 22
PIE1 Register ...................................................................... 16 OSCTUNE (Oscillator Tuning).................................... 26
Pin Diagram ...................................................................... 2, 3 PCON (Power Control Register)................................. 18
Pinout Description PCON (Power Control) ............................................. 115
PIC16F688.................................................................... 6 PIE1 (Peripheral Interrupt Enable 1) .......................... 16
PIR1 Register...................................................................... 17 PIR1 (Peripheral Interrupt Register 1) ........................ 17
PORTA................................................................................ 33 PORTA ....................................................................... 33
Additional Pin Functions ............................................. 34 PORTC ....................................................................... 42

PIC16F688
RCSTA (Receive Status and Control)......................... 93 Comparator Output ..................................................... 53
Reset Values............................................................. 117 Fail-Safe Clock Monitor (FSCM)................................. 32
Reset Values (Special Registers) ............................. 118 INT Pin Interrupt ....................................................... 121
Special Function Register Map ..................................... 8 Internal Oscillator Switch Timing ................................ 28
Special Register Summary ........................................... 9 Reset, WDT, OST and Power-up Timer ................... 156
STATUS ...................................................................... 13 Send Break Character Sequence ............................. 102
T1CON ........................................................................ 51 Synchronous Reception (Master Mode, SREN) ....... 106
TRISA (Tri-State PORTA) ........................................... 33 Synchronous Transmission ...................................... 104
TRISC (Tri-State PORTC) .......................................... 42 Synchronous Transmission (Through TXEN) ........... 104
TXSTA (Transmit Status and Control) ........................ 92 Time-out Sequence .................................................. 116
VRCON (Voltage Reference Control) ......................... 63 Case 3 .............................................................. 116
WDTCON (Watchdog Timer Control)........................ 124 Timer0 and Timer1 External Clock ........................... 158
WPUA (Weak Pull-Up PORTA) .................................. 35 Timer1 Incrementing Edge ......................................... 50
Reset................................................................................. 112 Two Speed Start-up.................................................... 30
Revision History ................................................................ 193 Wake-up from Interrupt............................................. 126
Timing Parameter Symbology .......................................... 152
S TRISA ................................................................................. 33
Software Simulator (MPLAB SIM)..................................... 140 TRISA Register................................................................... 33
SPBRG................................................................................ 95 TRISC Register................................................................... 42
SPBRGH ............................................................................. 95 Two-Speed Clock Start-up Mode........................................ 29
Special Function Registers ................................................... 7 TXREG ............................................................................... 85
STATUS Register................................................................ 13 TXSTA Register.................................................................. 92
BRGH Bit .................................................................... 95
T
T1CON Register.................................................................. 51 U
Thermal Considerations .................................................... 151 Ultra Low-Power Wake-up........................................ 6, 34, 36
Time-out Sequence........................................................... 115
Timer0 ................................................................................. 45 V
Associated Registers .................................................. 47 Voltage Reference. See Comparator Voltage
External Clock ............................................................. 46 Reference (CVREF)
Interrupt....................................................................... 47 Voltage References
Operation .............................................................. 45, 48 Associated registers ................................................... 64
Specifications ............................................................ 158 VREF. SEE ADC Reference Voltage
T0CKI .......................................................................... 46
Timer1 ................................................................................. 48 W
Associated registers.................................................... 52 Wake-up on Break ............................................................ 100
Asynchronous Counter Mode ..................................... 49 Wake-up Using Interrupts ................................................. 125
Reading and Writing ........................................... 49 Watchdog Timer (WDT).................................................... 123
Interrupt....................................................................... 50 Associated Registers ................................................ 124
Modes of Operation .................................................... 48 Clock Source ............................................................ 123
Operation During Sleep .............................................. 50 Modes ....................................................................... 123
Oscillator ..................................................................... 49 Period ....................................................................... 123
Prescaler ..................................................................... 49 Specifications ........................................................... 157
Specifications ............................................................ 158 WDTCON Register ....................................................... 9, 124
Timer1 Gate WPUA Register................................................................... 35
Inverting Gate ..................................................... 49 WWW Address ................................................................. 199
Selecting Source........................................... 49, 62 WWW, On-Line Support ....................................................... 4
Synchronizing COUT w/Timer1 .......................... 62
TMR1H Register ......................................................... 48
TMR1L Register .......................................................... 48
Timers
Timer1
T1CON................................................................ 51
Timing Diagrams
A/D Conversion ......................................................... 162
A/D Conversion (Sleep Mode) .................................. 162
Asynchronous Reception ............................................ 90
Asynchronous Transmission ....................................... 86
Asynchronous Transmission (Back to Back) .............. 86
Auto Wake-up Bit (WUE) During Normal Operation . 100
Auto Wake-up Bit (WUE) During Sleep .................... 101
Automatic Baud Rate Calculator ................................. 99
Brown-out Reset (BOR) ............................................ 156
Brown-out Reset Situations ...................................... 114
CLKOUT and I/O....................................................... 155
Clock Timing ............................................................. 153

PIC16F688
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PIC16F688
READER RESPONSE
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PIC16F688
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO. X /XX XXX
Examples:
Device Temperature Package Pattern a) PIC16F688-E/P 301 = Extended Temp., PDIP
Range package, 20 MHz, QTP pattern #301
b) PIC16F688-I/SO = Industrial Temp., SOIC
package, 20 MHz.
Device PIC16F688, PIC16F688T(1)
VDD range 2.0V to 5.5V
Temperature Range I = -40°C to +85°C (Industrial)

E = -40°C to +125°C (Extended)
Package ML = Quad Flat No Leads (QFN)

P = Plastic DIP
SL = 16-lead Small Outline (3.90 mm)
ST = Thin Shrink Small Outline (4.4 mm)
Note 1: T=In tape and reel TSSOP, SOIC and

Pattern QTP, SQTPSM or ROM Code; Special Requirements QFN packages only.
(blank otherwise)

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Pic16F688 Data Sheet: 14-Pin Flash-Based, 8-Bit Cmos Microcontrollers With Nanowatt Technology

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PIC16F688

© 2009 Microchip Technology Inc. DS41203E

Information contained in this publication regarding device Trademarks

Microchip received ISO/TS-16949:2002 certification for its worldwide

DS41203E-page ii © 2009 Microchip Technology Inc.

High-Performance RISC CPU: Low-Power Features:

© 2009 Microchip Technology Inc. DS41203E-page 1

Pin Diagram (PDIP, SOIC, TSSOP)

14-pin PDIP, SOIC, TSSOP

TABLE 1: PIC16F688 14-PIN SUMMARY (PDIP, SOIC, TSSOP)

DS41203E-page 2 © 2009 Microchip Technology Inc.

TABLE 2: PIC16F688 16-PIN SUMMARY (QFN)

© 2009 Microchip Technology Inc. DS41203E-page 3

TO OUR VALUED CUSTOMERS

Most Current Data Sheet

Customer Notification System

DS41203E-page 4 © 2009 Microchip Technology Inc.

FIGURE 1-1: PIC16F688 BLOCK DIAGRAM

STATUS Reg RC3

Timer0 Timer1 EUSART

© 2009 Microchip Technology Inc. DS41203E-page 5

DS41203E-page 6 © 2009 Microchip Technology Inc.

Interrupt Vector 0004h

© 2009 Microchip Technology Inc. DS41203E-page 7

Unimplemented data memory locations, read as ‘0’.

DS41203E-page 8 © 2009 Microchip Technology Inc.

© 2009 Microchip Technology Inc. DS41203E-page 9

DS41203E-page 10 © 2009 Microchip Technology Inc.

© 2009 Microchip Technology Inc. DS41203E-page 11

DS41203E-page 12 © 2009 Microchip Technology Inc.

© 2009 Microchip Technology Inc. DS41203E-page 13

REGISTER 2-2: OPTION_REG: OPTION REGISTER

bit 7 RAPU: PORTA Pull-up Enable bit

000 1:2 1:1

DS41203E-page 14 © 2009 Microchip Technology Inc.

REGISTER 2-3: INTCON: INTERRUPT CONTROL REGISTER

bit 7 GIE: Global Interrupt Enable bit

Note 1: IOCA register must also be enabled.

© 2009 Microchip Technology Inc. DS41203E-page 15

REGISTER 2-4: PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1

bit 7 EEIE: EE Write Complete Interrupt Enable bit

DS41203E-page 16 © 2009 Microchip Technology Inc.

REGISTER 2-5: PIR1: PERIPHERAL INTERRUPT REQUEST REGISTER 1

bit 7 EEIF: EEPROM Write Operation Interrupt Flag bit

© 2009 Microchip Technology Inc. DS41203E-page 17

REGISTER 2-6: PCON: POWER CONTROL REGISTER

bit 7-6 Unimplemented: Read as ‘0’

DS41203E-page 18 © 2009 Microchip Technology Inc.

PCLATH<4:0> 8 2: There are no instructions/mnemonics

2.3.1 COMPUTED GOTO

© 2009 Microchip Technology Inc. DS41203E-page 19

FIGURE 2-4: DIRECT/INDIRECT ADDRESSING PIC16F688

Direct Addressing Indirect Addressing

RP1 RP0 6 From Opcode 0 IRP 7 File Select Register 0

Bank Select Location Select Bank Select Location Select

Note: For memory map detail, see Figure 2-2.

DS41203E-page 20 © 2009 Microchip Technology Inc.

FIGURE 3-1: PIC® MCU CLOCK SOURCE BLOCK DIAGRAM

Power-up Timer (PWRT)