Ad 8479
Ad 8479
Ad 8479
11118-001
±10 µV/°C maximum offset voltage drift NOTES
1. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN.
±5 ppm/°C maximum gain drift
Figure 1.
APPLICATIONS
High voltage current sensing
Battery cell voltage monitors
Power supply current monitors
Motor controls
Isolation
GENERAL DESCRIPTION
The AD8479 is a difference amplifier with a very high input 800
11118-110
–20 –15 –10 –5 0 5 10 15 20
common-mode rejection ratio (CMRR) over a wide frequency VOUT (V)
range. Figure 2. Input Common-Mode Voltage vs. Output Voltage
The AD8479 is available in a space-saving 8-lead SOIC package
and is operational over the −40°C to +125°C temperature range.
TABLE OF CONTENTS
Features .............................................................................................. 1 Applications Information ............................................................. 13
Applications ...................................................................................... 1 Basic Connections ...................................................................... 13
Functional Block Diagram .............................................................. 1 Single-Supply Operation ........................................................... 13
General Description ......................................................................... 1 System-Level Decoupling and Grounding ............................. 13
Revision History ............................................................................... 2 Using a Large Shunt Resistor.................................................... 14
Specifications .................................................................................... 3 Output Filtering ......................................................................... 15
Absolute Maximum Ratings ........................................................... 5 Gain of 60 Differential Amplifier............................................. 15
Thermal Resistance ...................................................................... 5 Error Budget Analysis Example ............................................... 16
ESD Caution.................................................................................. 5 Outline Dimensions ....................................................................... 17
Pin Configuration and Function Descriptions ............................ 6 Ordering Guide .......................................................................... 17
Typical Performance Characteristics ............................................. 7
Theory of Operation ...................................................................... 12
REVISION HISTORY
1/2021—Rev. B to Rev. C Added Thermal Resistance Section and Table 3; Renumbered
Changes to Features Section ........................................................... 1 Sequentially ........................................................................................5
Changes to Specifications Section and Table 1 ............................ 3 Added Figure 3 and Figure 4; Renumbered Sequentially ............5
Changes to Figure 3 Caption .......................................................... 5 Changes to Figure 6 to Figure 11 ....................................................7
Changes to Figure 12 ....................................................................... 8 Changes to Figure 12, Figure 16, and Figure 17 ...........................8
Changes to Figure 23 ....................................................................... 9 Changes to Figure 20 to Figure 22 ..................................................9
Changes to Figure 24, Figure 25, and Figure 26......................... 10 Changes to Figure 27 to Figure 29 ............................................... 10
Changes to Theory of Operation Section.................................... 12 Changes to Figure 30 to Figure 34 ............................................... 11
Changes to Single-Supply Operation Section............................. 13 Added Figure 35 ............................................................................. 11
Changes to Table 7 ......................................................................... 16
8/2019—Rev. A to Rev. B Changes to Ordering Guide .......................................................... 17
Changes to Features Section ........................................................... 1
Changes to Specifications Section .................................................. 3 9/2015—Rev. 0 to Rev. A
Deleted Input Voltage Range Continuous Parameter, Table 2....... 5 Changes to Single-Supply Operation Section ............................ 12
Rev. C | Page 2 of 17
Data Sheet AD8479
SPECIFICATIONS
VS = ±15 V, REF(−) = REF(+) = 0 V, RL = 2 kΩ, common-mode voltage (VCM) = 0 V, ambient temperature (TA) = 25°C, unless otherwise
noted.
Table 1.
A Grade B Grade
Parameter Test Conditions/Comments Min Typ Max Min Typ Max Unit
GAIN VOUT = ±10 V
Nominal Gain 1 1 V/V
Gain Error 1 0.01 ±0.02 0.005 ±0.01 %
Gain Nonlinearity 4 ±10 2 ±5 ppm
Gain Drift TA = TMIN to TMAX 3 ±5 3 ±5 ppm/°C
OFFSET VOLTAGE
Offset Voltage VS = ±15 V 0.5 ±3 0.5 ±1 mV
VS = ±5 V 0.5 ±3 0.5 ±1 mV
Offset Voltage Drift TA = TMIN to TMAX 3 ±15 3 ±10 µV/°C
Power Supply Rejection VS = ±2.5 V to ±18 V 84 100 90 100 dB
Ratio (PSRR)
INPUT
Common-Mode Rejection
Ratio (CMRR) 2
TA = 25°C, VCM = ±10 V 80 90 90 96 dB
Junction temperature (TJ) = 25°C, 80 90 90 96 dB
VCM = ±600 V
TJ = 25°C, VCM = 1200 V p-p, dc to 80 80 dB
6 kHz
CMRR Drift2 TJ = TMIN to TMAX −0.3 ±1.5 −0.25 ±1.3 ppm/°C
Operating Voltage Range Common mode ±600 ±600 V
Differential ±14.7 ±14.7 V
Input Operating Common mode 500 500 kΩ
Impedance
Differential 2 2 MΩ
OUTPUT
Output Voltage Swing −VS + 0.3 +VS − 0.3 −VS + 0.3 +VS − 0.3 V
Output Short-Circuit ±55 ±55 mA
Current
Capacitive Load Stable operation 500 500 pF
DYNAMIC RESPONSE
Small Signal −3 dB 310 310 kHz
Bandwidth
Slew Rate 8.8 8.8 V/µs
Full Power Bandwidth VOUT = 20 V p-p 140 140 kHz
Settling Time 0.01%, VOUT = 10 V step 5.9 5.9 µs
0.001%, VOUT = 10 V step 8.7 8.7 µs
OUTPUT VOLTAGE NOISE
0.1 Hz to 10 Hz 30 40 30 40 µV p-p
Noise Spectral Density 100 Hz ≤ f ≤ 100 kHz 1.6 1.6 μV/√Hz
Rev. C | Page 3 of 17
AD8479 Data Sheet
A Grade B Grade
Parameter Test Conditions/Comments Min Typ Max Min Typ Max Unit
POWER SUPPLY
Operating Voltage Range ±2.5 ±18 ±2.5 ±18 V
Supply Current VOUT = 0 V 550 650 550 650 μA
TA = TMIN to TMAX 850 850 μA
TEMPERATURE RANGE
Specified Performance TA = TMIN to TMAX −40 +85 −40 +85 °C
Operational −40 +125 −40 +125 °C
1
See Figure 35 for gain error shift over lifetime.
2
TJ is affected by VCM. Use the values in Table 3 and the data shown in Figure 3 when estimating TJ. If TJ is required, use the derating curves in Figure 3.
Rev. C | Page 4 of 17
Data Sheet AD8479
11118-203
Lead Temperature (Soldering, 60 sec) 300°C 0 100 200 300 400 500 600 700
INPUT COMMON-MODE VOLTAGE (V rms)
Stresses at or above those listed under Absolute Maximum Figure 3. Junction Temperature (TJ) vs. Input Common-Mode Voltage
Ratings may cause permanent damage to the product. This is a Derived from Table 3
stress rating only; functional operation of the product at these 1.4
or any other conditions above those indicated in the
operational section of this specification is not implied.
11118-204
soldered in a circuit board for surface-mount packages. ΨJT is –40 –20 0 20 40 60 80 100 120
AMBIENT TEMPERATURE (°C)
the junction-to-top-of-package characterization parameter.
Figure 4. Maximum Power Dissipation vs. Ambient Temperature
Table 3. Thermal Resistance ESD CAUTION
Package Type 1 θJA ΨJT Unit
R-8 151.4 2.5 °C/W
1
Thermal impedance simulated values are based on a JEDEC 2S2P thermal
test board for θJA and ΨJT. See JEDEC JESD-51.
Rev. C | Page 5 of 17
AD8479 Data Sheet
11118-002
NOTES
1. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN.
Rev. C | Page 6 of 17
Data Sheet AD8479
50
80
CMRR (dB)
40
HITS
70
30
60
20
10 50
0 40
11118-003
11118-006
–100 –80 –60 –40 –20 0 20 40 60 80 100 1 10 100 1k 10k 100k 1M
CMRR (µV/V) FREQUENCY (Hz)
150 120
N = 500
MEAN = –0.3269 100
125 SD = 27.4492
80 +PSRR
100
60 –PSRR
PSRR (dB)
HITS
75 40
20
50
0
25
–20
0 –40
11118-004
11118-007
–200 –160 –120 –80 –40 0 40 80 120 160 200 0.1 1 10 100 1k 10k 100k 1M
GAIN ERROR (µV/V) FREQUENCY (Hz)
100 35
N = 500
MEAN = 189.8972
SD = 658.2455 30 VS = ±15V
80
25
VOUT (V p-p)
60
20
HITS
15
40
10 VS = ±5V
20
5
0 0
11118-008
600
1200
1800
2400
3000
–3000
–2400
–1800
–1200
FREQUENCY (Hz)
11118-005
Figure 8. Offset Voltage Distribution Figure 11. Large Signal Frequency Response
Rev. C | Page 7 of 17
AD8479 Data Sheet
10 150
VS = +5V, VREF = MIDSUPPLY
0
100
–20
50
GAIN (dB)
–30
–40
0
–50
–60 –50
–70
–80 –100
11118-112
11118-009
100 1k 10k 100k 1M 10M 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
FREQUENCY (Hz) VOUT (V)
Figure 12. Small Signal Frequency Response Figure 15. Input Common-Mode Voltage vs. Output Voltage, Single Supply,
VS = +5 V, VREF = Midsupply
800
VS = ±15V
600
COMMON-MODE VOLTAGE (V)
5.9µs TO 0.01%
0 8.7µs TO 0.001%
–200
0.002%/DIV V OUT SETTLING
–400
–600
11118-113
–800
11118-210
Figure 13. Input Common-Mode Voltage vs. Output Voltage, Dual Supplies, Figure 16. Settling Time
VS = ±15 V, ±5 V
250
VS = +5V, VREF = 0V 20
RL = 2kΩ
200 15 CL = 1000pF
COMMON-MODE VOLTAGE (V)
10
150
5
VOUT (V)
100
0
50 –5
–10
0
–15
11118-114
–50
11118-111
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 –20
TIME (4µs/DIV)
VOUT (V)
Figure 14. Input Common-Mode Voltage vs. Output Voltage, Single Supply, Figure 17. Large Signal Pulse Response
VS = +5 V, VREF = 0 V
Rev. C | Page 8 of 17
Data Sheet AD8479
15 150
RL = 2kΩ
100
10
50
0 –50
–100
–5 –40°C
+25°C
–150
+85°C
–10 +105°C
+125°C –200
–15 –250
11118-118
11118-014
100 1k 10k 100k 1M –40 –25 –10 5 20 35 50 65 80 95 110 125
RESISTANCE (Ω) TEMPERATURE (°C)
Figure 18. Output Voltage vs. Load over Temperature Figure 21. Gain Drift
15 20
RL = 2kΩ
15
10
10
NONLINEARITY (ppm)
5
5
VOUT (V)
0 0
–5
–5 –40°C
+25°C
+85°C –10
+105°C
–10 +125°C
–15
–15 –20
11118-019
11118-015
0 5 10 15 20 25 30 35 40 45 –10 –8 –6 –4 –2 0 2 4 6 8 10
ILOAD (mA) VOUT (V)
Figure 19. Output Voltage vs. Output Current over Temperature Figure 22. Gain Nonlinearity
80
NORMALIZED AT 25°C NORMALIZED AT 0V; OFFSET TO SHOW
REPRESENTATIVE DATA DIFFERENT POWER SUPPLIES
60
OUTPUT ERROR (2mV/DIV)
40
20
CMRR (µV/V)
–20
VS = ±18V
–40 VS = ±15V
VS = ±12V
VS = ±10V
–60 VS = ±5V
–80
11118-020
11118-117
Figure 20. CMRR vs. Temperature, VCM = ±20 V Figure 23. Output Error vs. Output Voltage, RL = 10 kΩ
Rev. C | Page 9 of 17
AD8479 Data Sheet
6
NORMALIZED AT 0V; OFFSET TO SHOW
DIFFERENT POWER SUPPLIES
4
OUTPUT ERROR (2mV/DIV)
VOUT (mV)
0
VS = ±18V –2
VS = ±15V
VS = ±12V
VS = ±10V –4
VS = ±5V
–6
11118-021
11118-025
–20 –16 –12 –8 –4 0 4 8 12 16 20 –10 –5 0 5 10 15 20 25 30 35 40
VOUT (V)
TIME (5µs/DIV)
Figure 24. Output Error vs. Output Voltage, RL = 2 kΩ Figure 27. Small Signal Pulse Response
VOUT (mV) 20
VS = ±18V –20
VS = ±15V
VS = ±12V
VS = ±10V –40
VS = ±5V
11118-026
11118-022
Figure 25. Output Error vs. Output Voltage, RL = 1 kΩ Figure 28. Small Signal Pulse Response vs. Capacitive Load
40
RL = 10kΩ
20
RL = 2kΩ 0
–20
RL = 1kΩ
–40
–ISC
–60
11118-023
–6 –5 –4 –3 –2 –1 0 1 2 3 4 5 6 –80
11118-027
VOUT (V)
TEMPERATURE (°C)
Figure 26. Output Error vs. Output Voltage, VS = ±5 V Figure 29. Short-Circuit Current vs. Temperature
Rev. C | Page 10 of 17
Data Sheet AD8479
15 4.0
9 3.2
6 2.8
SLEW RATE (V/µs)
3 2.4
0 2.0
–3 1.6
–6 1.2
–9 0.8
–12 0.4
–15 0
11118-031
11118-028
–40 –25 –10 5 20 35 50 65 80 95 110 125 0.1 1 10 100 1k 10k 100k 1M
TEMPERATURE (°C) FREQUENCY (Hz)
Figure 30. Slew Rate vs. Temperature Figure 33. Voltage Noise Spectral Density vs. Frequency
1000
–40°C
0°C
900 +25°C
+50°C
+85°C
800 +100°C
SUPPLY CURRENT (µA)
+125°C
NOISE (20µV/DIV)
700
600
500
400
300
11118-032
200
11118-029
2 4 6 8 10 12 14 16 18 TIME (1s/DIV)
SUPPLY VOLTAGE (±V)
Figure 31. Supply Current vs. Supply Voltage Figure 34. 0.1 Hz to 10 Hz Noise
1000 120
N = 245
900 VS = ±2.5V MEAN = –88.5344
VS = ±5.0V SD = 42.7075
VS = ±6.0V 100
800
VS = ±10.0V
VS = ±15.0V
SUPPLY CURRENT (µA)
700 VS = ±18.0V
80
600
HITS
500 60
400
300 40
200
20
100
0
11118-030
50
100
150
200
250
–300
–250
–200
–150
–100
TEMPERATURE (°C)
11118-235
Rev. C | Page 11 of 17
AD8479 Data Sheet
THEORY OF OPERATION
The AD8479 is a unity-gain, differential-to-single-ended To achieve the high common-mode voltage range, an internal
amplifier that can reject extremely high common-mode signals resistor divider—connected to Pin 3 and Pin 5—attenuates the
up to 600 V with ±15 V supplies. The AD8479 consists of an noninverting signal by a factor of 61. The internal resistors at
operational amplifier (op amp) and a resistor network (see Pin 1 and Pin 2, as well as the feedback resistor, restore the gain
Figure 36). to provide a differential gain of unity.
AD8479 The complete transfer function is
REF(–) 1 8 NC VOUT = V (+IN) − V (−IN)
+VS
Laser wafer-trimming provides resistor matching so that
7
1MΩ common-mode signals are rejected and differential input
–IN 2
6 OUTPUT signals are amplified.
+IN 3
1MΩ To reduce output voltage drift, the op amp uses super beta transis-
–VS 4
tors in its input stage. The input offset current and its associated
5 REF(+)
temperature coefficient contribute no appreciable output voltage
offset or drift, which has the added benefit of reducing voltage
11118-033
NOTES noise because the corner where 1/f noise becomes dominant is
1. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN.
below 5 Hz. To reduce the dependence of gain accuracy on the
Figure 36. Functional Block Diagram
op amp, the open-loop voltage gain of the op amp exceeds
20 million V/V, and the PSRR exceeds 90 dB.
Rev. C | Page 12 of 17
Data Sheet AD8479
APPLICATIONS INFORMATION
BASIC CONNECTIONS REF(–) AD8479
+VS
1 8 NC
Figure 37 shows the basic connections for operating the
AD8479 with a dual supply. A supply voltage from ±2.5 V to –IN
2 7
VX +VS 0.1µF
±18 V is applied across Pin 7 and Pin 4. Both supplies should be ISHUNT RSHUNT
+IN
decoupled close to the pins using 0.1 μF capacitors. Electrolytic 3
VY
6
capacitors of 10 μF, also located close to the supply pins, may be –VS
4 5
REF(+)
OUTPUT = VOUT – VREF
required if low frequency noise is present on the power supply.
Although multiple amplifiers can be decoupled by a single set NC = NO CONNECT
11118-035
VREF
directly at the IC power pins.
+VS Figure 38. Operation with a Single Supply
+2.5V TO +18V
REF(–)
1
AD8479
8 NC
When the AD8479 is operated with a single supply and a
reference voltage is applied to REF(+) and REF(−), the input
–IN
2 7
(SEE
common-mode voltage range of the AD8479 is reduced. The
+VS 0.1µF
ISHUNT RSHUNT
+IN
TEXT) reduced input common-mode range depends on the voltage at
3 6
VOUT = ISHUNT × RSHUNT the inverting and noninverting inputs of the internal op amp,
–VS REF(+) labeled VX and VY in Figure 38. These nodes can swing to within
4 5
(SEE
0.1µF
1 V of either rail. Therefore, for a single supply voltage of 10 V,
TEXT)
NC = NO CONNECT VX and VY can have a value from 1 V to 9 V. If VREF is set to 5 V,
11118-034
–VS
–2.5V TO –18V
the allowable common-mode voltage range is +249 V to −239 V.
Figure 37. Basic Connections
The common-mode voltage range can be calculated as follows:
VCM(±) = 61 × (VX or VY(±)) − (60 × VREF)
The differential input signal, which typically results from a
load current flowing through a small shunt resistor, is applied SYSTEM-LEVEL DECOUPLING AND GROUNDING
to Pin 2 and Pin 3 with the polarity shown in Figure 37 to The use of ground planes is recommended to minimize the
obtain a positive gain. The common-mode voltage on the impedance of ground returns and, therefore, the size of dc errors.
differential input signal can range from −600 V to +600 V, and Figure 39 shows how to use grounding in a mixed-signal
the maximum differential voltage is ±14.7 V. When configured environ-ment, that is, with digital and analog signals present.
as shown in Figure 37, the device operates as a simple gain-of-1, To isolate low level analog signals from a noisy digital
differential-to-single-ended amplifier where the output voltage is environment, many data acquisition components have separate
the shunt resistance times the shunt current. The output is analog and digital ground returns. All ground pins from mixed-
measured with respect to Pin 1 and Pin 5. signal components, such as ADCs, should return through a low
Pin 1 and Pin 5 (REF(−) and (REF(+)) should be grounded for impedance analog ground plane. Digital ground lines of mixed-
a gain of unity and connected to the same low impedance signal converters should also be connected to the analog
ground plane. Failure to do this results in degraded common- ground plane.
mode rejection. Pin 8 is a no connect pin and should be left ANALOG POWER DIGITAL
open. –5V
SUPPLY
+5V GND
POWER SUPPLY
GND +5V
about 0.3 V of either rail, an offset must be applied to the 4 7 VDD AGND DGND
VDD
output. This offset can be applied by connecting REF(+) and +IN 3
–VS +VS 12 GND
REF(−) to a low impedance reference voltage that is capable of AD8479 OUTPUT 6 VIN1 ADC
MICROPROCESSOR
–IN 2
sinking current (some ADCs provide this voltage as an output). REF(–) REF(+) VIN2
11118-036
bipolar input signal, allowing the output to swing 9.4 V p-p Figure 39. Optimal Grounding Practice for a Dual Supply Environment
around the central 5 V reference voltage. For unipolar input with Separate Analog and Digital Supplies
signals, VREF can be set to approximately 1 V, allowing the
output to swing from 1 V (for a 0 V input) to within 0.3 V of
the positive rail.
Rev. C | Page 13 of 17
AD8479 Data Sheet
Typically, analog and digital grounds should be separated. At USING A LARGE SHUNT RESISTOR
the same time, however, the voltage difference between digital The insertion of a large value shunt resistor across the input pins,
and analog grounds on a converter must also be minimized to Pin 2 and Pin 3, unbalances the input resistor network, thereby
keep this difference as small as possible (typically <0.3 V). The introducing common-mode error. The magnitude of the error
increased noise—caused by the digital return currents of the depends on the common-mode voltage and the magnitude of
converter flowing through the analog ground plane—is typically the shunt resistor (RSHUNT).
negligible.
Table 5 shows some sample error voltages generated by a
Maximum isolation between analog and digital signals is achieved common-mode voltage of 600 V dc with shunt resistors from
by connecting the ground planes back to the supplies. Note that 20 Ω to 2000 Ω. Assuming that the shunt resistor is selected to
Figure 39 suggests a star ground system for the analog circuitry, use the full ±10 V output swing of the AD8479, the error voltage
with all ground lines connected, in this case, to the analog ground becomes quite significant as the value of RSHUNT increases.
of the ADC. However, when ground planes are used, it is
sufficient to connect ground pins to the nearest point on the Table 5. Error Resulting from Large Values of RSHUNT
low impedance ground plane. (Uncompensated Circuit)
If only one power supply is available, it must be shared by both RSHUNT (Ω) Error VOUT (V) Error Indicated (mA)
digital and analog circuitry. Figure 40 shows how to minimize 20 0.012 0.6
interference between the digital and analog circuitry. In Figure 40, 1000 0.583 0.6
the reference of the ADC is used to drive the REF(+) and REF(−) 2000 1.164 0.6
pins of the AD8479. Therefore, the reference must be capable of
To measure low current or current near zero in a high common-
sourcing and sinking a current equal to VCM/500 kΩ.
mode voltage environment, an external resistor equal to the
POWER SUPPLY
+5V GND
shunt resistor value can be added to the low impedance side of the
shunt resistor, as shown in Figure 41.
0.1µF
+VS
0.1µF REF(–) AD8479
0.1µF 1 8 NC
7 4 RCOMP –IN
VDD AGND DGND 2 7
+VS –VS VDD +VS 0.1µF
+IN 3 GND ISHUNT RSHUNT
AD8479 OUTPUT 6 VIN1 ADC +IN
MICROPROCESSOR
–IN 2 3 6
VIN2 VOUT
REF(–) REF(+)
11118-037
1 5 –VS REF(+)
VREF 4 5
11118-038
–VS NC = NO CONNECT
Rev. C | Page 14 of 17
Data Sheet AD8479
OUTPUT FILTERING GAIN OF 60 DIFFERENTIAL AMPLIFIER
To limit noise at the output, a simple two-pole, low-pass Low level signals can be connected directly to the −IN and +IN
Butterworth filter can be implemented using the ADA4077-2 inputs of the AD8479. Differential input signals can also be con-
after the AD8479, as shown in Figure 42. nected to give a precise gain of 60 (see Figure 43); however, large
+VS common-mode voltages are no longer permissible. Cold junction
REF(–) AD8479
1 8 NC C1 +VS
compensation can be implemented using a temperature sensor,
0.1µF 0.1µF such as the AD590.
–IN
ADA4077-2
2 7
+VS +VS
REF(–) AD8479
R1 R2 VOUT 1 8 NC
+IN 3 6 0.1µF
C2 THERMOCOUPLE –IN
REF(+) 2 7
–VS 4 5 +VS 0.1µF
–VS
+IN
0.1µF 3 6 VOUT
11118-039
NC = NO CONNECT
VREF
REF(+)
4 5
Figure 42. Filtering Output Noise Using a Two-Pole Butterworth Filter
11118-041
Table 6 provides recommended component values for various NC = NO CONNECT
corner frequencies and the peak-to-peak output noise for each Figure 43. Gain of 60 Thermocouple Amplifier
case.
Rev. C | Page 15 of 17
AD8479 Data Sheet
ERROR BUDGET ANALYSIS EXAMPLE The calculations in Table 7 assume an induced noise level of
In the dc application described in this section, the 10 A output 1 V p-p at 60 Hz on the lead wires, in addition to a full-scale dc
current from a device with a high common-mode voltage (such differential voltage of 10 V. The error budget table quantifies
as a power supply or current-mode amplifier) is sensed across a the contribution of each error source. Note that the dominant
1 Ω shunt resistor (see Figure 44). The common-mode voltage is error source in this example is due to the dc common-mode
600 V, and the resistor terminals are connected through a long voltage.
pair of lead wires located in a high noise environment, for example,
50 Hz/60 Hz, 440 V ac power lines.
OUTPUT
CURRENT
REF(–) AD8479
10A 1 8 NC
600V CMDC
TO GROUND –IN +VS
2 7
1Ω 0.1µF
SHUNT +IN
3 6 VOUT
REF(+)
–VS 4 5
60Hz
11118-042
POWER LINE 0.1µF
NC = NO CONNECT
Figure 44. Error Budget Analysis Example: VIN = 10 V Full Scale, VCM = 600 V DC,
RSHUNT = 1 Ω, 1 V p-p, 60 Hz Power Line Interference
Rev. C | Page 16 of 17
Data Sheet AD8479
OUTLINE DIMENSIONS
5.00 (0.1968)
4.80 (0.1890)
8 5
4.00 (0.1574) 6.20 (0.2441)
3.80 (0.1497) 1 5.80 (0.2284)
4
012407-A
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
ORDERING GUIDE
Package
Model 1 Temperature Range Package Description Option Qty.
AD8479ARZ −40°C to +125°C 8-Lead SOIC_N R-8
AD8479ARZ-RL −40°C to +125°C 8-Lead SOIC_N, 13-Inch Tape and Reel R-8 2,500 pieces
AD8479BRZ −40°C to +125°C 8-Lead SOIC_N R-8
AD8479BRZ-RL −40°C to +125°C 8-Lead SOIC_N, 13-Inch Tape and Reel R-8 2,500 pieces
AD8479R-EBZ Evaluation Board
1
Z = RoHS Compliant Part.
Rev. C | Page 17 of 17