Arithmetic Unit

Dr. Sowmya BJ
UNIT 2 – Arithmetic unit & Processing unit
Multiplication of two Numbers
A Signed Operand Multiplication
oBooth algorithm
Fast Multiplication
oBit pair recoding
oCarry Save Addition(CSA)
Integer Division
oRestoring Division
oNo restoring Division
IEEE standard for floating point numbers
 Multiplication of unsigned numbers
 Algorithm for multiplying unsigned
number and positive signed
numbers.
 The product of two n-digit number
can be accommodated in 2n digits
 n=4 digits  2*4= 8 digits
 Multiplication of unsigned numbers
 Algorithm for multiplying unsigned number
 If the multiplier bit is 1, the multiplicand is entered in the
appropriate position to be added to the partial product.
 If the multiplier bit is 0, then 0s are entered in the appropriate
position to be added to the partial product.
 2 13

2 6 1
13 (Multiplicand M) * 11 (Multiplier Q) =143
1101 1011 2 3

M 1 1 0 1 1

Q 1 0 1 1

P
 2 13

2 6 1
13 (Multiplicand M) * 11 (Multiplier Q) =143
1101 1011 2 3

M 1 1 0 1 1

Q 1 0 1 1
1 1 0 1

P
 2 13

2 6 1
13 (Multiplicand M) * 11 (Multiplier Q) =143
1101 1011 2 3

M 1 1 0 1 1

Q 1 0 1 1
1 1 0 1
1 1 0 1

P
 2 13

2 6 1
13 (Multiplicand M) * 11 (Multiplier Q) =143
1101 1011 2 3

M 1 1 0 1 1

Q 1 0 1 1
1 1 0 1
1 1 0 1
0 0 0 0

P
 2 13

2 6 1
13 (Multiplicand M) * 11 (Multiplier Q) =143
1101 1011 2 3

M 1 1 0 1 1

Q 1 0 1 1
1 1 0 1
1 1 0 1
0 0 0 0
1 1 0 1
P
 2 13

2 6 1
13 (Multiplicand M) * 11 (Multiplier Q) =143
1101 1011 2 3

M 1 1 0 1 1

Q 1 0 1 1
1 1 0 1
1 1 0 1
0 0 0 0
1 1 0 1
P 1
 2 13

2 6 1
13 (Multiplicand M) * 11 (Multiplier Q) =143
1101 1011 2 3

M 1 1 0 1 1

Q 1 0 1 1
1 1 0 1
1 1 0 1
0 0 0 0
1 1 0 1
P 1 1
 2 13

2 6 1
13 (Multiplicand M) * 11 (Multiplier Q) =143
1101 1011 2 3

M 1 1 0 1 1

Q 1 0 1 1
1 1 0 1
1 1 0 1
0 0 0 0
1 1 0 1
P 1 1 1
 2 13

2 6 1
13 (Multiplicand M) * 11 (Multiplier Q) =143
1101 1011 2 3

M 1 1 0 1 1

Q 1 0 1 1
1 1 1 0 1
1 1 0 1
0 0 0 0
1 1 0 1
P 1 1 1 1
 2 13

2 6 1
13 (Multiplicand M) * 11 (Multiplier Q) =143
1101 1011 2 3

M 1 1 0 1 1

Q 1 0 1 1
1 1 1 0 1
1 1 1 0 1
0 0 0 0
1 1 0 1
P 0 1 1 1 1
 2 13

2 6 1
13 (Multiplicand M) * 11 (Multiplier Q) =143
1101 1011 2 3

M 1 1 0 1 1

Q 1 0 1 1
1 1 1 0 1
1 1 1 0 1
1 0 0 0 0
1 1 0 1
P 0 0 1 1 1 1
 2 13

2 6 1
13 (Multiplicand M) * 11 (Multiplier Q) =143
1101 1011 2 3

M 1 1 0 1 1

Q 1 0 1 1
1 1 1 0 1
1 1 1 0 1
1 0 0 0 0
1 1 0 1
P 1 0 0 0 1 1 1 1
 2 13

2 6 1
13 (Multiplicand M) * 11 (Multiplier Q) =143
1101 1011 2 3

M 1 1 0 1 1

Q 1 0 1 1
1 1 1 0 1
1 1 1 0 1 P 1 0 0 0 1 1 1 1

1 0 0 0 0 27 26 25 24 23 22 21 20

1 1 0 1 128 8 4 2 1

P 1 0 0 0 1 1 1 1 128+8+4+2+1 = 143
Implementation of Multiplication
1. Array multiplier
2. Sequential multiplier
3. Booth multiplier
Multiplication of Positive Numbers
Simple algorithm
Multiplication of Positive Numbers
m3 m2 m1 m0

q0

m3 m2 m1 m0

q1
Multiplication of Positive Numbers
m3 m2 m1 m0

q0

m3 m2 m1 m0

q1

FA FA FA FA
Multiplication of Positive Numbers
Binary multiplication of positive
operands can be implemented in a Multiplicand

combinational 2D logic array (PP0)

0 m3 0 m2 0 m1 0 m0

q0
0
PP1 p0
q1
0
PP2 p1
q2
0
PP3 p2
q3
0
,
p7 p6 p5 p4 p3
Implementation of Multiplication
The main component in each cell Multiplicand

is a full adder 0 m3 0 m2 0 m1 0 m0
(PP0)
q0
0
PP1 p0
q1
0
PP2 p1
q2
0
PP3 p2
q3
0
,
p7 p6 p5 p4 p3
Implementation of Multiplication
The AND gate in each cell determines Multiplicand
whether a multiplicand bit mj, is added 0 m3 0 m2 0 m1 0 m0
to the incoming partial- product bit, (PP0)
q0
based on the value of the multiplier bit 0
PP1
qi q1
p0

0
PP2
p1
q2
0
PP3 p2
q3
0
,
p7 p6 p5 p4 p3
Combinatorial array multiplier
Combinatorial array multipliers are:
◦ Extremely inefficient.
◦ Have a high gate count for multiplying numbers of practical size such as 32-bit
or 64-bit numbers.
◦ Perform only one function, namely, unsigned integer product.
Improve gate efficiency by using a mixture of combinatorial array techniques and
sequential techniques requiring less combinational logic.
Sequential multiplication
Recall the rule for generating partial products:
◦ If the ith bit of the multiplier is 1, add the appropriately shifted multiplicand
to the current partial product.
◦ Multiplicand has been shifted left when added to the partial product.
However, adding a left-shifted multiplicand to an unshifted partial product is
equivalent to adding an unshifted multiplicand to a right-shifted partial
product.
Sequential multiplication procedure
1. Multiplicand(M) and Multiplier(Q) bits are loaded into register, C is initially
set to 0, Register A is initially set to 0
2. 0th Bit of Multiplier is checked
3. If 0th bit = 1
• Multiplicand and partial product is added
• All bits of Q, A and C registers are shifted to right one bit
4. If 0th bit = 0
• No addition is performed, only shift operation is carried out
Step 2, 3 and 4 are repeated n times to get desired result in A and Q registers
 Sequential multiplication
Multiply using sequential circuit multiplier 13 x 11
M
1 1 0 1
Initial configuration
0 0 0 0 0 1 0 1 1
C A Q
0 1 1 0 1 1 0 1 1 Add
Shift First cycle
0 0 1 1 0 1 1 0 1

1 0 0 1 1 1 1 0 1 Add
Shift Second cycle
0 1 0 0 1 1 1 1 0

0 1 0 0 1 1 1 1 0 No add
Shift Third cycle
0 0 1 0 0 1 1 1 1

1 0 0 0 1 1 1 1 1 Add
Shift Fourth cycle
0 1 0 0 0 1 1 1 1

Product
 M 1 1 0 1

C A Q
0 0 0 0 0 1 0 1 1
M 1 1 0 1

C A Q
0 0 0 0 0 1 0 1 1

1 1 0 1 ADD
M 1 1 0 1

C A Q
0 0 0 0 0 1 0 1 1

0 1 1 0 1 1 0 1 1 ADD
M 1 1 0 1

C A Q
0 0 0 0 0 1 0 1 1

0 1 1 0 1 1 0 1 1 ADD
1 SHIFT
M 1 1 0 1

C A Q
0 0 0 0 0 1 0 1 1

0 1 1 0 1 1 0 1 1 ADD
0 1 SHIFT
M 1 1 0 1

C A Q
0 0 0 0 0 1 0 1 1

0 1 1 0 1 1 0 1 1 ADD
1 0 1 SHIFT
M 1 1 0 1

C A Q
0 0 0 0 0 1 0 1 1

0 1 1 0 1 1 0 1 1 ADD
1 1 0 1 SHIFT
M 1 1 0 1

C A Q
0 0 0 0 0 1 0 1 1

0 1 1 0 1 1 0 1 1 ADD
0 1 1 0 1 SHIFT
M 1 1 0 1

C A Q
0 0 0 0 0 1 0 1 1

0 1 1 0 1 1 0 1 1 ADD
1 0 1 1 0 1 SHIFT
M 1 1 0 1

C A Q
0 0 0 0 0 1 0 1 1

0 1 1 0 1 1 0 1 1 ADD
1 1 0 1 1 0 1 SHIFT
M 1 1 0 1

C A Q
0 0 0 0 0 1 0 1 1

0 1 1 0 1 1 0 1 1 ADD
0 1 1 0 1 1 0 1 SHIFT
M 1 1 0 1

C A Q
0 0 0 0 0 1 0 1 1

0 1 1 0 1 1 0 1 1 ADD
0 0 1 1 0 1 1 0 1 SHIFT
M 1 1 0 1

C A Q
0 0 0 0 0 1 0 1 1

0 1 1 0 1 1 0 1 1 ADD
0 0 1 1 0 1 1 0 1 SHIFT
1 0 0 1 1 1 1 0 1 ADD
0 1 0 0 1 1 1 1 0 SHIFT
1 1 1 0 NO ADD
0 1 0 0 1
1 1 1 1 SHIFT
0 0 1 0 0

1 0 0 0 1 1 1 1 1 ADD
0 1 0 0 0 1 1 1 1 SHIFT
Examples
Multiply following numbers using sequential circuit multiplier
1. 24 x 16
2. 45 x 12
 Illustrate a sequential circuit binary multiplier with a neat
diagram.

Sequential Circuit Multiplier

Figure shows the Hardware arrangement for sequential multiplication
Procedure for multiplication:
 Multiplier is loaded into register Q, Multiplicand is loaded into register M

 C & A are cleared to 0

 Registers A and Q combined hold PPi(partial product)

 Multiplier bit qi generates the signal Add/Noadd.

 Single n-bit adder is used n times

 Sequential Circuit Multiplier
 If q0=1, add M to A and store sum in A.
 The carry-out from the adder is stored in flip-flop C
 Then C, A and Q are shifted right one bit-position.
 If q0=0, no addition performed and C, A & Q are shifted right one bit-
position.
 After n cycles, the high-order half of the product is held in register A
and the low-order half is held in register Q.
UNIT 2 – Arithmetic unit
Multiplication of two Numbers
A Signed Operand Multiplication
◦ Booth algorithm
Fast Multiplication
◦ Bit pair recoding
◦ Carry Save Addition(CSA)
Integer Division
IEEE standard for floating point numbers
Signed Multiplication
Multiplication of 2’s complement signed operands, generating a double length product
◦ Case1 :
Positive Multiplier and Negative multiplicand, When we add a negative multiplicand to a partial
product , we must extend sign-bit value of the multiplicand to the left as far as the product will
extend.
◦ Case2:
For a negative multiplier, a straightforward solution is to form the 2’s-complement of both the
multiplier and the multiplicand and proceed as in the case of a positive multiplier.
A technique that works equally well for both negative and positive multipliers – Booth algorithm.
Signed Multiplication
Considering 2’s-complement signed operands, what will happen to (-13)(+11) if following the
same method of unsigned multiplication?

1 0 0 1 1  - 13
0 1 0 1 1 ( + 11)

1 1 1 1 1 1 0 0 1 1

1 1 1 1 1 0 0 1 1
Sign extension is
shown in blue 0 0 0 0 0 0 0 0

1 1 1 0 0 1 1

0 0 0 0 0 0

1 1 0 1 1 1 0 0 0 1  - 143 

Sign extension of negative multiplicand.

Booth Algorithm
Booths recoding scheme
Multiplier is scanned from right to left

1 1 0 1 0 0
0 -1 +1 -1 0
Booth Algorithm
Recode the multiplier 101100

1 0 1 1 0 0 0

-1 +1 0 -1 0 0
 Booth Algorithm
1. Compute +13 x -6 using Booth algorithm

0 1 1 0 1
Booth multiplication with a negative multiplier.
0 - 1 +1 - 1 0
0 1 1 0 1 ( + 13) 0 0 0 0 0 0 0 0 0 0
X1 1 0 1 0 - 6  1 1 1 1 1 0 0 1 1
0 0 0 0 1 1 0 1
1 1 1 0 0 1 1
0 0 0 0 0 0
1 1 1 0 1 1 0 0 1 0  - 78 
 2 13 2 6

2 6 1 2 3 0

Booth Algorithm 2 3 1

1 M= 1 1 0 1
Represent in 1
Binary form
+13 -6 = 2’s complement
Q= -6 0 1 1 0 0 1 1 0
1 0 0 1
2 M= 1 1 0 1 1
Take 2’s
complement of +13
Negative value
Q= -6 1 0 1 0 1 0 1 0

3 M= 0 1 1 0 1 4 Q= -6 1 1 0 1 0 0
Add Sign bit +13 Recode
Multiplier

Q= -6 1 1 0 1 0 0 -1 +1 -1 0
Booth Algorithm
M 0 1 1 0 1

Q 0 -1 1 -1 0

0 0 0 0 0

P
Booth Algorithm
M 0 1 1 0 1

Q 0 -1 1 -1 0

0 0 0 0 0 0 0 0 0 0

P
Booth Algorithm
M 0 1 1 0 1
+13 = 2’s complement
Q 0 -1 1 -1 0
0 1 1 0 1
0 0 0 0 0 0 0 0 0 0 1 0 0 1 0
1
1 0 0 1 1
1 0 0 1 1

P
Booth Algorithm
M 0 1 1 0 1
+13 = 2’s complement
Q 0 -1 1 -1 0
0 1 1 0 1
0 0 0 0 0 0 0 0 0 0 1 0 0 1 0
1
1 1 1 1 1 0 0 1 1
1 0 0 1 1

P
Booth Algorithm
M 0 1 1 0 1

Q 0 -1 1 -1 0

0 0 0 0 0 0 0 0 0 0
1 1 1 1 1 0 0 1 1
0 1 1 0 1

P
Booth Algorithm
M 0 1 1 0 1

Q 0 -1 1 -1 0

0 0 0 0 0 0 0 0 0 0
1 1 1 1 1 0 0 1 1
0 0 0 0 1 1 0 1

P
Booth Algorithm
M 0 1 1 0 1
+13 = 2’s complement
Q 0 -1 1 -1 0
0 1 1 0 1
0 0 0 0 0 0 0 0 0 0 1 0 0 1 0
1
1 1 1 1 1 0 0 1 1
1 0 0 1 1
0 0 0 0 1 1 0 1
1 0 0 1 1

P
Booth Algorithm
M 0 1 1 0 1
+13 = 2’s complement
Q 0 -1 1 -1 0
0 1 1 0 1
0 0 0 0 0 0 0 0 0 0 1 0 0 1 0
1
1 1 1 1 1 0 0 1 1
1 0 0 1 1
0 0 0 0 1 1 0 1
1 1 1 0 0 1 1

P
Booth Algorithm
M 0 1 1 0 1

Q 0 -1 1 -1 0

0 0 0 0 0 0 0 0 0 0
1 1 1 1 1 0 0 1 1
0 0 0 0 1 1 0 1
1 1 1 0 0 1 1
0 0 0 0 0
P
Booth Algorithm
M 0 1 1 0 1

Q 0 -1 1 -1 0

0 0 0 0 0 0 0 0 0 0
1 1 1 1 1 0 0 1 1
0 0 0 0 1 1 0 1
1 1 1 0 0 1 1
0 0 0 0 0 0
P
 M 0 1 1 0 1
Booth Algorithm Q 0 -1 1 -1 0

1+ 1 = 10 1 1 1 1 1 1 1
1+1+1 = 11
0 0 0 0 0 0 0 0 0 0
1 1 1 1 1 0 0 1 1
1+1+1+1 = 100
0 0 0 0 1 1 0 1
1+1+1+1+1 = 101
1 1 1 0 0 1 1
1+1+1+1+1+1 = 110 0 0 0 0 0 0
Carry
ignore P 1 1 1 1 0 1 1 0 0 1 0
 A 0 1 0 1 1 1
Booth Algorithm B 0 -1 +1 0 -1 0

2. Multiply each of the following pairs of

signed 2’s complement numbers using
0 0 0 0 0 0 0 0 0 0 0 0
booth algorithm (Assume A is the 1 1 1 1 1 1 0 1 0 0 1
Multiplicand and B is the Multiplier)
A = 010111 B = 110110 0 0 0 0 0 0 0 0 0 0
Q= 1 1 0 1 1 0 0
0 0 0 0 1 0 1 1 1

0 -1 +1 0 -1 0
1 1 1 0 1 0 0 1
0 0 0 0 0 0 0
P
 A 0 1 0 1 1 1
Booth Algorithm B 0 -1 +1 0 -1 0

1 1 1 0 1 1 1
1+ 1 = 10
0 0 0 0 0 0 0 0 0 0 0 0
1+1+1 = 11
1 1 1 1 1 1 0 1 0 0 1
1+1+1+1 = 100
0 0 0 0 0 0 0 0 0 0
1+1+1+1+1 = 101 0 0 0 0 1 0 1 1 1
1+1+1+1+1+1 = 110 1 1 1 0 1 0 0 1
Carry 0 0 0 0 0 0 0
ignore
P 1 1 1 1 1 0 0 0 1 1 0 1 0
Examples for Booth Algorithm
1. Compute 45 x -24 using Booth algorithm

2. Compute -13 x -20 using Booth algorithm

3. Computer -13 x +9 using Booth algorithm

4. Computer 14 x -8 using Booth algorithm

5. Multiply each of the following pairs of signed 2’s complement numbers using booth
algorithm (Assume A is the Multiplicand and B is the Multiplier)
• A = 110011 B = 101100
• A = 110101 B = 011011
• A = 001111 B = 001111
• A = 10101 B = 10101
UNIT 2 – Arithmetic unit
Multiplication of two Numbers
A Signed Operand Multiplication
◦ Booth algorithm
Fast Multiplication
◦ Bit-Pair algorithm
◦ Carry Save Addition(CSA)

Integer Division
IEEE standard for floating point numbers
Bit-Pair algorithm
Bit-pair recoding halves the maximum number of
summands (versions of the multiplicand).
Sign extension Implied 0 to right of LSB
1 1 1 0 1 0 0

0 0  1 + 1 1 0

0 1 2

(a) Example of bit-pair recoding derived from Booth recoding

Bit-Pair algorithm
Recode the multiplier 101100

1 0 1 1 0 0 0

-1 -1 0
Bit-Pair algorithm
Recode the multiplier 011011

0 1 1 0 1 1 0

+2 -1 -1
 Bit-Pair algorithm
Recode the multiplier 1 1 0 1 0
Add sign
extended 1 1 1 0 1 0 0
bit

0 -1 -2
Bit-Pair algorithm
0 1 1 0 1
0 - 1 +1 - 1 0
0 0 0 0 0 0 0 0 0 0
1 1 1 1 1 0 0 1 1
0 0 0 0 1 1 0 1
1 1 1 0 0 1 1
0 1 1 0 1 ( + 13) 0 0 0 0 0 0
´ 1 1 0 1 0 - 6  1 1 1 0 1 1 0 0 1 0  - 78 

0 1 1 0 1
0 -1 -2
1 1 1 1 1 0 0 1 1 0
1 1 1 1 0 0 1 1
0 0 0 0 0 0
1 1 1 0 1 1 0 0 1 0
 2 13 2 6

2 6 1 2 3 0

Bit-Pair algorithm 2 1
3
1. Compute +13 x -6 using Bit Pair Recoding
technique. 1
1 M= 1 1 0 1 -6 = 2’s complement
Represent in
Binary form +13
0 1 1 0
Q= -6 0 1 1 0 1 0 0 1
1
2 M= 1 1 0 1
Take 2’s
complement of +13 1 0 1 0
Negative value
Q= -6 1 0 1 0
4 1 1 1 0 1 0 0
3 M= 0 1 1 0 1
Recode
Multiplier
Add Sign bit
+13
Q= -6 1 1 0 1 0 0 -1 -2
 M 0 1 1 0 1

Bit-Pair algorithm Q 0 -1 -2

If Multiplier bit is -2, take 2’s complement of 1 1 1 1 1 0 0 1 1 0

Multiplicand and then multiply with 10

M= 0 1 1 0 1
1 0 0 1 0
1

1 0 0 1 1 X 10

0 0 0 0 0
1 0 0 1 1

1 0 0 1 1 0
P
 M 0 1 1 0 1

Bit-Pair algorithm Q 0 -1 -2

If Multiplier bit is -1, take 2’s complement of 1 1 1 1 1 0 0 1 1 0

Multiplicand
1 1 1 1 0 0 1 1
M= 0 1 1 0 1
1 0 0 1 0
1

1 0 0 1 1

P
 M 0 1 1 0 1

Bit-Pair algorithm Q 0 -1 -2

If Multiplier bit is 0, then 0 X M 1 1 1 1 1 0 0 1 1 0

1 1 1 1 0 0 1 1
0 0 0 0 0 0

P
 M 0 1 1 0 1

Bit-Pair algorithm Q 0 -1 -2

If Multiplier bit is 0, then 0 X M 1 1 1 1 1 1

1 1 1 1 1 0 0 1 1 0
1 1 1 1 0 0 1 1
Carry ignore 0 0 0 0 0 0
P 1 1 1 1 0 1 1 0 0 1 0
 Bit-Pair algorithm
Compute -11 x +27 using Bit Pair Recoding technique.
-11 = 2’s complement
M= 0 1 0 1 1
1 -11
Represent in 0 1 0 1 1
Binary form
Q= 1 1 0 1 1 1 0 1 0 0
27 1

2 M= 1 0 1 0 1 1 0 1 0 1
Take 2’s
complement of -11
Negative value
Q=
27 4 0 1 1 0 1 1 0
3 Recode
Multiplier
Add Sign bit
M= 1 1 0 1 0 1
-11 +2 -1 -1
Q= 0 1 1 0 1 1
27
 M 1 1 0 1 0 1

Bit-Pair algorithm Q +2 -1 -1

If Multiplier bit is -1, take 2’s complement of

0 0 1 0 1 1
Multiplicand

1 1 0 1 0 1
0 0 1 0 1 0
1

0 0 1 0 1 1

P
 M 1 1 0 1 0 1

Bit-Pair algorithm Q +2 -1 -1

If Multiplier bit is -1, take 2’s complement of 0 0 0 0 0 0 0 0 1 0 1 1

Multiplicand

1 1 0 1 0 1
0 0 1 0 1 0
1

0 0 1 0 1 1

P
 M 1 1 0 1 0 1

Bit-Pair algorithm Q +2 -1 -1

If Multiplier bit is -1, take 2’s complement of 0 0 0 0 0 0 0 0 1 0 1 1

Multiplicand
0 0 0 0 0 0 1 0 1 1
1 1 0 1 0 1
0 0 1 0 1 0
1

0 0 1 0 1 1

P
 M 1 1 0 1 0 1

Bit-Pair algorithm Q +2 -1 -1

If Multiplier bit is +2, multiply the multiplicand 0 0 0 0 0 0 0 0 1 0 1 1

with 10
0 0 0 0 0 0 1 0 1 1
M= 1 1 0 1 0 1 X 10
1 1 0 1 0 1 0
0 0 0 0 0 0
1 1 0 1 0 1
1 1 0 1 0 1 0

P
 M 1 1 0 1 0 1

Bit-Pair algorithm Q +2 -1 -1

If Multiplier bit is +2, multiply the multiplicand 0 0 0 0 0 0 0 0 1 0 1 1

with 10
0 0 0 0 0 0 1 0 1 1
M= 1 1 0 1 0 1 X 10
1 1 1 0 1 0 1 0
0 0 0 0 0 0
1 1 0 1 0 1
1 1 0 1 0 1 0

P
 M 1 1 0 1 0 1

Bit-Pair algorithm Q +2 -1 -1

If Multiplier bit is +2, multiply the multiplicand 1 1

with 10
0 0 0 0 0 0 0 0 1 0 1 1
M= 1 1 0 1 0 1 X 10
0 0 0 0 0 0 1 0 1 1
0 0 0 0 0 0
1 1 0 1 0 1 1 1 1 0 1 0 1 0
1 1 0 1 0 1 0
P 1 1 1 0 1 1 0 1 0 1 1 1
 Examples for Bit-Pair Recoding Technique
1. Compute -87 X -35 using Bit Pair Recoding technique.

2. Write Booth multiplier recoding table and explain good, ordinary and worst-case multiplier with suitable examples.

3. Solve using Bit Pair Recoding technique

i)-14 X -5
ii) 12 X -4
iii) 45 X -24
iv) -32 X -15

4. Multiply each of the following pairs of signed 2’s complement numbers using bit pairing of the multiplier (Assume A
is the Multiplicand and B is the Multiplier)
i) A=010111 B=110110
ii) A=110011 B=101100.
Carry-Save Addition(CSA) of Summands
Multiplication requires the addition of several
summands
CSA speeds up the addition process
Consider the array for 4 x 4 multiplication
 Carry-Save Addition of Summands
Consider the addition of many summands:
Group the summands in threes and perform carry-save addition on each of these groups in
parallel to generate a set of S and C vectors in one full-adder delay
Group all of the S and C vectors into threes, and perform carry-save addition on them,
generating a further set of S and C vectors in one more full-adder delay
Continue with this process until there are only two vectors remaining
They can be added in a RCA or CLA to produce the desired product
Carry-Save Addition(CSA) of Summands
1+ 1 = 10
1+1+1 = 11
1+1+1+1 = 100
1+1+1+1+1 = 101
1+1+1+1+1+1 = 110
Carry-Save Addition(CSA) of Summands
Carry-Save Addition(CSA) of Summands
Carry-Save Addition(CSA) of Summands
Carry-Save Addition(CSA) of Summands
Carry-Save Addition(CSA) of Summands
Carry-Save Addition(CSA) of Summands
Examples for CSA
1. Write the schematic representation of carry save addition and perform 47 x 60 using CSA

2. Illustrate the working of CSA with 45 and 63 as the Multiplicand and Multiplier
respectively.
 UNIT 2 – Arithmetic unit
Multiplication of two Numbers
A Signed Operand Multiplication
◦ Booth algorithm
Fast Multiplication
◦ Bit pair recoding
◦ Carry Save Addition(CSA)
Integer Division
◦ Restoring Division
◦ Nonrestoring Division
IEEE standard for floating point numbers
Integer Division
Algorithm to perform restoring division
1. Initialize Register A = n+1 bits with 0’s and Register Q with Dividend bits and M with
Divisor bits, Count = n
2. Shift A and Q left one binary position
3. Subtract M from A, and place the answer back in A ( A = A-M)
4. Observe the sign bit of A
oIf the sign bit of A is 1, set q0 = 0 and add M back to A( A=A+M) restoration is done
oIf the sign bit of A is 0, set q0 = 1 ,norestoration is done
5. Count = Count – 1
6. Repeat step 2,3,4,5 until count = 0
1. Compute 10/3 using restoring division 1 1 0 1
Dividend Q=10

Divisor M=3 0 0 1 1

A Q
0 0 0 0 0 1 0 1 0 M 0 0 0 1 1
 1. Compute 10/3 using restoring division 1 1 0 1
Dividend Q=10

Divisor M=3 0 0 1 1

Count =4 A Q
0 0 0 0 0 1 0 1 0 M 0 0 0 1 1

Shift 0 0 0 0 1 0 1 0
 1. Compute 10/3 using restoring division 1 1 0 1
Dividend Q=10

Divisor M=3 0 0 1 1

Count =4 A Q
0 0 0 0 0 1 0 1 0 M 0 0 0 1 1

Shift 0 0 0 0 1 0 1 0
Subtract 1 1 1 0 1 2’s complement of M

M= 0 0 0 1 1
1 1 1 0 0
1
1 1 1 0 1
 1. Compute 10/3 using restoring division 1 1 0 1
Dividend Q=10

Divisor M=3 0 0 1 1

Count =4 A Q
0 0 0 0 0 1 0 1 0 M 0 0 0 1 1

Shift 0 0 0 0 1 0 1 0
Subtract 1 1 1 0 1
1 1 1 1 0
 1. Compute 10/3 using restoring division 1 1 0 1
Dividend Q=10

Divisor M=3 0 0 1 1

Count =4 A Q
0 0 0 0 0 1 0 1 0 M 0 0 0 1 1

Shift 0 0 0 0 1 0 1 0
Subtract 1 1 1 0 1
Set q0 1 1 1 1 0

0 1 0 0
 1. Compute 10/3 using restoring division 1 1 0 1
Dividend Q=10

Divisor M=3 0 0 1 1

Count =4 A Q
0 0 0 0 0 1 0 1 0 M 0 0 0 1 1

Shift 0 0 0 0 1 0 1 0
Subtract 1 1 1 0 1
M 0 0 0 1 1
Set q0 1 1 1 1 0
Restore 1 0 0 0 0 1 0 1 0 0 A 1 1 1 1 0

A+M 1 0 0 0 0 1
 1. Compute 10/3 using restoring division 1 1 0 1
Dividend Q=10

Divisor M=3 0 0 1 1

Count = 3 A Q
0 0 0 0 1 0 1 0 0 M 0 0 0 1 1

Shift 0 0 0 1 0 1 0 0
 1. Compute 10/3 using restoring division 1 1 0 1
Dividend Q=10

Divisor M=3 0 0 1 1

Count =3 A Q
0 0 0 0 1 0 1 0 0 M 0 0 0 1 1

Shift 0 0 0 1 0 1 0 0
Subtract 1 1 1 0 1 2’s complement of M

M= 0 0 0 1 1
1 1 1 0 0
1
1 1 1 0 1
 1. Compute 10/3 using restoring division 1 1 0 1
Dividend Q=10

Divisor M=3 0 0 1 1

Count =3 A Q
0 0 0 0 1 0 1 0 0 M 0 0 0 1 1

Shift 0 0 0 1 0 1 0 0
Subtract 1 1 1 0 1
1 1 1 1 1
 1. Compute 10/3 using restoring division 1 1 0 1
Dividend Q=10

Divisor M=3 0 0 1 1

Count =3 A Q
0 0 0 0 1 0 1 0 0 M 0 0 0 1 1

Shift 0 0 0 1 0 1 0 0
Subtract 1 1 1 0 1
Set q0 1 1 1 1 1

1 0 0 0
 1. Compute 10/3 using restoring division 1 1 0 1
Dividend Q=10

Divisor M=3 0 0 1 1

Count =3 A Q
0 0 0 0 1 0 1 0 0 M 0 0 0 1 1

Shift 0 0 0 1 0 1 0 0
Subtract 1 1 1 0 1
M 0 0 0 1 1
Set q0 1 1 1 1 1
Restore 1 0 0 0 1 0 1 0 0 0 A 1 1 1 1 1

A+M 1 0 0 0 1 0
 1. Compute 10/3 using restoring division 1 1 0 1
Dividend Q=10

Divisor M=3 0 0 1 1

Count =2 A Q
0 0 0 1 0 1 0 0 0 M 0 0 0 1 1

Shift 0 0 1 0 1 0 0 0
 1. Compute 10/3 using restoring division 1 1 0 1
Dividend Q=10

Divisor M=3 0 0 1 1

Count =2 A Q
0 0 0 1 0 1 0 0 0 M 0 0 0 1 1

Shift 0 0 1 0 1 0 0 0
Subtract 1 1 1 0 1 2’s complement of M

M= 0 0 0 1 1
1 1 1 0 0
1
1 1 1 0 1
 1. Compute 10/3 using restoring division 1 1 0 1
Dividend Q=10

Divisor M=3 0 0 1 1

Count =2 A Q
0 0 0 1 0 1 0 0 0 M 0 0 0 1 1

Shift 0 0 1 0 1 0 0 0
Subtract 1 1 1 0 1
0 0 0 1 0
 1. Compute 10/3 using restoring division 1 1 0 1
Dividend Q=10

Divisor M=3 0 0 1 1

Count =2 A Q
0 0 0 1 0 1 0 0 0 M 0 0 0 1 1
Shift 0 0 1 0 1 0 0 0
Subtract 1 1 1 0 1
Set q0 1 0 0 0 1 0

0 0 0 1
 1. Compute 10/3 using restoring division 1 1 0 1
Dividend Q=10

Divisor M=3 0 0 1 1

Count =2 A Q
0 0 0 1 0 1 0 0 0 M 0 0 0 1 1

Shift 0 0 1 0 1 0 0 0
Subtract 1 1 1 0 1
Set q0 1 0 0 0 1 0
NoRestore 0 0 0 1
 1. Compute 10/3 using restoring division 1 1 0 1
Dividend Q=10

Divisor M=3 0 0 1 1

Count =1 A Q
0 0 0 1 0 0 0 0 1 M 0 0 0 1 1

Shift 0 0 1 0 0 0 0 1
 1. Compute 10/3 using restoring division 1 1 0 1
Dividend Q=10

Divisor M=3 0 0 1 1

Count =1 A Q
0 0 0 1 0 0 0 0 1 M 0 0 0 1 1

Shift 0 0 1 0 0 0 0 1
Subtract 1 1 1 0 1 2’s complement of M

M= 0 0 0 1 1
1 1 1 0 0
1
1 1 1 0 1
 1. Compute 10/3 using restoring division 1 1 0 1
Dividend Q=10

Divisor M=3 0 0 1 1

Count =1 A Q
0 0 0 1 0 0 0 0 1 M 0 0 0 1 1
Shift 0 0 1 0 0 0 0 1
Subtract 1 1 1 0 1
1 0 0 0 0 1
 1. Compute 10/3 using restoring division 1 1 0 1
Dividend Q=10

Divisor M=3 0 0 1 1

Count =1 A Q
0 0 0 1 0 0 0 0 1 M 0 0 0 1 1

Shift 0 0 1 0 0 0 0 1
Subtract 1 1 1 0 1
Set q0 1 0 0 0 0 1

0 0 1 1
 1. Compute 10/3 using restoring division 1 1 0 1
Dividend Q=10

Divisor M=3 0 0 1 1

Count =1 A Q
0 0 0 1 0 0 0 0 1 M 0 0 0 1 1

Shift 0 0 1 0 0 0 0 1
Subtract 1 1 1 0 1
Set q0 0 0 0 0 1
Norestore 0 0 1 1

Remainer A = 00001 and Quotient Q = 0011

 2. Compute 8/3 using restoring division

Initially0 0 0 0 0 1 0 0 0
0 0 0 1 1
Shift 0 0 0 0 1 0 0 0
Subtract 1 1 1 0 1 First cycle
Set q0 1 1 1 1 0
Restore 1 1
0 0 0 0 1 0 0 0 0
1 0 Shift 0 0 0 1 0 0 0 0
1 1 10 0 0 Subtract 1 1 1 0 1
1 1 Set q0 1 1 1 1 1 Second cycle
Restore 1 1
1 0 0 0 0 1 0 0 0 0 0
Shift 0 0 1 0 0 0 0 0
Subtract 1 1 1 0 1
Set q0 0 0 0 0 1 Third cycle

Shift 0 0 0 1 0 0 0 0 1
Subtract 1 1 1 0 1 0 0 1
Set q0 1 1 1 1 1 Fourth cycle
Restore 1 1
0 0 0 1 0 0 0 1 0

Remainder Quotient
Restoring division - Circuit Arrangement
Shift left

an an-1 a0 qn-1 q0
Dividend Q
A Quotient
Setting

N+1 bit Add/Subtract

adder
Control
Sequencer

0 mn-1 m0

Divisor M
Examples for Restoring Division
1. Perform the following using restoring division algorithm.
i)20/5 ii) 12/3
2. Give an Algorithm for Restoring division method.
3. Compute 22/5 using restoring division
Algorithm to perform Nonrestoring division
1. Initialize Register A = n+1 bits with 0’s and Register Q with Dividend bits and M with
Divisor bits, Count = n
2. Shift A and Q left one binary position
3. After left shift ,if the sign bit of A is 0 , then
Then if Sign bit of A=1 Set Q0=0
Perform A=A-M Then if Sign bit of A =0 Set Q0=1

else, If the sign bit of A is 1, then

Then if Sign bit of A=1 Set Q0=0
Perform A=A+M Then if Sign bit of A =0 Set Q0=1

4. Repeat step 2 and 3 , n times

5. If the sign bit of A is 1, add Divisor to A
 1. Compute 8/3 using nonrestoring division 1 0
1 1 1 0 0 0
Q 1 1
A
M= 0 0 0 1 1 1 0
Initially 0 0 0 0 0 1 0 0 0

Shift 0 0 0 0 1 0 0 0 First cycle

Subtract 1 1 1 0 1
Set q 0 1 1 1 1 0 0 0 0 0
M= 0 0 0 1 1
Shift 1 1 1 0 0 0 0 0 1 1 1 0 0
Add 0 0 0 1 1 Second cycle 1
Set q 1 1 1 1 1 0 0 0 0
1 1 1 0 1
0

Shift 1 1 1 1 0 0 0 0
1 1 1 1 1 Add 0 0 0 1 1 Third cycle
Restore
0 0 0 1 1 Set q 0 0 0 0 1 0 0 0 1
remainder 0
Add 0 0 0 1 0
Remainder Shift 0 0 0 1 0 0 0 1
Subtract 1 1 1 0 1 Fourth cycle
Set q 1 1 1 1 1 0 0 1 0
0

Quotient
Examples for Nonrestoring division
1. State and apply non-restoring division algorithm to perform integer division 59/5.

2. Perform Nonrestoring division 10/3

3. Perform Nonrestoring division 11/5

4. Perform Nonrestoring division 23/5

 UNIT 2 – Arithmetic unit
Multiplication of two Numbers
A Signed Operand Multiplication
◦ Booth algorithm
Fast Multiplication
◦ Bit pair recoding
◦ Carry Save Addition(CSA)
Integer Division
◦ Restoring Division
◦ Nonrestoring Division
IEEE standard for floating point numbers
IEEE standard for floating point numbers
• The IEEE Standard for Floating-Point Arithmetic is a technical
standard for floating-point computation which was established
in 1985 by the Institute of Electrical and Electronics Engineers
(IEEE).
• The standard addressed many problems found in the diverse
floating point implementations that made them difficult to use
reliably and reduced their portability.
• IEEE Standard floating point is the most common representation
today for real numbers on computers, including Intel-based PC’s,
Macs, and most Unix platforms.
IEEE standard for floating point numbers
Datatype Representation
• Fixed Point number
• Floating Point number

Fixed Point number 0111

1000
• (+7)10 = (0 111)2 1
• (-7)10 = (100 1)2 ----------
1001
IEEE standard for floating point numbers
Floating Point numbers -It has 3 parts
• Mantissa (M)
Scientific Notation M x BE
• Base (B)
• Exponent (E)
Number M B E
9 x 108 9 10 8
110 x 27 110 2 7
4364.784 4364784 10 -3
 IEEE standard for floating point numbers
• Single Precision format M x BE
1.The Sign of Mantissa
0 represents a positive number while 1 represents a negative number.
2.The Biased exponent
The exponent field needs to represent both positive and negative
exponents. A bias is added to the actual exponent in order to get the
stored exponent.
3.The Normalised Mantissa
The mantissa is part of a number in scientific notation or a floating-point
number, consisting of its significant digits. Here we have only 2 digits, i.e.
O and 1. So a normalised mantissa is one with only one 1 to the left of the
decimal.
IEEE standard for floating point numbers
• Double Precision format M x BE

• Normalize
 Example
1.Represent (1259.125)10 in single and double precision IEEE floating point format.

Solution

Step 1: Convert decimal to Binary form

Step 2: Normalize the number

Step 3: Represent in Single precision form

Step 4: Represent in double precision form

 Example
1.Represent (1259.125)10 in single and double precision IEEE floating point format.

Solution

Step 1: Convert decimal to Binary form

(1259)10 10011101011
(0.125)10 0.125 x 2 = 0.25 0 001
0.25 x 2 = 0.5 0
0.5 x 2 = 1 1
(1259.125)10 = (10011101011.001)
 Example
1.Represent (1259.125)10 in single and double precision IEEE floating point format.

Solution

Step 2: Normalize the number (1259.125)10 = (10011101011.001)

 1.0011101011001 x 210
 Example
1.Represent (1259.125)10 in single and double precision IEEE floating point format.

Solution

Step 3: Represent in Single precision form

 1.0011101011001 x 210
 210 0 10001001 0011101011001000000000
E’ - 127 = 10
S-1bit E’ -8bits M- 23bits
E’ = 10+ 127

E’ = 137  Binary form 10001001

 Example
1.Represent (1259.125)10 in single and double precision IEEE floating point format.

Solution

Step 4: Represent in Double precision form

 1.0011101011001 x 210
 210 0 10000001001 001110101100100…..0000
E’ - 1023 = 10
S-1bit E’ -11bits M- 52bits
E’ = 10+ 1023

E’ = 1033  Binary form 10000001001

 Example
2. Compute the single precision IEEE 754 binary representation of the number
(−118.625)10.

Solution

Step 1: Convert decimal to Binary form

(118)10 1110110
(0.625)10 0.625 x 2 = 1.25 1 101
0.25 x 2 = 0.5 0
0.5 x 2 = 1 1
(118.625)10 = (1110110.101)2
 Example
2.Compute the single precision IEEE 754 binary representation of the number
(−118.625)10.

Step 2: Normalize the number (118.625)10 = (1110110.101)2

 1.110110101 x 26
 Example
2.Compute the single precision IEEE 754 binary representation of the number
(−118.625)10.

Step 3: Represent in Single precision form

 1.110110101 x 26
 26
1 10000101 110110101000…000000
E’ - 127 = 6
E’ = 6+ 127 S-1bit E’ -8bits M- 23bits

E’ = 133  Binary form 10000101

 Example
3.Represent (85.125)10 in single and double precision IEEE floating point format.

Solution

Step 1: Convert decimal to Binary form

(85)10 1010101
(0.125)10 0.125 x 2 = 0.25 0 001
0.25 x 2 = 0.5 0
0.5 x 2 = 1 1
(85.125)10 = (1010101.001)
 Example
3.Represent (85.125)10 in single and double precision IEEE floating point format.

Step 2: Normalize the number (85.125)10 = (1010101.001)

 1.010101001 x 26
10000101

Example
3.Represent (85.125)10 in single and double precision IEEE floating point format.

Step 3: Represent in Single precision form

 1.010101001 x 26
 26 0 10000101 01010100100000..0000
E’ - 127 = 6
S-1bit E’ -8bits M- 23bits
E’ = 6+ 127

E’ = 133  Binary form 10001001

 Example
3.Represent (85.125)10 in single and double precision IEEE floating point format.

Step 4: Represent in Double precision form

 1.010101001 x 26

 26 0 10000000101 01010100100………..0000

E’ - 1023 = 6 S-1bit E’ -11bits M- 52bits

E’ = 6+ 1023

E’ = 1029  Binary form 10000000101

 Example
4.Represent (263.3)10 in single precision IEEE floating point format.

Solution 0.3 *2= 0.6  0

0.6 *2= 1.2  1
Step 1: Convert decimal to Binary form 0.2 *2= 0.4 0
0.4 *2 = 0.8  0
(263)10 100000111 0.8 *2= 1.6  1
(0.3)10 0.3 x 2 = 0.6 0 010011001…. 0.6 *2 =1.2  1
0.2 *2= 0.4 0
0.6 x 2 = 1.2 1 0.4 *2 = 0.8  0
0.8 *2= 1.6  1
0.2 x 2 = 0.4 0 0.6 *2 =1.2  1
0.4 x 2 = 0.8 0 0.2 *2= 0.4 0
0.4 *2 = 0.8  0
0.8 x 2 = 1.6 1 0.8 *2= 1.6  1
(263.3)10 = (100000111. 010011001….)
 Example
4.Represent (263.3)10 in single precision IEEE floating point format.

Solution

Step 2: Normalize the number (263.3)10 = (100000111. 010011001….)

 1.00000111010011001…… x 28
 Example
4.Represent (1259.125)10 in single precision IEEE floating point format.

Solution

Step 3: Represent in Single precision form

 1.00000111010011001…… x 28

 28 0 10000111 00000111010011001……
E’ - 127 = 8
E’ = 8+ 127 S-1bit E’ -8bits M- 23bits

E’ = 135  Binary form 10000111

 Examples
1.Use IEEE single and double precision formats to represent the following floating point
numbers.
i) 120.75 ii) -875.45
2. Represent the following in binary using IEEE 754 Double precision format:
i) 12.0875 ii) 0.625.

3. Show the following numbers using IEEE double precision formats.

i)124.45 ii) -369.25.
4. Represent -307.1875 in single and double precision IEEE floating point numbers.