AMRITA SCHOOL OF ENGINEERING, BENGALURU

DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING

B. TECH. III SEMESTER AY 2023-2024

19ECE282 DIGITAL ELECTRONICS AND SYSTEMS LAB
SYSTEM DESIGN REPORT
DECEMBER 2023

TITLE OF THE SYSTEM DESIGN

Submitted by

BL.EN.U4ECE22021 E GOKUL KRISHNA

BL.EN.U4ECE22022 E SANDEEP REDDY

BL.EN.U4ECE22023 G SATHWICK

BL.EN.U4ECE22033 M BHANU CHARAN

BATCH NUMBER: A1-

FACULTY EXAMINER SIGNATURE WITH EVALUATION DATE

COMMENTS (IF ANY)
AIM: To design a digital calculator for 5 operations.

COMPONENTS REQUIRED: Three dip switches(8 pin,6 pin,2 pin),Four bit magnitude comparator
(7485), Four bit parallel adder/subtractor (7483), XOR Gate (7486) Three, LED(5+3+4), Resisters(5+3+4).

THEORY:

Binary to Gray Code Converter:-

A binary code represents text, computer processor instructions, or any other data using a twosymbol system.
The two-symbol system used is often "0" and "1" from the binary number system. The reflected binary code,
also known just as reflected binary or Gray code after Frank Gray, is an ordering of the binary numeral
system such that two successive values differ in only one bit. It is an unweighted code, as here like other
number systems, no particular weight is provided to various bit positions. Basically, binary code is changed
to gray equivalent in order to lessen the switching operations. As only a single bit is changed at a particular
time duration this leads to a reduction in switching from one bit to another.

Binary to Gray Conversion Procedure:

• In the Gray code, the MSB will always be the same as the 1'st bit of the given binary number.
• In order to perform the 2nd bit of the gray code, perform the exclusive-or (XOR) of the 1'st and 2nd
bit of the binary number. It means that if both the bits are different, the result will be one else the
result will be 0.
• n order to get the 3rd bit of the gray code, perform the exclusive-or (XOR) of the 2nd and 3 rd bit of
the binary number. The process remains the same for the remaining bits of the Gray code.

Let's take an example to understand these steps. Consider a binary number 01101

Truth Table:

Binary Code Gray Code

B3 B2 B1 B0 G3 G2 G1 G0
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 0 0 0 1 1
0 0 1 1 0 0 1 0
0 1 0 0 0 1 1 0
0 1 0 1 0 1 1 1
0 1 1 0 0 1 0 1
0 1 1 1 0 1 0 0
1 0 0 0 1 1 0 0
1 0 0 1 1 1 0 1
1 0 1 0 1 1 1 1
1 0 1 1 1 1 1 0
 1 1 0 0 1 0 1 0
1 1 0 1 1 0 1 1
1 1 1 0 1 0 0 1
1 1 1 1 1 0 0 0

Logical Equation:

G3 = Ʃm (8,9,10,11,12,13,14,15)
G2 = Ʃm (4,5,6,7,8,9,10,11)
G1 = Ʃm (2,3,4,5,10,11,12,13)
G0 = Ʃm (1,2,5,6,9,10,13,14)

K-Map Simplification:
K map for g0 K map for g1

go= b0b1’ + b1b0’ = b0 ⊕ b1 g1= b1b2’ + b2b1’ = b1 ⊕ b2

K map for g2 K map for g3

g2= b2b3’ + b3b2’ = b2 ⊕ b3 g3 = b3

Logic Diagram:
Gray to Binary Code Converter :
The Gray to Binary code converter is a logical circuit that is used to convert the gray code into its equivalent
binary code.
Gray to Binary Conversion Procedure:
• Just like binary to gray, in gray to binary, the 1st bit of the binary number is similar to the MSB of
the Gray code.
• In order to perform the 2nd bit of the binary code, perform the exclusive-or (XOR) of the 1'st bit of
binary output and 2nd bit of the gray number. It means that if both the bits are different, the result
will be one else the result will be 0.
• In order to get the 3rd bit of the binary code, perform the exclusive-or (XOR) of the 2nd bit of binary
output and 3rd bit of the gray number. The process remains the same for the remaining bits of the
Gray code.

Truth Table:

Gray Code Binary Code

G3 G2 G1 G0 B3 B2 B1 B0
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 0 0 0 1 1
0 0 1 1 0 0 1 0
0 1 0 0 0 1 1 1
0 1 0 1 0 1 1 0
0 1 1 0 0 1 0 0
0 1 1 1 0 1 0 1
1 0 0 0 1 1 1 1
1 0 0 1 1 1 1 0
1 0 1 0 1 1 1 0
1 0 1 1 1 1 1 1
1 1 0 0 1 0 0 0
1 1 0 1 1 0 0 1
1 1 1 0 1 0 0 1
1 1 1 1 1 0 0 0

Logic Equation:

B3 = Ʃm(8,9,10,11,12,13,14,15)

B2 = Ʃm (4,5,6,7,8,9,10,11)

B1 = Ʃm (2,3,4,5,8,9,10,11)

B0 = Ʃm (1,2,4,7,8,11,13,14)
K-Map Simplification
K map for b0 K map for b1
bo= g3 ⊕g2 ⊕g1 ⊕go b1=g3 ⊕g2 ⊕g1

K map for b2 K map for b3

B2= g3 ⊕g2 B2= g3

Logic Diagram:
4-bit Magnitude Comparator:
A comparator used to compare two binary numbers each of four bits is called a 4-bit magnitude comparator.
It consists of eight inputs each for two four-bit numbers and three outputs to generate less than, equal to, and
greater than between two binary numbers.
In a 4-bit comparator, the condition of A>B can be possible in the following four cases.
1. If A3 = 1 and B3 = 0
2. If A3 = B3 and A2 = 1 and B2 = 0
3. If A3 = B3, A2 = B2 and A1 = 1 and B1 = 0
4. If A3 = B3, A2 = B2, A1 = B1 and A0 = 1 and B0 = 0
Similarly, the condition for A<B can be possible in the following four cases.
1. If A3 = 0 and B3 = 1
2. If A3 = B3 and A2 = 0 and B2 = 1
3. If A3 = B3, A2 = B2 and A1 = 0 and B1 = 1
4. If A3 = B3, A2 = B2, A1 = B1 and A0 = 0 and B0 = 1
The condition of A=B is possible only when all the individual bits of one number exactly coincide with the
corresponding bits of another number.

Pin Diagram of IC 7485 (4-bit Magnitude Comparator):

Truth Table: (total 256 different inputs can provide , some of them given below)

A inputs B inputs A<B A=B A>B

A3 A2 A1 A0 B3 B2 B1 B0
1 1 1 1 1 1 1 1 0 1 0
0 0 1 0 0 0 1 0 0 1 0
0 0 0 1 1 0 0 0 1 0 0
1 0 0 0 0 0 0 1 0 0 1
1 0 1 1 1 1 1 1 1 0 0
0 0 0 0 0 0 0 0 0 1 0
0 0 0 1 0 0 1 0 1 0 0
0 0 1 0 0 0 0 1 0 0 1
0 0 1 1 0 0 1 1 0 1 0
0 1 0 0 1 0 0 0 1 0 0
0 1 0 1 1 0 1 0 1 0 0
0 1 1 0 1 0 0 1 1 0 0
0 1 1 1 1 0 1 1 1 0 0
1 0 0 0 1 1 0 0 1 0 0
1 0 0 1 1 1 1 1 1 0 0
1 0 1 0 1 1 0 0 1 0 0
1 0 1 1 1 1 1 1 1 0 0
1 1 0 0 0 1 0 0 0 0 1
1 1 0 1 0 1 1 1 0 0 1
1 1 1 0 0 1 0 0 0 0 1
1 1 1 1 0 1 1 1 0 0 1

Parallel Adder/Subtractor:

A parallel adder/subtractor is a system consists of n full adders connected in series for an n bit addition. The
inputs for the system are two n bit numbers and carry-in, output for the system is n bit sum and carry-out.
The Arithmetic micro-operations like addition and subtraction can be combined into one common circuit by
including an exclusive-OR gate with each full adder. The Subtraction micro-operation can be done easily by
taking the 2's complement of addend bits and adding it to the augend bits.
Logic Diagram of Adder/Subtractor:
Parallel Adder/Subtractor using IC7483:

A3A2A1A0 = 4-bits of 1 st input A B3B2B1B0 = 4-bits of 2 nd input B

Ci = Carry input Co = 1-bit carry output
S3S2S1S0 = 4-bit sum output

If ADD’/SUB = 0, then the circuit acts as a parallel adder.

If ADD’/SUB = 1, then the circuit acts as a parallel subtractor.
(Subtraction is carried out here using 2’s complement method, ignore Cout that is CO output)

Example:
Assume two unsigned 4-bit numbers A and B where
A = 1011 B = 0110
To perform (A + B), use 4-bit Ripple carry adder where the carry-in Ci is 0. 
For subtraction (A – B), A is added with 2’s complement of B i.e. A + (-B)
A = 1011 A = 1011
B = 0110 (-B) = 1001 1’s comp of B
+ 0˿ c0 + 1 (1’s comp + 1 = 2’s comp of B)
10001 10101

Another Inputs
A = 1010 B = 1110
A+B A-B
A=1010 A= 1010
B=1110 (-B)= 0001 1’s comp of B
+ 0-Cin + 1 (1’s comp + 1 = 2’s comp of B)
11000 01100

A = 1010 B = 0011
A+B A-B
A=1010 A= 1010
B=0011 (-B)= 1100 1’s comp of B
+ 0-Cin + 1 (1’s comp + 1 = 2’s comp of B)
01101 10111
BLOCK DIAGRAM CONSISTING ALL THE REQUIRED FUNCTIONS:
Pin description:

Dip switch’s

For 8 way switch:

1 – a3
2 – a2
3 – a1
4 – a0
5 – b3
6 – b2
7 – b1
8 – b0

For 2 way switch:

2 – (is used for connection between XOR IC’s of Binary to gray and Gray to Binary)

For 6 way switch:

1 – is used to on 7485 magnitude comparator

2 – 7483( 5 pin), 7486( 16 pin )
3 – 7483( 13 pin), 7486( 2,5,10,13 pin )
4 – is used to on 7486 XOR (gray to binary)
5 – is used to on 7486 XOR (binary to gray)

For Binary to Gray:

7486:-

1 – a3
2 – a2
3 – o/p(g2)
4 – a2
5 – a3
6 – o/p(g1)
7 – GND
8 – o/p(g0)
9 – a0
10 – a3
14 – Vcc

For Gray to Binary:

7486:-

1 – a3
2 – a2
3 – o/p(g2)
4 – g2
5 – a3
6 – o/p(g1)
7 – GND
8 – o/p(g0)
9 – a0
10 – g1
14 – Vcc

For Parallel adder/subtractor:

7486:-
1 – b3
2 – Cin
3 – o/p(b3)
4 – b2
5 – Cin
6 – o/p(b2)
7 – GND
8 – o/p(b1)
9 – Cin
10 – b1
11 – o/p(b0)
12 – Cin
13 – b0
14 –Vcc

7483:
1 – a3
2 – o/p(s2)
3 – a2
4 – b2(o/p of XOR)
5 – Vcc
6 – s1(o/p)
7 – b1(o/p of XOR)
8 – a1
9 – s0(o/p)
10 – a0
11 – b0(o/p of XOR)
12 – GND
13 – Cin
14 –Cout(o/p)
15 – s3(o/p)
16 – b3(o/p of 7486)
For Magnitude Comparator:

7485:-
1 – b3
2–
3 – 1(Vcc)
4–
5 – o/p(A>B)
6 – o/p(A=B)
7 – o/p(A<B)
8 – GND
9 – b0
10 – a0
11 – b1
12 – a1
13 – a2
14 –b2

SCREENSHOT OF THE WORKING HARDWARE FOR ALL THE REQUIRED

FUNCTIONS:

For binary to gray code

For gray to binary code

For magnitude comparator

OUTPUT OBTAINED (PREFERABLY IN A TABLE):

Truth Table for Binary to Gray Conversion:

Binary Code Gray Code

B3 B2 B1 B0 G3 G2 G1 G0
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 0 0 0 1 1
0 0 1 1 0 0 1 0
0 1 0 0 0 1 1 0
 0 1 0 1 0 1 1 1
0 1 1 0 0 1 0 1
0 1 1 1 0 1 0 0
1 0 0 0 1 1 0 0
1 0 0 1 1 1 0 1
1 0 1 0 1 1 1 1
1 0 1 1 1 1 1 0
1 1 0 0 1 0 1 0
1 1 0 1 1 0 1 1
1 1 1 0 1 0 0 1
1 1 1 1 1 0 0 0

Truth Table for Gray to Binary Code Converter:

Gray Code Binary Code

G3 G2 G1 G0 B3 B2 B1 B0
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 0 0 0 1 1
0 0 1 1 0 0 1 0
0 1 0 0 0 1 1 1
0 1 0 1 0 1 1 0
0 1 1 0 0 1 0 0
0 1 1 1 0 1 0 1
1 0 0 0 1 1 1 1
1 0 0 1 1 1 1 0
1 0 1 0 1 1 1 0
1 0 1 1 1 1 1 1
1 1 0 0 1 0 0 0
1 1 0 1 1 0 0 1
1 1 1 0 1 0 0 1
1 1 1 1 1 0 0 0

Truth table for 4-bit Magnitude Comparator:

A inputs B inputs A<B A=B A>B

A3 A2 A1 A0 B3 B2 B1 B0
1 1 1 1 1 1 1 1 0 1 0
0 0 1 0 0 0 1 0 0 1 0
0 0 0 1 1 0 0 0 1 0 0
1 0 0 0 0 0 0 1 0 0 1
1 0 1 1 1 1 1 1 1 0 0
0 0 0 0 0 0 0 0 0 1 0
0 0 0 1 0 0 1 0 1 0 0
0 0 1 0 0 0 0 1 0 0 1
0 0 1 1 0 0 1 1 0 1 0
0 1 0 0 1 0 0 0 1 0 0
0 1 0 1 1 0 1 0 1 0 0
0 1 1 0 1 0 0 1 1 0 0
0 1 1 1 1 0 1 1 1 0 0
1 0 0 0 1 1 0 0 1 0 0
1 0 0 1 1 1 1 1 1 0 0
1 0 1 0 1 1 0 0 1 0 0
 1 0 1 1 1 1 1 1 1 0 0
1 1 0 0 0 1 0 0 0 0 1
1 1 0 1 0 1 1 1 0 0 1
1 1 1 0 0 1 0 0 0 0 1
1 1 1 1 0 1 1 1 0 0 1

For Parallel adder and subtractor

Some examples
Assume two unsigned 4-bit numbers A and B where
A = 1011 B = 0110
To perform (A + B), use 4-bit Ripple carry adder where the carry-in Ci is 0. 
For subtraction (A – B), A is added with 2’s complement of B i.e. A + (-B)
A = 1011 A = 1011
B = 0110 (-B) = 1001 1’s comp of B
+ 0˿ c0 + 1 (1’s comp + 1 = 2’s comp of B)
10001 10101

Another Inputs
A = 1010 B = 1110
A+B A-B
A=1010 A= 1010
B=1110 (-B)= 0001 1’s comp of B
+ 0-Cin + 1 (1’s comp + 1 = 2’s comp of B)
11000 01100

A = 1010 B = 0011
A+B A-B
A=1010 A= 1010
B=0011 (-B)= 1100 1’s comp of B
+ 0-Cin + 1 (1’s comp + 1 = 2’s comp of B)
01101 10111

RESULT:
The implementation of system level design, where we asked to show
(1) Binary code to grey code
(2) Grey code to binary code
(3) Magnitude comparator
(4) Parallel adder/subtractor
has been performed successfully.

CONCLUSION:
The truth tables of all the experiments which were asked have been verified successful and
the outputs of respective experiments have been showcased using LED’s.

ACTUAL COST REQUIRED:

IC 7486 – 3*15 =45
IC 7485 – 18 =18
IC 7483 - 22 =22
Dip 8 way =22
 Dip 6 way =18
Dip 2 way =14
Leds - 12*1.35 =17
1k resistor -12*0.5 =6
Wire 3mtrs =20
IC stands 14 pin -3*6=18
IC stands 16 pin – 2*8 =16
Lead roll = 72
PCB =50
Total cost = 340/-

PROBLEMS FACED DURING THE IMPLEMENTATION:

Short circuit of multiple joints due to lead, which resulted in getting only few outputs and
poor quality of lead made some joints to be incompletely soldered.
Initially some LED’s have been fluctuated while checking output.
The circuit had became complex, while giving multiple Vcc(5V) connections to each and
every IC.

PROBLEMS RESOLVED USING SOLUTIONS:

Short circuit of multiple joints verified using continuity check, quality lead has been used for
further development of PCB board.
Resistors have been used in order to minimize load on LED’s and to give a stable output.
We have used couple of DIP switches in order to control flow of Vcc to different IC’s,which
made the implementation on PCB board easier.

ANY OTHER COMMENT:

A basic idea have been developed among the team members on how to design a PCB model
and also implementation of few concepts on PCB which were taught in class helped us to
recall those concepts.
Hence we used lead and solder to make connections, this gave us a basic idea on how to
implement system design using solder which could help us in further system design projects
and even in lab sessions.
 Encoders and Decoders in Digital Logic
- E Gokul
BL.EN.U4ECE22021
Binary code of N digits can be used to store 2N distinct elements of coded information. This is what
encoders and decoders are used for. Encoders convert 2N lines of input into a code of N bits and Decoders
decode the N bits into 2N lines.

1. Encoders –
An encoder is a combinational circuit that converts binary information in the form of a 2N input lines into N
output lines, which represent N bit code for the input. For simple encoders, it is assumed that only one input
line is active at a time.

As an example, let’s consider Octal to Binary encoder. As shown in the following figure, an octal-to-binary
encoder takes 8 input lines and generates 3 output lines.

Truth Table –
D7 D6 D5 D4 D3 D2 D1 D0 X Y Z
0 0 0 0 0 0 0 1 0 0 0
0 0 0 0 0 0 1 0 0 0 1
0 0 0 0 0 1 0 0 0 1 0
0 0 0 0 1 0 0 0 0 1 1
0 0 0 1 0 0 0 0 1 0 0
0 0 1 0 0 0 0 0 1 0 1
0 1 0 0 0 0 0 0 1 1 0
1 0 0 0 0 0 0 0 1 1 1

As seen from the truth table, the output is 000 when D0 is active; 001 when D1 is active; 010 when D2 is
active and so on.

Implementation –
From the truth table, the output line Z is active when the input octal digit is 1, 3, 5 or 7. Similarly, Y is 1
when input octal digit is 2, 3, 6 or 7 and X is 1 for input octal digits 4, 5, 6 or 7. Hence, the Boolean
functions would be:

X = D4 + D5 + D6 + D7
Y = D2 +D3 + D6 + D7
Z = D1 + D3 + D5 + D7
Hence, the encoder can be realised with OR gates as follows:
One limitation of this encoder is that only one input can be active at any given time. If more than one inputs
are active, then the output is undefined. For example, if D6 and D3 are both active, then, our output would
be 111 which is the output for D7. To overcome this, we use Priority Encoders.

Another ambiguity arises when all inputs are 0. In this case, encoder outputs 000 which actually is the output
for D0 active. In order to avoid this, an extra bit can be added to the output, called the valid bit which is 0
when all inputs are 0 and 1 otherwise.

Priority Encoder –
A priority encoder is an encoder circuit in which inputs are given priorities. When more than one inputs are
active at the same time, the input with higher priority takes precedence and the output corresponding to that
is generated.

Let us consider the 4 to 2 priority encoder as an example.

From the truth table, we see that when all inputs are 0, our V bit or the valid bit is zero and outputs are not
used. The x’s in the table show the don’t care condition, i.e, it may either be 0 or 1. Here, D3 has highest
priority, therefore, whatever be the other inputs, when D3 is high, output has to be 11. And D0 has the
lowest priority, therefore the output would be 00 only when D0 is high and the other input lines are low.
Similarly, D2 has higher priority over D1 and D0 but lower than D3 therefore the output would be 010 only
when D2 is high and D3 are low (D0 & D1 are don’t care).

Truth Table-
D3 D2 D1 D0 X Y V
0 0 0 0 x x 0
0 0 0 1 0 0 1
0 0 1 x 0 1 1
0 1 x x 1 0 1
1 x x x 1 1 1

Implementation –
It can clearly be seen that the condition for valid bit to be 1 is that at least any one of the inputs should be
high. Hence,
V = D0 + D1 + D2 + D3
For X: For Y:

=> X = D2 + D3 => Y = D1 D2’ + D3

Hence, the priority 4-to-2 encoder can be realized as follows:

Decoders –
A decoder does the opposite job of an encoder. It is a combinational circuit that converts n lines of input into
2n lines of output.

Let’s take an example of 3-to-8 line decoder.

Truth Table –
X Y Z D0 D1 D2 D3 D4 D5 D6 D7

0 0 0 1 0 0 0 0 0 0 0

0 0 1 0 1 0 0 0 0 0 0

0 1 0 0 0 1 0 0 0 0 0

0 1 1 0 0 0 1 0 0 0 0

1 0 0 0 0 0 0 1 0 0 0

1 0 1 0 0 0 0 0 1 0 0
1 1 0 0 0 0 0 0 0 1 0

1 1 1 0 0 0 0 0 0 0 1
Implementation –
D0 is high when X = 0, Y = 0 and Z = 0. Hence,
D0 = X’ Y’ Z’
Similarly,
D1 = X’ Y’ Z
D2 = X’ Y Z’
D3 = X’ Y Z
D4 = X Y’ Z’
D5 = X Y’ Z
D6 = X Y Z’
D7 = X Y Z
Hence,
 EXCESS-3 Code:
-By Emani Sandeep Reddy
B.EN.U4ECE22022

Excess-3, also called XS3, is a non weighted code used to express decimal numbers. It can be used for the
representation of multi-digit decimal numbers as can BCD.The code for each decimal number is obtained by
adding decimal 3 and then converting it to a 4-bit binary number. For e.g. decimal 2 is coded as 0010 + 0011
= 0101 in Excess-3 code.

This is self complementing code which means 1‘s complement of the coded number yields 9‘s complement
of the number itself. Self complementing property of this helps considerably in performing subtraction
operation in digital systems, so this code is used for certain arithmetic operations.

BCD To Excess – 3 Code Conversions:

Convert BCD 2 i. e. 0010 to Excess – 3 codes

For converting 4 bit BCD code to Excess – 3, add 0011 i. e. decimal 3 to the respective code using rules of
binary addition.

0010 + 0011 = 0101 – Excess – 3 code for BCD 2

Excess – 3 Code To BCD Conversion:

The 4 bit Excess-3 coded digit can be converted into BCD code by subtracting decimal value 3 i.e. 0011
from 4 bit Excess-3 digit.

e.g. Convert 4-bit Excess-3 value 0101 to equivalent BCD code.

0101-0011= 0010- BCD for 2

Truth Table:

BCD to Excess-3 Code Conversion

BCD Code EXCESS Code
A B C D w x y z
0 0 0 0 0 0 1 1
0 0 0 1 0 1 0 0
0 0 1 0 0 1 0 1
0 0 1 1 0 1 1 0
0 1 0 0 0 1 1 1
0 1 0 1 1 0 0 0
0 1 1 0 1 0 0 1
0 1 1 1 1 0 1 0
1 0 0 0 1 0 1 1
1 0 0 1 1 1 0 0
1 0 1 0 x x x x
1 0 1 1 x x x x
1 1 0 0 x x x x
1 1 0 1 x x x x
1 1 1 0 x x x x
1 1 1 1 x x x x
 Excess-3 To BCD Conversion
EXCESS Code BCD Code
w x y z A B C D
0 0 0 0 x x x x
0 0 0 1 x x x x
0 0 1 0 x x x x
0 0 1 1 0 0 0 0
0 1 0 0 0 0 0 1
0 1 0 1 0 0 1 0
0 1 1 0 0 0 1 1
0 1 1 1 0 1 0 0
1 0 0 0 0 1 0 1
1 0 0 1 0 1 1 0
1 0 1 0 0 1 1 1
1 0 1 1 1 0 0 0
1 1 0 0 1 0 0 1
1 1 0 1 x x x x
1 1 1 0 x x x x
1 1 1 1 x x x x

K-Map
For BCD to Excess 3
K-Map for z K-Map for y

K-Map for x K-Map for w

z = D’
y =CD+C’D’
x= B’C+B’D+BC’D’
w = A+BC+BD
For Excess 3 to BCD
K-Map for D- K-Map for C-

K-Map for B- K-Map for A-

A= wx+wyz
B= x’y’+x’z’+xyz
C= y’z+yz’
D= z’

Circuit Diagram:

BCD TO EXCESS-3 CONVERTER

EXCESS-3 TO BCD CONVERTER
 Construct 4:1 Multiplexer and 1:4 De-Multiplexer Using Logic Gates
- By Gilaka Sathwick
BL.EN.U4ECE22023
A multiplexer is a Combinational circuit (it is a type of circuit whose output rely on the given inputs using
various logic gates ) that takes multiple inputs and delivers only a single output. It consists input data lines,
selection lines and a single output.

Multiplexer
To construct a 4 to 1 multiplexer, we need to know how many selection lines we required to create a MUX?
We require n selection lines, where 2n represents total input lines and n represents selection lines. (In this
case, 22 that gives 4 input lines and 2 selection lines).

A multiplexer is often abbreviated as MUX or many to one circuit or parallel to serial circuit.

It is a data selector that provides the mechanism to select single binary information from many input lines
and passes it to output line

Types of Multiplexers
There are various types of multiplexers and few are given below:

2:1 MUX
4:1 MUX
8:1 MUX
16:1 MUX
32:1 MUX
Now we’ll be discussing 4:1 MUX.

Here are the steps to design or construct 4 to 1 Multiplexer or 4:1 MUX using Logic Gates :
1) Now, make a diagram of multiplexer with 4 input lines, 2 selection lines and 1 output. In below diagram,
A0 , A1 , A2 and A3 are input data lines, S0 and S1 are Selection lines and lastly one output line named Y

2) This is how a truth table for 4 to 1 MUX looks like . According to the truth table, the output of the
multiplexer fully depends on selection lines (binary data , 00,01,10 & 11) and one input would be selected
from all the input data lines as the output.
Truth table

Selection Lines Output

A B Output
0 0 D0
0 1 D1
1 0 D2
1 1 D3

Above table is created as per follow :

When S0 =0 and S1=0 , then A0 would be the output.

Similarly When S0 =0 and S1=1, then A1 would be the output.

We can represent this by an expression.

Output = S0‘.S1‘A0 + S0‘.S1A1+ S0.S1‘A2 + S0.S1 A3

3) In last step, design 4 to 1 multiplexer by using 4 AND gates and a single OR gate.

Explanation:
In above diagram, there were two selection lines along with their respective complements using Inverters.
Each and every AND gate were holding three inputs from S1, S0 and a particular input A. lastly, outputs of
all AND gates became the input for OR gate and providing a single output.

1x4 De-Multiplexer:-
1x4 De-Multiplexer has one input I, two selection lines, s1 & s0 and four outputs Y3, Y2, Y1 &Y0. The block
diagram of 1x4 De-Multiplexer is shown in the following figure.
The single input ‘I’ will be connected to one of the four outputs, Y3 to Y0 based on the values of selection
lines s1 & s0. The Truth table of 1x4 De-Multiplexer is shown below.

We can implement these Boolean functions using Inverters & 3-input AND gates. The circuit diagram of
1x4 De-Multiplexer is shown in the following figure.
 To Convert BCD into Seven Segment Display
- By M Bhanu Charan
BL.EN.U4ECE22033

In Binary Coded Decimal (BCD) encoding scheme each of the decimal numbers(0-9) is represented by its
equivalent binary pattern(which is generally of 4-bits).

Whereas, Seven segment display is an electronic device which consists of seven Light Emitting Diodes
(LEDs) arranged in a some definite pattern (common cathode or common anode type), which is used to
display Hexadecimal numerals(in this case decimal numbers,as input is BCD i.e., 0-9).

Two types of seven segment LED display:

Common Cathode Type: In this type of display all cathodes of the seven LEDs are connected together to the
ground or -Vcc(hence,common cathode) and LED displays digits when some ‘HIGH’ signal is supplied to
the individual anodes.
Common Anode Type: In this type of display all the anodes of the seven LEDs are connected to battery or
+Vcc and LED displays digits when some ‘LOW’ signal is supplied to the individual cathodes.

But, seven segment display does not work by directly supplying voltage to different segments of LEDs.
First, our decimal number is changed to its BCD equivalent signal then BCD to seven segment decoder
converts that signals to the form which is fed to seven segment display.

This BCD to seven segment decoder has four input lines (A, B, C and D) and 7 output lines (a, b, c, d, e, f
and g), this output is given to seven segment LED display which displays the decimal number depending
upon inputs.

Truth Table – For common cathode type BCD to seven segment decoder:

Note –
For Common Anode type seven segment LED display, we only have to interchange all ‘0s’ and ‘1s’ in the
output side i.e., (for a, b, c, d, e, f, and g replace all ‘1’ by ‘0’ and vice versa) and solve using K-map.
Output for first combination of inputs (A, B, C and D) in Truth Table corresponds to ‘0’ and last
combination corresponds to ‘9’. Similarly rest corresponds from 2 to 8 from top to bottom.
BCD numbers only range from 0 to 9,thus rest inputs from 10-F are invalid inputs.

Explanation –
For combination where all the inputs (A, B, C and D) are zero (see Truth Table), our output lines are a = 1, b
= 1, c = 1, d = 1, e = 1, f = 1 and g = 0. So 7 segment display shows ‘zero’ as output.
Similarly, for combination where one of the input is one (D = 1) and rest are zero,our output lines are a = 0,
b = 1, c = 1, d = 0, e = 0, f = 0 and g = 0. So only LEDs ‘b’ and ‘c’ (see diagram above) will glow and 7
segment display shows ‘one’ as output.

K-Maps:
#for a: #for b:

#for c: #for d:

#for e: #for g:
Applications – Seven-segment displays are used to display the digits in calculators, clocks, various
measuring instruments, digital watches and digital counters.