Microprocessor Note

Microprocessor
Note
(Diploma in Computer Engineering)
2nd year / 1st part
iii
Semester
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Contents
Unit-1 ............................................................................................................................................... 5
History of Microprocessors ........................................................................................................... 5
Analog Computer Vs Digital Computer ......................................................................................... 6
Microprocessor ............................................................................................................................. 7
Microcontroller .............................................................................................................................. 7
Microcomputer .............................................................................................................................. 7
Stored program concept ............................................................................................................... 7
Von-Neumann‟s architecture .....................................................................................................................8
Buses............................................................................................................................................ 9
Three types of buses ................................................................................................................. 9
Programming Language ............................................................................................................. 10
Types Of Programming Languages ......................................................................................... 10
Instruction set ............................................................................................................................. 11
Examples of instruction set...................................................................................................... 11
SAP 1 Vs SAP 2 ......................................................................................................................... 12
Unit-2 ............................................................................................................................................. 12
Pin Diagram Of 8085 Microprocessor ......................................................................................... 13
Address Bus and Data Bus ..................................................................................................... 13
Control and Status Signals ...................................................................................................... 13
Power Supply and Clock Frequency........................................................................................ 14
Interrupts and Peripheral Initiated Signals ............................................................................... 15
Reset Signals .......................................................................................................................... 15
DMA Signals ............................................................................................................................ 15
Serial I/O Ports ........................................................................................................................ 15
Internal Architecture Of 8085 Microprocessor ............................................................................ 16
Functional Units of 8085 Microprocessor ................................................................................ 16
Instruction and Data Format ....................................................................................................... 18
One–byte instructions .............................................................................................................. 19
Two–byte instructions .............................................................................................................. 19
Three–byte instructions ........................................................................................................... 19
Instruction Set Classification ....................................................................................................... 19
Data Transfer Group................................................................................................................ 20
Arithmetic Group ..................................................................................................................... 21
Logical Group .......................................................................................................................... 21
Branch Group .......................................................................................................................... 22
Stack Instructions .................................................................................................................... 23
I/0 instructions ......................................................................................................................... 23
Machine Control instructions ................................................................................................... 23
Addressing modes in 8085 ......................................................................................................... 23
1. Immediate Addressing Mode ............................................................................................ 24
2. Register Addressing Mode................................................................................................ 24
3. Direct Addressing Mode.................................................................................................... 24
4. Register Indirect Addressing Mode ................................................................................... 24
5. Implied/Implicit Addressing Mode ..................................................................................... 25
Instruction Set of 8085 ................................................................................................................ 25
Unit-3 ............................................................................................................................................. 26
Assembly Language ................................................................................................................... 26
Assembler ................................................................................................................................... 26
Simple assembly language programs ......................................................................................... 26
Subroutine .................................................................................................................................. 27
Stack........................................................................................................................................... 28
Unit-4 ............................................................................................................................................. 28
Instruction Cycle ......................................................................................................................... 28
Fetch cycle .............................................................................................................................. 28
Decode instruction ................................................................................................................... 28
Reading effective address ....................................................................................................... 28
Execution cycle ....................................................................................................................... 28
Address Decoding ...................................................................................................................... 31
Memory Interfacing ..................................................................................................................... 31
IO Interfacing .............................................................................................................................. 31
Direct Memory Access ................................................................................................................ 32
DMA 8257 Architecture ........................................................................................................... 33
8257 Pin Description ............................................................................................................... 34
Unit-5 ............................................................................................................................................. 36
Interrupts .................................................................................................................................... 36
Interrupt Service Routine (ISR) ................................................................................................... 37
Interrupt in 8085.......................................................................................................................... 37
TRAP ....................................................................................................................................... 37
RST7.5 .................................................................................................................................... 37
RST 6.5 ................................................................................................................................... 37
RST 5.5 ................................................................................................................................... 37
INTR ........................................................................................................................................ 38
Priority of Interrupts .................................................................................................................... 38
Instruction for Interrupts .............................................................................................................. 38
Enable Interrupt (EI) ................................................................................................................ 38
Disable Interrupt (DI) ............................................................................................................... 38
Set Interrupt Mask (SIM) ......................................................................................................... 39
Read Interrupt Mask (RIM) ...................................................................................................... 39
8085 Vectored Interrupts ............................................................................................................ 39
8085 Non-Vectored Interrupts .................................................................................................... 39
Restart instructions (RSTn) in 8085 Microprocessor .................................................................. 39
Unit – 6 .......................................................................................................................................... 40
Programmable peripheral interface 8255 .................................................................................... 40
Programmable peripheral interface 8255 Architecture ............................................................ 40
Programmable peripheral interface 8255 Pin Diagram ............................................................ 41
Operating modes ..................................................................................................................... 41
8253 (8254) Programmable Interval Timer ................................................................................. 42
8254 Programmable Interval Timer Architecture ..................................................................... 43
8253 (8254) Programmable Interval Timer Pin Diagram ......................................................... 43
8259 Programmable Interrupt Controller .................................................................................... 44
Features of 8259 PIC microprocessor ..................................................................................... 45
8259 Programmable Interrupt Controller Pin Diagram............................................................. 45
8259 Programmable Interrupt Controller Architecture ............................................................. 46
8251 USART .............................................................................................................................. 47
Block Diagram of 8251 USART ............................................................................................... 48
Unit-1
History of Microprocessors
Analog Computer Vs Digital Computer
Microprocessor
A microprocessor is a multi-purpose. Programmable, clock driven, register-based electronic device
that reads binary instructions from a storage device called memory, accepts binary data as input
and processes data according to those instructions and provide results as output.
It is an electronic device that fetches instructions from memory, execute them and provide results.
A microprocessor is an electronic device that has computing and decision-making capability.
Microcontroller
A microcontroller is a programmable device that includes microprocessor, memory and I/O signal
lines on a single chip, fabricated using VLSI technology. Microcontrollers are also known as signle
microcomputers.
A Microcontroller is a small and low-cost microcomputer, which is designed to perform the specific
tasks of embedded systems like displaying microwave information, receiving remote signals etc.
Microcomputer
A microcomputer can be defined as a small sized, inexpensive, and limited capability computer. It
has the same architectural block structure that is present on a computer.
Microcomputer is a small, relatively inexpensive computer with a microprocessor as its central

processing unit (CPU). It includes a single printed circuit board containing a microprocessor,
memory, and minimal input/output(I/O) circuitry mounted.
Stored program concept

Stored-program concept, Storage of instructions in computer memory to enable it to perform a
variety of tasks in sequence or intermittently. The idea was introduced in the late 1940s by John
von Neumann, who proposed that a program be electronically stored in binary-number format in a
memory device so that instructions could be modified by the computer as determined by
intermediate computational results
Von-Neumann’s architecture
Von Neumann architecture was first published by John von Neumann in 1945. His computer
architecture design consists of a Control Unit, Arithmetic and Logic Unit (ALU), Memory Unit,
Registers and Inputs/Outputs.
Von Neumann architecture is based on the stored-program computer concept, where instruction
data and program data are stored in the same memory.
Buses
Bus is a group of conducting wires which carries information, all the peripherals are connected to
microprocessor through Bus.
Three types of buses
Address Bus
It is a group of conducting wires which carries address only. Address bus is unidirectional
because data flow in one direction, from microprocessor to memory or from microprocessor to
Input/output devices.
Length of Address Bus of 8085 microprocessor is 16 Bit, ranging from 0000 H to FFFF H. The
microprocessor 8085 can transfer maximum 16 bit address which means it can address 65, 536
different memory location.
Data Bus
It is a group of conducting wires which carries Data only. Data bus is bidirectional because
data flow in both directions, from microprocessor to memory or Input/Output devices and from
memory or Input/Output devices to microprocessor.
Length of Data Bus of 8085 microprocessor is 8 Bit, ranging from 00 H to FF H.
Control Bus
It is a group of conducting wires, which is used to generate timing and control signals to control all
the associated peripherals, microprocessor uses control bus to process data, that is what to do
with selected memory location. Some control signals are:
 Memory read
 Memory write
 I/O read
 I/O Write
 Opcode fetch
Programming Language
A programming language is a computer language that is used by programmers (developers) to
communicate with computers. It is a set of instructions written in any specific language ( C, C++,
Java, Python) to perform a specific task.
A programming language is mainly used to develop desktop applications, websites, and mobile
applications.
Types Of Programming Languages
Low-level programming language

Low-level language is machine-dependent (0s and 1s) programming language. The processor
runs low- level programs directly without the need of a compiler or interpreter, so the programs
written in low-level language can be run very fast.
High-level programming language

High-level programming language (HLL) is designed for developing user-friendly software
programs and websites. This programming language requires a compiler or interpreter to translate
the program into machine language (execute the program).
The main advantage of a high-level language is that it is easy to read, write, and maintain.
Instruction set
The instruction set is part of a computer that pertains to programming, which is more or less
machine language. The instruction set provides commands to the processor, to tell it what it needs
to do. The instruction set consists of addressing modes, instructions, native data types, registers,
memory architecture, interrupt, and exception handling, and external I/O
Examples of instruction set

 ADD - Add two numbers together.
 COMPARE - Compare numbers.
 IN - Input information from a device, e.g., keyboard.
 JUMP - Jump to designated RAM address.
 JUMP IF - Conditional statement that jumps to a designated RAM address.
 LOAD - Load information from RAM to the CPU.
 OUT - Output information to device, e.g., monitor.
 STORE - Store information to RAM
SAP 1 Vs SAP 2
Unit-2
Pin Diagram Of 8085 Microprocessor
Address Bus and Data Bus
The address bus is a group of sixteen lines i.e A0-A15. The address bus is unidirectional, i.e., bits
flow in one direction from the microprocessor unit to the peripheral devices and uses the high
order address bus.
Control and Status Signals

ALE – It is an Address Latch Enable signal. It goes high during first T state of a machine cycle and
enables the lower 8-bits of the address, if its value is 1 otherwise data bus is activated.
IO/M‟ – It is a status signal which determines whether the address is for input-output or memory.
When it is high(1) the address on the address bus is for input-output devices. When it is low(0) the
address on the address bus is for the memory.
SO, S1 – These are status signals. They distinguish the various types of operations such as halt,
reading, instruction fetching or writing.
RD‟ – It is a signal to control READ operation. When it is low the selected memory or input-output
device is read.
WR‟ – It is a signal to control WRITE operation. When it goes low the data on the data bus is
written into the selected memory or I/O location.
READY – It senses whether a peripheral is ready to transfer data or not. If READY is high(1) the
peripheral is ready. If it is low(0) the microprocessor waits till it goes high. It is useful for interfacing
low speed devices.
Power Supply and Clock Frequency

Vcc – +5v power supply
Vss – Ground Reference
XI, X2 – A crystal is connected at these two pins. The frequency is internally divided by two,
therefore, to operate a system at 3MHZ the crystal should have frequency of 6MHZ.
CLK (OUT) – This signal can be used as the system clock for other devices.
Interrupts and Peripheral Initiated Signals
The 8085 has five interrupt signals that can be used to interrupt a program execution.
(i) INTR
(ii) RST 7.5
(iii) RST 6.5
(iv) RST 5.5
(v) TRAP
The microprocessor acknowledges Interrupt Request by INTA‟ signal. In addition to Interrupts,

there are three externally initiated signals namely RESET, HOLD and READY. To respond to
HOLD request, it has one signal called HLDA.
INTR – It is an interrupt request signal.
INTA‟ – It is an interrupt acknowledgment sent by the microprocessor after INTR is received.
Reset Signals
RESET IN‟ – When the signal on this pin is low(0), the program-counter is set to zero, the buses
are tristated and the microprocessor unit is reset.
RESET OUT – This signal indicates that the MPU is being reset. The signal can be used to reset
other devices.
DMA Signals
HOLD – It indicates that another device is requesting the use of the address and data bus. Having
received HOLD request the microprocessor relinquishes the use of the buses as soon as the
current machine cycle is completed. Internal processing may continue. After the removal of the
HOLD signal the processor regains the bus.
HLDA – It is a signal which indicates that the hold request has been received after the removal of
a HOLD request, the HLDA goes low.
Serial I/O Ports

Serial transmission in 8085 is implemented by the two signals,
SID and SOD – SID is a data line for serial input where as SOD is a data line for serial output.
Internal Architecture Of 8085 Microprocessor
Functional Units of 8085 Microprocessor

Accumulator
It is an 8-bit register used to perform arithmetic, logical, I/O & LOAD/STORE operations. It is
connected to internal data bus & ALU.
Arithmetic and logic unit

As the name suggests, it performs arithmetic and logical operations like Addition, Subtraction,
AND, OR, etc. on 8-bit data.
General purpose register

There are 6 general purpose registers in 8085 processor, i.e. B, C, D, E, H & L. Each register can
hold 8-bit data.
These registers can work in pair to hold 16-bit data and their pairing combination is like B-C, D-E &
H-L.
Program counter
It is a 16-bit register used to store the memory address location of the next instruction to be
executed. Microprocessor increments the program whenever an instruction is being executed, so
that the program counter points to the memory address of the next instruction that is going to be
executed.
Stack pointer
It is also a 16-bit register works like stack, which is always incremented/decremented by 2 during
push & pop operations.
Temporary register
It is an 8-bit register, which holds the temporary data of arithmetic and logical operations.
Flag register
It is an 8-bit register having five 1-bit flip-flops, which holds either 0 or 1 depending upon the result
stored in the accumulator.
These are the set of 5 flags −
Sign (S)
Zero (Z)
Auxiliary Carry (AC)
Parity (P)
Carry (C)
Its bit position is shown in the following table –
Instruction register and decoder

It is an 8-bit register. When an instruction is fetched from memory then it is stored in the Instruction
register. Instruction decoder decodes the information present in the Instruction register.
Timing and control unit
It provides timing and control signal to the microprocessor to perform operations. Following are the
timing and control signals, which control external and internal circuits −
Control Signals: READY, RD‟, WR‟, ALE
Status Signals: S0, S1, IO/M‟
DMA Signals: HOLD, HLDA
RESET Signals: RESET IN, RESET OUT
Interrupt control
As the name suggests it controls the interrupts during a process. When a microprocessor is
executing a main program and whenever an interrupt occurs, the microprocessor shifts the control
from the main program to process the incoming request. After the request is completed, the
control goes back to the main program.
There are 5 interrupt signals in 8085 microprocessor: INTR, RST 7.5, RST 6.5, RST 5.5, TRAP.
Serial Input/output control

It controls the serial data communication by using these two instructions: SID (Serial input data)
and SOD (Serial output data).
Address buffer and address-data buffer

The content stored in the stack pointer and program counter is loaded into the address buffer and
address-data buffer to communicate with the CPU. The memory and I/O chips are connected to
these buses; the CPU can exchange the desired data with the memory and I/O chips.
Address bus and data bus

Data bus carries the data to be stored. It is bidirectional, whereas address bus carries the location
to where it should be stored and it is unidirectional. It is used to transfer the data & Address I/O
devices.
Instruction and Data Format

An instruction (instruction format) is a command to the microprocessor to perform a given task on
a particular data. Each instruction (instruction format) is of two parts. One is to be performed,
called the operation code or opcode and the second one is the data to be operated on, called the
operand. Operands or data can be specified in different ways. It may include an 8-bit or 16-bit
data, an internal register. a memory location, or it or 16-bit address. In some instructions, the
operand is implicit.
According to the word or byte size the 8085 instructions are classified into three types. They are
(a) One byte (single) instructions
(b)Two byte instructions
(c) Three byte instructions
One–byte instructions
An instruction with only opcode and do not require any dat or address is called a one byte
instruction.
Ex: 1. MOV C, A Hex code = 4FH (one byte)
2. ADD B Hex code = 80H (one byte)
3. CMA Hex code = 2FH (one byte)
Two–byte instructions
A two byte instruction is one which c ontains an 8-bit op-code and 8-bit operand (Data).
Ex: 1. MVI A, 09 Hex code = 3E, 09 (two bytes)
2. ADD B, 07 Hex code = 80, 07 (two bytes)
3. SUB A, 05 Hex code = 97, 05 (two bytes)
Three–byte instructions
A three byte instruction contains an opcode plus a 16 – bit address.
Ex: 1.LXI H, 8509 Hex code = 21, 09, 85 (Three bytes)
2 .LDA 8509 Hex code = 3A, 09, 85 (Three bytes)
3. JMP 9567 Hex code = C3, 67, 95 (Three bytes)
4. STA 3525 Hex code = 32, 35, 25 (Three bytes)
Instruction Set Classification

An instruction is a binary pattern designed inside a microprocessor to perform a specific function.
The entire group of instructions, called the instruction set, determines what functions the
microprocessor can perform. These instructions can be classified into the following five functional
categories: data transfer (copy) operations, arithmetic operations, logical operations, branching
operations, and machine-control operations.
Data Transfer Group

The data transfer instructions move data between registers or between memory and registers.
MOV Move
MVI Move Immediate
LDA Load Accumulator Directly from Memory
STA Store Accumulator Directly in Memory
LHLD Load H & L Registers Directly from Memory
SHLD Store H & L Registers Directly in Memory
An 'X' in the name of a data transfer instruction implies that it deals with a register pair (16-bits);
LXI Load Register Pair with Immediate data

LDAX Load Accumulator from Address in Register Pair
STAX Store Accumulator in Address in Register Pair
XCHG Exchange H & L with D & E
XTHL Exchange Top of Stack with H & L
Arithmetic Group
The arithmetic instructions add, subtract, increment, or decrement data in registers or memory.
ADD Add to Accumulator

ADI Add Immediate Data to Accumulator
ADC Add to Accumulator Using Carry Flag
ACI Add immediate data to Accumulator Using Carry
SUB Subtract from Accumulator
SUI Subtract Immediate Data from Accumulator
SBB Subtract from Accumulator Using Borrow (Carry) Flag
SBI Subtract Immediate from Accumulator Using Borrow (Carry) Flag
INR Increment Specified Byte by One
DCR Decrement Specified Byte by One
INX Increment Register Pair by One
DCX Decrement Register Pair by One
DAD Double Register Add; Add Content of Register
Pair to H & L Register Pair
Logical Group
This group performs logical (Boolean) operations on data in registers and memory and on
condition flags. The logical AND, OR, and Exclusive OR instructions enable you to set specific bits
in the accumulator ON or OFF.
ANA Logical AND with Accumulator

ANI Logical AND with Accumulator Using Immediate Data
ORA Logical OR with Accumulator
OR Logical OR with Accumulator Using Immediate Data
XRA Exclusive Logical OR with Accumulator
XRI Exclusive OR Using Immediate Data
The Compare instructions compare the content of an 8-bit value with the contents of the
accumulator;
CMP Compare
CPI Compare Using Immediate Data
The rotate instructions shift the contents of the accumulator one bit position to the left or right:
RLC Rotate Accumulator Left

RRC Rotate Accumulator Right
RAL Rotate Left Through Carry
RAR Rotate Right Through Carry
Complement and carry flag instructions:
CMA Complement Accumulator

CMC Complement Carry Flag
STC Set Carry Flag
Branch Group
The branching instructions alter normal sequential program flow, either unconditionally orconditionally.
The unconditional branching instructions are as follows:
JMP Jump
CALL Call
RET Return
Conditional branching instructions examine the status of one of four condition flags to determine
whether the specified branch is to be executed. The conditions that may be specified are as
follows:
NZ Not Zero (Z = 0)
Z Zero (Z = 1)
NC No Carry (C = 0)
C Carry (C = 1)
PO Parity Odd (P = 0)
PE Parity Even (P = 1)
P Plus (S = 0)
M Minus (S = 1)
Thus, the conditional branching instructions are specified as follows:
Jumps Calls Returns

INC CNC RNC (No Carry)
JNZ CNZ RNZ (Not Zero)
JM CM RM (Minus)
JP0 CPO RPO (Parity Odd)
JM CM RM (Minus)
JPE CPE RPE (Parity Even)
JP0 CPO RPO (Parity Odd)
Two other instructions can affect a branch by replacing the contents or the program counter:
PCHL Move H & L to Program Counter

RST Special Restart Instruction Used with Interrupts
Stack Instructions
The following instructions affect the Stack and/or Stack Pointer
PUSH Push Two bytes of Data onto the Stack

POP Pop Two Bytes of Data off the Stack
XTHL Exchange Top of Stack with H & L
SPHL Move content of H & L to Stack Pointer
I/0 instructions
IN Initiate Input Operation
OUT Initiate Output Operation
Machine Control instructions

EI Enable Interrupt System
DI Disable Interrupt System
HLT Halt
NOP No Operation
Addressing modes in 8085
1. Immediate Addressing Mode

In immediate addressing mode the source operand is always data. If the data is 8-bit, then the
instruction will be of 2 bytes, if the data is of 16-bit then the instruction will be of 3 bytes.
Examples:
MVI B 45 (move the data 45H immediately to register B)
LXI H 3050 (load the H-L pair with the operand 3050H immediately)
JMP address (jump to the operand address immediately)
2. Register Addressing Mode
In register addressing mode, the data to be operated is available inside the register(s) and
register(s) is(are) operands. Therefore the operation is performed within various registers of the
microprocessor.
Examples:
MOV A, B (move the contents of register B to register A)
ADD B (add contents of registers A and B and store the result in register A)
INR A (increment the contents of register A by one)
3. Direct Addressing Mode

In direct addressing mode, the data to be operated is available inside a memory location and that
memory location is directly specified as an operand. The operand is directly available in the
instruction itself.
Examples:
LDA 2050 (load the contents of memory location into accumulator A)
LHLD address (load contents of 16-bit memory location into H-L register pair)
IN 35 (read the data from port whose address is 35)
4. Register Indirect Addressing Mode

In register indirect addressing mode, the data to be operated is available inside a memory location
and that memory location is indirectly specified by a register pair.
Examples:
MOV A, M (move the contents of the memory location pointed by the H-L pair to the accumulator)
LDAX B (move contents of B-C register to the accumulator)
LXIH 9570 (load immediate the H-L pair with the address of the location 9570)
5. Implied/Implicit Addressing Mode –
In implied/implicit addressing mode the operand is hidden and the data to be operated is available
in the instruction itself.
Examples:
CMA (finds and stores the 1‟s complement of the contains of accumulator A in A)
RRC (rotate accumulator A right by one bit)
RLC (rotate accumulator A left by one bit)
Instruction Set of 8085

- An instruction is a binary pattern designed inside a microprocessor to perform a specific
function.
- The entire group of instructions that a microprocessor supports is called Instruction Set.
- 8085 has 246 instructions.
- Each instruction is represented by an 8-bit binary value.
- These 8-bits of binary value is called Op-Code or Instruction Byte.
Unit-3
Assembly Language
An assembly language is a type of low-level programming language that is intended to
communicate directly with a computer's hardware. Unlike machine language, which consists of
binary and hexadecimal characters, assembly languages are designed to be readable by humans.
Assembler
An assembler is a program that converts assembly language into machine code. It takes the basic
commands and operations from assembly code and converts them into binary code that can be
recognized by a specific type of processor. Assemblers are similar to compilers in that they
produce executable code.
Simple assembly language programs
Subroutine
Subroutine is a sequence of program instructions that perform a specific task, packaged as a unit.
This unit can then be used in programs wherever that particular task have to be performed. A
subroutine is often coded so that it can be called several times and from several places during one
execution of the program, including from other subroutines, and then branch back (return) to the
next instruction after the call, once the subroutine‟s task is done. It is implemented by using Call
and Return instructions.
Advantages of Subroutine –
 Decomposing a complex programming task into simpler steps.
 Reducing duplicate code within a program.
 Enabling reuse of code across multiple programs.
 Improving tractability or makes debugging of a program easy.
Stack
The stack is a reserved area of the memory in RAM where we can store temporary information.
Interestingly, the stack is a shared resource as it can be shared by the microprocessor and the
programmer. The programmer can use the stack to store data. And the microprocessor uses the
stack to execute subroutines. The 8085 has a 16-bit register known as the „Stack Pointer.‟
Unit-4
Instruction Cycle
Time required to execute and fetch an entire instruction is called instruction cycle. It consists:
Fetch cycle
The next instruction is fetched by the address stored in program counter (PC) and then stored in
the instruction register.
Decode instruction
Decoder interprets the encoded instruction from instruction register.
Reading effective address

The address given in instruction is read from main memory and required data is fetched. The
effective address depends on direct addressing mode or indirect addressing mode.
Execution cycle
It consists memory read (MR), memory write (MW), input output read (IOR) and input output write
(IOW)
The time required by the microprocessor to complete an operation of accessing memory or

input/output devices is called machine cycle. One time period of frequency of microprocessor is
called t-state. A t-state is measured from the falling edge of one clock pulse to the falling edge of
the next clock pulse.
Fetch cycle takes four t-states and execution cycle takes three t-states.
Example: Timing diagram for fetch cycle or opcode fetch
Above diagram represents:
05 – lower bit of address where opcode is stored. Multiplexed address and data bus AD0-AD7 are
used.
20 – higher bit of address where opcode is stored. Multiplexed address and data bus AD8-AD15
are used.
ALE – Provides signal for multiplexed address and data bus. If signal is high or 1, multiplexed
address and data bus will be used as address bus. To fetch lower bit of address, signal is 1 so that
multiplexed bus can act as address bus. If signal is low or 0, multiplexed bus will be used as data
bus. When lower bit of address is fetched then it will act as data bus as the signal is low.
RD (low active) – If signal is high or 1, no data is read by microprocessor. If signal is low or 0,

data is read by microprocessor.
WR (low active) – If signal is high or 1, no data is written by microprocessor. If signal is low or 0,

data is written by microprocessor.
IO/M (low active) and S1, S0 – If signal is high or 1, operation is performing on input output. If
signal is low or 0, operation is performing on memory.
Address Decoding
Address decoding refers to the way a computer system decodes the addresses on the address
bus to select memory locations in one or more memory or peripheral devices. The 68000's 23-bit
address bus permits 223 16-bit words to be uniquely addressed.
In full address decoding, each addressable memory location corresponds to a unique address
value on the address bus. Figure shows an example of two memory devices configured using full
address decoding. Memory M1 is selected whenever A12- A23=000000000000, while M2 is
selected whenever A12- A23=100000000000.
Memory Interfacing
When we are executing any instruction, we need the microprocessor to access the memory for
reading instruction codes and the data stored in the memory. For this, both the memory and the
microprocessor requires some signals to read from and write to registers.
The interfacing process includes some key factors to match with the memory requirements and
microprocessor signals. The interfacing circuit therefore should be designed in such a way that it
matches the memory signal requirements with the signals of the microprocessor.
IO Interfacing
There are various communication devices like the keyboard, mouse, printer, etc. So, we need to
interface the keyboard and other devices with the microprocessor by using latches and buffers.
This type of interfacing is known as I/O interfacing.
Block Diagram of Memory and I/O Interfacing
8085 Interfacing Pins
Following is the list of 8085 pins used for interfacing with other devices −
 A15 - A8 (Higher Address Bus)

 AD7 - AD0(Lower Address/Data Bus)
 ALE
 RD
 WR
 READY
Direct Memory Access

DMA stands for Direct Memory Access. It is designed by Intel to transfer data at the fastest rate. It
allows the device to transfer the data directly to/from memory without any interference of the CPU.
Using a DMA controller, the device requests the CPU to hold its data, address and control bus, so
the device is free to transfer data directly to/from the memory. The DMA data transfer is initiated
only after receiving HLDA signal from the CPU.
Sequence of operations performed by a DMA
 Initially, when any device has to send data between the device and the memory, the device
has to send DMA request (DRQ) to DMA controller.
 The DMA controller sends Hold request (HRQ) to the CPU and waits for the CPU to assert
the HLDA.
 Then the microprocessor tri-states all the data bus, address bus, and control bus. The CPU
leaves the control over bus and acknowledges the HOLD request through HLDA signal.
 Now the CPU is in HOLD state and the DMA controller has to manage the operations over
buses between the CPU, memory, and I/O devices.
DMA 8257 Architecture
8257 Pin Description
DRQ0−DRQ3
These are the four individual channel DMA request inputs, which are used by the peripheral
devices for using DMA services. When the fixed priority mode is selected, then DRQ0 has the
highest priority and DRQ3 has the lowest priority among them.
DACKo − DACK3
These are the active-low DMA acknowledge lines, which updates the requesting peripheral about
the status of their request by the CPU. These lines can also act as strobe lines for the requesting
devices.
Do − D7
These are bidirectional, data lines which are used to interface the system bus with the internal
data bus of DMA controller. In the Slave mode, it carries command words to 8257 and status word
from 8257. In the master mode, these lines are used to send higher byte of the generated address
to the latch. This address is further latched using ADSTB signal.
IOR
It is an active-low bidirectional tri-state input line, which is used by the CPU to read internal
registers of 8257 in the Slave mode. In the master mode, it is used to read data from the
peripheral devices during a memory write cycle.
IOW
It is an active low bi-direction tri-state line, which is used to load the contents of the data bus to the
8-bit mode register or upper/lower byte of a 16-bit DMA address register or terminal count register.
In the master mode, it is used to load the data to the peripheral devices during DMA memory read
cycle.
CLK
It is a clock frequency signal which is required for the internal operation of 8257.
RESET
This signal is used to RESET the DMA controller by disabling all the DMA channels.
Ao - A3
These are the four least significant address lines. In the slave mode, they act as an input, which
selects one of the registers to be read or written. In the master mode, they are the four least
significant memory address output lines generated by 8257.
CS
It is an active-low chip select line. In the Slave mode, it enables the read/write operations to/from
8257. In the master mode, it disables the read/write operations to/from 8257.
A4 - A7
These are the higher nibble of the lower byte address generated by DMA in the master mode.
READY
It is an active-high asynchronous input signal, which makes DMA ready by inserting wait states.
HRQ
This signal is used to receive the hold request signal from the output device. In the slave mode, it
is connected with a DRQ input line 8257. In Master mode, it is connected with HOLD input of the
CPU.
HLDA
It is the hold acknowledgement signal which indicates the DMA controller that the bus has been
granted to the requesting peripheral by the CPU when it is set to 1.
MEMR
It is the low memory read signal, which is used to read the data from the addressed memory
locations during DMA read cycles.
MEMW
It is the active-low three state signal which is used to write the data to the addressed memory
location during DMA write operation.
ADST
This signal is used to convert the higher byte of the memory address generated by the DMA
controller into the latches.
AEN
This signal is used to disable the address bus/data bus.
TC
It stands for „Terminal Count‟, which indicates the present DMA cycle to the present peripheral
devices.
MARK
The mark will be activated after each 128 cycles or integral multiples of it from the beginning. It
indicates the current DMA cycle is the 128th cycle since the previous MARK output to the selected
peripheral device.
Vcc
It is the power signal which is required for the operation of the circuit.
Unit-5
Interrupts
When microprocessor receives any interrupt signal from peripheral(s) which are requesting its
services, it stops its current execution and program control is transferred to a sub-routine by
generating CALL signal and after executing sub-routine by generating RET signal again program
control is transferred to main program from where it had stopped.
When microprocessor receives interrupt signals, it sends an acknowledgement (INTA) to the

peripheral which is requesting for its service.
Interrupt are classified into following groups based on their parameter:
Vector interrupt − In this type of interrupt, the interrupt address is known to the processor. For
example: RST7.5, RST6.5, RST5.5, TRAP.
Non-Vector interrupt − In this type of interrupt, the interrupt address is not known to the
processor so, the interrupt address needs to be sent externally by the device to perform interrupts.
For example: INTR.
Maskable interrupt − In this type of interrupt, we can disable the interrupt by writing some
instructions into the program. For example: RST7.5, RST6.5, RST5.5.
Non-Maskable interrupt − In this type of interrupt, we cannot disable the interrupt by writing some
instructions into the program. For example: TRAP.
Software interrupt − In this type of interrupt, the programmer has to add the instructions into the
program to execute the interrupt. There are 8 software interrupts in 8085, i.e. RST0, RST1, RST2,
RST3, RST4, RST5, RST6, and RST7.
Hardware interrupt − There are 5 interrupt pins in 8085 used as hardware interrupts, i.e. TRAP,
RST7.5, RST6.5, RST5.5, INTA.
Interrupt Service Routine (ISR)

A small program or a routine that when executed, services the corresponding interrupting source
is called an ISR.
Interrupt in 8085
TRAP
It is a non-maskable interrupt, having the highest priority among all interrupts. Bydefault, it is
enabled until it gets acknowledged. In case of failure, it executes as ISR and sends the data to
backup memory. This interrupt transfers the control to the location 0024H.
RST7.5
It is a maskable interrupt, having the second highest priority among all interrupts. When this
interrupt is executed, the processor saves the content of the PC register into the stack and
branches to 003CH address.
RST 6.5
It is a maskable interrupt, having the third highest priority among all interrupts. When this interrupt
is executed, the processor saves the content of the PC register into the stack and branches to
0034H address.
RST 5.5
It is a maskable interrupt. When this interrupt is executed, the processor saves the content of the
PC register into the stack and branches to 002CH address.
INTR
It is a maskable interrupt, having the lowest priority among all interrupts. It can be disabled by
resetting the microprocessor.
When INTR signal goes high, the following events can occur −
• The microprocessor checks the status of INTR signal during the execution of each
instruction.
• When the INTR signal is high, then the microprocessor completes its current instruction and
sends active low interrupt acknowledge signal.
• When instructions are received, then the microprocessor saves the address of the next
instruction on stack and executes the received instruction.
Priority of Interrupts –
When microprocessor receives multiple interrupt requests simultaneously, it will execute the
interrupt service request (ISR) according to the priority of the interrupts.
Instruction for Interrupts –

Enable Interrupt (EI) –
The interrupt enable flip-flop is set and all interrupts are enabled following the execution of next
instruction followed by EI. No flags are affected. After a system reset, the interrupt enable flip-flop
is reset, thus disabling the interrupts. This instruction is necessary to enable the interrupts again
(except TRAP).
Disable Interrupt (DI) –
This instruction is used to reset the value of enable flip-flop hence disabling all the interrupts. No
flags are affected by this instruction.
Set Interrupt Mask (SIM) –
It is used to implement the hardware interrupts (RST 7.5, RST 6.5, RST 5.5) by setting various bits
to form masks or generate output data via the Serial Output Data (SOD) line. First the required
value is loaded in accumulator then SIM will take the bit pattern from it.
Read Interrupt Mask (RIM) –

This instruction is used to read the status of the hardware interrupts (RST 7.5, RST 6.5, RST 5.5)
by loading into the A register a byte which defines the condition of the mask bits for the interrupts.
It also reads the condition of SID (Serial Input Data) bit on the microprocessor.
8085 Vectored Interrupts
Vectored Interrupts are those which have fixed vector address (starting address of sub-routine)
and after executing these, program control is transferred to that address.
Vector Addresses are calculated by the formula 8 * TYPE.
8085 Non-Vectored Interrupts

Non-Vectored Interrupts are those in which vector address is not predefined. The interrupting
device gives the address of sub-routine for these interrupts. INTR is the only non-vectored
interrupt in 8085 microprocessor.
Restart instructions (RSTn) in 8085 Microprocessor

In 8085 Instruction set, RSTn is actually standing for “Restart n”. And in this case, n has a value
from 0 to 7 only. Thus the eight possible RST instructions are there, e.g. RST 0, RST 1, …, RST 7.
They are 1-Byte call instructions. Functionally RST n instruction is similar with:
RST n = CALL n*8
Unit – 6
Programmable peripheral interface 8255

PPI 8255 is a general purpose programmable I/O device designed to interface the CPU with its
outside world such as ADC, DAC, keyboard etc. We can program it according to the given
condition. It can be used with almost any microprocessor.
It consists of three 8-bit bidirectional I/O ports i.e. PORT A, PORT B and PORT C. We can assign
different ports as input or output functions.
Programmable peripheral interface 8255 Architecture
It consists of 40 pins and operates in +5V regulated power supply. Port C is further divided into
two 4-bit ports i.e. port C lower and port C upper and port C can work in either BSR (bit set rest)
mode or in mode 0 of input-output mode of 8255. Port B can work in either mode or in mode 1 of
input-output mode. Port A can work either in mode 0, mode 1 or mode 2 of input-output mode.
It has two control groups, control group A and control group B. Control group A consist of port A
and port C upper. Control group B consists of port C lower and port B.
Depending upon the value if CS‟, A1 and A0 we can select different ports in different modes as
input-output function or BSR. This is done by writing a suitable word in control register (control
word D0-D7).
Programmable peripheral interface 8255 Pin Diagram
 PA0 – PA7 – Pins of port A

 PB0 – PB7 – Pins of port B
 PC0 – PC7 – Pins of port C
 D0 – D7 – Data pins for the transfer of data
 RESET – Reset input
 RD’ – Read input
 WR’ – Write input
 CS’ – Chip select
 A1 and A0 – Address pins
Operating modes
Bit set reset (BSR) mode
If MSB of control word (D7) is 0, PPI works in BSR mode. In this mode only port C bits are used
for set or reset.
Input-Output mode
If MSB of control word (D7) is 1, PPI works in input-output mode. This is further divided into three
modes:
Mode 0 – In this mode all the three ports (port A, B, C) can work as simple input function or simple
output function. In this mode there is no interrupt handling capacity.
Mode 1 – Handshake I/O mode or strobbed I/O mode. In this mode either port A or port B can
work as simple input port or simple output port, and port C bits are used for handshake signals
before actual data transmission. It has interrupt handling capacity and input and output are
latched.
Example: A CPU wants to transfer data to a printer. In this case since speed of processor is very
fast as compared to relatively slow printer, so before actual data transfer it will send handshake
signals to the printer for synchronization of the speed of the CPU and the peripherals.
Mode 2 – Bi-directional data bus mode. In this mode only port A works, and port B can work either
in mode 0 or mode 1. 6 bits port C are used as handshake signals. It also has interrupt handling
capacity.
8253 (8254) Programmable Interval Timer

The Intel 8253 and 8254 are Programmable Interval Timers (PTIs) designed for microprocessors
to perform timing and counting functions using three 16-bit registers. Each counter has 2 input
pins, i.e. Clock & Gate, and 1 pin for “OUT” output. To operate a counter, a 16-bit count is loaded
in its register. On command, it begins to decrement the count until it reaches 0, then it generates a
pulse that can be used to interrupt the CPU.
8254 Programmable Interval Timer Architecture
8253 (8254) Programmable Interval Timer Pin Diagram
In the above figure, there are three counters, a data bus buffer, Read/Write control logic, and a
control register. Each counter has two input signals - CLOCK & GATE, and one output signal -
OUT.
Data Bus Buffer
It is a tri-state, bi-directional, 8-bit buffer, which is used to interface the 8253/54 to the system data
bus. It has three basic functions −
 Programming the modes of 8253/54.

 Loading the count registers.
 Reading the count values.
Read/Write Logic
It includes 5 signals, i.e. RD, WR, CS, and the address lines A 0 & A1. In the peripheral I/O mode,
the RD and WR signals are connected to IOR and IOW, respectively. In the memorymapped I/O
mode, these are connected to MEMR and MEMW.
Address lines A0 & A1 of the CPU are connected to lines A0 and A1 of the 8253/54, and CS is tied
to a decoded address. The control word register and counters are selected according to the
signals on lines A0 & A1.
Control Word Register

This register is accessed when lines A0 & A1 are at logic 1. It is used to write a command word,
which specifies the counter to be used, its mode, and either a read or write operation.
Counters
Each counter consists of a single, 16 bit-down counter, which can be operated in either binary or
BCD. Its input and output is configured by the selection of modes stored in the control word
register. The programmer can read the contents of any of the three counters without disturbing the
actual count in process.
8259 Programmable Interrupt Controller

8259 microprocessor is defined as Programmable Interrupt Controller (PIC) microprocessor. There
are 5 hardware interrupts and 2 hardware interrupts in 8085 and 8086 respectively. But by
connecting 8259 with CPU, we can increase the interrupt handling capability. 8259 combines the
multi interrupt input sources into a single interrupt output. Interfacing of single PIC provides 8
interrupts inputs from IR0-IR7.
Features of 8259 PIC microprocessor –

 Intel 8259 is designed for Intel 8085 and Intel 8086 microprocessor.
 It can be programmed either in level triggered or in edge triggered interrupt level.
 We can masked individual bits of interrupt request register.
 We can increase interrupt handling capability upto 64 interrupt level by cascading further
8259 PIC.
 Clock cycle is not required.
8259 Programmable Interrupt Controller Pin Diagram
In above diagram that there are total 28 pins in 8259 PIC microprocessor where Vcc :5V Power
supply and Gnd: ground.
8259 Programmable Interrupt Controller Architecture
The Block Diagram consists of 8 blocks which are – Data Bus Buffer, Read/Write Logic, Cascade
Buffer Comparator, Control Logic, Priority Resolver and 3 registers- ISR, IRR, IMR.
Data bus buffer –

This Block is used as a mediator between 8259 and 8085/8086 microprocessor by acting as a
buffer. It takes the control word from the 8085 (let say) microprocessor and transfer it to the control
logic of 8259 microprocessor. Also, after selection of Interrupt by 8259 microprocessor, it transfer
the opcode of the selected Interrupt and address of the Interrupt service sub routine to the other
connected microprocessor. The data bus buffer consists of 8 bits represented as D0-D7 in the
block diagram. Thus, shows that a maximum of 8 bits data can be transferred at a time.
Read/Write logic –
This block works only when the value of pin CS is low (as this pin is active low). This block is
responsible for the flow of data depending upon the inputs of RD and WR. These two pins are
active low pins used for read and write operations.
Control logic –
It is the centre of the microprocessor and controls the functioning of every block. It has pin INTR
which is connected with other microprocessor for taking interrupt request and pin INT for giving the
output. If 8259 is enabled, and the other microprocessor Interrupt flag is high then this causes the
value of the output INT pin high and in this way 8259 responds to the request made by other
microprocessor.
Interrupt request register (IRR) –
It stores all the interrupt level which are requesting for Interrupt services.
Interrupt service register (ISR) –

It stores the interrupt level which are currently being executed.
Interrupt mask register (IMR) –

It stores the interrupt level which have to be masked by storing the masking bits of the interrupt
level.
Priority resolver –
It examines all the three registers and set the priority of interrupts and according to the priority of
the interrupts, interrupt with highest priority is set in ISR register. Also, it reset the interrupt level
which is already been serviced in IRR.
Cascade buffer –
To increase the Interrupt handling capability, we can further cascade more number of pins by
using cascade buffer. So, during increment of interrupt capability, CSA lines are used to control
multiple interrupt structure.
SP/EN (Slave program/Enable buffer) pin is when set to high, works in master mode else in slave
mode. In Non Buffered mode, SP/EN pin is used to specify whether 8259 work as master or slave
and in Buffered mode, SP/EN pin is used as an output to enable data bus.
8251 USART
8251 universal synchronous asynchronous receiver transmitter (USART) acts as a mediator
between microprocessor and peripheral to transmit serial data into parallel form and vice versa.
1. It takes data serially from peripheral (outside devices) and converts into parallel data.
2. After converting the data into parallel form, it transmits it to the CPU.
3. Similarly, it receives parallel data from microprocessor and converts it into serial form.
4. After converting data into serial form, it transmits it to outside device (peripheral).
Block Diagram of 8251 USART
Data bus buffer –

This block helps in interfacing the internal data bus of 8251 to the system data bus. The data
transmission is possible between 8251 and CPU by the data bus buffer block.
Read/Write control logic –

It is a control block for overall device. It controls the overall working by selecting the operation to
be done. The operation selection depends upon input signals as:
In this way, this unit selects one of the three registers- data buffer register, control register, status
register.
Modem control (modulator/demodulator) –

A device converts analog signals to digital signals and vice-versa and helps the computers to
communicate over telephone lines or cable wires. The following are active-low pins of Modem.
 DSR: Data Set Ready signal is an input signal.

 DTR: Data terminal Ready is an output signal.
 CTS: It is an input signal which controls the data transmit circuit.
 RTS: It is an output signal which is used to set the status RTS.
Transmit buffer –
This block is used for parallel to serial converter that receives a parallel byte for conversion into
serial signal and further transmission onto the common channel.
 TXD: It is an output signal, if its value is one, means transmitter will transmit the data.
Transmit control –
This block is used to control the data transmission with the help of following pins:
 TXRDY: It means transmitter is ready to transmit data character.

 TXEMPTY: An output signal which indicates that TXEMPTY pin has transmitted all the data
characters and transmitter is empty now.
 TXC: An active-low input pin which controls the data transmission rate of transmitted data.
Receive buffer –
This block acts as a buffer for the received data.
 RXD: An input signal which receives the data.
Receive control –
This block controls the receiving data.
 RXRDY: An input signal indicates that it is ready to receive the data.

 RXC: An active-low input signal which controls the data transmission rate of received data.
 SYNDET/BD: An input or output terminal. External synchronous mode-input terminal and
asynchronous mode-output terminal.

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Microprocessor

2nd year / 1st part

Microcomputer is a small, relatively inexpensive computer with a microprocessor as its central

Stored program concept

Three types of buses

Length of Data Bus of 8085 microprocessor is 8 Bit, ranging from 00 H to FF H.

Types Of Programming Languages

Low-level programming language

High-level programming language

Examples of instruction set

Control and Status Signals

Power Supply and Clock Frequency

Vss – Ground Reference

(ii) RST 7.5

(iii) RST 6.5

(iv) RST 5.5

The microprocessor acknowledges Interrupt Request by INTA‟ signal. In addition to Interrupts,

INTR – It is an interrupt request signal.

INTA‟ – It is an interrupt acknowledgment sent by the microprocessor after INTR is received.

Serial I/O Ports

Functional Units of 8085 Microprocessor

Arithmetic and logic unit

General purpose register

These are the set of 5 flags −

Auxiliary Carry (AC)

Its bit position is shown in the following table –

Instruction register and decoder

Control Signals: READY, RD‟, WR‟, ALE

Status Signals: S0, S1, IO/M‟

DMA Signals: HOLD, HLDA

RESET Signals: RESET IN, RESET OUT

Serial Input/output control

Address buffer and address-data buffer

Address bus and data bus

Instruction and Data Format

(a) One byte (single) instructions

(b)Two byte instructions

(c) Three byte instructions

Ex: 1. MOV C, A Hex code = 4FH (one byte)

2. ADD B Hex code = 80H (one byte)

3. CMA Hex code = 2FH (one byte)

Ex: 1. MVI A, 09 Hex code = 3E, 09 (two bytes)

2. ADD B, 07 Hex code = 80, 07 (two bytes)

3. SUB A, 05 Hex code = 97, 05 (two bytes)

Ex: 1.LXI H, 8509 Hex code = 21, 09, 85 (Three bytes)

2 .LDA 8509 Hex code = 3A, 09, 85 (Three bytes)

3. JMP 9567 Hex code = C3, 67, 95 (Three bytes)

4. STA 3525 Hex code = 32, 35, 25 (Three bytes)

Instruction Set Classification

Data Transfer Group

LXI Load Register Pair with Immediate data

ADD Add to Accumulator

ANA Logical AND with Accumulator

RLC Rotate Accumulator Left

Complement and carry flag instructions:

CMA Complement Accumulator

Thus, the conditional branching instructions are specified as follows:

Jumps Calls Returns