Chapter 7
Chapter 7
Memory Organization
Chapter Objectives
7.1. Memory Hierarchy
7.2. Main memory
7.3. Cache memory
7.4. Mapping functions
7.4.1. Direct mapping
7.4.2. Associative mapping
7.4.3. Set associative mapping
7.5. External memory
7.5.1. Magnetic disks
7.5.2. RAID technology
7.5.3. Optical disks
7.5.4. Magnetic tape
• Memory Organization in Computer Architecture
• The memory is divided into cells; each of them is identified by a unique number
called an address. The CPU generates the memory request in order to access the
instruction. When the CPU wants to read or write an address, it generates control
signals such as “read” and “write,” which each cell can identify. Because the
program is present in memory, the instruction must be transferred from memory
to the CPU whenever the CPU executes the program.
• Memory Request
• The address and control signals are included in the memory request. When
inserting data and information into the stack, each block uses memory (in the
form of RAM), and the number of memory cells is determined by the memory
chip’s capacity.
Example
• We will find the number of cells present in the 64k*8 memory chips.
• Here, the size of each cell = 8
• And the number of bytes present in 64k = (2^6)*(2^10)
• Thus, Total number of cells here = 2^16 cells
• Along with the total number of cells, the total number of address lines that are
needed to enable any cell can be determined here.
• Word Size
• It refers to the maximum amount of bits a CPU
can handle at one time, and it fluctuates by the
processor. The hardware or the instruction set of a
processor handles a fixed amount of data as a unit
called word size.
• Because of generation and current technology,
word size varies based on processor architectures;
it could be as small as 4-bits or as large as 64-bits,
depending on what a given processor can handle.
Addresses, Registers, Fixed-point numbers, and
Floating-point numbers are all examples of
notions that require word size.
7.1. Memory Hierarchy
• The total memory capacity of a computer can be visualized by hierarchy of
components. The memory hierarchy system consists of all storage devices
contained in a computer system from the slow Auxiliary Memory to fast Main
Memory and to smaller Cache memory.
• Auxillary memory access time is generally 1000 times that of the main
memory, hence it is at the bottom of the hierarchy.
• The main memory occupies the central position because it is equipped to
communicate directly with the CPU and with auxiliary memory devices
through Input/output processor (I/O).
• When the program not residing in main memory is needed by the CPU, they
are brought in from auxiliary memory. Programs not currently needed in main
memory are transferred into auxiliary memory to provide space in main
memory for other programs that are currently in use.
• The cache memory is used to store program data which is currently being
executed in the CPU. Approximate access time ratio between cache memory
and main memory is about 1 to 7~10
• The cache memory is very small, relatively expensive, and has very high
access speed. The CPU has direct access to both cache and main memory but
not to auxiliary memory.
Memory Access Methods:
• Each memory type, is a collection of numerous
memory locations. To access data from any memory,
first it must be located and then the data is read from
the memory location. Following are the methods to
access information from memory locations:
• Random Access: Main memories are random access
memories, in which each memory location has a
unique address. Using this unique address any
memory location can be reached in the same amount
of time in any order.
• Sequential Access: This methods allows memory
access in a sequence or in order.
• Direct Access: In this mode, information is stored in
tracks, with each track having a separate read/write
head.
7.2. Main memory
• The memory unit that communicates directly within the CPU,
Auxillary memory and Cache memory, is called main memory. It is
the central storage unit of the computer system. It is a large and fast
memory used to store data during computer operations. Main
memory is made up of RAM and ROM, with RAM integrated
circuit chips holing the major share.
• RAM: Random Access Memory
– DRAM: Dynamic RAM, is made of capacitors and transistors,
and must be refreshed every 10~100 ms. It is slower and cheaper
than SRAM.
– SRAM: Static RAM, has a six transistor circuit in each cell and
retains data, until powered off.
– NVRAM: Non-Volatile RAM, retains its data, even when turned
off. Example: Flash memory.
• ROM: Read Only Memory, is non-volatile and is more like a
permanent storage for information. It also stores the bootstrap
loader program, to load and start the operating system when
computer is turned on.
• PROM(Programmable ROM), EPROM(Erasable PROM)
Auxiliary Memory
• Devices that provide backup storage are called
auxiliary memory. For example: Magnetic
disks and tapes are commonly used auxiliary
devices. Other devices used as auxiliary
memory are magnetic drums, magnetic
bubble memory and optical disks.
• It is not directly accessible to the CPU, and is
accessed using the Input/Output channels.
7.3. Cache memory
• The data or contents of the main memory that are used again
and again by CPU, are stored in the cache memory so that we
can easily access that data in shorter time.
• Whenever the CPU needs to access memory, it first checks the
cache memory. If the data is not found in cache memory then
the CPU moves onto the main memory. It also transfers block
of recent data into the cache and keeps on deleting the old data
in cache to accomodate the new one.
• Hit Ratio:
• The performance of cache memory is measured in terms of a
quantity called hit ratio. When the CPU refers to memory and
finds the word in cache it is said to produce a hit. If the word
is not found in cache, it is in main memory then it counts as
a miss.
• The ratio of the number of hits to the total CPU references to
memory is called hit ratio.
• Hit Ratio = Hit/(Hit + Miss)
•
Hit Ratio(H) = hit / (hit + miss) = no. of hits/total accesses
Miss Ratio = miss / (hit + miss) = no. of miss/total accesses = 1 - hit ratio(H)
Case 1 : System Design without Cache Memory