Cache Memory
Cache Memory
Cache Memory
Location-
Cache memory lies on the path between the CPU and the main memory.
It facilitates the transfer of data between the processor and the main memory at the
speed which matches to the speed of the processor.
Data is transferred in the form of words between the cache memory and the CPU.
Data is transferred in the form of blocks or pages between the cache memory and the
main memory.
Cache Performance
When the processor needs to read or write a location in the main memory, it
first checks for a corresponding entry in the cache.
If the processor finds that the memory location is in the cache, a Cache
Hit has occurred and data is read from the cache.
If the processor does not find the memory location in the cache, a cache
miss has occurred. For a cache miss, the cache allocates a new entry and
copies in data from the main memory, then the request is fulfilled from the
contents of the cache.
The performance of cache memory is frequently measured in terms of a
quantity called Hit ratio.
Purpose-
1. Direct Mapping
The simplest technique, known as direct mapping, maps each block of main
memory into only one possible cache line. or In Direct mapping, assign each
memory block to a specific line in the cache. If a line is previously taken up by
a memory block when a new block needs to be loaded, the old block is trashed.
An address space is split into two parts index field and a tag field. The cache
is used to store the tag field whereas the rest is stored in the main memory.
Direct mapping`s performance is directly proportional to the Hit ratio.
i = j modulo m
where
i = cache line number
j = main memory block number
m = number of lines in the cache
Direct Mapping
For purposes of cache access, each main memory address can be viewed as
consisting of three fields. The least significant w bits identify a unique word or
byte within a block of main memory. In most contemporary machines, the
address is at the byte level. The remaining s bits specify one of the 2s blocks
of main memory. The cache logic interprets these s bits as a tag of s-r bits (the
most significant portion) and a line field of r bits. This latter field identifies one
of the m=2r lines of the cache. Line offset is index bits in the direct mapping.
Direct Mapping – Structure
2. Associative Mapping
In this type of mapping, associative memory is used to store the content and
addresses of the memory word. Any block can go into any line of the cache.
This means that the word id bits are used to identify which word in the block
is needed, but the tag becomes all of the remaining bits. This enables the
placement of any word at any place in the cache memory. It is considered to
be the fastest and most flexible mapping form. In associative mapping, the
index bits are zero.
3. Set-Associative Mapping
This form of mapping is an enhanced form of direct mapping where the
drawbacks of direct mapping are removed. Set associative addresses the
problem of possible thrashing in the direct mapping method. It does this by
saying that instead of having exactly one line that a block can map to in the
cache, we will group a few lines together creating a set. Then a block in
memory can map to any one of the lines of a specific set. Set-associative
mapping allows each word that is present in the cache can have two or more
words in the main memory for the same index address. Set associative cache
mapping combines the best of direct and associative cache mapping
techniques. In set associative mapping the index bits are given by the set
offset bits. In this case, the cache consists of a number of sets, each of which
consists of a number of lines.
2. Associative Mapping
In this type of mapping, associative memory is used to store the content and
addresses of the memory word. Any block can go into any line of the cache.
This means that the word id bits are used to identify which word in the block
is needed, but the tag becomes all of the remaining bits. This enables the
placement of any word at any place in the cache memory. It is considered to
be the fastest and most flexible mapping form. In associative mapping, the
index bits are zero.
Set-Associative Mapping
Example-
Three level cache organization consists of three cache memories of different size
organized at three different levels as shown below-
Size (L1 Cache) < Size (L2 Cache) < Size (L3 Cache) < Size (Main Memory)
Cache memory bridges the speed mismatch between the processor and the main memory.
When cache hit occurs,
The required word is present in the cache memory.
The required word is delivered to the CPU from the cache memory.