MODULE 2

8085 Instructions
 An instruction of computer is a command given to the computer to perform a
specified operation on given data.
 Some instructions of Intel 8085 microprocessor are: MOV, MVI, LDA, STA, ADD,
SUB, RAL, INR, MVI, etc.
Instruction and Data Formats
The various techniques to specify data for instructions are:
1. 8-bit or 16-bit data may be directly given in the instruction itself.
2. The address of the memory location, I/O port or I/O device, where data
resides, may be given in the instruction itself.
3. In some instructions, only one register is specified. The content of the
specified register is one of the operands.
4. Some instructions specify two registers. The contents of the registers are the
required data.
5. In some instructions, data is implied. The most instructions of this type
operate on the content of the accumulator.
Due to different ways of specifying data for instructions, the machine codes of all
instructions are not of the same length. It may 1-byte, 2-byte or 3-byte instruction.
Opcode and Operands
 Each instruction contains two parts: Opcode (Operation code) and Operand.

 The 1st part of an instruction which specifies the task to be performed by the
computer is called Opcode.

 The 2nd part of the instruction is the data to be operated on, and it is called
Operand. The Operand (or data) given in the instruction may be in various forms
such as 8-bit or 16-bit data, 8-bit or 16-bit address, internal registers or a
register or memory location.

Example:
MOV B, C
Opcode: MOV
Operand: B and C
Given instruction copies the contents of the source register into the destination
register and the contents of the source register are not altered. B is the
destination register and C is the source register whose contents need to be
transferred to the destination register.
Mnemonics
 A mnemonic in the microprocessor is a symbol, a name or a term that defines a
computer function or operation.
 A mnemonic is always used to give users quick access to computer functions,
processes or services.
  Through mnemonics, a user will bypass the actual and long ways or path to
perform a task.
 An assembly language makes use of mnemonics to describe an opcode.
 An example of a mnemonic is MOV which means moving data from one memory
location or register to another.
 There are many other mnemonics in the microprocessor that makes achieving a
computer task easier and faster.
 The mnemonic in the microprocessor is acronym/abbreviation, for operation.
 It is used in instruction code to make easy and suitable coding.
 The mnemonics are R used for the register, A for the accumulator, Z for zero
flags, etc.

8085 Instruction Sets

 The instruction set of 8085 microprocessor is the collection of the instructions
that the microprocessor is designed to execute.
 The programmer writes a program in assembly language using these
instructions.
 These instructions have been classified into the following groups:
o Data-transfer/ Copy Instructions
o Arithmetic Instructions
o Logical Instructions
o Branching Instructions/ Branch Control Instructions/ Jump Instructions
o Stack, I/O and Machine Control Instructions
o Shift and Rotate Instructions

Data-transfer/ Copy Instructions

 Instructions which are used to transfer the data from a register to another
register from memory to register or register to memory come under this group.
 They are also called copy instructions.

OPCOD OPERAND EXPLANATION EXAMPLE

E

MOV Rd, Rs Rd = Rs MOV A, B

Move the content of the one register to
another

MOV Rd, M Rd = Mc MOV A, 2050

Move the content of memory to
register

MOV M, Rs M = Rs MOV 2050, A

Move the content of register to
memory
 OPCOD OPERAND EXPLANATION EXAMPLE
E

MVI Rd, 8-bit data Rd = 8-bit data MVI A, 50

Move immediate data to register

MVI M, 8-bit data M = 8-bit data MVI 2050, 50

Move immediate data to memory

LDA 16-bit address A = contents at address LDA 2050

Load Accumulator direct

STA 16-bit address contents at address = A STA 2050

Store accumulator direct

LHLD 16-bit address directly loads at H & L registers LHLD 2050

SHLD 16-bit address directly stores from H & L registers SHLD 2050

LXI r.p., 16-bit Load Register pair immediate (loads LXI H, 3050
data the specified register pair with data)

LDAX r.p. indirectly loads at the accumulator A LDAX H

STAX 16-bit address indirectly stores from the accumulator STAX 2050
A

XCHG None Change the contents of H-L with D-E XCHG

pair (exchanges H with D, and L with
E)

In the table,
R stands for register
M stands for memory
Mc stands for memory contents
r.p. stands for register pair
Arithmetic Instructions
 The instructions of this group perform arithmetic operations such as addition,
subtraction, increment or decrement of the content of a register or a memory.
 In 8085 microprocessor, the destination operand is generally the accumulator.
Opcod Operand Explanation Example
e

ADD R A=A+R ADD B

Add register to accumulator

ADD M A = A + Mc ADD 2050

Add memory to accumulator

ADI 8-bit A = A + 8-bit data ADI 50

data Add immediate data to
accumulator

ADC R A = A + R + prev. carry ADC B

Add register with carry to
accumulator

ADC M A = A + Mc + prev. carry ADC 2050

Add memory with carry to
accumulator

ACI 8-bit A = A + 8-bit data + prev. carry ACI 50

data Add with carry immediate data to
accumulator

SUB R A=A–R SUB B

Subtract register from
accumulator

SUB M A = A – Mc SUB 2050

Subtract memory from
accumulator

SUI 8-bit A = A – 8-bit data SUI 50

data Subtract immediate data from
accumulator

SBB R A = A – R – prev. carry SBB B

Subtract contents of register from
accumulator with borrow

SBB M A = A – Mc -prev. carry SBB 2050

Subtract contents of memory from
 Opcod Operand Explanation Example
e

accumulator with borrow

SBI 8-bit A = A – 8-bit data – prev. carry SBI 50

data Subtract immediate data from
accumulator with borrow

INR R R=R+1 INR B

Increment register content

INR M M = Mc + 1 INR 2050

Increment memory content

INX r.p. r.p. = r.p. + 1 INX H

Increment register pair content

DCR R R=R–1 DCR B

Decrement register pair

DCR M M = Mc – 1 DCR 2050

Decrement memory content

DCX r.p. r.p. = r.p. – 1 DCX H

Decrement register pair

DAD r.p. HL = HL + r.p. DAD D

Add the register pair to H-L
register pair

Logical Instructions
 The instructions in this group perform logical operation such as AND, OR,
compare, etc.
 In 8085 microprocessor, the destination operand is always the accumulator.
Here logical operation works on a bitwise level.

OPCODE OPERAND DESTINATION EXAMPLE

A = A AND R
ANA R AND register with accumulator ANA B
 OPCODE OPERAND DESTINATION EXAMPLE

A = A AND Mc
ANA M AND memory with accumulator ANA 2050

A = A AND 8-bit data

ANI 8-bit data AND immediate data with accumulator ANI 50

A = A OR R
ORA R OR-register with accumulator ORA B

A = A OR Mc
ORA M OR-memory with accumulator ORA 2050

A = A OR 8-bit data
ORI 8-bit data OR -immediate data with accumulator ORI 50

A = A XOR R
XRA R XOR register with accumulator XRA B

A = A XOR Mc
XRA M XOR memory with accumulator XRA 2050

A = A XOR 8-bit data

XRI 8-bit data XOR immediate data with accumulator XRI 50

A = 1’s compliment of A
CMA none Complement the accumulator CMA

CMP R Compare register with accumulator CMP B

CMP M Compare contents of memory with accumulator CMP 2050

CPI 8-bit data Compare immediate data with accumulator CPI 50

CMC none Compliments the carry flag CMC

STC none Sets the carry flag STC

Branching Instructions/ Branch Control Instructions

 Branching instructions refer to the act of switching execution to a different
instruction sequence as a result of executing a branch instruction.
  The three types of branching instructions are:
o Jump (unconditional and conditional)
o Call (unconditional and conditional)
o Return (unconditional and conditional)

1. Jump Instructions – The jump instruction transfers the program sequence to

the memory address given in the operand based on the specified flag. Jump
instructions are 2 types:
a. Unconditional Jump Instructions
b. Conditional Jump Instructions

(a) Unconditional Jump Instructions: Transfers the program sequence to the

described memory address.

OPCODE OPERAND EXPLANATION EXAMPLE

JMP Address Jumps to the JMP 2050

address

(b) Conditional Jump Instructions: Transfers the program sequences to the

described memory address only if the condition in satisfied.

OPCOD OPERAND EXPLANATION EXAMPLE

E

Jumps to the address if carry flag is

JC Address 1 JC 2050

Jumps to the address if carry flag is JNC

JNC Address 0 2050

JZ Address Jumps to the address if zero flag is 1 JZ 2050

JNZ Address Jumps to the address if zero flag is 0 JNZ 2050

Jumps to the address if parity flag is

JPE Address 1 JPE 2050

Jumps to the address if parity flag is

JPO Address 0 JPO 2050

JM Address Jumps to the address if sign flag is 1 JM 2050

OPCOD OPERAND EXPLANATION EXAMPLE
E

JP Address Jumps to the address if sign flag 0 JP 2050

2. Call Instructions – The call instruction transfers the program sequence to the
memory address given in the operand. Before transferring, the address of the
next instruction after CALL is pushed onto the stack. Call instructions are 2 types:
a. Unconditional Call Instructions
b. Conditional Call Instructions

(a) Unconditional Call Instructions: It transfers the program sequence to the

memory address given in the operand.

OPCODE OPERAND EXPLANATION EXAMPLE

CALL Address Unconditionally calls CALL 2050

(b) Conditional Call Instructions: Only if the condition is satisfied, the instructions
execute.

OPCODE OPERAND EXPLANATION EXAMPLE

CC Address Call if carry flag is 1 CC 2050

CNC Address Call if carry flag is 0 CNC 2050

CZ Address Calls if zero flag is 1 CZ 2050

CNZ Address Calls if zero flag is 0 CNZ 2050

CPE Address Calls if parity flag is 1 CPE 2050

CPO Address Calls if parity flag is 0 CPO 2050

CM Address Calls if sign flag is 1 CM 2050

CP Address Calls if sign flag is 0 CP 2050

3. Return Instructions – The return instruction transfers the program sequence

from the subroutine to the calling program. Return instructions are 2 types:
 a. Unconditional Return Instructions
b. Conditional Return Instructions
(a) Unconditional Return Instruction: The program sequence is transferred
unconditionally from the subroutine to the calling program.
OPCODE OPERAND EXPLANATION EXAMPLE

Return from the subroutine

RET none unconditionally RET

(b) Conditional Return Instruction: The program sequence is transferred

unconditionally from the subroutine to the calling program only is the condition is
satisfied.
OPCOD
E OPERAND EXPLANATION EXAMPLE

RC None Return from the subroutine if carry flag is 1 RC

RNC None Return from the subroutine if carry flag is 0 RNC

RZ None Return from the subroutine if zero flag is 1 RZ

RNZ None Return from the subroutine if zero flag is 0 RNZ

RPE None Return from the subroutine if parity flag is 1 RPE

RPO None Return from the subroutine if parity flag is 0 RPO

RM None Returns from the subroutine if sign flag is 1 RM

RP None Returns from the subroutine if sign flag is 0 RP

Stack, I/O and Machine Control Instructions

OPCOD OPERAND EXPLANATION EXAMPLE

E

PUSH r.p. pushes r.p. to the stack PUSH H

POP r.p. pops the stack to r.p. POP H

OPCOD OPERAND EXPLANATION EXAMPLE
E

IN 8-bit port inputs contents of the specified port to A IN 15

address

OUT 8-bit port outputs contents of A to the specified port OUT 15

address

NOP None No operation is performed, i.e., the

instruction is fetched and decoded.

HLT None Halt and enter wait state (The CPU finishes
executing the current instruction and stops
further execution. An interrupt or reset is
necessary to exit from the halt state.)

DI None Disable interrupts (The interrupt enable

flip-flop is reset and all the interrupts are
disabled except TRAP.)

EI None Enable interrupts (The interrupt enable

flip-flop is set and all the interrupts are
enabled.)

RIM None Read interrupt mask (This instruction is

used to read the status of interrupts 7.5,
6.5, 5.5 and read serial data input bit.)

SIM None Set interrupt mask (This instruction is used

to implement the interrupts 7.5, 6.5, 5.5,
and serial data output.)

Shift and Rotate Instructions

 ROTATE is a logical operation of 8085 microprocessor.
o It is a 1 byte instruction.
o This instruction does not require any operand after the opcode.
o It operates the content of accumulator and the result is also stored in the
accumulator.
o The Rotate instruction is used to rotating the bits of accumulator.
o There are 4 categories of the ROTATE instruction:
 Rotate accumulator left (RLC)
 Rotate accumulator left through carry (RAL)
 Rotate accumulator right (RRC)
  Rotate accumulator right through carry (RAR).
o Among these four instructions; two are for rotating left and two are for
rotating right.
 Shift instructions can perform two basic types of shift operations; the logical shift
and the arithmetic shift.
 Also, each of these operations can be performed to the right or to the left.

OPCODE OPERAND EXPLANATION EXAMPLE

RRC None Rotate accumulator right without carry RRC

RLC None Rotate accumulator left without carry RLC

RAR None Rotate accumulator right with carry RAR

RAL None Rotate accumulator left with carry RAR

Contents of register is logically shifted left

SHL R, count by number of bit positions equal to count SHL AX, 1

Contents of register is logically shifted

right by number of bit positions equal to SHR BX,
SHR R, count count 12

Contents of register is arithmetically

shifted left by number of spaces specified
SAL R, count by count SAL C, 2

Contents of register is arithmetically

shifted right by number of spaces specified
R, count by count SAR D, 5
SAR

Subroutine in 8085

 In computers, a subroutine is a sequence of program instructions that perform a

specific task, packaged as a unit.
 This unit can then be used in programs wherever that particular task have to be
performed.
  A subroutine is often coded so that it can be started (called) several times and
from several places during one execution of the program, including from other
subroutines, and then branch back (return) to the next instruction after the call,
once the subroutine’s task is done.
 It is implemented by using Call and Return instructions.
 The different types of subroutine instructions are:
o Unconditional Call instruction
CALL address is the format for unconditional call instruction. After execution of
this instruction program control is transferred to a sub-routine whose starting
address is specified in the instruction. Value of PC (Program Counter) is
transferred to the memory stack and value of SP (Stack Pointer) is decremented
by 2.
o Conditional Call instruction
In these instructions program control is transferred to subroutine and value of
PC is pushed into stack only if condition is satisfied.

INSTRUCTION PARAMETER COMMENT

CC 16-bit address Call at address if cy (carry flag) = 1

CNC 16-bit address Call at address if cy (carry flag) = 0

CZ 16-bit address Call at address if ZF (zero flag) = 1

CNZ 16-bit address Call at address if ZF (zero flag) = 0

CPE 16-bit address Call at address if PF (parity flag) = 1

CPO 16-bit address Call at address if PF (parity flag) = 0

CN 16-bit address Call at address if SF (signed flag) = 1

CP 16-bit address Call at address if SF (signed flag) = 0

o Unconditional Return instruction

RET is the instruction used to mark the end of sub-routine. It has no parameter. After
execution of this instruction program control is transferred back to main program from
where it had stopped. Value of PC (Program Counter) is retrieved from the memory
stack and value of SP (Stack Pointer) is incremented by 2.
o Conditional Return instruction
By these instructions program control is transferred back to main program and value of
PC is popped from stack only if condition is satisfied. There is no parameter for return
instruction.

INSTRUCTION COMMENT

RC Return from subroutine if cy (carry flag) = 1

RNC Return from subroutine if cy (carry flag) = 0

RZ Return from subroutine if ZF (zero flag) = 1

RNZ Return from subroutine if ZF (zero flag) = 0

RPE Return from subroutine if PF (parity flag) = 1

RPO Return from subroutine if PF (parity flag) = 0

RN Return from subroutine if SF (signed flag) = 1

RP Return from subroutine if SF (signed flag) = 0

Advantages of Subroutine –
1. Decomposing a complex programming task into simpler steps.
2. Reducing duplicate code within a program.
3. Enabling reuse of code across multiple programs.
4. Improving tractability or makes debugging of a program easy.

Addressing Modes in 8085

 Each instruction requires some data on which it has to operate. There are
different techniques to specify data for instructions. These techniques are
called addressing modes.
 These are the instructions used to transfer the data from one register to another
register, from the memory to the register, and from the register to the memory
without any alteration in the content.
 Addressing modes in 8085 is classified into 5 groups –
 Immediate addressing mode
 Register addressing mode
 Direct addressing mode
 Register Indirect addressing mode
 Implied addressing mode
 1. Immediate addressing mode
 In this addressing mode, the operand is specified within the instruction itself.
 The 8/16-bit data is specified in the instruction itself as one of its operand.
 For example:
o MVI B, 20F - means 20F is copied into register B.
o LXI H, 2500 - 2500 is 16-bit data which is given in the instruction
itself. It is to be loaded into H-L pair.
2. Register addressing mode
 In this addressing mode, the data is copied from one register to another.
 The operand is in one of the general purpose registers. The opcode specifies the
address of the register(s) in addition to the operation to be performed.
 For example:
o MOV A, B - means data in register B is copied to register A.
3. Direct addressing mode
 In this addressing mode, the address of the operand (data) is given in the
instruction itself.
 The data is directly copied from the given address to the register.
 For example:
o STA 2400H - It stores the content of the accumulator in the memory
location 2400H.
4. Register Indirect addressing mode
 In Register Indirect mode of addressing, the data is transferred from one register
to another by using the address pointed by the register.
 The address of the operand is specified by a register pair.
 For example:
o MOV C, B - means data is transferred from the memory address
pointed by the register B to the register C.
5. Implied addressing mode
 This mode doesn’t require any operand; the data is specified by the opcode itself.
 There are certain instructions which operate on the content of the accumulator.
Such instructions do not require the address of the operand.
 For example:
o CMP, RAL, RAR, etc.

Interrupts in 8085

Interrupts are the signals generated by the external devices to request the
microprocessor to perform a task. There are 5 interrupt signals, i.e. TRAP, RST 7.5, RST
6.5, RST 5.5, and INTR.

Interrupt are classified into following groups based on their parameter −

  Vector interrupt − In this type of interrupt, the interrupt address is known to
the processor. For example: RST7.5, RST6.5, RST5.5, TRAP.

 Non-Vector interrupt − In this type of interrupt, the interrupt address is not

known to the processor so, the interrupt address needs to be sent externally by
the device to perform interrupts. For example: INTR.

 Maskable interrupt − In this type of interrupt, we can disable the interrupt by

writing some instructions into the program. For example: RST7.5, RST6.5,
RST5.5.

 Non-Maskable interrupt − In this type of interrupt, we cannot disable the

interrupt by writing some instructions into the program. For example: TRAP.

 Software interrupt − In this type of interrupt, the programmer has to add the
instructions into the program to execute the interrupt. There are 8 software
interrupts in 8085, i.e. RST0, RST1, RST2, RST3, RST4, RST5, RST6, and RST7.

 Hardware interrupt − There are 5 interrupt pins in 8085 used as hardware

interrupts, i.e. TRAP, RST7.5, RST6.5, RST5.5, INTR.

Interrupt Service Routine (ISR)

 A small program or a routine that when executed, services the corresponding

interrupting source is called an ISR.

TRAP: It is a non-maskable interrupt, having the highest priority among all interrupts.
By default, it is enabled until it gets acknowledged. In case of failure, it executes as ISR
and sends the data to backup memory.

RST7.5: It is a maskable interrupt, having the second highest priority among all
interrupts. When this interrupt is executed, the processor saves the content of the PC
register into the stack and branches to 003CH address.

RST 6.5: It is a maskable interrupt, having the third highest priority among all
interrupts. When this interrupt is executed, the processor saves the content of the PC
register into the stack and branches to 0034H address.

RST 5.5: It is a maskable interrupt. When this interrupt is executed, the processor saves
the content of the PC register into the stack and branches to 002CH address.

INTR: It is a maskable interrupt, having the lowest priority among all interrupts. It can
be disabled by resetting the microprocessor.

When INTR signal goes high, the following events can occur −
  The microprocessor checks the status of INTR signal during the execution of each
instruction.
 When the INTR signal is high, then the microprocessor completes its current
instruction and sends active low interrupt acknowledge signal.
 When instructions are received, then the microprocessor saves the address of
the next instruction on stack and executes the received instruction.

I/O Interfacing
Interface is the path for communication between two components. Interfacing is
of two types:
 Memory interfacing and
 I/O interfacing
Several memory chips and I/O devices are connected to a microprocessor. The
following figure shows a schematic diagram to interface memory chips and I/O devices
to a microprocessor.

Memory Interfacing
 When we are executing any instruction, we need the microprocessor to access
the memory for reading instruction codes and the data stored in the memory.
 For this, both the memory and the microprocessor require some signals to read
from and write to registers.
 The interfacing process includes matching the memory requirements with the
microprocessor signals.
 Therefore, the interfacing circuit should be designed in such a way that it
matches the memory signal requirements with the microprocessor's signals.

I/O Interfacing
 Any application of a microprocessor based system requires the transfer of data
between external circuitry to the microprocessor and microprocessor to the
external circuitry.
  There are various communication devices like the keyboard, mouse, printer, etc.
 User can give information to the microprocessor using keyboard and user can
see the result or output information from the microprocessor with the help of
display device.
 So, we need to interface the keyboard and other devices with the
microprocessor. This type of interfacing is known as I/O interfacing.
 In other words, the transfer of data between keyboard and microprocessor, and
microprocessor and display device is called Input Output Interfacing 8085
Microprocessor or I/O data transfer.
 For this type of interfacing, we use latches and buffers for interfacing the
keyboards and displays with the microprocessor or we can say, the data transfer
is done with the help of I/O ports.

Input Port:
o It is used to read data from the input device such as keyboard.
o The simplest form of input port is a buffer.
o The input device is connected to the microprocessor through buffer as shown in
the figure. This buffer is a tri-state buffer and its output is available only when
enable signal is active.

When microprocessor wants to read data from the input device (keyboard), the
control signals from the microprocessor activates the buffer by asserting enable input of
the buffer. Once the buffer is enabled, data from the input device is available on the data
bus. Microprocessor reads this data by initiating read command.
Output Port:
o It is used to send data to the output device such as display from the
microprocessor.
o The simplest form of output port is a latch.
o The output device is connected to the microprocessor through latch as shown in
the figure.
 When microprocessor wants to send data to the output device, it puts the data on
the data bus and activates the clock signal of the latch, latching the data from the data
bus at the output of latch. It is then available at the output of latch for the output device.
In 8085 Instruction set, there are two instructions in 8085 for communication
with I/O ports. They are the IN and OUT instructions. The IN or OUT instruction
mnemonic should be followed by an 8-bit port address. Thus we can have 2 8 = 256 input
ports and 256 output ports are possible in 8085-based microcomputer. IN and OUT
both are 2-Bytes instructions.
There are two ways of communication in which the microprocessor can connect with
the outside world.
 Serial Communication Interface
 Parallel Communication interface
Serial Communication Interface − In this type of communication, the interface gets a
single byte of data from the microprocessor and sends it bit by bit to the other system
serially and vice-a-versa.
Parallel Communication Interface − In this type of communication, the interface gets
a byte of data from the microprocessor and sends it bit by bit to the other systems in
simultaneous (or) parallel fashion and vice-a-versa.

Instruction Cycle
  The time required to fetch an instruction and necessary data from memory and
to execute it, is called an instruction cycle. Or the total time required to execute
an instruction is given by:
IC = FC + EC
Where,
IC = Instruction Cycle
FC = Fetch Cycle
EC = Execute Cycle
Timing Diagram for Instruction Cycle

Fetch the instruction (Fetch Cycle)

In the beginning of the fetch cycle, the content of the program counter (PC), which is the
address of the memory location where opcode is available, is sent to the memory. The
memory puts the opcode on the data bus so as to transfer it to the CPU.
The whole operation of fetching an opcode takes three clock cycles. A slow memory may
take more time.
Decode the instruction (Decode Cycle)
The opcode fetched from the memory goes to the data register, DR and then to
instruction register, IR. From the IR it goes to the decoder circuitry which decodes the
instruction. Decoder circuitry is within the microprocessor.
Execute the Instruction (Execute Cycle)
After the instruction is decoded, execution begins.
If the operand is reside the general purpose registers, execution is immediately
performed. The time taken in decoding and execution of an instruction is one clock
cycle.
In some situations, an execute cycle may involve one or more read or write cycles or
both.
 Read Cycle: If an instruction contains data or operand address which are in the
memory, the CPU has to perform some read operations to get the desired data. In
case of a read cycle the instruction received from the memory are data or
operand address instead of an opcode.
 Write Cycle: In write cycle data are sent from the CPU to the memory or an
output device.
Machine Cycle and State
The necessary steps carried out to perform the operation of accessing either memory or
input output device, constitute a machine cycle.
In other words, necessary steps carried out to perform a fetch, a read or a write
operation constitutes a machine cycle.
One sub-division of an operation performed in one clock cycle is called a state or T-
state. In short, one clock cycle of the system clock is referred to as a state.
Timing Diagram
The necessary steps carried out in a machine cycle can be represented graphically. Such
a graphical representation is called timing diagram. The timing diagram for opcode
fetch, memory read, memory write, I/O read and I/O write will be discussed below:
o Timing Diagram for Opcode Fetch Cycle:
o Timing Diagram for Memory Read

o Timing Diagram for Memory Write

o Timing Diagram for I/O Read

 o Timing Diagram for I/O Write

In the above diagrams, the basic used parameters are:

ALE: ALE indicates the availability of a valid address on the multiplexed address/data
lines. When it is high or 1, then it acts as an address bus and when low or 0, then it acts
as a data bus.
RD (low active): If it is high or 1, then no data is read by the microprocessor. If signal is
low or 0, then data is read by the microprocessor.
WR (low active): If it is high or 1, then no data is written by the microprocessor. If
signal is low or 0, then data is written by the microprocessor.
IO/M (low active): A high or 1 on this signal indicates I/O operation while a low or 0
indicates memory operation.
S0, S1: S0 and S1 Indicate the type of machine cycle in progress.
The below table, shows the status of different control signal for different operation: