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Efm 32 GG

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EFM32GG Data Sheet

System Summary

3. System Summary

3.1 System Introduction

The EFM32 MCUs are the world’s most energy friendly microcontrollers. With a unique combination of the powerful 32-bit ARM Cortex-
M3, innovative low energy techniques, short wake-up time from energy saving modes, and a wide selection of peripherals, the
EFM32GG microcontroller is well suited for any battery operated application as well as other systems requiring high performance and
low-energy consumption. This section gives a short introduction to each of the modules in general terms and also shows a summary of
the configuration for the EFM32GG devices. For a complete feature set and in-depth information on the modules, refer to the
EFM32GG Reference Manual.

A block diagram of the EFM32GG is shown in the following figure.

Core / Memory Clock Management Energy Management Security


High Frequency High Frequency Voltage Voltage
ARM CortexTM Memory Crystal Oscillator RC Oscillator Regulator Comparator Hardware AES
M3 processor Protection Unit
Auxiliary High Low Freq. Brown-out Power-on
Flash Program Freq. RC Osc. RC Oscillator Detector Reset
Debug w/ ETM
Memory
Low Frequency Ultra Low Freq. Back-up Power
RAM Memory DMA Controller Crystal Oscillator RC Oscillator Domain

32-bit bus
Peripheral Reflex System

Serial Interfaces I/O Ports Timers and Triggers Analog Interfaces


External Bus Timer/Counter LESENSE
USART UART TFT Driver ADC LCD Controller
Interface
Low Energy Timer Real Time Counter
Low Energy External General Operational
I2C DAC
UARTTM Interrupts Purpose I/O Amplifier
Pulse Counter Watchdog Timer
Analog
USB Pin Reset Pin Wakeup Back-up RTC Comparator

Lowest power mode with peripheral operational:


EM0 - Active EM1 - Sleep EM2 – Deep Sleep EM3 - Stop EM4 - Shutoff

Figure 3.1. Block Diagram

3.1.1 ARM Cortex-M3 Core

The ARM Cortex-M3 includes a 32-bit RISC processor which can achieve as much as 1.25 Dhrystone MIPS/MHz. A Memory Protection
Unit with support for up to 8 memory segments is included, as well as a Wake-up Interrupt Controller handling interrupts triggered while
the CPU is asleep. The EFM32 implementation of the Cortex-M3 is described in detail in EFM32GG Reference Manual.

3.1.2 Debug Interface (DBG)

This device includes hardware debug support through a 2-pin serial-wire debug interface and an Embedded Trace Module (ETM) for
data/instruction tracing. In addition there is also a 1-wire Serial Wire Viewer pin which can be used to output profiling information, data
trace and software-generated messages.

3.1.3 Memory System Controller (MSC)

The Memory System Controller (MSC) is the program memory unit of the EFM32GG microcontroller. The flash memory is readable and
writable from both the Cortex-M3 and DMA. The flash memory is divided into two blocks; the main block and the information block.
Program code is normally written to the main block. Additionally, the information block is available for special user data and flash lock
bits. There is also a read-only page in the information block containing system and device calibration data. Read and write operations
are supported in the energy modes EM0 and EM1.

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