ES9039MPRO ES9039PRO v0.2.1

ES9039MPRO & ES9039PRO
32-bit High-Performance 8-Channel DAC

Analog Reinvented Product Datasheet
The ESS Sabre® ES9039MPRO & ES9039PRO are the fully redesigned flagship 32-bit 8 Channel digital-to-analog converters (DAC) that target
high end consumer devices, professional audio applications such as recording systems, mixer consoles and digital audio workstations (DAW), test
equipment, instruments, audio processors applications. It was designed to create the new generation of the world’s highest performing audio DAC.
The ES9039PRO has 8 integrated DACs which use ESS’ patented Hyperstream® IV DAC Architecture. Using the QUAD modulator architecture, it
delivers unprecedented audio sound quality and specifications, including a world class +132dB DNR per channel, +140dB DNR and a THD+N of
-122dB in mono mode.
The ES9039PRO SABRE® DAC improves on previous designs to include:

• MQA Hardware renderer (ES9039MPRO) to reveal the original master resolution
• TDM & SPI support for more options in connectively
• Lower power consumption than previous generations, including the Hyperstream IV DAC modulator
• New Hardware mode for simplified programming.
TDM, DSD, DoP, and I2S, LJ, RJ master/slave interfaces as well as synchronous S/PDIF are supported.
The ES9039PRO has 7 built-in pre-programmed and programmable digital filters which allows the most discerning user to tune the SABRE sound
to their own personal sound signature.
The ES9039MPRO includes a built-in stereo hardware MQA renderer that helps recreate the natural sound of the recording.
FEATURE DESCRIPTION
Patented 32-bit HyperStream® IV Architecture

32-bit audio DAC with ultra high dynamic range & ultra-low distortion
DAC Technology
+140dB DNR mono mode
+132db DNR per channel Unprecedented dynamic range and ultra-low distortion
-122dB THD+N mono
s Stereo MQA Renderer Built-In
MQA Renderer (ES9039MPRO only) Easily paired with software MQA core decoder
Eliminates the need for complicated DAC filter tuning
High Sample Rates Up to PCM 768kHz & native DSD1024
7 presets of digital optimal filters, with custom filter programmability for each channel to
Customizable filter characteristics
allow for a unique sound signature
Multiple Input formats are available I2S, LJ, RJ, TDM, DSD, DoP and S/PDIF
I2C, SPI, and Hardware interface control Configured by microcontroller or other I2C/SPI source, or pins through Hardware Mode
Lower Power Consumption than Previous Gen Simplifies power supply design
Standardized Packaging 10mm x 10mm, 64 pin eTQFP for reduced PCB board space
APPLICATIONS
• Professional digital audio workstations (DAW) Audio Playback
• A/V Receivers
• Personal Audio Devices & Media Streamers
• High End Audiophile Equipment
• Any equipment that requires the very best audio digital to analog conversion
ESS TECHNOLOGY, INC. 109 Bonaventura Drive, San Jose, CA 95134, USA Tel (408) 643-8800 • WWW.ESSTECH.COM 1
CONFIDENTIAL ADVANCE INFORMATION 0.2.1
ES9039MPRO & ES9039PRO Product Brief
Table of Contents
Table of Contents ............................................................................................................................................................................................................. 2
List of Figures ................................................................................................................................................................................................................... 4
List of Tables .................................................................................................................................................................................................................... 4
Functional Block Diagram ................................................................................................................................................................................................. 5
ES9039MSPRO/ES9039SPRO Pinout............................................................................................................................................................................. 6
64 QFP Pin Descriptions .................................................................................................................................................................................................. 7
Feature List ....................................................................................................................................................................................................................... 9
Configuration Modes......................................................................................................................................................................................................... 9
Software Mode ............................................................................................................................................................................................................. 9
I2C ............................................................................................................................................................................................................................ 9
SPI ........................................................................................................................................................................................................................... 9
Hardware Mode .......................................................................................................................................................................................................... 10
Design Information ................................................................................................................................................................................................. 10
Muting .................................................................................................................................................................................................................... 10
Hardware Mode Pin Configurations ....................................................................................................................................................................... 11
Recommended Hardware Mode Setup Sequence ................................................................................................................................................ 13
Hardware Mode Input Datatypes Compatibility ...................................................................................................................................................... 14
Hardware Mode Features ...................................................................................................................................................................................... 14
Digital Features............................................................................................................................................................................................................... 15
Digital Signal Path ...................................................................................................................................................................................................... 15
Note: Channel Mapping is only available with the TDM/I2S & DoP interface. ........................................................................................................... 15
GPIO Configuration .................................................................................................................................................................................................... 15
Audio Input Formats ................................................................................................................................................................................................... 16
Time-division multiplexing (TDM) ........................................................................................................................................................................... 16
I2S (subset of TDM interface) ................................................................................................................................................................................ 16
DSD ....................................................................................................................................................................................................................... 17
Pre-Programmed Digital Filters .................................................................................................................................................................................. 17
PCM Filter Latency ................................................................................................................................................................................................ 18
PCM Filter Properties (44.1kHz Sampling) ............................................................................................................................................................ 19
PCM Filter Frequency Response ........................................................................................................................................................................... 20
PCM Filter Impulse Response ............................................................................................................................................................................... 24
Absolute Maximum Ratings ............................................................................................................................................................................................ 29
IO Electrical Characteristics............................................................................................................................................................................................ 29
Recommended Operating Conditions............................................................................................................................................................................. 30
Power Consumption ................................................................................................................................................................................................... 31
Performance ............................................................................................................................................................................................................... 33
Register Overview .......................................................................................................................................................................................................... 34
I2C Slave Interface (Device Address 0x90, 0x92, 0x94, 0x96) ................................................................................................................................... 34
ES9039MPRO & ES9039PRO Datasheet
Read/Write Register Addresses ............................................................................................................................................................................. 34

Read-only Register Addresses .............................................................................................................................................................................. 34
Multi-Byte Registers ................................................................................................................................................................................................... 34
I2C Slave/Synchronous Slave Interface Timing .......................................................................................................................................................... 35
SPI Slave Interface ..................................................................................................................................................................................................... 36
Register Map .................................................................................................................................................................................................................. 37
Register Listings ............................................................................................................................................................................................................. 40
System Registers ....................................................................................................................................................................................................... 40
GPIO Registers .......................................................................................................................................................................................................... 53
DAC Registers............................................................................................................................................................................................................ 63
Readback Registers ................................................................................................................................................................................................... 81
ES9039MPRO/ES9039PRO Reference Schematic ....................................................................................................................................................... 86
Hardware (HW) mode ................................................................................................................................................................................................ 86
Software Mode ........................................................................................................................................................................................................... 87
Output Stage (for Reference) ..................................................................................................................................................................................... 88
64 eTQFP Package Dimensions .................................................................................................................................................................................... 89
64 QFP Top View Marking .............................................................................................................................................................................................. 90
Reflow Process Considerations ...................................................................................................................................................................................... 91
Temperature Controlled ............................................................................................................................................................................................. 91
Manual........................................................................................................................................................................................................................ 91
RPC-1 Classification reflow profile ............................................................................................................................................................................. 92
RPC-2 Pb-Free Process – Classification Temperatures (Tc)..................................................................................................................................... 93
Ordering Information ....................................................................................................................................................................................................... 94
Revision History .............................................................................................................................................................................................................. 94
3 ESS TECHNOLOGY, INC. 109 Bonaventura Drive, San Jose, CA 95134, USA Tel (408) 643-8800 • WWW.ESSTECH.COM
List of Figures
Figure 1 - ES9039MPRO & ES9039PRO Block Diagram ................................................................................................................................................ 5
Figure 2 – Hardware mode pin configurations ................................................................................................................................................................ 10
Figure 3 – Hardware mode startup sequence ................................................................................................................................................................ 13
Figure 4 – Example of using 8 channels of TDM showing both a 50/50 word select mode and a pulse word select mode ........................................... 16
Figure 5 – I2S & LJ Output Format ................................................................................................................................................................................. 16
Figure 6 – DSD format .................................................................................................................................................................................................... 17
Figure 7 – I2C Slave Control Interface Timing................................................................................................................................................................ 35
Figure 8 – I2C single byte R/W ....................................................................................................................................................................................... 35
Figure 9 – SPI single byte write ...................................................................................................................................................................................... 36
Figure 10 – SPI single byte Read ................................................................................................................................................................................... 36
Figure 11 – SPI multi-byte read ...................................................................................................................................................................................... 36
Figure 12 – HW mode reference schematic ................................................................................................................................................................... 86
Figure 13 – Software mode reference schematic ........................................................................................................................................................... 87
Figure 14 – Software mode reference schematic ........................................................................................................................................................... 88
Figure 15 – ES9039SPRO/ES9039MSPRO 64 eTQFP package dimensions ............................................................................................................... 89
Figure 16 – ES9039SPRO Marking ................................................................................................................................................................................ 90
Figure 17 – ES9039MSPRO Marking ............................................................................................................................................................................. 90
Figure 18 – IR/Convection Reflow Profile (IPC/JEDEC J-STD-020D.1)......................................................................................................................... 91
List of Tables
Table 1 – I2C address configurations ............................................................................................................................................................................... 9
Table 2 – Standard GPIO Functions............................................................................................................................................................................... 15
Table 3 – Absolute Maximum Ratings ............................................................................................................................................................................ 29
Table 4 – IO electrical characteristics ............................................................................................................................................................................. 29
Table 5 – Recommended operating conditions .............................................................................................................................................................. 30
Table 6 – Power consumption with test conditions 1 ...................................................................................................................................................... 31
Table 7 – Power consumption with test conditions 2 ...................................................................................................................................................... 32
Table 8 – Performance data ........................................................................................................................................................................................... 33
Table 9 – I2C slave/synchronous slave interface timing definitions ............................................................................................................................... 35
Table 10 – RPC-1 Classification reflow profile ............................................................................................................................................................... 92
Table 11 – RPC-2 Pb free classification temperatures ................................................................................................................................................... 93
Functional Block Diagram
DVDD VCCA AVDD
MCLK CLOCK
NETWORK
POR (POWER-ON-RESET)
AVDD_L
DIGITAL CORE
Hyperstream® IV DAC1
HiFi Sabre® DAC DAC1B
MISO/ADDR0/HW3 Hyperstream®IV DAC3

SS/ADDR1/HW2 I2C SLAVE
SCLK/SCL/HW1 SPI
MOSI/SDA/HW0
Hardware Hyperstream® IV DAC5
CHIP_EN Interface HiFi Sabre® DAC
MODE DAC5B
RT1
VOLUME CONTROL
DIGITAL FILTERS,
GPIO1
MODULATORS

GPIO2
GPIO3
DIGITAL HiFi Sabre® DAC DAC2B
DATA_CLK AUDIO
DATA1 PORT
(I2S, Hyperstream® IV DAC4
DATA2 DSD,
DATA3 DoP,
DATA4/GPIO4 TDM)
DATA5/GPIO5 S/PDIF
DATA6/GPIO6 DECODER
DATA7/GPIO7 ES9039MPRO
DATA8/GPIO8 (MQA)
AVDD_R
DGND AGND
Figure 1 - ES9039MPRO & ES9039PRO Block Diagram
ES9039MSPRO/ES9039SPRO Pinout
64 QFP Pinout
ES9039MPRO & ES9039PRO

(Top View)
Note: Pin 65 is a package pad, used for AGND, and should be connected to Analog Ground
64 QFP Pin Descriptions

Pin Name Pin Type Reset State Pin Description
1 DVDD Power Power Digital Core Supply, 1.2V
2 DAC1 AO Ground Differential Positive Output for Channel 1
3 DAC1B AO Ground Differential Negative Output for Channel 1
6 AVCC_L Power Power 3.3V DAC analog output stage reference supply for the Left side
7 AGND Ground Ground DAC analog output stage ground
8 CHIP_EN I HiZ Active-high Chip Enable
9 RT1 I HiZ Reserved. Must be connected to DGND for normal operation.
20 DGND Ground Ground Digital Ground
21 MOSI/SDA/HW0 I HiZ Serial communication for SPI/I2C & HW0 interface pin, controlled by MODE
22 SCLK/SCL/HW1 I HiZ Serial Clock for SCLK (SPI), SCL (I2C), also HW1 controlled by MODE pin
23 MODE I HiZ I2C/SPI Control selection or HW mode
24 MCLK I HiZ Oscillator input
25 VCCA Power Power Analog Supply, 3.3V
26 GPIO1 I/O HiZ General I/O w/extended functions
29 DGND Ground Ground Digital Ground
30 DVDD Power Power Digital Supply, 1.2V
32 AVCC_R Power Power 3.3V DAC analog output stage reference supply for the Right side
40 SS/ADDR1/HW2 I HiZ Serial communication for SPI/I2C & HW2 interface pin, controlled by MODE pin
41 MISO/ADDR0/ I HiZ Serial communication for SPI/I2C & HW (MUTE_CTRL) interface pin, controlled
MUTE_CTRL by MODE pin
42 AGND_R Ground Ground DAC analog output stage ground for the Right Side

52 DGND Ground Ground Digital Core Ground
53 DATA8/GPIO8 I/O HiZ Serial DATA8, General I/O 8
58 DATA3 I HiZ Serial DATA3 pin
61 DATA_CLK I HiZ Serial Data Clock pin
62 AVDD Power Power 3.3V I/O Supply
65* Package Pad AGND AGND Must be connected to AGND
* Note: Pin 65 is the package pad and should be connected to AGND, AO = Analog Output, I = Digital Input, I/O = Digital Input/Output, AGND =
Analog Ground, DGND = Digital Ground
Feature List
The ES9039(M)PRO are SABRE 8 channel Flagship performance digital to analog converters (DAC) with features and performance including the
new Hyperstream IV modulator that produces a device that is well suited for all Audiophile and PRO Audio applications.
These features include TDM & SPI support as well as a Hardware (HW) mode for simplifying configuration of the ES9039PRO. The ES9039MPRO
includes a built in MQA renderer.
TDM / I2S / LJ / RJ / DSD / DoP interfaces are supported.
Sample rates up to 768kHz with PCM data and 7 selectable build-in digital filters as well as programmable filters. DSD rates up to DSD1024 are
supported as well.
Configuration Modes
The ES9039PRO/ES9039MPRO have 4 control programming modes. They are controlled by the state of the MODE (pin 23):
MODE PIN Configuration

0 I2C interface
Pull Low HW control mode (see Hardware Mode Table)
Pull High HW control mode (see Hardware Mode Table)
1 SPI interface
Software Mode
To configure the ES9039MPRO & ES9039PRO registers manually over I2C or SPI, connect the following pins:
I2C
o MODE (Pin 23) – GND
o Connect per I2C standard
▪ SDA (Pin 21)
▪ SCL (Pin 22)
▪ ADDR0 (Pin 41)
▪ ADDR1 (Pin 40)
Available I2C Addresses for the ES9039(M)PRO:
I2C Address ADDR1 ADDR0

0x90 GND GND
0x92 GND AVDD
0x94 AVDD GND
0x96 AVDD AVDD
Table 1 – I2C address configurations
SPI
o Mode (Pin 23) – AVDD
o Connect per SPI standard
▪ MOSI (Pin 21)
▪ SCLK (Pin 22)
▪ SS (Pin 40)
▪ MISO (Pin 41)
Hardware Mode
The ES9039MPRO & ES9039PRO has 32 pre-configured modes that can be set with external pin configuration. These modes configure the DAC for
different input serial data rates and set the DAC muting.
These modes are set with pins:
• MODE (Pin 23)
• HW0 (Pin 21)
• HW1 (Pin 22)
• HW2 (Pin 40)
• MUTE_CTRL (Pin 41)
Each hardware mode pin has 4 states:

• 0 – Pin directly connected to GND
• 1 – Pin directly connected to AVDD
• Pull 0 – Pin pulled to GND through 47kΩ resistor
• Pull 1 – Pin pulled to AVDD through 47kΩ resistor
Design Information
Each hardware mode pin can be configured with either a pull-up or pull-down resistor. Therefore, it is important that the pin is configured to allow for
the desired hardware modes. Some guidelines include the following:
• The HW0 and HW1 pins never require a pull up or pull-down resistor.
Pull-up Pull-down
AVDD or GPIO
47k
HW2/ HW2/
MODE MODE
47k
GND or GPIO
Figure 2 – Hardware mode pin configurations
Muting
MUTE_CTRL (Pin 41) is used to control the muting of the output and enabling of the Automute feature while in Hardware Mode:
• 0 – Output Muted, No Automute
• 1 – Output Unmuted, No Automute
• Pull 0 – Output Muted, Automute Enabled
• Pull 1 – Output Unmuted, Automute Enabled
Hardware Mode Pin Configurations
BCK/
HW HW
HW FS (kHz) BCK (MHz) MCLK (MHz) Channe MODE HW2
1 0
Mode l
I2S Master Mode
0 MCLK / 128 MCLK / 2 5 < MCLK < 50 32 Pull 0 0 0 0
LJ Master Mode
4 MCLK / 128 MCLK / 2 5 < MCLK < 50 32 Pull 0 Pull 0 0 0
I2S Slave SYNC, Auto Detect FS & BCK, MCLK/1
8 Auto (8 < FS < 384) 64FS 128FS < MCLK < 50 32 Pull 0 Pull 1 0 0
I2S Slave SYNC, Auto Clock Gear (128FS), Auto Detect FS & BCK
LJ Slave SYNC, Auto Detect FS & BCK, MCLK/1
12 Auto (8 < FS < 384) 64FS 128FS < MCLK < 50 32 Pull 0 1 0 0
LJ Slave SYNC, Auto Clock Gear (128FS) , Auto Detect FS & BCK
S/PDIF, DoP, or I2S Slave ASYNC, Auto Detect, MCLK/1
16** Auto (8 < FS < 384) 64FS 130FS < MCLK < 50 32 Pull 1 0 0 0
I2S Slave ASYNC, Auto Clock Gear (>130FS), Auto Detect
LJ Slave ASYNC, Auto Detect, MCLK/1

LJ Slave ASYNC, Auto Clock Gear, Auto Detect
DSD Slave, SYNC, Auto Detect
24 64FS 64FS 128FS < MCLK < 50 -- Pull 1 Pull 1 0 0
DSD Slave, SYNC, Auto Clock Gear, Auto Detect
DSD Slave, ASYNC, Auto FS
DSD Slave, ASYNC, Auto Clock Gear, Auto FS
TDM MSB Justified, Slave, SYNC, Auto Detect
Auto
28* Auto (8 < FS < 192) (256FS,512FS, 128FS < MCLK < 50 32 Pull 1 1 0 0
1024FS)
Auto
29* Auto (8 < FS < 96) (512FS, 128FS < MCLK < 50 32 Pull 1 1 0 1
1024FS)
Auto
30* Auto (8 < FS < 48) 128FS < MCLK < 50 32 Pull 1 1 1 0
(1024FS)
Auto
31* Auto (8 < FS < 48) 128FS < MCLK < 50 32 Pull 1 1 1 1
(1024FS)
*Note 1: Mode 28 = Channel Slots 1 to 8, Mode 29 = Channel Slots 9 to 16, Mode 30 = Channel slots 17 to 24, Mode 31 = Channel slots 25 to 32.
** Note 2 If DoP is required, HW modes 16-18 must be used
Recommended Hardware Mode Setup Sequence

The hardware mode setup sequence is shown below with all hardware pins being defined after CHIP_EN is asserted.
Note: It is recommended that MUTE_CTRL is set low until the HW mode is finalized, then asserted last.
CHIP_EN
1ms
HW0
HW1
HW2
1ms
MUTE_CTRL
OUT
Figure 3 – Hardware mode startup sequence
Hardware Mode Audio Input Format Compatibility
Input Datatype
Hardware Modes I2S LJ RJ TDM DOP DSD S/PDIF
Equivalent
Software Mode ✓ ✓ ✓ ✓ ✓ ✓ ✓
HW 0-3 ✓
HW 4-7 ✓
HW 8-11 ✓
HW 12-15 ✓
HW 16-18 ✓ ✓1 ✓2
HW 19 ✓
HW 20-23 ✓
HW 24-27 ✓
HW 28-31 ✓
Note 1. For hardware modes 16-18, DoP is enabled by pulling DATA8/GPIO8 high
Note 2. For hardware modes 16-18, SPDIF stream is input through DATA7/GPIO7
Hardware Mode Features
Input HW Mode Features

Hardware SYNC ASYNC
Modes AUTO_FS_DETECT AUTO_CH_NUM AUTO_INPUT_SEL mode mode
Equivalent
Software Mode Reg 3[7] Reg 57[7] Reg57[0] Reg1[6] Reg1[6]
HW 0-15 ✓ ✓
HW 16-18 ✓ ✓
HW 19-23 ✓
HW 24-25 ✓ ✓
HW 26-27 ✓
HW 28-31 ✓ ✓ ✓
Digital Features
Digital Signal Path
SABRE DAC DIGITAL PATH
DSD DSD FIR
Volume
Automute 16x IIR Noise Shaped
Control 8x Oversampling Filter SRC
TDM/I2S/ CH Filter Modulators
DoP MAPPING
2x OSF 4x OSF Bypass
Bypass Bypass
S/PDIF
Note: Channel Mapping is only available with the TDM/I2S & DoP interface.
GPIO Configuration
GPIO_CONFIG Function I/O Direction
0 Analog Shutdown* N/A
1 1’b0 Output
2 1’b1 Output
3 CLK_IDAC Output
4 Interrupt Output
5 Mute all channel Input
6 Input Selection Input
7 Lock_status Output
8 CLK_VALID flag Output
9 PWM1 Output
10 PWM2 Output
11 PWM3 Output
12 Volume min Output
13 Automute status Output
14 Soft Ramp finished Output
15 MQA_Auth_True** Output
Table 2 – Standard GPIO Functions
For GPIO_CONFIG 0:
*Analog Shutdown is input disabled, output is tri-stated
For GPIO_CONFIG 15:
**MQA_Auth_True is for ES9039MPRO only. Determines if the incoming stream is an MQA stream or not.
GPIOx Default states:
GPIO1: Automute Status
GPIO3-8: Analog Shutdown
GPIO2: Lock Status
Audio Input Formats

For configuring TDM, I2S, DSD, use Registers 57-71
Time-division multiplexing (TDM)

The ES9039(M)PRO supports up to 32 channel TDM modes. Application Note regarding setup for TDM will be available soon.
Figure 4 – Example of using 8 channels of TDM showing both a 50/50 word select mode and a pulse word select mode
PCM (subset of TDM interface)

Data is latched on the positive edge of BCK
Figure 5 – I2S & LJ Output Format
DSD
Data is latched on the positive edge of DCLK.
DCLK
DSD1 D1D2D3D4 .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
1bit DSD2 D1D2D3D4 .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
DSD FORMAT
Figure 6 – DSD format
Note: There is no internal DSD channel mapping, DSD data must be physically connected to each pin DATA1-DATA8.
Pre-Programmed Digital Filters

The ES9039MPRO & ES9039PRO has 7 pre-programmed digital filters. The latency for each filter reduces (scales) with increasing sample rates.
(See Register 88[2:0])
• Minimum Phase (default)
• Linear Phase Apodizing
• Linear Phase Fast Roll-off
• Linear Phase Slow Roll-off
• Minimum Phase Fast Roll-off
• Minimum Phase Slow Roll-off
• Minimum Phase Slow Roll-off Low Dispersion
PCM Filter Latency
The following table shows the simulated latency of each filter at 48kHz sampling rate. Latency delay will reduce (scale) with sampling rate.
Delay(us) @
Digital Filter
fs=48kHz
Minimum phase (default) 158us
Linear Phase Apodizing 760us
Linear Phase Fast Roll-Off 771us
Linear Phase Slow Roll-Off 208us
Minimum Phase fast roll-off 158us
Minimum Phase slow roll-off 137us
Minimum Phase Slow roll-off low dispersion 282us
PCM Filter Properties (44.1kHz Sampling)
Minimum Phase
Parameter Conditions MIN TYP MAX UNIT
Pass band –3dB 0.49 x fs Hz
Stop band -97dB 0.64 x fs Hz
Group Delay 3.29/fs 9.37/fs s
Flatness (ripple) 0.0004 dB
Linear Phase Apodizing

Group Delay 33.2/fs s
Linear Phase Fast Roll-off

Linear Phase Slow Roll-off

Minimum Phase Fast Roll-off

Minimum Phase Slow Roll-off

Group Delay 2.5/fs 3/fs s
Minimum Phase Slow Roll-off Low Dispersion

PCM Filter Frequency Response

The following frequency responses were obtained from software simulations of these filters. Simulation sample rate is 44.1kHz.
Filter Frequency Response
Minimum Phase

Low Ripple
Linear Phase Slow Roll-off
Minimum Phase Fast Roll-off

Low Dispersion
PCM Filter Impulse Response

The following impulse responses were obtained from software simulations of these filters. Simulation sample rate is 44.1kHz.
Filter Impulse Response
Minimum Phase

Low Ripple
Linear Phase slow roll-off
Minimum phase fast roll-off
Minimum phase slow roll-off
Minimum phase slow roll-off

low dispersion
Absolute Maximum Ratings

PARAMETER RATING
Positive Supply Voltage
• AVCC_L • +3.7V with respect to Ground
• AVCC_R • +3.7V with respect to Ground
• AVDD • +3.7V with respect to Ground
• VCCA • +3.7V with respect to Ground
• DVDD • +1.4V with respect to Ground
Storage temperature –65C to +150C

Operating Junction Temperature +125C
Voltage range for digital input pins –0.3V to AVDD(nom)+0.3V
ESD Protection
Human Body Model (HBM) TBD
Charge Device Model (CDM) TBD
Table 3 – Absolute Maximum Ratings
WARNING: Stresses beyond those listed under here may cause permanent damage to the device. These are stress ratings only and functional operation
of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied.
WARNING: Electrostatic Discharge (ESD) can damage this device. Proper procedures must be followed to avoid ESD when handling this device.
IO Electrical Characteristics
PARAMETER SYMBOL MINIMUM MAXIMUM UNIT COMMENTS
High-level input voltage VIH (AVDD / 2) + 0.4 V
Low-level input voltage VIL 0.4 V
High-level output voltage VOH AVDD – 0.2 V
Low-level output voltage VOL 0.2 V

Table 4 – IO electrical characteristics
Recommended Operating Conditions

There are the recommended operating conditions for the ES9039MPRO/ES9039PRO
PARAMETER SYMBOL CONDITIONS
Operating temperature TA –20C to +85C
AVCC_L 3.3V
AVCC_R 3.3V
AVDD 3.3V
VCCA 3.3V
DVDD 1.2V
Table 5 – Recommended operating conditions
Power Consumption
Power numbers are given when the device is in slave mode.
Test Condition 0 Standby
Standby (CHIP_EN = 0)
AVCC <60 uA
AVDD 3 uA
VCCA 1 uA
DVDD 1.4 mA
Test Conditions 1 (unless otherwise noted)

TA = 25oC, AVCC_R = AVCC_L = VCCA = AVDD = +3.3V, DVDD= +1.2V, fs = 48kHz, DAC enabled, 1kHz sine full scale
Parameter Min Typ Max Unit
Hardware Mode: 3 (MCLK = 49.152MHz) Master Mode 1024*fs

AVCC_R 57.0 mA
AVCC_L 57.0 mA
VCCA 1.1 mA
AVDD 2.4 mA
DVDD 69.4 mA
Hardware Mode: 2 (MCLK = 24.576MHz)
AVCC_R 50.5 mA
AVCC_L 50.5 mA
VCCA 0.6 mA
AVDD 2.4 mA
DVDD 36.0 mA
Hardware Mode: 18 (MCLK = 50MHz)
AVCC_R 45.3 mA
AVCC_L 45.3 mA
VCCA 0.42 mA
AVDD 0.4 mA
DVDD 41.6 mA
Table 6 – Power consumption with test conditions 1

TA = 25oC, AVCC_R = AVCC_L = VCCA = AVDD = +3.3V, DVDD= +1.2V, fs = 48kHz, DAC enabled, streaming zeros

AVCC_R 13.7 mA
AVCC_L 13.7 mA
VCCA 1.0 mA
AVDD 2.3 mA
DVDD 42.3 mA
AVCC_R 7.6 mA
AVCC_L 7.6 mA
VCCA 0.6 mA
AVDD 2.4 mA
DVDD 17.1 mA
Hardware Mode: 18 (MCLK = 50MHz)
AVCC_R 4.0 mA
AVCC_L 4.0 mA
VCCA 0.5 mA
AVDD 0.4 mA
DVDD 29.3 mA
Table 7 – Power consumption with test conditions 2
Performance
TA = 25oC, AVCC_R = AVCC_L = VCCA = AVDD = +3.3V, DVDD= +1.2V, fs = 48kHz, HW mode 3
Resolution 32 Bit
Max MCLK frequency 50 MHz
THD+N Ratio
@ fs=48kHz, BW=20Hz-20kHz
-120 dB
(differential)
8 Channel
THD+N Ratio
@ fs=48kHz, BW=20Hz-20kHz
-122 dB
(differential)
Mono
DNR (A-weighted)
132 dB
8 Channel mode – Single channel diff
DNR (A-weighted)
-60dBFS 137 dB
(Stereo mode – 4 channel sum diff)
DNR (A-weighted)
140 dB
(Mono mode – 8 channel sum diff)
Voltage output amplitude Full-scale out 0.889 x AVCC Vpp
Voltage output offset Bipolar zero out AVCC/2 V
1000 x 0.889 x
Current output amplitude Full-scale out mApp
AVCC / Rdac
1000 x (AVCC/2 –
Current output offsets Bipolar zero out mA
Vg) / Rdac
Output impedance
(Per + or – pin of each differential DAC output pair)
Rdac 195±15% Ω
Table 8 – Performance data
Register Overview
I2C Slave Interface (Device Address 0x90, 0x92, 0x94, 0x96)
This interface contains Read/Write and Read-only registers. A system clock must be present.
Multi-byte registers must be written from LSB to MSB. Data is latched when MSB is written.
Multi-byte registers must be read from LSB to MSB. Data is latched when LSB is read.
MSB is always stored in the highest register address.
Read/Write Register Addresses

Registers 0-130 (0x00 – 0x82) are read/write registers
Read-only Register Addresses

Registers 224 – 249 (0xE0 – 0xF9) are read only registers.
Multi-Byte Registers
Multi-byte registers must be written from LSB to MSB. Data is latched when MSB is written.
MSB is always stored in the highest register address.
I2C Slave/Synchronous Slave Interface Timing
Start Start Stop Start

Figure 7 – I2C Slave Control Interface Timing
Parameter Symbol CLK Standard-Mode Fast-Mode Unit

Constraint
MIN MAX MIN MAX
lock Frequency fSCL < k z
condition hold time tHD;STA . - . - s
period of tLOW > . - . - s
period of (> ) tHIGH > . - . - s
condition setup time (repeat) tSU;STA . - . - s
hold time from falling
- ll except read tHD;DAT - - s
s
- read only
setup time from rising tSU;DAT - - ns

ise time of and tr - ns
Fall time of and tf - ns
condition setup time tSU;STO - . - s
us free time between transmissions tBUF . - . - s
apacitive load for each bus line b - - pF
Table 9 – I2C slave/synchronous slave interface timing definitions
Single Byte R/W

SDA S AC K/
A6 A5 A4 A3 A2 A1 A0 R/W ACK D7 D6 D5 D4 D3 D2 D1 D0
NA CK
SP
SCL
0 8 16
Figure 8 – I2C single byte R/W
SPI Slave Interface

The SPI slave interface is used when the MODE pin (pin 23) is pulled high.
• The SPI Slave interface can be accessed using the Pins 21,16,30,31
• Pin 21 MOSI
• Pin 22 SCLK
• Pin 40 SS
• Pin 41 MISO
The 4-wire SPI data format is: Command (1 byte) + Address (1 byte) + Data
Single byte Write

SS
SCLK
0 8 16
MISO Hig h Z
MOSI C7 C6 C5 C4 C3 C2 C1 C0 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
Figure 9 – SPI single byte write
Single byte Read

SS
SCLK
0 8 16
MISO Hig h Z D7 D6 D5 D4 D3 D2 D1 D0
MOSI C7 C6 C5 C4 C3 C2 C1 C0 A7 A6 A5 A4 A3 A2 A1 A0
Figure 10 – SPI single byte Read
Multi-byte Read
SS
SCLK
0 8 16 24
MISO High Z D7
Byte 1
D6 D5 D4 D3 D2 D1 D0 D7
Byte 2
D6 D5 D4 D3 D2 D1 D0
MOSI C7 C6 C5 C4 C3 C2 C1 C0 A7 A6 A5 A4 A3 A2 A1 A0
Figure 11 – SPI multi-byte read
Register Map
Addr Addr
Register 7 6 5 4 3 2 1 0
(Hex) (Dec)
ENABLE_ DAC_
0x00 0 SYSTEM CONFIG SOFT_RESET CH78_SEL CH56_SEL CH34_SEL RESERVED
2X_MODE MODE_REG
ENABLE_SPDIF ENABLE_DOP_ ENABLE_DSD_ ENABLE_TDM_
0x01 1 SYS MODE CONFIG ENABLE_DAC SYNC_MODE RESERVED
_DECODE DECODE DECODE DECODE
0x02 2 RESERVED RESERVED
AUTO_ SELECT_
0x03 3 DAC CLOCK CONFIG SELECT_IDAC_NUM
FS_DETECT IDAC_HALF
0x04 4 CLOCK CONFIG MASTER_BCK_DIV
AUTO_
0x05 5 CLK GEAR SELECT RESERVED SEL_CLK_GEAR RESERVED RESERVED
CLK_GEAR
0x06 - 6-
RESERVED RESERVED
0x09 9
VOL_MIN_CH8_ VOL_MIN_CH7_ VOL_MIN_CH6_ VOL_MIN_CH5_ VOL_MIN_CH4_ VOL_MIN_CH3_ VOL_MIN_CH2_ VOL_MIN_CH1_
0x0A 10 INTERUPT VOL MIN MASK P
MASKP MASKP MASKP MASKP MASKP MASKP MASKP MASKP
AUTOMUTE_ AUTOMUTE_ AUTOMUTE_ AUTOMUTE_ AUTOMUTE_ AUTOMUTE_ AUTOMUTE_ AUTOMUTE_
0x0B 11 INTERRUPT AUTOMUTE MASKP FLAG_CH8_ FLAG_CH7_ FLAG_CH6_ FLAG_CH5_ FLAG_CH4_ FLAG_CH3_ FLAG_CH2_ FLAG_CH1_
SS_FULL_ SS_FULL_ SS_FULL_ SS_FULL_ SS_FULL_ SS_FULL_ SS_FULL_ SS_FULL_
0x0C 12 SS FULL RAMP MASKP RAMP_CH8_ RAMP_CH7_ RAMP_CH6_ RAMP_CH5_ RAMP_CH4_ RAMP_CH3_ RAMP_CH2_ RAMP_CH1_
TDM_VALID_ BCK_WS_ DOP_VALID_
0x0D 13 INTERRUPT MASKP INPUT_SELECT_OVERRIDE_MASKP RESERVED
EDGE_MASKP FAIL_MASKP MASKP
0x0E 14 INTERRUPT MASKP RESERVED
0x0F 15 INTERUPT VOL MIN MASKN
MASKN MASKN MASKN MASKN MASKN MASKN MASKN MASKN
0x10 16 INTERRUPT AUTOMUTE MASKN FLAG_CH8_ FLAG_CH7_ FLAG_CH6_ FLAG_CH5_ FLAG_CH4_ FLAG_CH3_ FLAG_CH2_ FLAG_CH1_
0x11 17 INTERRUPT SS FULL RAMP MASKN RAMP_CH8_ RAMP_CH7_ RAMP_CH6_ RAMP_CH5_ RAMP_CH4_ RAMP_CH3_ RAMP_CH2_ RAMP_CH1_
0x12 18 INTERRUPT MASKN INPUT_SELECT_OVERRIDE_MASKN RESERVED
EDGE_MASKN FAIL_MASKN MASKN
0x13 19 INTERRUPT MASKN RESERVED
0x14 20 INTERRUPT VOL MIN CLEAR
CLEAR CLEAR CLEAR CLEAR CLEAR CLEAR CLEAR CLEAR
0x15 21 INTERRUPT AUTOMUTE CLEAR FLAG_CH8_ FLAG_CH7_ FLAG_CH6_ FLAG_CH5_ FLAG_CH4_ FLAG_CH3_ FLAG_CH2_ FLAG_CH1_
0x16 22 INTERRUPT SS FULL RAMP CLEAR RAMP_CH8_ RAMP_CH7_ RAMP_CH6_ RAMP_CH5_ RAMP_CH4_ RAMP_CH3_ RAMP_CH2_ RAMP_CH1_
0x17 23 INTERRUPT CLEAR INPUT_SELECT_OVERRIDE_CLEAR RESERVED
EDGE_CLEAR FAIL_CLEAR CLEAR
0x18 24 INTERRUPT CLEAR RESERVED
0x1A 26 DPLL BW RESERVED
0x1B 27 DPLL BW RESERVED
0x1C 28 DPLL BW RESERVED
0x1D 29 DPLL BW DPLL_BW RESERVED
0x1E - 30 -
RESERVED RESERVED
0x24 36
0x25 37 GPIO1/2 CONFIG GPIO2_CFG GPIO1_CFG
0x29 41 GPIO OUTPUT ENABLE GPIO8_OE GPIO7_OE GPIO6_OE GPIO5_OE GPIO4_OE GPIO3_OE GPIO2_OE GPIO1_OE
0x2A 42 GPIO INPUT GPIO8_SDB GPIO7_SDB GPIO6_SDB GPIO5_SDB GPIO4_SDB GPIO3_SDB GPIO2_SDB GPIO1_SDB
0x2B 43 GPIO WK EN GPIO8_WK_EN GPIO7_WK_EN GPIO6_WK_EN GPIO5_WK_EN GPIO4_WK_EN GPIO3_WK_EN GPIO2_WK_EN GPIO1_WK_EN
0x2C 44 INVERT GPIO INVERT_GPIO8 INVERT_GPIO7 INVERT_GPIO6 INVERT_GPIO5 INVERT_GPIO4 INVERT_GPIO3 INVERT_GPIO2 INVERT_GPIO1
0x2D 45 GPIO READ GPIO8_READ GPIO7_READ GPIO6_READ GPIO5_READ GPIO4_READ GPIO3_READ GPIO2_READ GPIO1_READ
GPIO_OR_ GPIO_OR_ GPIO_OR_ GPIO_AND_ GPIO_AND_ GPIO_AND_
0x2E 46 GPIO OUTPUT LOGIC GPIO_SEL
SS_RAMP VOL_MIN AUTOMUTE SS_RAMP VOL_MIN AUTOMUTE
GPIO_
0x2F 47 GPIO OUTPUT LOGIC RESERVED GPIO_SEL
DAC_MODE
0x30 48 PWM1 COUNT PWM1_COUNT
0x31 49 PWM1 FREQUENCY PWM1_FREQ
ENABLE_
AUTO_ DSD_MASTER_ PCM_MASTER_ AUTO_
0x39 57 INPUT SELECTION DSD_FAULT_ RESERVED INPUT_SEL
CH_DETECT MODE MODE INPUT_SEL
DETECTION
MASTER_WS_ MASTER_ MASTER_
0x3A 58 SERIAL MASTER ENCODER CONFIG TDM_RESYNC BCK_INV RESERVED MASTER_FRAME_LENGTH
PULSE_MODE WS_INVERT BCK_INVERT
0x3B 59 TDM CONFIG RESERVED TDM_CH_NUM
TDM_VALID_ED
0x3C 60 TDM CONFIG1 TDM_LJ_MODE RESERVED
GE
0x3D 61 TDM CONFIG2 RESERVED TDM_BIT_WIDTH TDM_DATA_LATCH_ADJ
DISABLE_ DISABLE_ ENABLE_WS_ ENABLE_BCK_ DISABLE_

0x3E 62 BCK/WS MONITOR CONFIG RESERVED
DSD_DC DSD_MUTE MONITOR MONITOR PCM_DC
0x3F 63 RESERVED RESERVED
0x40 64 TDM CH1 CONFIG RESERVED TDM_CH1_LINE_SEL TDM_CH1_SLOT_SEL
0x48 - 72 -
RESERVED RESERVED
0x49 73
0x4A 74 VOLUME1 VOLUME1
0x4B 75 VOLUME2 VOLUME2
0x4C 76 VOLUME3 VOLUME3
0x4D 77 VOLUME4 VOLUME4
0x4E 78 VOLUME5 VOLUME5
0x4F 79 VOLUME6 VOLUME6
0x50 80 VOLUME7 VOLUME7
0x51 81 VOLUME8 VOLUME8
0x52 82 DAC VOL UP RATE DAC_VOL_RATE_UP
0x53 83 DAC VOL DOWN RATE DAC_VOL_RATE_DOWN
0x54 84 DAC VOL DOWN RATE FAST DAC_VOL_RATE_FAST
DAC_MUTE_ DAC_MUTE_ DAC_MUTE_ DAC_MUTE_ DAC_MUTE_ DAC_MUTE_ DAC_MUTE_ DAC_MUTE_
0x56 86 DAC MUTE
CH8 CH7 CH6 CH5 CH4 CH3 CH2 CH1
DAC_INVERT_ DAC_INVERT_ DAC_INVERT_ DAC_INVERT_ DAC_INVERT_ DAC_INVERT_ DAC_INVERT_ DAC_INVERT_
0x57 87 DAC INVERT
0x58 88 FILTER SHAPE RESERVED FILTER_SHAPE
0x59 89 S/PDIF PIN SELECT SPDIF_SEL VOLUME_HOLD IIR_BW
0x5A 90 DAC PATH CONFIG RESERVED BYPASS_IIR BYPASS_FIR4X BYPASS_FIR2X
0x5B 91 THD_C2_L THD_C2_0
0x5C 92 THD_C2_L THD_C2_0
0x5D 93 THD_C2_L THD_C2_1
0x5E 94 THD_C2_L THD_C2_1
0x5F 95 THD_C2_L THD_C2_2
0x60 96 THD_C2_L THD_C2_2
0x63 99 THD_C2_H THD_C2_4
0x64 100 THD_C2_H THD_C2_4
0x65 101 THD_C2_H THD_C2_5
0x66 102 THD_C2_H THD_C2_5
0x67 103 THD_C2_H THD_C2_6
0x68 104 THD_C2_H THD_C2_6
0x69 105 THD_C2_H THD_C2_7
0x6A 106 THD_C2_H THD_C2_7
0x6B 107 THD_C3_L THD_C3_0
0x6C 108 THD_C3_L THD_C3_0
0x6D 109 THD_C3_L THD_C3_1
0x6E 110 THD_C3_L THD_C3_1
0x6F 111 THD_C3_L THD_C3_2
0x70 112 THD_C3_L THD_C3_2
0x71 113 THD_C3_L THD_C3_3
0x72 114 THD_C3_L THD_C3_3
0x73 115 THD_C3_H THD_C3_4
0x74 116 THD_C3_H THD_C3_4
0x75 117 THD_C3_H THD_C3_5
0x76 118 THD_C3_H THD_C3_5
0x77 119 THD_C3_H THD_C3_6
0x78 120 THD_C3_H THD_C3_6
0x79 121 THD_C3_H THD_C3_7
0x7A 122 THD_C3_H THD_C3_7
0x7B 123 AUTOMUTE ENABLE
EN_CH8 EN_CH7 EN_CH6 EN_CH5 EN_CH4 EN_CH3 EN_CH2 EN_CH1
0x7C 124 AUTOMUTE TIME AUTOMUTE_TIME
AUTOMUTE_
0x7D 125 AUTOMUTE TIME RESERVED RAMP_TO_ AUTOMUTE_TIME
GROUND
0x7E 126 AUTOMUTE LEVEL AUTOMUTE_LEVEL
0x7F 127 AUTOMUTE LEVEL AUTOMUTE_LEVEL
0x80 128 AUTOMUTE OFF LEVEL AUTOMUTE_OFF_LEVEL
0x81 129 AUTOMUTE OFF LEVEL AUTOMUTE_OFF_LEVEL
0x82 130 SOFT RAMP CONFIG RESERVED SOFT_RAMP_TIME
0x83 - 131 -
RESERVED RESERVED
0x86 134
PROG_ PROG_
0x87 135 PROGRAM RAM CONTROL RESERVED
|COEFF_WE COEFF_EN
PROG_COEFF_
0x89 137 PROGRAM RAM ADDRESS PROG_COEFF_ADDR
STAGE
0x8A 138 PROGRAM RAM DATA PROG_COEFF_IN
0x8B 139 PROGRAM RAM DATA PROG_COEFF_IN
0x8C 140 PROGRAM RAM DATA PROG_COEFF_IN
MQA_
0x8D 141 MQA CONFIG (ES9039MPRO only) RESERVED MQB_READER_ENABLE RENDERING_
ENABLE
0x8E - 142 -
RESERVED RESERVED
0x91 145
0xE0 224 SYS READ RESERVED MODES ADDR1 ADDR0
0xE1 225 CHIP ID READ CHIP_ID
0xE2 - 226 -
RESERVED RESERVED
0xE4 228
0xE5 229 INTERRUPT STATE VOL_MIN_STATE
0xE6 230 INTERRUPT STATE AUTOMUTE_STATE
0xE7 231 INTERRUPT STATE SS_FULL_RAMP_STATE
TDM_
BCK_WS_FAIL_ DOP_VALID_
0xE8 232 INTERRUPT STATE INPUT_SELECT_OVERRIDE_STATE DATA_VALID_ RESERVED
STATE STATE
STATE
0xE9 233 INTERRUPT STATE RESERVED
0xEA 234 INTERRUPT SOURCE VOL_MIN_SOURCE
0xEB 235 INTERRUPT SOURCE AUTOMUTE_SOURCE
0xEC 236 INTERRUPT SOURCE SS_FULL_RAMP_SOURCE
TDM_
INPUT_SELECT_ BCK_WS_FAIL_ DOP_VALID_
0xED 237 INTERRUPT SOURCE DATA_VALID_ RESERVED
OVERRIDE_SOURCE SOURCE SOURCE
SOURCE
0xEE 238 INTERRUPT SOURCE RESERVED
0xEF 239 RATIO VALID READ RATIO_VALID RESERVED
0xF0 240 GPIO READ GPIO8_I_READ GPIO7_I_READ GPIO6_I_READ GPIO5_I_READ GPIO4_I_READ GPIO3_I_READ GPIO2_I_READ GPIO1_I_READ
0xF1 241 VOL MIN READ VOL_MIN_CH8 VOL_MIN_CH7 VOL_MIN_CH6 VOL_MIN_CH5 VOL_MIN_CH4 VOL_MIN_CH3 VOL_MIN_CH2 VOL_MIN_CH1
0xF2 242 AUTOMUTE READ
SS_RAMP_ SS_RAMP_ SS_RAMP_ SS_RAMP_ SS_RAMP_ SS_RAMP_ SS_RAMP_ SS_RAMP_
0xF3 243 SOFT RAMP UP READ
UP_CH8 UP_CH7 UP_CH6 UP_CH5 UP_CH4 UP_CH3 UP_CH2 UP_CH1
SS_RAMP_ SS_RAMP_ SS_RAMP_ SS_RAMP_ SS_RAMP_ SS_RAMP_ SS_RAMP_DO SS_RAMP_
0xF4 244 SOFT RAMP DOWN READ
DOWN_CH8 DOWN_CH7 DOWN_CH6 DOWN_CH5 DOWN_CH4 DOWN_CH3 WN_CH2 DOWN_CH1
SPDIF, TDM, DOP, AND INPUT TDM_
0xF5 245 SPDIF_VALID DOP_VALID INPUT_SELECT_OVERRIDE
READBACK DATA_VALID
0xF6 246 PROG COEFF OUT READ PROG_COEFF_OUT
0xF9 - 249 -
RESERVED RESERVED
0xFB 251
Register Listings
Some reserved registers values might be asserted in default mode. This is normal and does not need to be changed.
System Registers
Register 0: SYSTEM CONFIG
Bits [7] [6] [5:4] [3] [2] [1] [0]
Default 1'b0 1'b0 2'b00 1'b0 1'b0 1'b0 1'b0
Bits Mnemonic Description

[7] SOFT_RESET Performs soft reset to digital core.
• 1'b0: Normal operation
• 1'b1: Reset digital core (all settings are set to default)
[6] ENABLE_64FS_MODE Enables 64FS mode to run the DAC interpolation path at 64FS.
• 1'b0: 64FS mode disabled (default)
• 1'b1: 64FS mode enabled
Note: This mode should be used for high sample rate (i.e., 705.6/768kHz)
[5:4] CH78_SEL Selects ch7/8 nsmod input.
• 2'b00: Input from ch7/8 interpolation path (default)
• 2'b01: Input from ch5/6 interpolation path
• 2'b11: Reserved
[3] CH56_SEL Selects ch5/6 nsmod input.
[2] CH34_SEL Selects ch3/4 nsmod input.
[1] DAC_MODE_REG Enables DAC data path
• 1'b0: DAC disabled
• 1'b1: DAC enabled
[0] RESERVED NA
Register 1: SYS MODE CONFIG

Bits [7] [6] [5:4] [3] [2] [1] [0]
Default 1'b1 1'b0 2'b11 1'b0 1'b0 1'b0 1'b1

[7] ENABLE_DAC_CLK Enables DAC interpolation path clock.
• 1'b0: Clock disabled
• 1'b1: Clock enabled (default)
[6] SYNC_MODE Enables SYNC mode
• 1'b0: ASYNC mode enabled (default)
• 1'b1: SYNC mode enabled
[5:4] RESERVED NA
[3] ENABLE_SPDIF_DECODE Enables S/PDIF decoding.
• 1'b0: Disabled (default)
• 1'b1: Enabled
[2] ENABLE_DOP_DECODE Enables DoP decoding.
• 1'b1: Enabled
[1] ENABLE_DSD_DECODE Enables DSD decoding.
• 1'b1: Enabled
[0] ENABLE_TDM_DECODE Enables TDM decoding.
• 1'b1: Enabled
Register 2: RESERVED
Register 3: DAC CLOCK CONFIG

Bits [7] [6] [5:0]
Default 1'b1 1'b0 6'd0

[7] AUTO_FS_DETECT • 1'b0: Disabled
• 1'b1: Auto tune CLK_DAC/CLK_IDAC ratio according to detected FS
(default)
Note: Cannot be used in ASYNC mode
[6] SELECT_IDAC_HALF • 1'b0: Divide by SELECT_IDAC_NUM + 1 (default)
• 1'b1: Divide by half of SELECT_IDAC_NUM + 1
Note: Can only produce half of an odd number divide
[5:0] SELECT_IDAC_NUM CLK_IDAC divider. Whole number divide value + 1 for CLK_IDAC
(SYS_CLK/divide_value).
• 6'd0: Whole number divide value + 1 = 1
Register 4: CLOCK CONFIG

Bits [7:0]
Default 8'd7

[7:0] MASTER_BCK_DIV Master mode clock divider. Whole number divide value + 1 for CLK_Master
(SYS_CLK/divide_value).
Register 5: CLK GEAR SELECT

Bits [7:6] [5:4] [3] [2] [1:0]
Default 2'b00 2'd0 1'b0 1'b0 2'b00

[7:6] RESERVED NA
[5:4] SEL_CLK_GEAR Clock Gearing
• 2'd0: SYS_CLK/1
• 2'd1: SYS_CLK/2
• 2'd2: SYS_CLK/4
• 2'd3: SYS_CLK/8
[3] RESERVED NA
[2] AUTO_CLK_GEAR • 1'b0: Disable automatic clock gearing. SYS_CLK = SEL_CLK_GEAR
• 1'b1: Enable automatic clock gearing. SYS_CLK will increase up to
SEL_CLK_GEAR
[1:0] RESERVED NA
Register 9-7: RESERVED
Register 10: INTERUPT VOL MIN MASK P

Bits [7] [6] [5] [4] [3] [2] [1] [0]
Default 1'b0 1'b0 1'b0 1'b0 1'b0 1'b0 1'b0 1'b0

[7] VOL_MIN_CH8_MASKP Masks negative to positive interrupt toggling.
• 1'b0: Ignore interrupt if toggled from negative to positive
• 1'b1: Service interrupt if toggled from negative to positive
Register 11: INTERRUPT AUTOMUTE MASKP

Bits [7] [6] [5] [4] [3] [2] [1] [0]

[7] AUTOMUTE_FLAG_CH8_MASKP Masks negative to positive interrupt toggling.
Register 12: SS FULL RAMP MASKP

Bits [7] [6] [5] [4] [3] [2] [1] [0]

[7] SS_FULL_RAMP_CH8_MASKP Masks negative to positive interrupt toggling.
Register 14-13: INTERRUPT MASKP

Bits [15:8] [7:6] [5] [4:2] [1] [0]
Default 8'd0 2'b00 1'b0 3'b000 1'b0 1'b0

[15:8] RESERVED NA
[7:6] INPUT_SELECT_OVERRIDE_MASKP Masks negative to positive interrupt toggling.
[5] TDM_VALID_EDGE_MASKP Masks negative to positive interrupt toggling.
[4:2] RESERVED NA
[1] BCK_WS_FAIL_MASKP Masks negative to positive interrupt toggling.
[0] DOP_VALID_MASKP Masks negative to positive interrupt toggling.
Register 15: INTERUPT VOL MIN MASKN

Bits [7] [6] [5] [4] [3] [2] [1] [0]

[7] VOL_MIN_CH8_MASKN Masks positive to negative interrupt toggling.
• 1'b0: Ignore interrupt if toggled from positive to negative
• 1'b1: Service interrupt if toggled from positive to negative
Register 16: INTERRUPT AUTOMUTE MASKN

Bits [7] [6] [5] [4] [3] [2] [1] [0]

[7] AUTOMUTE_FLAG_CH8_MASKN Masks positive to negative interrupt toggling.
Register 17: INTERRUPT SS FULL RAMP MASKN

Bits [7] [6] [5] [4] [3] [2] [1] [0]

[7] SS_FULL_RAMP_CH8_MASKN Masks positive to negative interrupt toggling.
Register 19-18: INTERRUPT MASKN

Bits [15:8] [7:6] [5] [4:2] [1] [0]
Default 8'd0 2'b00 1'b0 3'b000 1'b0 1'b0

[15:8] RESERVED NA
[7:6] INPUT_SELECT_OVERRIDE_MASKN Masks positive to negative interrupt toggling.
[5] TDM_VALID_EDGE_MASKN Masks positive to negative interrupt toggling.
[4:2] RESERVED NA
[1] BCK_WS_FAIL_MASKN Masks positive to negative interrupt toggling.
[0] DOP_VALID_MASKN Masks positive to negative interrupt toggling.
Register 20: INTERRUPT VOL MIN CLEAR

Bits [7] [6] [5] [4] [3] [2] [1] [0]

[7] VOL_MIN_CH8_CLEAR Write a 1'b1 to clear the interrupt
Register 21: INTERRUPT AUTOMUTE CLEAR

Bits [7] [6] [5] [4] [3] [2] [1] [0]

[7] AUTOMUTE_FLAG_CH8_CLEAR Write a 1'b1 to clear the interrupt
Register 22: INTERRUPT SS FULL RAMP CLEAR

Bits [7] [6] [5] [4] [3] [2] [1] [0]

[7] SS_FULL_RAMP_CH8_CLEAR Write a 1'b1 to clear the interrupt
Register 24-23: INTERRUPT CLEAR

Bits [15:8] [7:6] [5] [4:2] [1] [0]
Default 8'd0 2'b00 1'b0 3'b000 1'b0 1'b0

[15:8] RESERVED NA
[7:6] INPUT_SELECT_OVERRIDE_CLEAR Write a 1'b1 to clear the interrupt
[5] TDM_VALID_EDGE_CLEAR Write a 1'b1 to clear the interrupt
[4:2] RESERVED NA
[1] BCK_WS_FAIL_CLEAR Write a 1'b1 to clear the interrupt
[0] DOP_VALID_CLEAR Write a 1'b1 to clear the interrupt
Register 29-26: SSRC N AND DPLL BW

Bits [31:28] [27:0]
Default 4'd4 28'd0

[31:28] DPLL_BW Sets the bandwidth of the DPLL.
• 4'd0: Reserved
• 4'd1: Lowest Bandwidth
• 4'd15: Highest Bandwidth
[27:0] RESERVED NA
GPIO Registers
Register 37: GPIO1/2 CONFIG
Bits [7:4] [3:0]
Default 4’d7 4’d13

[7:4] GPIO2_CFG Configures GPIO2
• 4’d0: analog shutdown – shutdown
• 4’d1: output 0 – output
• 4’d3: CLK_IDAC – output
• 4’d4: interrupt – output
• 4’d5: mute all channel – input
• 4’d6: input selection – input
• 4’d7: lock_status – output (default)
• 4’d8: clk_avalid – output
• 4’d9: output PWM1 – output
• 4’d12: volume minimum – output
• 4’d13: automute status – output
• 4’d14: soft ramp done – output
• 4’d15: MQA_AUTH_TRUE – output
• 4’d0: analog shutdown – shutdown
• 4’d3: CLK_IDAC – output
• 4’d4: interrupt – output
• 4’d5: mute all channel – input
• 4’d6: input selection – input
• 4’d7: lock_status – output
• 4’d8: clk_avalid – output
• 4’d12: volume minimum – output
• 4’d13: automute status – output (default)
• 4’d14: soft ramp done – output
• 4’d15: MQA_AUTH_TRUE – output

Bits [7:4] [3:0]
Default 4'd0 4'd0

• 4'd0: analog shutdown - shutdown
• 4'd1: output 0 - output
• 4'd3: CLK_IDAC - output
• 4'd4: interrupt - output
• 4'd5: mute all channel - input
• 4'd6: input selection - input
• 4'd7: lock_status - output
• 4'd8: clk_avalid - output
• 4'd9: output PWM1 - output
• 4'd12: volume minimum - output
• 4'd13: automute status - output
• 4'd14: soft ramp done - output
• 4'd15: MQA_AUTH_TRUE - output

Bits [7:4] [3:0]
Default 4'd0 4'd0


Bits [7:4] [3:0]
Default 4'd0 4'd0

Register 41: GPIO OUTPUT ENABLE

Bits [7] [6] [5] [4] [3] [2] [1] [0]

[7] GPIO8_OE • 1'b0: Tristate GPIO8 (default)
• 1'b1: GPIO8 Output Enable
[1] GPIO2_OE • 1'b0: Tristate GPIO2
• 1'b1: GPIO2 Output Enable (default)
[0] GPIO1_OE • 1'b0: Tristate GPIO1
• 1'b1: GPIO1 Output Enable (default)
Register 42: GPIO INPUT

Bits [7] [6] [5] [4] [3] [2] [1] [0]

[7] GPIO8_SDB • 1'b0: Disables GPIO8 input (default)
• 1'b1: Enables GPIO8 input
[4] GPIO5_SDB • 1'b0: Disables GPIO5 input
• 1'b1: Enables GPIO5 input (default)
[3] GPIO4_SDB • 1'b0: Disables GPIO4 input
• 1'b1: Enables GPIO4 input (default)
Register 43: GPIO WK EN

Bits [7] [6] [5] [4] [3] [2] [1] [0]

[7] GPIO8_WK_EN • 1'b0: GPIO8 weak keeper disabled (default)
• 1'b1: GPIO8 weak keeper enabled
Register 44: INVERT GPIO

Bits [7] [6] [5] [4] [3] [2] [1] [0]

[7] INVERT_GPIO8 • 1'b1: Inverts GPIO8 output.
Register 45: GPIO READ

Bits [7] [6] [5] [4] [3] [2] [1] [0]

[7] GPIO8_READ • 1'b0: GPIO8 Readback disabled (default)
• 1'b1: Allow readback of GPIO8_I
Register 47-46: GPIO OUTPUT LOGIC

Bits [15] [14:9] [8:6] [5] [4] [3] [2] [1] [0]
Default 1'b0 6'd0 3'd0 1'b0 1'b0 1'b0 1'b1 1'b1 1'b1

[15] GPIO_DAC_MODE When any GPIOx_CFG = 6 (input system mode control):
• 1'b0: Power down when GPIO input is 1
• 1'b1: HIFI when GPIO input is 1 (when GPIO input is 0, system mode
is determined by register DAC_MODE_REG (register 0, bit[1]))
[14:9] RESERVED NA
[8:6] GPIO_SEL When GPIOx_CFG = 12, 13 or 14, and the corresponding GPIO_AND and
GPIO_OR are not set:
• 3'd0: Outputs status/flag from ch1
[5] GPIO_OR_SS_RAMP When GPIOx_CFG = 14 (output soft ramp done flag):
• 1'b0: The soft ramp done flag is determined by
GPIO_AND_SS_RAMP and GPIO_SEL (default)
• 1'b1: The soft ramp done flag is the "OR" of all 8ch soft ramp done
flags
[4] GPIO_OR_VOL_MIN When GPIOx_CFG = 12 (output vol_min flag):
• 1'b0: The vol_min flag is determined by GPIO_AND_VOL_MIN and
GPIO_SEL (default)
• 1'b1: The vol_min flag is the "OR" of all 8ch vol_min flags
[3] GPIO_OR_AUTOMUTE When GPIOx_CFG = 13 (output automute status):
• 1'b0: The automute status is determined by
GPIO_AND_AUTOMUTE and GPIO_SEL (default)
• 1'b1: The automute status is the "OR" of all 8ch automute status
[2] GPIO_AND_SS_RAMP When GPIOx_CFG = 14 (output soft ramp done flag) and
GPIO_OR_SS_RAMP is not set:
• 1'b0: The soft ramp done flag is from a single channel selected by
GPIO_SEL
• 1'b1: The soft ramp done flag is the "AND" of all 8ch soft ramp done
flags (default)
[1] GPIO_AND_VOL_MIN When GPIOx_CFG = 12 (output vol_min flag) and GPIO_OR_VOL_MIN is
not set:
• 1'b0: The vol_min flag is from a single channel selected by
GPIO_SEL
• 1'b1: The vol_min flag is the "AND" of all 8ch vol_min flags (default)
[0] GPIO_AND_AUTOMUTE When GPIOx_CFG = 13 (output automute status) and
GPIO_OR_AUTOMUTE is not set:
• 1'b0: The automute status is from a single channel selected by
GPIO_SEL
• 1'b1: The automute status is the "AND" of all 8ch automute status
(default)
Register 48: PWM1 COUNT

Bits [7:0]
Default 8'd0

[7:0] PWM1_COUNT 8-bit value to set the number of SYS_CLK periods the PWM signal is high
for.
Valid from 8'd0 to 8'd255
Register 50-49: PWM1 FREQUENCY

Bits [15:0]
Default 16'd0

[15:0] PWM1_FREQ 16-bit value to set the frequency of the PWM signal in terms of SYS_CLK
divisions.
Valid from 16'h0000 to 16'hFFFF
𝑆𝑌𝑆_𝐶𝐿𝐾
𝑓𝑟𝑒𝑞𝑢𝑒𝑛𝑐𝑦 (𝐻𝑧) =
𝑃𝑊𝑀1_𝐹𝑅𝐸𝑄 + 1
(𝑃𝑊𝑀1_𝐹𝑅𝐸𝑄 + 1) − 𝑃𝑊𝑀1_𝐶𝑂𝑈𝑁𝑇
𝐷𝑢𝑡𝑦 𝐶𝑦𝑐𝑙𝑒 (%) = (1 − ) × 100

Bits [7:0]
Default 8'd0

for.

Bits [15:0]
Default 16'd0

divisions.
𝐷𝑢𝑡𝑦 𝐶𝑦𝑐𝑙𝑒 (%) = (1 − ) × 100

Bits [7:0]
Default 8'd0

for.

Bits [15:0]
Default 16'd0

divisions.
𝐷𝑢𝑡𝑦 𝐶𝑦𝑐𝑙𝑒 (%) = (1 − ) × 100
DAC Registers
Register 57: INPUT SELECTION
Bits [7] [6] [5] [4] [3] [2:1] [0]
Default 1'b0 1'b1 1'b0 1'b0 1'b0 2'd0 1'b0

[7] AUTO_CH_DETECT Auto detect BCK/FRAME ratio to determine the number of TDM channels
• 1'b1: Enabled
[6] ENABLE_DSD_FAULT_DETECTION • 1'b0: Disabled
• 1'b1: Enabled (default)
[5] DSD_MASTER_MODE DSD master mode config.
• 1'b0: DSD slave mode (default)
• 1'b1: DSD master mode. DSD_CLK outputs from DATA_CLK
[4] PCM_MASTER_MODE PCM master mode config.
• 1'b0: PCM slave mode (default)
• 1'b1: PCM master mode enabled. Master BCK and WS output from
DATA_CLK and DATA1
[3] RESERVED NA
[2:1] INPUT_SEL Selects input data format when AUTO_INPUT_SELECT is disabled.
• 2'd0: TDM (default)
• 2'd1: DSD
• 2'd2: DoP
• 2'd3: SPDIF
[0] AUTO_INPUT_SEL Automatic input data selection config.
• 1'b0: Disables auto input select. Input data format is set by
INPUT_SEL (default)
• 1'b1: Automatically determine the input data format.
Note: When using AUTO_INPUT_SEL data must be provided on the DATA2
pin, to properly decode the input format
Register 58: SERIAL MASTER ENCODER CONFIG

Bits [7] [6] [5] [4:3] [2] [1] [0]
Default 1'b0 1'b0 1'b0 2'd0 1'b0 1'b0 1'b1

[7] TDM_RESYNC Force TDM decoder to resync.
• 1'b0: Let decoder sync (default)
• 1'b1: Force decoder not sync
[6] BCK_INV Invert the slave BCK
• 1'b0: Normal operation
• 1'b1: Invert slave BCK
[5] RESERVED NA
[4:3] MASTER_FRAME_LENGTH Selects the bit length in each TDM channel in master mode.
• 2'd0: 32-bit (default)
• 2'd1: 24-bit
• 2'd2: 16-bit
• 2'd3: Reserved
[2] MASTER_WS_PULSE_MODE When enabled, master WS is a pulse signal instead of a 50% duty cycle
signal. The pulse width is 1 BCK cycle.
• 1'b0: 50% duty cycle WS signal (default)
• 1'b1: Pulse WS signal
[1] MASTER_WS_INVERT Inverts master WS.
• 1'b0: Non-inverted (default)
• 1'b1: Inverted
[0] MASTER_BCK_INVERT Inverts master BCK or DSD_CLK.
• 1'b0: Non-inverted
• 1'b1: Inverted (default)
Register 59: TDM CONFIG

Bits [7:5] [4:0]
Default 3'd0 5'd1

[7:5] RESERVED NA
[4:0] TDM_CH_NUM Total number of TDM slots per frame = TDM_CH_NUM + 1.
Register 60: TDM CONFIG1

Bits [7] [6] [5:0]

[7] TDM_LJ_MODE TDM LJ mode.
• 1'b0: Standard I2S (default)
• 1'b1: LJ mode
[6] TDM_VALID_EDGE TDM WS valid edge.
• 1'b0: negative edge (default)
• 1'b1: positive edge
[5:0] RESERVED NA
Register 61: TDM CONFIG2

Bits [7] [6:5] [4:0]

[7] RESERVED NA
[6:5] TDM_BIT_WIDTH Bit width of each TDM slot.
• 2'b00: 32-bit (default)
• 2'b01: 24-bit
• 2'b10: 16-bit
• 2'b11: Reserved
[4:0] TDM_DATA_LATCH_ADJ Sets the position of the start bit within each TDM slot.
Can be moved +ve or -ve relative to MSB
Register 62: BCK/WS MONITOR CONFIG

Bits [7] [6] [5] [4] [3] [2:0]
Default 1'b0 1'b0 1'b1 1'b1 1'b0 3'd0

[7] DISABLE_DSD_DC • 1'b0: DSD DC can trigger an automute if automute is enabled
(default)
• 1'b1: DSD DC is ignored.
[6] DISABLE_DSD_MUTE • 1'b0: DSD mute pattern can trigger an automute is automute is
enabled (default)
• 1'b1: DSD mute pattern is ignored.
[5] ENABLE_WS_MONITOR Enable WS monitor.
• 1'b0: Disable
• 1'b1: Enable (default)
[4] ENABLE_BCK_MONITOR Enable BCK monitor.
• 1'b0: Disable (default)
• 1'b1: Enable
[3] DISABLE_PCM_DC • 1'b0: PCM DC signal can trigger an automute if automute is enabled.
• 1'b1: PCM DC is ignored.
[2:0] RESERVED NA
Register 64: TDM CH1 CONFIG

Bits [7] [6:5] [4:0]
Default 1'b0 2'd0 5'd0

[7] RESERVED NA
[6:5] TDM_CH1_LINE_SEL CH1 data line selection. CH1 receives data from Nth line.
N = TDM_CH1_LINE_SEL + 1.
Note: Valid for TDM, PCM and DoP.
[4:0] TDM_CH1_SLOT_SEL CH1 data slot selection. CH1 receives data from Mth slot.
M = TDM_CH1_SLOT_SEL + 1.

Bits [7] [6:5] [4:0]

[7] RESERVED NA

Bits [7] [6:5] [4:0]

[7] RESERVED NA

Bits [7] [6:5] [4:0]

[7] RESERVED NA

Bits [7] [6:5] [4:0]

[7] RESERVED NA

Bits [7] [6:5] [4:0]

[7] RESERVED NA

Bits [7] [6:5] [4:0]

[7] RESERVED NA

Bits [7] [6:5] [4:0]

[7] RESERVED NA
Register 74: VOLUME1

Bits [7:0]
Default 8'd0

[7:0] VOLUME1 DAC ch1 volume. -0dB to -127.5dB, 0.5dB steps
• 8'd0: 0dB
• 8'd255: -127.5dB

Bits [7:0]
Default 8'd0

• 8'd0: 0dB
• 8'd255: -127.5dB

Bits [7:0]
Default 8'd0

• 8'd0: 0dB
• 8'd255: -127.5dB

Bits [7:0]
Default 8'd0

• 8'd0: 0dB
• 8'd255: -127.5dB

Bits [7:0]
Default 8'd0

• 8'd0: 0dB
• 8'd255: -127.5dB

Bits [7:0]
Default 8'd0

• 8'd0: 0dB
• 8'd255: -127.5dB

Bits [7:0]
Default 8'd0

• 8'd0: 0dB
• 8'd255: -127.5dB

Bits [7:0]
Default 8'd0

• 8'd0: 0dB
• 8'd255: -127.5dB
Register 82: DAC VOL UP RATE

Bits [7:0]
Default 8'd4
[7:0] DAC_VOL_RATE_UP Value by which the old VOLUME value is incremented to reach the new
VOLUME value
Valid from 8'd0 (instant) to 8'd255 (fastest), where 8'd0 instantly changes the
VOLUME value
• 8'd0: Instant change
• 8'd4: Default
• 8'd255: Fastest change
215
𝑟𝑎𝑚𝑝_𝑟𝑎𝑡𝑒 [𝑠] =
𝐷𝐴𝐶_𝑉𝑂𝐿_𝑅𝐴𝑇𝐸_𝑈𝑃 ∗ 𝐹𝑆
Register 83: DAC VOL DOWN RATE

Bits [7:0]
Default 8'd4

[7:0] DAC_VOL_RATE_DOWN Value by which the old VOLUME value is incremented to reach the new
VOLUME value
VOLUME value
• 8'd4: Default
• 8'd255: Fastest change
215
𝐷𝐴𝐶_𝑉𝑂𝐿_𝑅𝐴𝑇𝐸_𝐷𝑂𝑊𝑁 ∗ 𝐹𝑆
Register 84: DAC VOL DOWN RATE FAST

Bits [7:0]
Default 8'd255

[7:0] DAC_VOL_RATE_FAST Value by which the old VOLUME value is incremented to reach the new
VOLUME value
VOLUME value
Only used during abnormal mute (PLL unlock or BCK_WS ratio failed)
• 8'd255: Fastest change (default)
215
𝐷𝐴𝐶_𝑉𝑂𝐿_𝑅𝐴𝑇𝐸_𝐹𝐴𝑆𝑇 ∗ 𝐹𝑆
Register 86: DAC MUTE

Bits [7] [6] [5] [4] [3] [2] [1] [0]

[7] DAC_MUTE_CH8 • 1'b0: Normal operation (default)
• 1'b1: Mute ch8

• 1'b1: Mute ch7
• 1'b1: Mute ch6
• 1'b1: Mute ch5
• 1'b1: Mute ch4
• 1'b1: Mute ch3
• 1'b1: Mute ch2
• 1'b1: Mute ch1
Register 87: DAC INVERT

Bits [7] [6] [5] [4] [3] [2] [1] [0]

[7] DAC_INVERT_CH8 Invert the output on Ch8 at the input to the NSMOD
Register 88: FILTER SHAPE

Bits [7:3] [2:0]
Default 5'd12 3'd0

[7:3] RESERVED NA
[2:0] FILTER_SHAPE Selects the 8x interpolation FIR filter shape.
• 3'd0: Minimum phase (default)
• 3'd1: Linear phase apodizing
• 3'd2: Linear phase fast roll-off
• 3'd4: Linear phase slow roll-off
• 3'd5: Minimum phase fast roll-off
• 3'd6: Minimum phase slow roll-off
• 3'd7: Minimum phase slow roll-off low dispersion
Register 89: IIR BANDWIDTH & S/PDIF Select

Bits [7:4] [3] [2:0]
Default 4'd0 1'b0 3'd4

[7:4] SPDIF_SEL Selects the S/PDIF data input pin
• 4'd1: GPIO1
• 4'd2: GPIO2
• 4'd3: GPIO3
• 4'd4: DATA1
• 4'd5: DATA2
• 4'd6: DATA3
• 4'd7: DATA4/GPIO4
• Others: Reserved
Note: GPIOx pins also require the GPIO input to be enabled
[3] VOLUME_HOLD Hold volume coefficients to allow for all channels to update at same time
[2:0] IIR_BW Controls the IIR bandwidth in the digital data path
• 3’d0: Not valid
• 3’d1: BW*8 (Maximum bandwidth)
• 3’d2: BW*4
• 3’d3: BW*2
• 3’d4: Default BW
• 3’d5: BW/2
• 3’d6: BW/4
• 3’d7: BW/8 (Minimum bandwidth)
Register 90: DAC PATH CONFIG

Bits [7:3] [2] [1] [0]
Default 5'b00000 1'b0 1'b0 1'b0

[7:3] RESERVED NA
[2] BYPASS_IIR • 1'b0: Non-bypass IIR1 (default)
• 1'b1: Bypass IIR1
[1] BYPASS_FIR4X • 1'b0: Non-bypass IFir_4x (default)
• 1'b1: Bypass IFir_4x
[0] BYPASS_FIR2X • 1'b0: Non-bypass IFir_2x (default)
• 1'b1: Bypass IFir_2x
Register 98-91: THD_C2_L

Bits [63:48] [47:32] [31:16] [15:0]
Default 16'd0 16'd0 16'd0 16'd0

[63:48] THD_C2_3 A 16-bit signed coefficient for correcting for the CH4 second harmonic
distortion.
𝑜𝑢𝑡𝑝𝑢𝑡 = 𝑥 + 𝑐2 ∗ 𝑥 2 + 𝑐3 ∗ 𝑥 3
distortion.
𝑜𝑢𝑡𝑝𝑢𝑡 = 𝑥 + 𝑐2 ∗ 𝑥 2 + 𝑐3 ∗ 𝑥 3
distortion.
𝑜𝑢𝑡𝑝𝑢𝑡 = 𝑥 + 𝑐2 ∗ 𝑥 2 + 𝑐3 ∗ 𝑥 3
distortion.
𝑜𝑢𝑡𝑝𝑢𝑡 = 𝑥 + 𝑐2 ∗ 𝑥 2 + 𝑐3 ∗ 𝑥 3
Register 106-99: THD_C2_H

Bits [63:48] [47:32] [31:16] [15:0]
Default 16'd0 16'd0 16'd0 16'd0

distortion.
𝑜𝑢𝑡𝑝𝑢𝑡 = 𝑥 + 𝑐2 ∗ 𝑥 2 + 𝑐3 ∗ 𝑥 3
distortion.
𝑜𝑢𝑡𝑝𝑢𝑡 = 𝑥 + 𝑐2 ∗ 𝑥 2 + 𝑐3 ∗ 𝑥 3
distortion.
𝑜𝑢𝑡𝑝𝑢𝑡 = 𝑥 + 𝑐2 ∗ 𝑥 2 + 𝑐3 ∗ 𝑥 3
distortion.
𝑜𝑢𝑡𝑝𝑢𝑡 = 𝑥 + 𝑐2 ∗ 𝑥 2 + 𝑐3 ∗ 𝑥 3
Register 114-107: THD_C3_L

Bits [63:48] [47:32] [31:16] [15:0]
Default 16'd0 16'd0 16'd0 16'd0

[63:48] THD_C3_3 A 16-bit signed coefficient for correcting for the CH4 third harmonic
distortion.
𝑜𝑢𝑡𝑝𝑢𝑡 = 𝑥 + 𝑐2 ∗ 𝑥 2 + 𝑐3 ∗ 𝑥 3
distortion.
𝑜𝑢𝑡𝑝𝑢𝑡 = 𝑥 + 𝑐2 ∗ 𝑥 2 + 𝑐3 ∗ 𝑥 3
distortion.
𝑜𝑢𝑡𝑝𝑢𝑡 = 𝑥 + 𝑐2 ∗ 𝑥 2 + 𝑐3 ∗ 𝑥 3
distortion.
𝑜𝑢𝑡𝑝𝑢𝑡 = 𝑥 + 𝑐2 ∗ 𝑥 2 + 𝑐3 ∗ 𝑥 3
Register 122-115: THD_C3_H

Bits [63:48] [47:32] [31:16] [15:0]
Default 16'd0 16'd0 16'd0 16'd0

distortion.
𝑜𝑢𝑡𝑝𝑢𝑡 = 𝑥 + 𝑐2 ∗ 𝑥 2 + 𝑐3 ∗ 𝑥 3
distortion.
𝑜𝑢𝑡𝑝𝑢𝑡 = 𝑥 + 𝑐2 ∗ 𝑥 2 + 𝑐3 ∗ 𝑥 3
distortion.
𝑜𝑢𝑡𝑝𝑢𝑡 = 𝑥 + 𝑐2 ∗ 𝑥 2 + 𝑐3 ∗ 𝑥 3
distortion.
𝑜𝑢𝑡𝑝𝑢𝑡 = 𝑥 + 𝑐2 ∗ 𝑥 2 + 𝑐3 ∗ 𝑥 3
Register 123: AUTOMUTE ENABLE

Bits [7] [6] [5] [4] [3] [2] [1] [0]

[7] AUTOMUTE_EN_CH8 • 1'b0: Disables ch8 automute
• 1'b1: Enables ch8 automute (default)
Note: Automute is available for PCM only
Register 125-124: AUTOMUTE TIME

Bits [15:12] [11] [10:0]
Default 4'd0 1'b1 11'd15

[15:12] RESERVED NA
[11] AUTOMUTE_RAMP_TO_GROUND • 1'b0: When ramped to min volume during normal mute, do not soft
ramp to ground
• 1'b1: When ramped to min volume during normal mute, soft ramp to
ground for power saving (default)
normal mute includes: automute, mute by register, mute by GPIO
[10:0] AUTOMUTE_TIME Configures the amount of time in seconds the audio must remain below
AUTOMUTE_LEVEL before an automute condition is flagged.
Valid from 0 (disabled) to 11'h7FF (fastest), where 11'h001 is the slowest
218
𝑇𝑖𝑚𝑒 [𝑠] =
𝐴𝑈𝑇𝑂𝑀𝑈𝑇𝐸_𝑇𝐼𝑀𝐸 ∗ 𝐹𝑆
Register 127-126: AUTOMUTE LEVEL

Bits [15:0]
Default 16'0008

[15:0] AUTOMUTE_LEVEL Configures the threshold which the audio must be below before an automute
condition is flagged.
Valid from: 16'hFFFF (-42dB) to 16'h0001 (-132dB)
Shift right 1 bit corresponds to -6dB
Note: this register works in tandem with AUTOMUTE_TIME to create the
automute condition
Register 129-128: AUTOMUTE OFF LEVEL

Bits [15:0]
Default 16'000A

[15:0] AUTOMUTE_OFF_LEVEL Configures the threshold which the audio must be above before the
automute condition is cleared (cleared immediately).
Valid from: 16'hFFFF (-42dB) to 16'h0001 (-132dB)
Shift right 1 bit corresponds to -6dB
Register 130: SOFT RAMP CONFIG

Bits [7:5] [4:0]
Default 3'd0 5'd3

[7:5] RESERVED NA
[4:0] SOFT_RAMP_TIME Sets the amount of time that it takes to perform a soft start ramp.
This time affects both ramp to ground and ramp to AVCC/2.
Valid from 0 to 20 (inclusive).
2𝑆𝑂𝐹𝑇_𝑅𝐴𝑀𝑃_𝑇𝐼𝑀𝐸+1
𝑇𝑖𝑚𝑒 [𝑠] = 4096 ∗
𝐶𝐿𝐾𝐼𝐷𝐴𝐶[𝐻𝑧]
Register 135: PROGRAM RAM CONTROL

Bits [7:2] [1] [0]
Default 6'd0 1'b0 1'b0

[7:2] RESERVED NA
[1] PROG_COEFF_WE Enables writing to the programmable coefficient RAM.
• 1’b0: Disables write signal to the coefficient RAM (default).
• 1’b1: Enables write signal to the coefficient RAM.
[0] PROG_COEFF_EN Enables the custom oversampling filter coefficients.
• 1’b0: Uses a built-in filter selected by filter_shape (default).
• 1’b1: Uses the coefficients programmed via prog_coeff_data.
Register 137: PROGRAM RAM ADDRESS

Bits [7] [6:0]
Default 1'b0 7'd0

[7] PROG_COEFF_STAGE Selects which stage of the filter to write.
• 1'b0: Selects the 2x stage of the oversampling filter (default).
• 1'b1: Selects the 4x stage of the oversampling filter.
[6:0] PROG_COEFF_ADDR Selects the coefficient address when writing custom coefficients for the
oversampling filter.
Register 140-138: PROGRAM RAM DATA

Bits [23:0]
Default 24'd0

[23:0] PROG_COEFF_IN A 24bit signed filter coefficient that will be written to the address defined in
prog_coeff_addr.
Register 141: MQA CONFIG

Bits [7:3] [2:1] [0]
Default 5'b10000 2'b00 1'b0

[7:3] RESERVED NA
[2:1] MQB_READER_ENABLE Enable the MQB stream reader
• 2'b00: The MQB stream reader is disabled. (default)
• 2'b01: The MQB stream reader is enabled (Normal Operation, 24-bit)
• 2'b10: The MQB stream reader is enabled (16-bit)
• 2'b11: Reserved
Note: ES9039MPRO has a MQA renderer built in, MQA stream must be
decoded by MQA core decoder first.
[0] MQA_RENDERING_ENABLE This allows the Sabre ES9039MPRO to render decoded MQA streams.
• 1'b1: Enabled
Readback Registers
Register 224: SYS READ
Bits [7:4] [3:2] [1] [0]
Default - - - -

[7:4] RESERVED NA
[3:2] MODES Chip mode readback. Based off MODE Pin
• 2'b00: I2C
• 2'b11: SPI
Note: All other values are invalid
[1] ADDR1 I2C address select bit 1 readback.
[0] ADDR0 I2C address select bit 0 readback.
Register 225: CHIP ID READ

Bits [7:0]
Default -

[7:0] CHIP_ID Chip ID.
Register 233-229: INTERRUPT STATE

Bits [39:32] [31:30] [29] [28:26] [25] [24] [23:16] [15:8] [7:0]
Default - - - - - - - - -

[39:32] RESERVED NA
[31:30] INPUT_SELECT_OVERRIDE_STATE State of the INPUT_SELECT_OVERRIDE interrupt.
Note: Interrupt clear bits are required to reset value.
[29] TDM_DATA_VALID_STATE State of the TDM_DATA_VALID interrupt.
Note: Interrupt clear bit is required to reset value.
[28:26] RESERVED NA
[25] BCK_WS_FAIL_STATE State of the BCK_WS_FAIL interrupt.
[24] DOP_VALID_STATE State of the DOP_VALID interrupt.
[23:16] SS_FULL_RAMP_STATE State of each channel's SS_FULL_RAMP interrupt.
[15:8] AUTOMUTE_STATE State of each channel's AUTOMUTE_STATE interrupt.
[7:0] VOL_MIN_STATE State of each channel's VOL_MIN_STATE interrupt.
Register 238-234: INTERRUPT SOURCE

Bits [39:32] [31:30] [29] [28:26] [25] [24] [23:16] [15:8] [7:0]
Default - - - - - - - - -

[39:32] RESERVED NA
[31:30] INPUT_SELECT_OVERRIDE_SOURCE Output of the AUTO_INPUT_SELECT logic.
[29] TDM_DATA_VALID_SOURCE TDM data valid flag.
[28:26] RESERVED NA
[25] BCK_WS_FAIL_SOURCE Validity of BCK, WS, and ASYNC_LOCK flag.
Requires respective monitor bits to be set.
[24] DOP_VALID_SOURCE Valid DoP flag for Channels 1 and 2.
[23:16] SS_FULL_RAMP_SOURCE Channel flag for whether it is fully ramped up or down.
[15:8] AUTOMUTE_SOURCE Channel flag for whether it is automute is active.
[7:0] VOL_MIN_SOURCE Channel flag for whether the corresponding volume register = 0x00
Register 239: RATIO VALID READ

Bits [7] [6:0]
Default - -

[7] RATIO_VALID Indicates validity of the CLK_DAC/CLK_IDAC ratio
• 1'b0: Invalid
• 1'b1: Valid
[6:0] RESERVED NA
Register 240: GPIO READ

Bits [7] [6] [5] [4] [3] [2] [1] [0]
Default - - - - - - - -

[7] GPIO8_I_READ GPIO8 Readback
Register 241: VOL MIN READ

Bits [7] [6] [5] [4] [3] [2] [1] [0]
Default - - - - - - - -

[7] VOL_MIN_CH8 Volume min flag ch8
Register 242: AUTOMUTE READ

Bits [7] [6] [5] [4] [3] [2] [1] [0]
Default - - - - - - - -

[7] AUTOMUTE_CH8 Automute status ch8
Register 243: SOFT RAMP UP READ

Bits [7] [6] [5] [4] [3] [2] [1] [0]
Default - - - - - - - -

[7] SS_RAMP_UP_CH8 Soft ramped up flag ch8
Register 244: SOFT RAMP DOWN READ

Bits [7] [6] [5] [4] [3] [2] [1] [0]
Default - - - - - - - -

[7] SS_RAMP_DOWN_CH8 Soft ramped down flag ch8
Register 245: SPDIF, TDM, DOP, AND INPUT READBACK

Bits [7] [6] [5:2] [1:0]
Default - - - -

[7] SPDIF_VALID S/PDIF valid flag
[6] TDM_DATA_VALID TDM valid data flag
[5:2] DOP_VALID DoP valid flag
[1:0] INPUT_SELECT_OVERRIDE AUTO_INPUT_SEL value
Register 248-246: PROG COEFF OUT READ

Bits [23:0]
Default -

[23:0] PROG_COEFF_OUT Programmable FIR coefficient readback
Register 251: SPDIF DATA READ

Bits [7:0]
Default -

[7:0] RESERVED NA
ES9039MPRO/ES9039PRO Reference Schematic

Hardware (HW) mode
Figure 12 – HW mode reference schematic
Software Mode
Figure 13 – Software mode reference schematic
Output Stage (for Reference)
Figure 14 – Software mode reference schematic
64 eTQFP Package Dimensions
Figure 15 – ES9039SPRO/ES9039MSPRO 64 eTQFP package dimensions
64 QFP Top View Marking
Figure 16 – ES9039SPRO Marking
Figure 17 – ES9039MSPRO Marking
Dimension in mm
Package Type A B C D E F G
64L eTQFP 10mm x 10mm 7.4 3.5 0.45 0.8 0.3 0.15 0.4
T Tracking number
W Work week
Y Last digit of year
L Lot number
R Silicon Revision
Reflow Process Considerations

Temperature Controlled
For lead-free soldering, the characterization and optimization of the reflow process is the most important factor to consider.
The lead-free alloy solder has a melting point of 217°C. This alloy requires a minimum reflow temperature of 235°C to ensure good wetting. The
maximum reflow temperature is in the 245°C to 260°C range, depending on the package size (RPC-2 Pb-Free Process – Classification
Temperatures (Tc)). This narrows the process window for lead-free soldering to 10°C to 20°C.
The increase in peak reflow temperature in combination with the narrow process window makes the development of an optimal reflow profile a
critical factor for ensuring a successful lead-free assembly process. The major factors contributing to the development of an optimal thermal profile
are the size and weight of the assembly, the density of the components, the mix of large and small components, and the paste chemistry being used.
Reflow profiling needs to be performed by attaching calibrated thermocouples well adhered to the device as well as other critical locations on the
board to ensure that all components are heated to temperatures above the minimum reflow temperatures and that smaller components do not
exceed the maximum temperature limits (Table RPC-2).
To ensure that all packages can be successfully and reliably assembled, the reflow profiles studied and recommended by ESS are based on the
JEDEC/IPC standard J-STD-020 revision D.1.
Figure 18 – IR/Convection Reflow Profile (IPC/JEDEC J-STD-020D.1)
Reflow is allowed 3 times. Caution must be taken to ensure time between re-flow runs does not exceed the allowed time by the moisture sensitivity
label. If the time elapsed between the re-flows exceeds the moisture sensitivity time bake the board according to the moisture sensitivity label
instructions.
Manual
Allowed up to 2 times with maximum temperature of 350°C no longer than 3 seconds.
RPC-1 Classification reflow profile

Profile Feature Pb-Free Assembly
Preheat/Soak
Temperature Min (Tsmin) 150°C
Temperature Max (Tsmax) 200°C
Time (ts) from (Tsmin to Tsmax) 60-120 seconds
Ramp-up rate (TL to Tp) 3°C / second maximum
Liquidous temperature (TL) 217°C
Time (tL) maintained above TL 60-150 seconds
For users Tp must not exceed the classification temp in Table RPC-
2.
Peak package body temperature (Tp)
For suppliers Tp must equal or exceed the Classification temp in
Table RPC-2.
Time (tp)* within 5°C of the specified classification temperature (Tc) 30* seconds
Ramp-down rate (Tp to TL) 6°C / second maximum
Time 25°C to peak temperature 8 minutes maximum
* Tolerance for peak profile temperature (Tp) is defined as a supplier minimum and a user maximum.
Table 10 – RPC-1 Classification reflow profile
All temperatures refer to the center of the package, measured on the package body surface that is facing up during assembly reflow (e.g., live-bug).
If parts are reflowed in other than the normal live-bug assembly reflow orientation (i.e., dead-bug), Tp shall be within ±2°C of the live-bug Tp and still
meet the Tc requirements, otherwise, the profile shall be adjusted to achieve the latter. To accurately measure actual peak package body
temperatures, refer to JEP140 for recommended thermocouple use.
Reflow profiles in this document are for classification/preconditioning and are not meant to specify board assembly profiles. Actual board assembly
profiles should be developed based on specific process needs and board designs and should not exceed the parameters in Table RPC-1.
For example, if Tc is 260°C and time tp is 30 seconds, this means the following for the supplier and the user.
For a supplier: The peak temperature must be at least 260°C. The time above 255°C must be at least 30 seconds.
For a user: The peak temperature must not exceed 260°C. The time above 255°C must not exceed 30 seconds.
All components in the test load shall meet the classification profile requirements.
RPC-2 Pb-Free Process – Classification Temperatures (Tc)

Package Thickness Volume mm3, <350 Volume mm3, 350 to 2000 Volume mm3, >2000
<1.6 mm 260°C 260°C 260°C
1.6 mm – 2.5 mm 260°C 250°C 245°C
>2.5 mm 250°C 245°C 245°C
Table 11 – RPC-2 Pb free classification temperatures
At the discretion of the device manufacturer, but not the board assembler/user, the maximum peak package body temperature (Tp) can exceed the
values specified in Table RPC-2. The use of a higher Tp does not change the classification temperature (Tc).
Package volume excludes external terminals (e.g., balls, bumps, lands, leads) and/or nonintegral heat sinks.
The maximum component temperature reached during reflow depends on package thickness and volume. The use of convection reflow processes
reduces the thermal gradients between packages. However, thermal gradients due to differences in thermal mass of SMD packages may still exist.
Ordering Information
Part Number Description Package
ES9039MSPRO SABRE PRO 32-bit 8 Channel Flagship DAC and MQA renderer
10mm x 10mm 64 eTQFP
ES9039SPRO SABRE PRO 32-bit 8 Channel Flagship DAC
Revision History
Current Version 0.2.1
Rev. Date Notes
0.1.3 June, 2022 Initial release
• Pin Description correction for pins 49 & 50
• Added note on DoP (HW modes 16-18) usage in HW mode to Hardware Mode Pin
Configurations
• Updated digital signal path diagram
• Updated Registers 1[6],5,58[4:3],64-71,82-84, 130, 135,137,140-138, 106-99
• Updated Registers 47-46[15] Description
0.2.1 Sept, 2022 • Updated HW mode table & added HW feature tables
• Unreserved Register 89[2:0] IIR_BW
• Added reference output stage schematic
• Updated Hardware mode configuration diagram
• Added Notes to Hardware Mode Audio Input Format Compatibility table, renamed table
• Modified Performance table to add more details on output levels
• Changed Audio Input Format name to PCM from I2S to be more inclusive of subsets
© 2022 ESS Technology, Inc.
ESS IC’s are not intended, authorized, or warranted for use as components in military applications, medical devices or life support systems. ESS assumes no liability and disclaims
any expressed, implied or statutory warranty for use of ESS IC’s in such unsuitable applications.
No part of this publication may be reproduced, stored in a retrieval system, transmitted, or translated in any form or by any means, electronic, mechanical, manual, optical, or otherwise,
without the prior written permission of ESS Technology, Inc. ESS Technology, Inc. makes no representations or warranties regarding the content of this document. All specifications
are subject to change without prior notice. ESS Technology, Inc. assumes no responsibility for any errors contained herein. U.S. patents pending.

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ES9039MPRO & ES9039PRO

32-bit High-Performance 8-Channel DAC

The ES9039PRO SABRE® DAC improves on previous designs to include:

Patented 32-bit HyperStream® IV Architecture

High Sample Rates Up to PCM 768kHz & native DSD1024

ES9039MPRO & ES9039PRO Product Brief

ES9039MPRO & ES9039PRO Datasheet

Read/Write Register Addresses ............................................................................................................................................................................. 34

ES9039MPRO & ES9039PRO Product Brief

ES9039MPRO & ES9039PRO Datasheet

Functional Block Diagram

DVDD VCCA AVDD

MISO/ADDR0/HW3 Hyperstream®IV DAC3

HiFi Sabre® DAC DAC7B

Figure 1 - ES9039MPRO & ES9039PRO Block Diagram

ES9039MPRO & ES9039PRO Product Brief