Src419X 192-Khz Stereo Asynchronous Sample-Rate Converters: 1 Features 3 Description

Product Sample & Technical Tools & Support &
Folder Buy Documents Software Community
SRC4192, SRC4193
SBFS022C – JUNE 2003 – REVISED OCTOBER 2015
SRC419x 192-kHz Stereo Asynchronous Sample-Rate Converters

1 Features 3 Description
1• Automatic Sensing of the Input-to-Output The SRC4192 and SRC4193 devices are
Sampling Ratio asynchronous, sample-rate converters designed for
professional and broadcast audio applications. The
• Wide Input-to-Output Sampling Range: 16:1 to SRC4192 and SRC4193 devices combine a wide
1:16 input-to-output sampling ratio with outstanding
• Supports Input and Output Sampling Rates Up to dynamic range and ultra-low distortion. Input and
212 kHz output serial ports support standard audio formats, as
• Dynamic Range: 144 dB (–60-dbFS Input, BW = well as a Time Division Multiplexed (TDM) mode.
Flexible audio interfaces allow the SRC4192 and
20 Hz to fS/2, A-Weighted)
SRC4193 devices to connect to a wide range of
• THD+N: –140 dB (0-dbFS Input, BW = 20 Hz to audio data converters, digital audio receivers and
fS/2) transmitters, and digital signal processors.
• Attenuates Sampling and Reference Clock Jitter The SRC4192 device is a standalone, pin-
• High-Performance, Linear-Phase Digital Filtering programmed device, with control pins for mode, data
with Stop Band Attenuation Greater than 140 dB format, mute, bypass, and low group-delay functions.
• Flexible Audio Serial Ports: The SRC4193 device is a software-controlled device
featuring a serial peripheral interface (SPI) port,
– Master or Slave-Mode Operation which is utilized to program all functions through the
– Supports I2S, Left-Justified, Right-Justified, internal control registers.
and TDM Data Formats
The SRC4192 and SRC4193 devices can operate
– Supports 16, 18, 20, or 24-Bit Audio Data from a single 3.3-V power supply. A separate digital
– TDM Mode Allows Daisy-Chaining of up to I/O supply (VIO) operates over the 1.65-V to 3.6-V
Eight Devices supply range, allowing greater flexibility when
interfacing to current and future generation signal
• Supports 24-, 20-, 18-, or 16-Bit Input and Output
processors and logic devices. Both devices are
Data: All Output Data is Dithered from the Internal available in a 28-pin SSOP package.
28-Bit Data Path
• Low Group Delay Option for Interpolation Filter Device Information(1)
• Direct Downsampling Option for Decimation Filter PART NUMBER PACKAGE BODY SIZE (NOM)
(SRC4193 Only) SRC4192
SSOP (28) 5.30 mm × 10.20 mm
• SPI Port Provides Access to Internal Control SRC4193
Registers (SRC4193 Only) (1) For all available packages, see the orderable addendum at
• Soft Mute Function the end of the data sheet.
• Bypass Mode
Simplified Application Diagram
• Programmable Digital Output Attenuation
(SRC4193 Only); 256 Steps: 0 dB to –127.5 dB, Reference
Clock
0.5-dB/step
• Power Down Mode
Data
• Operates From a Single 3.3-V Power Supply Data TX+ AES,
SRC4192 LRCK DIT4192 S/PDIF
• Small 28-Pin SSOP Package DSP LRCK TX±
BCK Output
BCK
• Pin Compatible with the AD1896 (SRC4192 Only)
2 Applications
• Digital Mixing Consoles
• Digital Audio Workstations
• Audio Distribution Systems
• Broadcast Studio Equipment
• High-End A/V Receivers
• General Digital Audio Processing
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SRC4192, SRC4193
SBFS022C – JUNE 2003 – REVISED OCTOBER 2015 www.ti.com
Table of Contents
1 Features .................................................................. 1 7.4 Device Functional Modes........................................ 24
2 Applications ........................................................... 1 7.5 Register Maps ......................................................... 25
3 Description ............................................................. 1 8 Application and Implementation ........................ 28
4 Revision History..................................................... 2 8.1 Application Information............................................ 28
8.2 Typical Application ................................................. 31
5 Pin Configuration and Functions ......................... 3
6 Specifications......................................................... 4 9 Power Supply Recommendations...................... 33
6.1 Absolute Maximum Ratings ...................................... 4 10 Layout................................................................... 33
6.2 ESD Ratings ............................................................ 4 10.1 Layout Guidelines ................................................. 33
6.3 Recommended Operating Conditions....................... 4 10.2 Layout Example .................................................... 35
6.4 Thermal Information .................................................. 5 11 Device and Documentation Support ................. 37
6.5 Electrical Characteristics........................................... 5 11.1 Documentation Support ....................................... 37
6.6 Switching Characteristics .......................................... 6 11.2 Related Links ........................................................ 37
6.7 Typical Characteristics .............................................. 7 11.3 Community Resources.......................................... 37
7 Detailed Description ............................................ 18 11.4 Trademarks ........................................................... 37
7.1 Overview ................................................................. 18 11.5 Electrostatic Discharge Caution ............................ 37
7.2 Functional Block Diagram ....................................... 19 11.6 Glossary ................................................................ 37
7.3 Feature Description................................................. 19 12 Mechanical, Packaging, and Orderable
Information ........................................................... 37
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (September 2007) to Revision C Page
• Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section. ................................................................................................. 1
Changes from Revision A (July 2003) to Revision B Page
• Added U.S. patent number to note (1) U.S. Patent No. 7,262,716. ...................................................................................... 1
2 Submit Documentation Feedback Copyright © 2003–2015, Texas Instruments Incorporated
Product Folder Links: SRC4192 SRC4193

SRC4192, SRC4193
www.ti.com SBFS022C – JUNE 2003 – REVISED OCTOBER 2015
5 Pin Configuration and Functions
SRC4192 DB Package SRC4193 DB Package

28-Pin SSOP 28-Pin SSOP
Top View Top View
LGRP 1 28 MODE2 RCKI 1 28 CDATA
RCKI 2 27 MODE1 NC 2 27 CCLK
NC 3 26 MODE0 NC 3 26 CS
SDIN 4 25 BCKO SDIN 4 25 BCKO
BCKI 5 24 LRCKO BCKI 5 24 LRCKO
LRCKI 6 23 SDOUT LRCKI 6 23 SDOUT
VIO 7 SRC4192 22 VDD VIO 7 SRC4193 22 VDD
DGND 8 21 DGND DGND 8 21 DGND
BYPAS 9 20 TDMI BYPAS 9 20 TDMI
IFMT0 10 19 OFMT0 NC 10 19 NC
IFMT1 11 18 OFMT1 NC 11 18 NC
IFMT2 12 17 OWL0 NC 12 17 NC
RST 13 16 OWL1 RST 13 16 RATIO
MUTE 14 15 RDY MUTE 14 15 RDY
Pin Functions
PIN
I/O DESCRIPTION
NAME SRC4192 SRC4193
BCKI 5 5 I Input port bit clock I/O
BCKO 25 25 O Output port bit clock I/O
BYPAS 9 9 I ASRC bypass control input (Active High)
CCLK — 27 I SPI port data clock input
CDATA — 28 I SPI port serial data input
CS — 26 I SPI port chip select input (Active Low)
DGND 8, 21 8, 21 – Digital ground
IFMT0 10 — I Input port data format control input
LGRP 1 — I Low group delay control input (active high)
LRCKI 6 6 I Input port left/right word clock I/O
LRCKO 24 24 O Output port left/right word clock I/O
MODE0 26 — I Serial port mode control input
MUTE 14 14 I Output mute control input (active high)
2,3,10,11,12,
NC 3 – No connection
17,18,19
OFMT0 19 — I Output port data format control input
OFMT1 18 — I Output port data format control input
OWL0 17 — I Output port data word length control input
OWL1 16 — I Output port data word length control input
Input-to-output ratio flag output

RATIO — 16 O Low output denotes output rate lower than input rate.
High output denotes output rate higher than input rate.
RCKI 2 1 I Reference Clock Input
RDY 15 15 O ASRC Ready Status Output (Active Low)
Copyright © 2003–2015, Texas Instruments Incorporated Submit Documentation Feedback 3

SRC4192, SRC4193
Pin Functions (continued)

PIN
I/O DESCRIPTION
NAME SRC4192 SRC4193
RST 13 13 I Reset Input (Active Low)
SDIN 4 4 I Audio Serial Data Input
SDOUT 23 23 O Audio Serial Data Output
TDMI 20 20 I TDM Data Input (Connect to DGND when not in use)
VDD 22 22 I Digital Core Supply, 3.3 V
VIO 7 7 I Digital I/O Supply, 1.65 V to VDD
6 Specifications
6.1 Absolute Maximum Ratings
(1)
over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
VDD –0.3 4
Supply Voltage V
VIO –0.3 4
Digital Input Voltage –0.3 4
Operating Temperature –45 85 °C
Storage temperature, Tstg –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings

VALUE UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) ±3000
V(ESD) Electrostatic discharge Charged-device model (CDM), per JEDEC specification JESD22- V
±1500
C101 (2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions

MIN NOM MAX UNIT
VDD 3 3.3 3.6
Supply voltage VIO 1.8 V 1.65 1.8 1.95 V
VIO 3.3 V 3 3.3 3.6
Operating temperature –45 85 °C

SRC4192, SRC4193
6.4 Thermal Information

SRC4192
SRC4193
(1)
THERMAL METRIC UNIT
DB (SSOP)
28 PINS
RθJA Junction-to-ambient thermal resistance 78.6 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 38.1 °C/W
RθJB Junction-to-board thermal resistance 39.3 °C/W
ψJT Junction-to-top characterization parameter 7.1 °C/W
ψJB Junction-to-board characterization parameter 38.9 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance N/A °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
6.5 Electrical Characteristics

All parameters specified with TA = 25°C, VDD = 3.3 V, and VIO = 3.3 V, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
DYNAMIC PERFORMANCE (1)
Resolution 24 Bits
fSIN Input sampling frequency 4 212 kHz
fSOUT Output sampling frequency 4 212 kHz
Upsampling 1:16
Input: output sampling ratio
Downsampling 16:1
44.1 kHz; 48 kHz 140
48 kHz; 44.1 kHz 140
48 kHz; 96 kHz 140
44.1 kHz; 192 kHz 138
96 kHz; 48 kHz BW = 20 Hz to fSOUT/2, –60-dBFS Input 141
Dynamic range fIN = 1 kHz, Unweighted (add 3 dB to spec for A- dB
192 kHz; 12 kHz weighted result) 141
192 kHz; 32 kHz 141
192 kHz; 48 kHz 141
32 kHz; 48 kHz 140
12 kHz; 192 kHz 138
44.1 kHz; 48 kHz –140
48 kHz; 44.1 kHz –140
48 kHz; 96 kHz –140
44.1 kHz; 192 kHz –137
Total harmonic distortion + 96 kHz; 48 kHz BW = 20 Hz to fSOUT/2, 0-dBFS Input fIN = 1 kHz, –140
dB
noise 192 kHz; 12 kHz Unweighted –140
192 kHz; 32 kHz –141
192 kHz; 48 kHz –141
32 kHz; 48 kHz –140
12 kHz; 192 kHz –137
Interchannel gain mismatch 0 dB
Interchannel phase deviation 0 °
Minimum 0
Digital attenuation Maximum SRC4193 Only –127.5 dB
Step Size 0.5
Mute attenuation 24-Bit Word Length, A-weighted –144 dB
DIGITAL INTERPOLATION FILTER CHARACTERISTICS
Passband 0.4535 × fSIN Hz
Passband ripple ±0.007 dB
Transition band 0.4535 × fSIN 0.5465 × fSIN Hz
Stop band 0.5465 × fSIN Hz
Stop band attenuation –144 dB
(1) Dynamic performance measured with an Audio Precision System Two Cascade or Cascade Plus.
SRC4192, SRC4193
Electrical Characteristics (continued)

All parameters specified with TA = 25°C, VDD = 3.3 V, and VIO = 3.3 V, unless otherwise noted.
Decimation Filter On (DFLT = 0) 102.53125/fSIN
Normal group delay (LGRP = 0) s
Decimation Filter Off (DFLT = 1) 102/fSIN
Decimation Filter On (DFLT = 0) 70.53125/fSIN
Low group delay (LGRP = 1) s
Decimation Filter Off (DFLT = 1) 70/fSIN
DIGITAL DECIMATION FILTER CHARACTERISTICS
Passband 0.4535 × fSOUT Hz
Passband ripple ±0.008 dB
Transition band 0.4535 × fSOUT 0.5465 × fSOUT Hz
Stop band 0.5465 × fSOUT Hz
Stop band attenuation –143 dB
Group delay – decimation filter DFLT = 0 for SRC4193 36.46875/fSOUT s
Direct downsampling SRC4193 only, DFLT = 1 0 s
DIGITAL I/O CHARACTERISTICS
VIH High-level input voltage 0.7 × VIO VIO V
VIL Low-level input voltage 0 0.3 × VIO V
IIH High-level input current 0.5 10 µA
IIL Low-level input current 0.5 10 µA
VOH High-level output voltage IO = –4 mA 0.8 × VIO VIO V
VOL Low-level output voltage IO = +4 mA 0 0.2 × VIO V
CIN Input Capacitance 3 pF
POWER SUPPLIES
Operating voltage, VDD 3 3.3 3.6
V
Operating voltage, VIO 1.65 3.3 3.6
VDD = 3.3 V, VIO = 3.3 V, RST = 0, No Clocks 100 µA
Supply current, IDD, power down SRC4193 only, VDD = 3.3 V, VIO = 3.3 V,
5 mA
PDN Bit = 0, No Clocks
Supply current, IDD, dynamic VDD = 3.3 V, VIO = 3.3 V, fSIN = fSOUT = 192 kHz 66 mA
VDD = 3.3 V, VIO = 3.3 V, RST = 0, No Clocks 100
Supply current, IIO, power down SRC4193 only, VDD = 3.3 V, VIO = 3.3 V, µA
21
Supply current, IIO, dynamic VDD = 3.3 V, VIO = 3.3 V, fSIN = fSOUT = 192 kHz 2 mA
VDD = 3.3 V, VIO = 3.3 V, RST = 0, No Clocks 660 µW
Total power dissipation, PD, power down SRC4193 only, VDD = 3.3 V, VIO = 3.3 V,
16.6 mW
Total power dissipation, PD, dynamic VDD = 3.3 V, VIO = 3.3 V, fSIN = fSOUT = 192 kHz 225 mW
6.6 Switching Characteristics

REFERENCE CLOCK TIMING
fSMIN = min (fSIN, fSOUT), 128 ×
RCKI frequency 50 MHz
fSMAX = max (fSIN, fSOUT) fSMIN
1/(128
tRCKIP RCKI period 20 ns
×fSMIN)
0.4 ×
tRCKIH RCKI pulsewidth high ns
tRCKIP
0.4 ×
tRCKIL RCKI pulsewidth low ns
tRCKIP
RESET TIMING
tRSTL RST pulse width low 500 ns
Delay following RST rising edge SRC4193 only 500 µs
INPUT SERIAL PORT TIMING
tLRIS LRCKI to BCKI setup time 10 ns
tSIH BCKI pulsewidth high 10 ns

SRC4192, SRC4193
Switching Characteristics (continued)

tSIL BCKI pulsewidth low 10 ns
tLDIS SDIN data setup time 10 ns
tLDIH SDIN data hold time 10 ns
OUTPUT SERIAL PORT TIMING
tDOPD SDOUT data delay time 10 ns
tDOH SDOUT data hold time 2 ns
tSOH BCKO pulsewidth high 10 ns
tSOL BCKO pulsewidth low 5 ns
TDM MODE TIMING
tLROS LRCKO setup time 10 ns
tLROH LRCKO hold time 10 ns
tTDMS TDMI data setup time 10 ns
tTDMH TDMI data hold time 10 ns
SPI TIMING
CCLK frequency 25 MHz
tCDS CDATA setup time 12 ns
tCDH CDATA hold time 8 ns
tCSCR CS falling to CCLK rising 15 ns
tCFCS CCLK falling to CS rising 12 ns
6.7 Typical Characteristics

At TA = 25°C, VDD = 3.3 V, and VIO = 3.3 V, unless otherwise noted.
0 –60
–20 –70
–80
–40
–90
–60 –100
–80 –110
dBFS
dBFS
–120
–100
–130
–120 –140
–140 –150
–160
–160
–170
–180 –180
0 20k 40k 60k 80k 96k 0 20k 40k 60k 80k 96k
Frequency (Hz) Frequency (Hz)
12 kHz:192 kHz 12 kHz:192 kHz
Figure 1. FFT With 1-kHz Input Tone at 0 dBFS Figure 2. FFT With 1-kHz Input Tone at –60 dBFS

SRC4192, SRC4193
Typical Characteristics (continued)

0 –60
–20 –70
–80
–40
–90
–60 –100
–80 –110
dBFS
dBFS
–120
–100
–130
–120 –140
–140 –150
–160
–160
–170
–180 –180
0 5k 10k 15k 20k 24k 0 5k 10k 15k 20k 24k
0 –60
–20 –70
–80
–40
–90
–60 –100
–80 –110
dBFS
dBFS
–120
–100
–130
–120 –140
–140 –150
–160
–160
–170
–180 –180
0 5k 10k 15k 20k 24k 0 5k 10k 15k 20k 24k
44.1 kHz:48 kHz 44.1 kHz:48 kHz
0 –60
–20 –70
–80
–40
–90
–60 –100
–80 –110
dBFS
dBFS
–120
–100
–130
–120 –140
–140 –150
–160
–160
–170
–180 –180
0 10k 20k 30k 40k 48k 0 10k 20k 30k 40k 48k
44.1 kHz:96 kHz 44.1 kHz:96 kHz

SRC4192, SRC4193

0 –60
–20 –70
–80
–40
–90
–60 –100
–80 –110
dBFS
dBFS
–120
–100
–130
–120 –140
–140 –150
–160
–160
–170
–180 –180
0 20k 40k 60k 80k 96k 0 20k 40k 60k 80k 96k
44.1 kHz:192 kHz 44.1 kHz:192 kHz
0 –60
–70
–20
–80
–40
–90
–60 –100
–110
dBFS
dBFS
–80
–120
–100
–130
–120 –140
–140 –150
–160
–160
–170
–180 –180
0 5k 10k 15k 20k 22k 0 5k 10k 15k 20k 22k
48 kHz:44.1 kHz 48 kHz:44.1 kHz
0 –60
–20 –70
–80
–40
–90
–60 –100
–80 –110
dBFS
dBFS
–120
–100
–130
–120 –140
–140 –150
–160
–160
–170
–180 –180
0 10k 20k 30k 40k 48k 0 10k 20k 30k 40k 48k

SRC4192, SRC4193

0 –60
–20 –70
–80
–40
–90
–60 –100
–80 –110
dBFS
dBFS
–120
–100
–130
–120 –140
–140 –150
–160
–160
–170
–180 –180
0 20k 40k 60k 80k 96k 0 20k 40k 60k 80k 96k
0 –60
–20 –70
–80
–40
–90
–60 –100
–110
dBFS
dBFS
–80
–120
–100
–130
–120 –140
–140 –150
–160
–160
–170
–180 –180
0 5k 10k 15k 20k 22k 0 5k 10k 15k 20k 22k
96 kHz:44.1 kHz 96 kHz:44.1 kHz
0 –60
–20 –70
–80
–40
–90
–60 –100
–80 –110
dBFS
dBFS
–120
–100
–130
–120 –140
–140 –150
–160
–160
–170
–180 –180
0 5k 10k 15k 20k 24k 0 5k 10k 15k 20k 24k

SRC4192, SRC4193

0 –60
–20 –70
–80
–40
–90
–60 –100
–80 –110
dBFS
dBFS
–120
–100
–130
–120 –140
–140 –150
–160
–160
–170
–180 –180
0 20k 40k 60k 80k 96k 0 20k 40k 60k 80k 96k
0 –60
–70
–20
–80
–40
–90
–60 –100
–110
dBFS
dBFS
–80
–120
–100
–130
–120 –140
–140 –150
–160
–160
–170
–180 –180
0 1k 2k 3k 4k 5k 6k 0 1k 2k 3k 4k 5k 6k
0 –60
–70
–20
–80
–40
–90
–60 –100
–110
dBFS
dBFS
–80
–120
–100
–130
–120 –140
–140 –150
–160
–160
–170
–180 –180
0 2.5 5k 7.5k 10k 12.5k 15k 16k 0 2.5k 5k 7.5k 10k 12.5k 15k 16k

SRC4192, SRC4193

0 –60
–70
–20
–80
–40
–90
–60 –100
–110
dBFS
dBFS
–80
–120
–100
–130
–120 –140
–140 –150
–160
–160
–170
–180 –180
0 5k 10k 15k 20k 22k 0 5k 10k 15k 20k 22k
192 kHz:44.1 kHz 192 kHz:44.1 kHz
0 –60
–20 –70
–80
–40
–90
–60 –100
–80 –110
dBFS
dBFS
–120
–100
–130
–120 –140
–140 –150
–160
–160
–170
–180 –180
0 5k 10k 15k 20k 24k 0 10k 20k 30k 40k 24k
0 –60
–20 –70
–80
–40
–90
–60 –100
–80 –110
dBFS
dBFS
–120
–100
–130
–120 –140
–140 –150
–160
–160
–170
–180 –180
0 10k 20k 30k 40k 48k 0 10k 20k 30k 40k 48k

SRC4192, SRC4193

0 0
–20 –20
–40 –40
–60 –60
–80
dBFS
dBFS
–80
–100 –100
–120 –120
–140 –140
–160 –160
–180 –180
0 5k 10k 15k 20k 24k 0 5k 10k 15k 20k 22k
44.1 kHz:48 kHz 48 kHz:44.1 kHz
Figure 33. FFT With 20-kHz Input Tone at 0 dBFS Figure 34. FFT With 20-kHz Input Tone at 0 dBFS
0 0
–20 –20
–40 –40
–60 –60
–80 –80
dBFS
dBFS
–100 –100
–120 –120
–140 –140
–160 –160
–180 –180
0 5k 10k 15k 20k 24k 0 10k 20k 30k 40k 48k
0 0
–20 –20
–40 –40
–60 –60
–80 –80
dBFS
dBFS
–100 –100
–120 –120
–140 –140
–160 –160
–180 –180
0 5k 10k 15k 20k 24k 0 20k 40k 60k 80k 96k

SRC4192, SRC4193

–120 –120
Total Harmonic Distortion+Noise (dB)

–125 –125
–130 –130
–135 –135
–140 –140
–145 –145
–150 –150
–155 –155
–160 –160
–140 –120 –100 –80 –60 –40 –20 0 –140 –120 –100 –80 –60 –40 –20 0
Input Amplitude (dBFS) Input Amplitude (dBFS)
44.1 kHz:48 kHz 48 kHz:44.1 kHz
Figure 39. THD+N vs Input Amplitude fIN = 1 kHz Figure 40. THD+N vs Input Amplitude fIN = 1 kHz
–120 –120
–125 Total Harmonic Distortion+Noise (dB) –125
–130 –130
–135 –135
–140 –140
–145 –145
–150 –150
–155 –155
–160 –160
–140 –120 –100 –80 –60 –40 –20 0 –140 –120 –100 –80 –60 –40 –20 0
–120 –120
–125 –125
–130 –130
–135 –135
–140 –140
–145 –145
–150 –150
–155 –155
–160 –160
–140 –120 –100 –80 –60 –40 –20 0 –140 –120 –100 –80 –60 –40 –20 0
44.1 kHz:192 kHz 192 kHz:48 kHz

SRC4192, SRC4193

–120 –120

–125 –125
–130 –130
–135 –135
–140 –140
–145 –145
–150 –150
–155 –155
–160 –160
0 5k 10k 15k 20k 0 5k 10k 15k 20k
Input Frequency (Hz) Input Frequency (Hz)
44.1 kHz:48 kHz 48 kHz:44.1 kHz
Figure 45. THD+N vs Input Frequency, 0-dBFS Input Figure 46. THD+N vs Input Frequency, 0-dBFS Input
–120 –120
–125 Total Harmonic Distortion+Noise (dB) –125
–130 –130
–135 –135
–140 –140
–145 –145
–150 –150
–155 –155
–160 –160
0 5k 10k 15k 20k 0 5k 10k 15k 20k
Input Frequency (Hz) Input Frequency (Hz)
Figure 47. THD+N vs Input Frequency, 0-dBFS Input Figure 48. THD+N vs Input Frequency, 0-dBFS Input
0 0
–10 –10
–20 –20
Output Amplitude (dBFS)
–30 –30
–40 –40
–50 –50
–60 –60
–70 –70
–80 –80
–90 –90
–100 –100
–110 –110
–120 –120
–130 –130
–140 –140
– 140– 130 – 120 – 110 – 100 – 90 – 80 – 70 – 60 – 50 – 40 – 30 – 20 – 10 0 – 140– 130 – 120 – 110 – 100 – 90 – 80 – 70 – 60 – 50 – 40 – 30 – 20 – 10 0
44.1 kHz:48 kHz 48 kHz:44.1 kHz
Figure 49. Linearity With fIN = 200 Hz Figure 50. Linearity With fIN = 200 Hz

SRC4192, SRC4193

0 0
–10 –10
–20 –20

–30 –30
–40 –40
–50 –50
–60 –60
–70 –70
–80 –80
–90 –90
–100 –100
–110 –110
–120 –120
–130 –130
–140 –140
– 140– 130 – 120 – 110 – 100 – 90 – 80 – 70 – 60 – 50 – 40 – 30 – 20 – 10 0 – 140–130–120– 110 –100 –90 –80 – 70 –60 –50 –40 –30 – 20 –10 0
0 0
–10 –10
–20 Output Amplitude (dBFS) –20
–30 –30
–40 –40
–50 –50
–60 –60
–70 –70
–80 –80
–90 –90
–100 –100
–110 –110
–120 –120
–130 –130
–140 –140
– 140– 130 – 120 – 110 – 100 – 90 – 80 – 70 – 60 – 50 – 40 – 30 – 20 – 10 0 – 140– 130 – 120 – 110 – 100 – 90 – 80 – 70 – 60 – 50 – 40 – 30 – 20 – 10 0
96 kHz:48 kHz 44.1 kHz:192 kHz
0 0
–10 –10
–20 –20
–30
–30
–40 –40
–50 –50
–60 –60
dBFS
–70
–70
–80
–80
–90
–90
–100
–100 –110
–110 –120 192kHz:32kHz
–120 –130 192kHz:48kHz
–130 –140 192kHz:96kHz
–140 –150
– 140– 130 – 120 – 110 – 100 – 90 – 80 – 70 – 60 – 50 – 40 – 30 – 20 – 10 0 0 10k 20k 30k 40k 50k 60k
Input Amplitude (dBFS) Frequency (Hz)
192 kHz:44.1 kHz
Figure 55. Linearity With fIN = 200 Hz Figure 56. Frequency Response With 0-dBFS Input

SRC4192, SRC4193

0 0
–0.004
–0.009 –0.01
–0.014
–0.019 –0.02
(dBFS)
dBFS
–0.024
–0.029 –0.03
–0.034
–0.039 –0.04
–0.044
–0.049 –0.05
0 2k 4k 6k 8k 10k 12k 14k 16k 18k 20k 22k 0 5k 10k 15k 20k 22k
Frequency (Hz) Input Amplitude (dBFS)
48k:48k 192k:48k
Figure 57. Pass Band Ripple Figure 58. Pass Band Ripple

SRC4192, SRC4193
7 Detailed Description
7.1 Overview
The SRC4192 and SRC4193 devices are asynchronous, sample-rate converters (ASRC) designed for
professional audio applications. Operation at input and output sampling frequencies up to 212 kHz is supported,
with an input and output sampling ratio range of 16:1 to 1:16. Excellent dynamic range and Total Harmonic
Distortion + Noise (THD+N) are achieved by employing high-performance, linear-phase digital filtering with image
rejection better than 140 dB. Digital filtering options allow for lower group-delay processing. These include a low
group-delay option for the interpolation and resampler function, as well as a direct down-sampling option for the
decimation function (SRC4193 device only).
The audio input and output ports support standard audio data formats, as well as a TDM interface mode. Word
lengths of 24-, 20-, 18-, and 16-bits are supported. Both ports may operate in slave mode, deriving their word
and bit clocks from external input and output devices. Alternatively, one port may operate in master mode while
the other remains in slave mode. In master mode, the LRCK and BCK clocks are derived from the reference
clock input, RCKI. The flexible configuration of the input and output ports allows connection to a wide variety of
audio data converters, interface devices, digital signal processors, and programmable logic.
A bypass mode is included, which allows audio data to be passed directly from the input port to the output port,
bypassing the ASRC function. The bypass option is useful for passing through encoded or compressed audio
data, or nonaudio control or status data.
A soft mute function is available on both the SRC4192 and SRC4193 devices. Digital output attenuation is
available only for the SRC4193 device. Both soft mute and digital attenuation functions provide artifact-free
operation, while allowing muting or level adjustment of the audio output signal. The mute attenuation is typically
–144 dB, while the digital attenuation control is adjustable from 0 dB to –127.5 dB in 0.5-dB steps.
The SRC4193 device includes a three-wire SPI port to access on-chip control registers for configuration of
internal functions. The port can be easily interfaced to microprocessors or digital signal processors with
synchronous serial port peripherals.
Functional Block Diagram shows a functional block diagram of the SRC4192 and SRC4193 devices. Audio data
is received at the input port, clocked by either the audio data source in slave mode, or by the SRC419x in master
mode. The output-port data is clocked by either the audio data source in slave mode, or by the SRC419x in
master mode. The input data is passed through interpolation filters which up-sample the data, which is then
passed on to the resampler. The rate estimator compares the input and output sampling frequencies by
comparing LRCKI, LRCKO, and a reference clock. The results include an offset for the FIFO pointer and the
coefficients needed for re-sampling function.
The output of the resampler is passed on to either the decimation filter or direct down-sampler function. The
decimation filter performs down-sampling and anti-alias filtering functions, and is required when the output
sampling frequency is lower than the input-sampling frequency. The direct down-sampler function does not
provide any filtering, and may be used in cases when aliasing is not an issue. This includes the case when the
output sampling frequency is equal to or greater than the input sampling frequency. The advantage of direct
down-sampling is a significant reduction in the group delay associated with the decimation filter, allowing lower
latency sample rate conversion. The direct down-sampler function is available only for the SRC4193 device.

SRC4192, SRC4193
7.2 Functional Block Diagram
LRCKI Audio fSIN Interpolation 16fSIN 16fSOUT

BCKI Input Re-Sampler
Filters
Port
SDIN
MODE [2:0]
IFMT [2:0
REFCLK
OFMT [1:0] LRCKI
Control
OWL [1:0]
Logic
MUTE (SRC4192) Rate
BYPAS Estimator
LGRP
RST LRCKO
RDY
MUTE RATIO (SRC4193 only)
BYPASS
SPI and
RST
Control Logic fSOUT Decimation
CS (SRC4193) Filters
CCLK
CDATA
fSOUT Direct
LRCKO
Audio Down-Sampler
BCKO (SRC4193 only)
Output Mux
SDOUT Port
TDMI
VDD
DGND
Reference Power
VIO
RCKI REFCLK
Clock
DGND
7.3 Feature Description
7.3.1 Input Port Operation

The audio input port is a three-wire synchronous serial interface that can operate in either slave or master mode.
The SDIN input (pin 4) is the serial audio data input. Audio data is input at this pin in one of three standard audio
data formats: Philips I2S, Left-Justified, or Right-Justified. The audio data word length may be up to 24-bits for
I2S and Left-Justified formats, while the Right-Justified format supports 16-, 18-, 20-, or 24-bit data. The data
formats are shown in Figure 59, while critical timing parameters are shown in Figure 60 and listed in Electrical
Characteristics.

SRC4192, SRC4193
Feature Description (continued)
Left Channel Right Channel
LRCKO
BCKI
SDIN MSB LSB MSB LSB
(a) Left Justified Data Format
LRCKI
BCKI
(b) Right Justified Data Format
LRCKI
BCKI
(c) I2S Data Format
1/fS
Figure 59. Input Data Formats
LRCKI
tLRIS tSIH
BCKI
tLDIS tSIL
SDIN
tLDIH
Figure 60. Input Port Timing
The bit clock is either an input or output at BCKI (pin 5). In slave mode, BCKI is configured as an input pin, and
may operate at rates from 32fS to 128fS,with a minimum of one clock cycle per data bit. In master mode, BCKI
operates at a fixed rate of 64fS.
The left/right word clock, LRCKI (pin 6), may be configured as an input or output pin. In slave mode, LRCKI is an
input pin, while in master mode LRCKI is an output pin. In either case, the clock rate is equal to fS, the input
sampling frequency. The LRCKI duty cycle is fixed to 50% for master mode operation.
Table 1 shows data format selection for the input port. For the SRC4192, the IFMT0 (pin 10), IFMT1 (pin 11),
and IFMT2 (pin 12) inputs are used to set the input port data format. For the SRC4193, the IFMT[2:0] bits in
Control Register 3 are used to select the data format.

SRC4192, SRC4193
Feature Description (continued)

Table 1. Input Port Data Format Selection
IFMT2 IFMT1 IFMT0 INPUT PORT DATA FORMAT
0 0 0 24-Bit Left Justified
0 0 1 24-Bit I2S
0 1 0 Unused
0 1 1 Unused
1 0 0 16-Bit Right Justified
7.3.2 Output Port Operation

The audio output port is a four-wire synchronous serial interface that can operate in either Slave or Master mode.
The SDOUT output (pin 23) is the serial audio data output. Audio data is output at this pin in one of four data
formats: Philips I2S, Left-Justified, Right-Justified, or TDM. The audio data word length may be 16-, 18-, 20-, or
24-bits. For all word lengths, the data is triangular PDF dithered from the internal 28-bit data path. The data
formats (with the exception of TDM mode) are shown in Figure 61, while critical timing parameters are shown in
Figure 62 and listed in Electrical Characteristics. The TDM format and timing are shown in Figure 72 and
Figure 73, respectively, while examples of standard TDM configurations are shown in Figure 74 and Figure 75
Left Channel Right Channel
LRCKO
BCKO
SDOUT MSB LSB MSB LSB
(a) Left Justified Data Format
LRCKO
BCKO
(b) Right Justified Data Format
LRCKO
BCKO
(c) I2S Data Format
1/fS
Figure 61. Output Data Formats

SRC4192, SRC4193
LRCKO
tSOH
BCKO
tDOPD tSOL
SDOUT
tDOH
Figure 62. Output Port Timing
The bit clock is either input or output at BCKO (pin 25). In Slave mode, BCKO is configured as an input pin, and
can operate at rates from 32fS to 128fS, with a minimum of one clock cycle for each data bit. The exception is the
TDM mode, where the BCKO must operate at N × 64fS, where N is equal to the number of SRC4192 or
SRC4193 devices included on the TDM interface. In master mode, BCKO operates at a fixed rate of 64fS for all
data formats except TDM, where BCKO operates at the reference clock (RCKI) frequency. Additional information
regarding TDM mode operation is included in Application and Implementation.
The left/right word clock, LRCKO (pin 24), can be configured as an input or output pin. In slave mode, LRCKO is
an input pin, while in master mode it is an output pin. In either case, the clock rate is equal to fS, the output
sampling frequency. The clock duty cycle is fixed to 50% for I2S, Left-Justified, and Right-Justified formats in
master mode. The LRCKO pulse width is fixed to 32 BCKO cycles for the TDM format in master mode.
Table 2 illustrates data format selection for the output port. For the SRC4192, the OFMT0 (pin 19), OFMT1 (pin
18), OWL0 (pin 17), and OWL1 (pin 16) inputs are used to set the output port data format and word length. For
the SRC4193, the OFMT[1:0] and OWL[1:0] bits in Control Register 3 are used to select the data format and
word length.
Table 2. Output Port Data Format Selection

OFMT1 OFMT0 OUTPUT PORT DATA FORMAT
0 0 Left-Justified
0 1 I2S
1 0 TDM
1 1 Right-Justified
OWL1 OWL0 OUTPUT PORT DATA WORD LENGTH
0 0 24-Bits
0 1 20-Bits
1 0 18-Bits
1 1 16-Bits
7.3.3 Soft Mute Function

The soft mute function of the SRC419x device is invoked by forcing the MUTE input (pin 14) high. For the
SRC4193 device, the mute function may also be accessed using the MUTE bit in Control Register 1. The soft
mute function slowly attenuates the output signal level down to all zeroes plus ±1LSB of dither. This provides an
artifact-free muting of the audio output port.
7.3.4 Digital Attenuation (SRC4193 Only)

The SRC4193 device includes independent digital attenuation for the left and right audio channels. The
attenuation ranges from 0 dB (or unity) to –127.5 dB in 0.5-dB steps. The attenuation settings are programmed
using Control Registers 4 and 5, corresponding to the left and right channels, respectively.
The TRACK bit in Control Register 1 selects independent or tracking attenuation modes. When TRACK = 0, the
left and right channels are controlled independently. When TRACK = 1, the attenuation setting for the left
channel is also used for the right channel, and the right channel is said to track the left channel attenuation
setting.

SRC4192, SRC4193
7.3.5 Ready Output

The SRC419x device includes an active low ready output named RDY (pin 15). This is an output from the rate
estimator block, which indicates that the input-to-output sampling frequency ratio has been determined. The
ready signal can be used as a flag or indicator output. The ready signal can also be connected to the active high
MUTE input (pin 14) to provide an auto-mute function, so that the output port is muted when the rate estimator is
in transition.
7.3.6 Ratio Output (SRC4193 Only)

The SRC4193 device includes a simple ratio flag output named RATIO (pin 16). When RATIO is low, it indicates
that the output sampling frequency is lower than the input sampling frequency. When RATIO is high, it indicates
that the output sampling frequency is higher than the input sampling frequency. The ratio output can be used as
an indicator or flag output for an LED or host device.
7.3.7 Serial Peripheral Interface (SPI) Port: SRC4193 Only

The SPI port is a three-wire synchronous serial interface used to access the on-chip control registers of the
SRC4193 device. The interface is comprised of a serial data clock input, CCLK (pin 27), a serial data input,
CDATA (pin 28), and an active low chip-select input, CS (pin 26). Figure 63 shows the protocol for writing control
registers using the serial control port. Figure 64 shows the critical timing parameters for the SPI port interface,
which are also listed in Electrical Characteristics.
Set CS = 1 here to write one register or buffer location. Keep CS = 0 to enable auto-increment mode.
CS
Header Register or Buffer Data

CDIN Byte 0 Byte 1 Byte 2 Byte 3 Byte N
CCLK
BYTE DEFINITION
MSB LSB
BYTE 0: 0 0 0 0 0 A2 A1 A0
Register Address
Set to 0.
Set to 0.
Byte 1: All 8 bits are Don’t Care. Set to 0 or 1.

Bytes 2 through N: Register Data.
All Bytes are written MSB first.
Figure 63. SPI Port Protocol
tCFCS
CS
tCSCR tCDS
CCLK
tCDH
CDATA
Figure 64. SPI Port Timing

SRC4192, SRC4193
Byte 0 indicates the address of the control register to be written. The two most significant bits are set to 0, while
the six least significant bits contain the control register address. Byte 1 is a don’t care byte. This byte is included
in the protocol to maintain compatibility with current and future Texas Instruments digital audio products,
including the DIT4096 and DIT4192 digital audio transmitters. Byte 2 contains the 8-bit data for the control
register addressed in Byte 0.
As shown in Figure 63, a write sequence starts by bringing the CS input low. Bytes 0, 1, and 2 are then written to
program a single control register. Bringing the CS input high after the third byte will write just one register.
However, if CS remains low after writing the first control byte, the port will autoincrement the address by 1,
allowing successive addresses to be written. The address is automatically incremented by 1 after each byte is
written, as long as the CS input remains low. This is referred to as auto-increment operation, and is always
enabled for the SPI port.
7.4 Device Functional Modes
7.4.1 Reset and Power Down Operation

The SRC419x device can be reset using the RST input (pin 13). There is no internal power-on reset, so the user
should force a reset sequence after power up to initialize the device. To force a reset, the reference clock input
must be active, with an external clock source supplying a valid reference clock signal (refer to Figure 80). The
user must assert RST low for a minimum of 500 ns, and then bring RST high again to force a reset. Figure 65
shows the reset timing for the SRC419x device.
For the SRC4193, there is an additional 500 µs delay after the RST rising edge, due to internal logic
requirements. The customer should wait at least 500 µs after the RST rising edge before attempting to write to
the SPI port of the SRC4193 device.
The SRC419x device also supports a power-down mode. Power-down mode may be set by either holding the
RST input low (SRC4192 and SRC4193 devices), or by setting the PDN bit in Control Register 1 to zero
(SRC4193 device only). The SRC4193 device will be in power-down mode by default after an external reset has
been issued. To enable normal operation for the SRC4193, disable power down mode by writing a 1 to the PDN
bit in Control Register 1.
When using the PDN bit in Control Register 1 to enable power-down mode for the SRC4193, the current state of
the control registers is maintained through the power-down and power-up transition.
RCKI
RST
tRSTL > 500ns
Figure 65. Reset Pulse Width Requirement
7.4.2 Audio Port Modes

The SRC4192 and SRC4193 devices both support seven serial-port modes, shown in Table 3. For the SRC4192
device, the audio port mode is selected using the MODE0 (pin 26), MODE1 (pin 27), and MODE2 (pin 28) inputs.
For the SRC4193 device, the mode is selected using the MODE[2:0] bits in Control Register 1. The default mode
setting for the SRC4193 device is both input and output ports set to slave mode.
In slave mode, the port LRCK and BCK clocks are configured as inputs, and receive their clocks from an external
audio device. In master mode, the LRCK and BCK clocks are configured as outputs, being derived from the
reference clock input (RCKI). Only one port can be set to master mode at any given time, as indicated in Table 3.
Table 3. Setting the Serial Port Modes

MODE2 MODE1 MODE0 SERIAL PORT MODE
0 0 0 Both Input and Output Ports are Slave mode
0 0 1 Output Port is Master mode with RCKI = 128 fS

SRC4192, SRC4193
Device Functional Modes (continued)

Table 3. Setting the Serial Port Modes (continued)
MODE2 MODE1 MODE0 SERIAL PORT MODE
1 0 0 Both Input and Output Ports are Slave mode
1 0 1 Input Port is Master mode with RCKI = 128 fS
7.4.3 Bypass Mode

The SRC419x device includes a bypass function, which routes the input port data directly to the output port
bypassing the ASRC function. Bypass mode may be invoked by forcing the BYPAS input (pin 9) high for the
devices. The bypass mode may also be accessed for the SRC4193 device using the BYPAS bit in Control
Register 1. The BYPAS pin and control bit should be set to 0 for normal operation.
No dithering is applied to the output data in bypass mode, and the digital attenuation and mute functions are also
unavailable.
7.5 Register Maps
7.5.1 Control Register Map (SRC4193 Device Only)

The control register map for the SRC4193 device is shown in Table 4. Register 0 is reserved for factory use and
defaults to all zeros upon reset. Avoid writing this register, as unexpected operation may result if Register 0 is
programmed to an arbitrary value. Registers 1 through 5 contain control bits used to configure the internal
functions of the SRC4193. All other register addresses are reserved and should not be used in customer
applications.
Table 4. SRC4193 Device Control Register Map

Register
Address D7 (MSB) D6 D5 D4 D3 D2 D1 D0 (LSB)
(Dec/Hex)
0 0 0 0 0 0 0 0 0
1 PDN TRACK 0 MUTE BYPAS MODE2 MODE1 MODE0
2 0 0 0 0 0 0 DFLT LGRP
3 OWL1 OWL0 OFMT1 OFMT0 0 IFMT2 IFMT1 IFMT0
4 AL7 AL6 AL5 AL4 AL3 AL2 AL1 AL0
5 AR7 AR6 AR5 AR4 AR3 AR2 AR1 AR0

SRC4192, SRC4193
7.5.1.1 System Control Register
Table 5. System Control Register Field Descriptions

Bit Field Description
7 PDN Power Down
Setting this bit to 0 sets the SRC4193 to the power-down state. All other
register settings are preserved and the SPI port remains active. (Default)
Setting this bit to 1 powers up the SRC4193 using the current register
settings.
6 TRACK Digital Attenuation Tracking
0 = Tracking Off: Attenuation for the Left and Right channels is controlled
independently. (Default)
1 = Tracking On: Left channel attenuation setting is used for both channels.
5 Reserved
4 MUTE Output Soft Mute
This bit is logically OR’d with the MUTE input (pin 14)
0 = Soft mute disabled (Default)
1 = Soft mute enabled with data attenuated to all 0s
3 BYPAS Bypass Mode
This bit is logically OR’d with the BYPAS input (pin 9)
0 = Bypass Mode disabled with normal ASRC operation. (Default)
1 = Bypass Mode enabled with data routed directly from the input port to the
output port, bypassing the ARSC function.
2-0 MODEx Audio Serial Port Mode
See Table 3.
7.5.1.2 Filter Control Register
Figure 66. Filter Control Register

7 6 5 4 3 2 1 0
Reserved DFLT LGRP
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 6. Filter Control Register Field Descriptions

7-2 Reserved
1 DFLT Decimation Filtering / Direct Down-Sampling
The DFLT bit enables or disables the direct down-sampling function.
0 = Decimation filter enabled (default) (Must be used when fSOUT is less than
fSIN)
1 = Direct down-sampling enabled without filtering. (May be enabled when
fSOUT is equal to or greater than fSIN)
0 LGRP Low Group Delay
This bit selects the number of input audio samples to be stored in the data
buffer before the ASRC starts processing the audio data.
0 = Normal delay, 64 samples (default)
1 = Low delay, 32 samples

SRC4192, SRC4193
7.5.1.3 Audio Data Format Register
Figure 67. Audio Data Format Register

7 6 5 4 3 2 1 0
OWL1 OWL0 OFMT1 OFMT0 Reserved IFMT2 IFMT1 IFMT0
Table 7. Audio Data Format Register Field Descriptions

7-6 OWLx Output Port Data Word Length
See Table 2.
5-4 OFMTx Output Port Data Format
See Table 2.
3 Reserved
2-0 IFMTx Input Port Data Format
See Table 1.
7.5.1.4 Digital Attenuation Register – Left Channel
Figure 68. Digital Attenuation Register – Left Channel

7 6 5 4 3 2 1 0
AL7 AL6 AL5 AL4 AL3 AL2 AL1 AL0
Table 8. Digital Attenuation Register – Left Channel Field Descriptions

7-0 ALx Register defaults to 00HEX, or 0 dB (unity gain).
Output Attenuation (dB) = (–N × 0.5), where N = AL[7:0]DEC
7.5.1.5 Digital Attenuation Register – Right Channel
Figure 69. Digital Attenuation Register – Right Channel

7 6 5 4 3 2 1 0
AR7 AR6 AR5 AR4 AR3 AR2 AR1 AR0
Table 9. Digital Attenuation Register – Right Channel Field Descriptions

7-0 ARx Register defaults to 00HEX, or 0 dB (unity gain).
Output Attenuation (dB) = (–N × 0.5), where N = AR[7:0]DEC
When the TRACK bit in Control Register 1 is set to 1, the Left Channel attenuation setting will be used
for the Right Channel attenuation.

SRC4192, SRC4193
8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information

This section of the data sheet provides practical applications information for hardware and systems engineers
designing the SRC4192 and SRC4193 devices into the end equipment.
8.1.1 Interfacing to Digital Audio Receivers and Transmitters

The input and output ports of the SRC4192 and SRC4193 devices are designed to interface to a variety of audio
devices, including receivers and transmitters commonly used for AES/EBU, S/PDIF, and CP1201
communications.
Texas Instruments manufactures the DIR1703 digital audio interface receiver and DIT4096/4192 digital audio
transmitters to address these applications.
Figure 70 shows interfacing the DIR1703 device to the input port of the SRC4192 or SRC4193 device. The
DIR1703 device operates from a single 3.3-V supply, which requires the VIO supply (pin 7) for the SRC4192 or
SRC4193 device to be set to 3.3 V for interface compatibility.
DIR1703 SRC4192, SRC4193
LRCKO LRCKI
AES3, S/PDIF BCKO BCKI

RCV DIN
Input DATA SDIN
SCKO
RCLI
Clock
Generator
Clock
Select
Assumes VIO = +3.3V for SRC4192, SRC4293
Figure 70. Interfacing the SRC4193 to the DIR1703 Digital Audio Interface Receiver
Figure 71 shows the interface between the output port of the SRC4192 or SRC4193 device and the audio serial
port of the DIT4096 or DIT4192 device. Again, the VIO supplies for both the SRC419x device and DIT4096/4192
device are set to 3.3 V for compatibility.

SRC4192, SRC4193
Application Information (continued)
SRC4192, SRC4193 DIT4096, DIT4192
LRCKO SYNC TX+ AES3, S/PDIF

BCKO SCLK TX– OUTPUT
SDOUT SDATA
RCKI
MCLK
REF Clock
Generator
DIT Clock
Generator
Clock
Select
Assumes VIO = +3.3V for SRC4192, SRC4293 and DIT4096, DIT4192
Figure 71. Interfacing the SRC4193 to the DIT4096/4192 Digital Audio Interface Transmitter
Like the output port of the SRC4192 or SRC4193 device, the audio serial port of the DIT4096 and DIT4192
device can be configured as a master or slave. In cases where the output port of the SRC419x device is set to
master mode, use the reference clock source (RCKI) as the master clock source (MCLK) for the DIT4096/4192
device, to ensure that the transmitter is synchronized to the output port data of the SRC419x device.
8.1.2 TDM Applications

The SRC4192 and SRC4193 devices support a TDM output mode, which allows multiple devices to be daisy-
chained together to create a serial frame. Each device occupies one subframe within a frame, and each sub-
frame carries two channels (Left followed by Right). Each sub-frame is 64 bits long, with 32 bits allotted for each
channel. The audio data for each channel is left justified within the allotted 32 bits. Figure 72 shows the TDM
frame format, while Figure 73 shows TDM input timing parameters, which are listed in Electrical Characteristics.
LRCKO
BCKO
SDOUT
Left Right Left Right Left Right

Sub-Frame 1 Sub-Frame 2 Sub-Frame N
One Frame = 1/fs
N = Number of Daisy-Chained Devices

One Sub-Frame contains 64 bits, with 32 bits per channel.
For each channel, the audio data is left justified, MSB first format, with the word length determined by the OWL[1:0] pins/bits.
Figure 72. TDM Frame Format

SRC4192, SRC4193
tLROS
LRCKO
tLROH
BCKO
tTDMS
TDMI
tTDMH
Figure 73. Input Timing for TDM Mode
The frame rate is equal to the output sampling frequency, fs. The BCKO frequency for the TDM interface is N ×
64fs, where N is the number of devices included in the daisy chain. For Master mode, the output BCKO
frequency is fixed to the reference clock (RCKI) input frequency. The number of devices that can be daisy-
chained in TDM mode is dependent upon the output sampling frequency and the BCKO frequency, leading to the
following numerical relationship:
Number of Daisy-Chained Devices = (fBCKO / fs) / 64
where
• fBCKO = Output Port Bit Clock (BCKO), 27.648-MHz maximum
• fs = Output Port Sampling (or LRCKO) Frequency, 216-kHz maximum. (1)
This relationship holds true for both slave and master modes.
Figure 74 and Figure 75 show typical connection schemes for TDM mode. Although the TMS320C671x DSP
device family is shown as the audio processing engine in these figures, other TI digital signal processors with a
multi-channel buffered serial port (McBSPTM) may also function with this arrangement. Interfacing to processors
from other manufacturers is also possible. Refer to Figure 62 in this data sheet, along with the equivalent serial
port timing diagrams shown in the DSP data sheet, to determine compatibility.
SRC4192, SRC4193 SRC4192, SRC4193 SRC4192, SRC4193 TMS320C671x
Slave #N Slave #2 Slave #1 McBSP
TDMI SDOUT TDMI SDOUT TDMI SDOUT DRn n = 0 or 1

LRCKO LRCKO LRCKO FSRn
BCKO BCKO BCKO CLKRn
RCKI RCKI RCKI CLKIN or CLKSn
Clock
Generator
Figure 74. TDM Interface where all Devices are Slaves

SRC4192, SRC4193
SRC4192, SRC4193 SRC4192, SRC4193 SRC4192, SRC4193 TMS320C671x

Master Slave #2 Slave #1 McBSP
TDMI SDOUT TDMI SDOUT TDMI SDOUT DRn n = 0 or 1

LRCKO LRCKO LRCKO FSRn
BCKO BCKO BCKO CLKRn
RCKI RCKI RCKI CLKIN or CLKSn
Clock
Generator
Figure 75. TDM Interface where one Device is Master to Multiple Slaves
8.2 Typical Application

Figure 76 and Figure 77 show typical connection diagrams for the SRC4192 and SRC4193 devices
(respectively). Recommended values for power supply bypass capacitors are included. These capacitors should
be placed as close to the IC package as possible.
From
Control SRC4192
Logic
1 28
LGRP MODE2
2 27
RCKI MODE1
3 26
NC MODE0
4 25
SDIN BCKO
Reference Audio Input 5 24
BCKI LRCKO
Clock Device 6 23
LRCKI SDOUT Audio Output
7 22 Device
VIO VDD
8 21
DGND DGND
9 20
BYPAS TDMI
10 19
IFMT0 OFMT0
11 18
IFMT1 OFMT1
12 17
IFMT2 OWL0
From/To 13 16
RST OWL1
Control 14 15
MUTE RDY
Logic
VIO = +1.65V to VDD VDD = +3.3V
To Pin 7 To Pin 22
10µF 0.1µF 0.1µF 10µF
To Pin 8 To Pin 21
Figure 76. Typical Connection Diagram for the SRC4192

SRC4192, SRC4193
Typical Application (continued)
Host
(MCU, DSP)
SRC4193
1 28
RCKI CDATA
2 27
NC CCLK
3 26
NC CS
4 25
SDIN BCKO
Reference Audio Input 5 24
BCKI LRCKO
Clock Device 6 23
LRCKI SDOUT Audio Output
7 22 Device
VIO VDD
8 21
DGND DGND
9 20
BYPAS TDMI
10 19
NC NC
11 18
NC NC
To/From 12 17
NC NC
Host 13 16
RST RATIO
or 14 15
MUTE RDY
Control
Logic
VIO = +1.65V to VDD VDD = +3.3V
To Pin 7 To Pin 22
10µF 0.1µF 0.1µF 10µF
To Pin 8 To Pin 21
Figure 77. Typical Connection Diagram for the SRC4193
8.2.1 Design Requirements

The following lists design requirements:
• Control: Hardware, I2C, or SPI
• Audio input: PCM serial data
• Audio output: PCM serial data
• Reference clock
8.2.2 Detailed Design Procedure
8.2.2.1 Control Method

The SRC4192 is a hardware controlled device while the SRC4193 is a software controlled device. The SRC4192
control pins can be connected to VDD or GND directly or by the GPIO of a host controller. The SRC4193 can
communicate over a 3 wire SPI.
8.2.2.2 Audio Input and Output

The Audio input and output ports can handle 16, 18, 20, or 24 bit right justified PCM serial data as well as 24 bit
I2S or left justified PCM serial data at up to a 212-kHz sampling rate. A TDM format is also available. Both input
and output can operate in slave mode, or one can operate as master while the other operates as a slave. A 16:1
or 1:16 is the max ratio supported between the input and output audio sampling rates.

SRC4192, SRC4193
Typical Application (continued)

8.2.3 Application Curves
0 0
–20 –20
–40 –40
–60 –60
–80 –80
dBFS
dBFS
–100 –100
–120 –120
–140 –140
–160 –160
–180 –180
0 5k 10k 15k 20k 24k 0 10k 20k 30k 40k 48k
44.1 kHz:48 kHz 44.1 kHz:96 kHz
9 Power Supply Recommendations

To ensure compatibility, the VDD_IO and VDD_CORE supplies of the AD1896 device must be set to 3.3 V, while
the VIO and VDD supplies of the SRC4192 device must be set to 3.3 V.
10 Layout
10.1 Layout Guidelines
10.1.1 Reference Clock

The SRC4192 and SRC4193 devices require a reference clock for operation. The reference clock is applied at
the RCKI input (pin 1 for the SRC4193 device, pin 2 for the SRC4192 device). Figure 80 shows the reference
clock connections and requirements for the SRC4192 and SRC4193 devices. The reference clock may operate
at 128fS, 256fS, or 512fS, where fS are the input or output sampling frequency. The maximum external reference
clock input frequency is 50 MHz.
SRC4192 SRC4193
RCKI RCKI
2 1
From External From External

Clock Source Clock Source
50MHz max 50MHz max
tRCKIP
RCKI tRCKIP > 20ns min

tRCKIH > 0.4 tRCKIP
tRCKIL > 0.4 tRCKIP
tRCKIH tRCKIL
Figure 80. Reference Clock Input Connections and Timing Requirements

SRC4192, SRC4193
Layout Guidelines (continued)

10.1.2 Pin Compatibility With the Analog Devices AD1896 (SRC4192 Only)
The SRC4192 device is pin-and function-compatible with the AD1896 device when observing the guidelines
indicated in the following paragraphs.
10.1.2.1 Crystal Oscillator

The SRC4192 does not have an on-chip crystal oscillator. An external reference clock is required at the RCKI
input (pin 2).
10.1.2.2 Reference Clock Frequency

The reference clock input frequency for the SRC4192 must be no higher than 30 MHz, to match the master clock
frequency specification of the AD1896 device. In addition, the SRC4192 device does not support the 768fS
reference clock rate.
10.1.2.3 Master Mode Maximum Sampling Frequency

When the input or output ports are set to master mode, the maximum sampling frequency must be limited to 96
kHz to support the AD1896 device specification. This is despite the fact that the SRC4192 device supports a
maximum sampling frequency of 212 kHz in master mode. The user should consider building an option into their
design to support the higher sampling frequency of the SRC4192 device.
10.1.2.4 Matched Phase Mode

Because of the internal architecture of the SRC4192 device, it does not require or support the matched phase
mode of the AD1896 device. Given multiple SRC4192 devices, if all reference clock (RCKI) inputs are driven
from the same clock source, the devices will be phase-matched.

SRC4192, SRC4193
10.2 Layout Example
1 LGRP MODE2 28
Control Logic
Reference Clock 2 RCKI MODE1 27
3 NC MODE0 26
4 SDIN SRC4192 BCKO 25
Audio Input 5 BCKI LRCKO 24

Device
6 LRCKI SDOUT 23
Audio Output
Device
1.65 V to VDD 7 VIO VDD 8
22 3.3 V
+ +
10 F
0.1 F 8 DGND DGND 21 0.1 F 10 F
9 BYPAS TDMI 20
10 IFMT0 OFMT0 19
11 IFMT1 OFMT1 18
Control Logic
12 IFMT2 OWL0 17 Control Logic
13 RST OWL1 16
14 MUTE RDY 15
Top layer ground pour(1) Via to bottom ground plane
Top layer signal traces Pad to top layer ground pour
(1) TI recommends placing a top-layer ground pour for shielding around the SRC4192 device and connecting it to the
lower main PCB-ground plane with multiple vias.
Figure 81. SRC4192 Layout Example

SRC4192, SRC4193
Layout Example (continued)
Reference Clock 1 RCKI CDATA 28
Host SPI
2 NC CCLK 27 Communication
3 NC CS 26
4 SDIN SRC4193 BCKO 25
Audio Input 5 BCKI LRCKO 24

Device
6 LRCKI SDOUT 23
Audio Output
Device
1.65 V to VDD 7 VIO VDD 8
22 3.3 V
+ +
10 F 0.1 F 8 DGND DGND 21 0.1 F 10 F
9 NC TDMI 20
10 NC NC 19
11 NC NC 18
12 NC NC 17
13 RST RATIO 16
Host or Control Host or Control
Logic Logic
14 MUTE RDY 15
Top layer ground pour(1) Via to bottom ground plane
Top layer signal traces Pad to top layer ground pour
(1) TI recommends placing a top-layer ground pour for shielding around the SRC4193 device and connecting it to the
lower main PCB-ground plane with multiple vias.
Figure 82. SRC4193 Layout Example

SRC4192, SRC4193
11 Device and Documentation Support
11.1 Documentation Support

11.1.1 Related Documentation
For related documentation, see the following: SRC4192EVM Evaluation Module, SBAU088
11.2 Related Links

The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 10. Related Links

TECHNICAL TOOLS & SUPPORT &
PARTS PRODUCT FOLDER SAMPLE & BUY
DOCUMENTS SOFTWARE COMMUNITY
SRC4192 Click here Click here Click here Click here Click here
SRC4193 Click here Click here Click here Click here Click here
11.3 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

PACKAGE OPTION ADDENDUM
www.ti.com 10-Dec-2020
PACKAGING INFORMATION
Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)
SRC4192IDB ACTIVE SSOP DB 28 50 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 SRC4192I
SRC4192IDBR ACTIVE SSOP DB 28 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 SRC4192I
SRC4192IDBRG4 ACTIVE SSOP DB 28 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 SRC4192I
SRC4193IDB ACTIVE SSOP DB 28 50 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 SRC4193I
SRC4193IDBR ACTIVE SSOP DB 28 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 SRC4193I
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com 10-Dec-2020
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com 26-Feb-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SRC4192IDBR SSOP DB 28 2000 330.0 16.4 8.1 10.4 2.5 12.0 16.0 Q1
SRC4193IDBR SSOP DB 28 2000 330.0 16.4 8.1 10.4 2.5 12.0 16.0 Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com 26-Feb-2019
*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SRC4192IDBR SSOP DB 28 2000 350.0 350.0 43.0
SRC4193IDBR SSOP DB 28 2000 350.0 350.0 43.0
Pack Materials-Page 2
PACKAGE OUTLINE
DB0028A SCALE 1.500
SSOP - 2 mm max height
SMALL OUTLINE PACKAGE
C
8.2
TYP
A 7.4
0.1 C SEATING
PIN 1 INDEX AREA
PLANE
26X 0.65
28
1
2X
10.5
8.45
9.9
NOTE 3
14
15
0.38
28X
0.22
5.6 0.15 C A B
B
5.0
NOTE 4
2 MAX
(0.15) TYP 0.25
SEE DETAIL A GAGE PLANE
0.95 0.05 MIN

0 -8 0.55
DETAIL A
A 15
TYPICAL
4214853/B 03/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-150.
www.ti.com
EXAMPLE BOARD LAYOUT
DB0028A SSOP - 2 mm max height
28X (1.85) SYMM
1 (R0.05) TYP
28X (0.45) 28
26X (0.65)
SYMM
14 15
(7)
LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE: 10X
SOLDER MASK METAL UNDER SOLDER MASK

METAL
OPENING SOLDER MASK OPENING
EXPOSED METAL EXPOSED METAL
0.07 MAX 0.07 MIN

ALL AROUND ALL AROUND
NON-SOLDER MASK SOLDER MASK

DEFINED DEFINED
(PREFERRED)
SOLDER MASK DETAILS
15.000
4214853/B 03/2018
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DB0028A SSOP - 2 mm max height
28X (1.85) SYMM

(R0.05) TYP
1
28X (0.45) 28
26X (0.65)
SYMM
14 15
(7)
SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE: 10X
4214853/B 03/2018
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
permission to use these resources only for development of an application that uses the TI products described in the resource. Other
reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third
party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims,
damages, costs, losses, and liabilities arising out of your use of these resources.
TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on
ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable
warranties or warranty disclaimers for TI products.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2020, Texas Instruments Incorporated

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Changes from Revision B (September 2007) to Revision C Page

Changes from Revision A (July 2003) to Revision B Page

2 Submit Documentation Feedback Copyright © 2003–2015, Texas Instruments Incorporated

Product Folder Links: SRC4192 SRC4193

5 Pin Configuration and Functions

SRC4192 DB Package SRC4193 DB Package

LGRP 1 28 MODE2 RCKI 1 28 CDATA

RCKI 2 27 MODE1 NC 2 27 CCLK

SDIN 4 25 BCKO SDIN 4 25 BCKO

BCKI 5 24 LRCKO BCKI 5 24 LRCKO

LRCKI 6 23 SDOUT LRCKI 6 23 SDOUT

VIO 7 SRC4192 22 VDD VIO 7 SRC4193 22 VDD

DGND 8 21 DGND DGND 8 21 DGND

BYPAS 9 20 TDMI BYPAS 9 20 TDMI

RST 13 16 OWL1 RST 13 16 RATIO

MUTE 14 15 RDY MUTE 14 15 RDY

Input-to-output ratio flag output

Copyright © 2003–2015, Texas Instruments Incorporated Submit Documentation Feedback 3

Pin Functions (continued)

6.2 ESD Ratings

6.3 Recommended Operating Conditions

4 Submit Documentation Feedback Copyright © 2003–2015, Texas Instruments Incorporated

Product Folder Links: SRC4192 SRC4193

6.4 Thermal Information

6.5 Electrical Characteristics

Electrical Characteristics (continued)

6.6 Switching Characteristics

6 Submit Documentation Feedback Copyright © 2003–2015, Texas Instruments Incorporated

Product Folder Links: SRC4192 SRC4193

Switching Characteristics (continued)

6.7 Typical Characteristics

Copyright © 2003–2015, Texas Instruments Incorporated Submit Documentation Feedback 7

Typical Characteristics (continued)

8 Submit Documentation Feedback Copyright © 2003–2015, Texas Instruments Incorporated

Product Folder Links: SRC4192 SRC4193

Typical Characteristics (continued)

Copyright © 2003–2015, Texas Instruments Incorporated Submit Documentation Feedback 9

Typical Characteristics (continued)

10 Submit Documentation Feedback Copyright © 2003–2015, Texas Instruments Incorporated

Product Folder Links: SRC4192 SRC4193

Typical Characteristics (continued)

Copyright © 2003–2015, Texas Instruments Incorporated Submit Documentation Feedback 11

Typical Characteristics (continued)

12 Submit Documentation Feedback Copyright © 2003–2015, Texas Instruments Incorporated

Product Folder Links: SRC4192 SRC4193

Typical Characteristics (continued)

Copyright © 2003–2015, Texas Instruments Incorporated Submit Documentation Feedback 13

Typical Characteristics (continued)

Total Harmonic Distortion+Noise (dB)

–125 Total Harmonic Distortion+Noise (dB) –125

Total Harmonic Distortion+Noise (dB)

14 Submit Documentation Feedback Copyright © 2003–2015, Texas Instruments Incorporated

Product Folder Links: SRC4192 SRC4193

Typical Characteristics (continued)

Total Harmonic Distortion+Noise (dB)

–125 Total Harmonic Distortion+Noise (dB) –125