Ddco Lab Manual

Kammavari Sangham(R) 1952,
K. S. Group of Institutions
K. S. SCHOOL OF ENGINEERING & MANAGEMENT
Mallasandra, Off Kanakapura Road, Bengaluru - 560 109
Department of
Computer Science & Business Systems
Digital Design and Computer

Organization
(BCSL302)
LABORATORY MANUAL
Digital Design & Computer Organization BCS302
K.S. SCHOOL OF ENGINEERING AND MANAGEMENT

BENGALURU - 560109
DEPARTMENT OF COMPUTER SCIENCE AND BUSINESS SYSTEMS
CO-PO Mapping
Course: Digital Design & Computer Organization Course Code: BCS302

No of Hours
Practical/Field
Total Number of Lab
Lab Hours Work/Allied Activities Total hours/Week
Contact Hours
20 Hours of
0 2 14
Practical
Marks
CIE SEE Total Credits
50 50 100 01
Course objectives:
 To demonstrate the functionalities of binary logic system
 To explain the working of combinational and sequential logic system
 To realize the basic structure of computer system
 To illustrate the working of I/O operations and processing unit
Course Learning Outcomes: -
After completing the course, the students will be able to
CO1 Apply the K–Map techniques to simplify various Boolean Applying (K3)
expressions.
CO2 Design different types of combinational and sequential circuits Applying (K3)
along with Verilog programs.
CO3 Describe the fundamentals of machine instructions, addressing Understand (K2)

modes and Processor performance.
CO4 Explain the approaches involved in achieving communication Understand (K2)

between processor and I/O devices
Analyse internal Organization of Memory and Impact of
CO5 cache/Pipelining on Processor Performance. Applying (K3)
Department of CS & BS, KSSEM Page 2 of 36

LIST OF PROGRAMS
Program – 1
Given a 4-variable logic expression, simplify it using appropriate technique and simulate the same
using basic gates.
Program – 2
Design a 4-bit full adder and subtractor and simulate the same using basic gates.
Program – 3
Design Verilog HDL to implement simple circuits using structural, Data flow and Behavioural
model.
Program – 4
Design Verilog HDL to implement Binary Adder-Subtractor – Half and Full Adder, Half and Full
Subtractor.
Program – 5
Design Verilog HDL to implement Decimal adder.
Program – 6
Design Verilog program to implement Different types of multiplexers like 2:1, 4:1 and 8:1.
Program – 7
Design Verilog program to implement types of De-Multiplexer.
Program – 8
Design Verilog program for implementing various types of Flip-Flops such as SR, JK and D.
PO PO PO PO PO PO PO PO PO PO PO PO PSO PSO
CO PO
1 2 3 4 5 6 7 8 9 10 11 12 1 2
BCS K-
302 level
CO1 3 3 1 - 3 - - 2 - - - - 2 2
CO2 3 3 2 - 3 - - 2 3 - - - 2 2
CO3 2 2 1 - - - - 1 - - - - 2 2
CO4 2 2 2 - - - - 1 - - - - 2 2
CO5 2 3 2 - - - - 2 - - - - 2 2

INSTITUTION VISION & MISSION
VISION:
“To impart quality education in engineering and management to meet technological, business
and societal needs through holistic education and research”
MISSION:
K.S. School of Engineering and Management shall,
 Establish state-of-art infrastructure to facilitate effective dissemination of technical and

Managerial knowledge.
 Provide comprehensive educational experience through a combination of curricular and
experiential learning, strengthened by industry-institute-interaction.
 Pursue socially relevant research and disseminate knowledge.
 Inculcate leadership skills and foster entrepreneurial spirit among students.

STEPS TO FOLLOW IN MULTISIM
Steps to follow in Multisim and to execute, verify the result:
NI Multisim is an easy-to-use schematic capture and simulation environment that engineers, students,
and professors can use to define and simulate circuits.
Step 1: Open Multisim: Select Start» All Programs» National Instruments» Circuit Design Suite
11.0» Multisim 11.0 to open Multisim. Multisim opens showcasing the default capture and
simulation environment.
Step 2: Place Components.
Step 3: Wire Components.
Step 4: Place a Simulation Source.
Step 5: Place Measurement Instruments.
Step 6: Run a Simulation

EXPERIMENTS
Experiment 1: -
Given a 4-variable logic expression, simplify it using appropriate technique and simulate the
same using basic gates.
4-variable expression: F (A, B, C, D) = Σm (0, 1, 2, 5, 7, 8, 9, 10, 13, 15)
Solution: -
 Since the given Boolean expression has 4 variables, so we draw a 4 x 4 K Map.

 We fill the cells of K Map in accordance with the given Boolean function.
 Then, we form the groups in accordance with the above rules.
Then, we have-
Now, F(A, B, C, D) = BD + C’D + B’D’
Thus, minimized Boolean expression is- F(A, B, C, D) = BD + C’D + B’D’
Implementation of the same using basic gates: -

Truth Table: -
Decimal A B C D Y
0 0 0 0 0 1
1 0 0 0 1 1
2 0 0 1 0 1
3 0 0 1 1 0
4 0 1 0 0 0
5 0 1 0 1 1
6 0 1 1 0 0
7 0 1 1 1 1
8 1 0 0 0 1
9 1 0 0 1 1
10 1 0 1 0 1
11 1 0 1 1 0
12 1 1 0 0 0
13 1 1 0 1 1
14 1 1 1 0 0
15 1 1 1 1 1
Circuit to be Built in Multisim: -

Experiment 2: -
Design a 4-bit full adder and subtractor and simulate the same using basic gates.
sum= A ⊕ B ⊕ C
carry=A B + B C + A C

Ex: A = 1101
+ B = 1001
Sum = 0110
C out = 1
2b. Full Subtractor: -
Difference = A⨁B⨁C
Borrow = A’ B + B C + A’ C

Result:
Example: -
A3A2A1A0 = 1000
B3B2B1B0 = 0001
D3D2D1D0 = 0111
Cout=1

INTRODUCTION TO XILINX
Xilinx is one of most popular software tool, used to synthesize VHDL/Verilog code. This tool
includes many steps. To make user feel comfortable with the tool, the steps are given below:
• Select Verilog Module

• Enter the following details in New Source: Port name: Declare inputs and outputs and then finish.
• Click Next. Check the Summary and Click Finish.
• Write the program and save it.
• Click on Save.
• Go to Processes window: Click on ‘+’ against Synthesize. Double click on “Check Syntax”.
STEPS TO CREATE TEST BENCH: -
 In the project window select simulation.

 Right click on the file name and select new source and select Verilog text fixture. Give the
file name and finish.
 In the new test bench window write the test bench code. Save and check syntax (select the
file).
 Select the file and click on simulate behavioural model for simulating the code.
 Enter the following details in New Source Wizard – Select Source Type window – Select
Test Bench Waveform

Experiment 3: -
Design Verilog HDL to implement simple circuits using Structural, Data flow and
Behavioural model.
Structural Model: -
module p3(y, a, b, c);
input a,b,c;
output y;
wire w1, w2;
and(w1, a, b);
and(w2, b, c);
or(y,w1,w2);
endmodule
Test Bench Code:
initial begin
// Initialize Inputs
#100 a=0; b=0; c=0;
#100 a=0; b=0; c=1;
#100 a=0; b=1; c=0;
#100 a=0; b=1; c=1;
#100 a=1; b=0; c=0;
#100 a=1; b=0; c=1;
#100 a=1; b=1; c=0;
#100 a=1; b=1; c=1;
Output Waveform: -

Data Flow Model: -
module p3(y,a,b,c);
input a,b,c;
output y;
assign y= (a&b)|(b&c);
endmodule
Output: -
Test Bench code and output is same as Structural model.
Behavioral Model: -
module p3(y,a,b,c);
input a,b,c;
output y;
reg y;
always @(a,b,c)
begin
y= (a&b)|(b&c);
end
endmodule
Output: -
Test Bench code and output is same as Structural model.

Experiment 4: -
Design Verilog HDL to implement Binary Adder-Subtractor – Half and Full Adder, Half and
Full Subtractor.
a. Half Adder:
module hfadd(
input a,b,
output sum,carry
);
assign sum = a^b;
assign carry= a&b;
endmodule
Test Bench Code: -
initial begin
a = 0;b = 0;#100;
a = 0;b = 1;#100;
a = 1;b = 0;#100;
a = 1;b = 1;#100;
Output Waveforms: -

b) Half subtractor: -
module hfadd(
input a,b,
output diff,borrow
);
assign diff=a^b;
assign borrow=(~a)&b;
endmodule
Test Bench Code: -
initial begin
a = 0;b = 0;#100;
a = 0;b = 1;#100;
a = 1;b = 0;#100;
a = 1;b = 1;#100;
Output Waveform: -
c) Full Adder: -
module hfadd(
input a,b,c,
output sum,carry
);

assign sum=a^b^c;
assign carry=(a&b)|(b&c)|(c&a);
endmodule
Test bench code: -
initial begin
#100 a=0; b=0;c=0;
#100 a=0; b=0;c=1;
#100 a=0; b=1;c=0;
#100 a=0; b=1;c=1;
#100 a=1; b=0;c=0;
#100 a=1; b=0;c=1;
#100 a=1; b=1;c=0;
#100 a=1; b=1;c=1;
Output Waveform: -
d) Full Subtractor Module: -
module hfadd(
input a,b,c,
output diff,borrow
);
assign diff=a^b^c;

assign borrow=((~a)&b)|(b&c)|(c&(~a));
endmodule
Test Bench Code: -
initial begin
#100 a=0; b=0;c=0;
#100 a=0; b=0;c=1;
#100 a=0; b=1;c=0;
#100 a=0; b=1;c=1;
#100 a=1; b=0;c=0;
#100 a=1; b=0;c=1;
#100 a=1; b=1;c=0;
#100 a=1; b=1;c=1;
Output Waveform: -

Experiment 5: -
Design Verilog HDL to implement Decimal adder.
module bcd_adder (a,b,c,sum,carry);

input [3:0] a,b;
input c;
output [3:0] sum;
output carry;
reg [4:0] sum_temp;
reg [3:0] sum;
reg carry;
always @(a,b,c)
begin
sum_temp = a+b+c;
if(sum_temp > 9) begin
sum_temp = sum_temp+6;
carry = 1; //set the carry output
sum = sum_temp[3:0];
end
else begin
carry = 0;
sum = sum_temp[3:0];
end
end
endmodule
Test Bench Code: -
initial begin
a = 0; b = 0; c = 0; #100;
a = 6; b = 9; c = 0; #100;
a = 3; b = 3; c = 1; #100;
a = 4; b = 5; c = 0; #100;
a = 8; b = 2; c = 0; #100;
a = 9; b = 9; c = 1; #100;
Output: -
Consider the below BCD addition:

1001+0110 = 1111
i.e. 9 + 6 = 15

The output 15 is more than 9.

So we add 6 to it.
So we get, 15+6 = 21 (in binary 21 is 10101)
Now the least significant 4 bits(which is "0101") represent the units digit and the MSB(4th bit
which is '1') bit represents the tens digit.
Output Waveform: -

Experiment 6: -
Design Verilog program to implement Different types of multiplexers like 2:1, 4:1 and 8:1.
a. 2:1 Multiplexer:
module mulpx(A,d0,d1,y);
output y;
input d0;
input d1;
input A;
reg y;
always @ (d0,d1,A)
begin
y=((~A & d0)|(A & d1));
end
endmodule
Test Bench Code: -
initial begin
#100 A=0;d0=0;d1=0;
#100 A=0;d0=0;d1=1;
#100 A=0;d0=1;d1=0;
#100 A=0;d0=1;d1=1;
#100 A=1;d0=0;d1=0;
#100 A=1;d0=0;d1=1;
#100 A=1;d0=1;d1=0;
#100 A=1;d0=1;d1=1;
Output Waveform: -

b. 4:1 Multiplexer: -
module mulpx(y,d0,d1,d2,d3,a0,a1);
output y;
input d0,d1,d2,d3,a0,a1;
reg y;
always @ (d0,d1,d2,d3,a0,a1)
begin
y= (~a0 & ~a1 & d0) | (~a0 & a1 & d1) | (a0 & ~a1 & d2) | (a0 & a1 & d3);
end
endmodule
Test Bench Code: -
initial begin
#100 a0=0;a1=0;d0=0;
#100 a0=0;a1=1;d1=1;
#100 a0=1;a1=0;d2=0;
#100 a0=1;a1=1;d3=1;
Output Waveform: -

c. 8:1 Multiplexer: -
module mux81( input [7:0]i,

input [2:0]s,
output reg y);
always @ (i,s)
begin
if (s==3'b000)y=i[0];
else if (s==3'b001)y=i[1];
else if (s==3'b010)y=i[2];
else if (s==3'b011)y=i[3];
else if (s==3'b100)y=i[4];
else if (s==3'b101)y=i[5];
else if (s==3'b110)y=i[6];
else y=i[7];
end
endmodule
Test Bench Code: -
reg [7:0] i;
reg [2:0] s;
// Outputs
wire y;
// Instantiate the Unit Under Test (UUT)
mux81 uut (
.i(i),
.s(s),
.y(y)
);
initial begin
i=0;
s=0;
repeat(30)
begin
#40 i=i+1;
#40 s=s+1;

Output Waveform: -

Experiment 7: -
Design Verilog program to implement types of De-Multiplexer.
a. 1:2 Demultiplexer
module demux(D,A,Y0,Y1);
input D,A;
output Y0,Y1;
reg Y0,Y1;
always @ (A,D)
begin
Y0=(~A & D);
Y1=(A & D);
end
endmodule
Test bench code: -

initial begin
#100 A=0;D=0;
#100 A=0;D=1;
#100 A=1;D=0;
#100 A=1;D=1;
Output Waveform: -

b. 1:4 Demultiplexer
module P714(D,A0,A1,Y0,Y1,Y2,Y3);
input D,A0,A1;
output Y0,Y1,Y2,Y3;
reg Y0,Y1,Y2,Y3;
always @(A0,A1,D)
begin
Y0=(~A0 & ~A1 & D);
Y1=(~A0 & A1 & D);
Y2=(A0 & ~A1 & D);
Y3=(A0 & A1 & D);
end
endmodule
Test Bench Code: -

initial begin
#100 A0=0;A1=0;D=0;
#100 A0=0;A1=0;D=1;
#100 A0=0;A1=1;D=0;
#100 A0=0;A1=1;D=1;
#100 A0=1;A1=0;D=0;
#100 A0=1;A1=0;D=1;
#100 A0=1;A1=1;D=0;
#100 A0=1;A1=1;D=1;
Output Waveform: -

c. 1:8 DEMULTIPLEXER
module demux18( input i,

input [2:0]s,
output reg [7:0]y );
always @ (i,s) begin
y=0;
if (s==3'b000)y[0]=i;
else if (s==3'b001)y[1]=i;
else if (s==3'b010)y[2]=i;
else if (s==3'b011)y[3]=i;
else if (s==3'b100)y[4]=i;
else if (s==3'b101)y[5]=i;
else if (s==3'b110)y[6]=i;
else y[7]=i;
end
endmodule
Test Bench code: -

initial begin
i=0;
s=0;
repeat(30)
begin
#40 i=1;
#10 s=s+1;
// Wait 100 ns for global reset to finish
#100;
Output Waveform: -


Experiment 8: -
Design Verilog program for implementing various types of Flip-Flops such as SR, JK and D.
a. SR FLIP-FLOP
module SR_flipflop (
input clk, rst_n,
input s,r,
output reg q,
output q_bar
);
// always@(posedge clk or negedge rst_n) // for asynchronous reset
always@(posedge clk) begin
if(!rst_n) q <= 0;
else begin
case({s,r})
2'b00: q <= q; // No change
2'b01: q <= 1'b0; // reset
2'b10: q <= 1'b1; // set
2'b11: q <= 1'bx; // Invalid inputs
endcase
end
end
assign q_bar = ~q;
endmodule
Test Bench Code: -

SR_flipflop uut (
.clk(clk),
.rst_n(rst_n),
.s(s),
.r(r),
.q(q),
.q_bar(q_bar)
);
always #5 clk = ~clk;
//4. apply test vectors
initial begin
clk=0;
forever #10 clk = ~clk;
end
initial begin
#100; s= 1; r= 0;

#100; s= 0; r= 0;
#100; s= 0; r= 1;
#100; s= 1; r=1;
end
Output Waveform: -
b. JK FLIP-FLOP
module JK_flipflop (
input clk, rst_n,
input j,k,
output reg q,
output q_bar
);
// always@(posedge clk or negedge rst_n) // for asynchronous reset
always@(posedge clk) begin // for synchronous reset
if(!rst_n) q <= 0;
else begin
case({j,k})
2'b00: q <= q; // No change
2'b01: q <= 1'b0; // reset
2'b10: q <= 1'b1; // set
2'b11: q <= ~q; // output toggles
endcase
end
end

assign q_bar = ~q;

endmodule
Test bench code:
JK_flipflop uut (
.clk(clk),
.rst_n(rst_n),
.j(j),
.k(k),
.q(q),
.q_bar(q_bar)
);
always #5 clk = ~clk;
//4. apply test vectors
initial begin
clk=0;
end
initial begin
j= 1; k= 0;
#100; j= 0; k= 0;
#100; j= 0; k= 1;
#100; j= 1; k=1;
end
endmodule
Output Waveform: -

D FLIP-FLOP
module p8dff(d,clk,q);
input d,clk;
output q;
reg q;
always @(posedge clk)
begin
q<=d;
end
endmodule
Test Bench Code: -
initial begin
clk=0;
end
initial begin
#100; d <= 0;
#100; d <= 1;
#100; d <= 0;
#100; d <=0;
#100; d <= 1;
#100; d <= 1;
Output Waveform: -

VIVA QUESTIONS
1. Define Logic gates
A logic gate is an elementary building block of a digital circuit. Most logic gates have two inputs
and one output. At any given moment, every terminal is in one of the two binary conditions low (0)
or high (1), represented by different voltage levels.
2. What are universal gates? Why it is called so?
NAND and NOR are called universal gates because all the other gates like and, or, not, xor and
xnor can be derived from it. ... Similarly, NOR means NOT of OR, so it is a combination of OR and
a NOT gate. A NOR gate is also implemented using inverted AND inputs and so also called as
bubbled AND gate.
3. Write the truth table for Ex-or gate and AND gate
4. What are ‘minterms’ and ‘maxterms’?

A minterm is a Boolean expression resulting in 1 for the output of a single cell, and 0s for all other
cells in a Karnaugh map, or truth table.
A maxterm is a Boolean expression resulting in a 0 for the output of a single cell expression, and 1s
for all other cells in the Karnaugh map, or truth table.
5. State and prove Demorgan’s theorem

6. What is a combinational circuit? Give example.
Combinational circuit does not use memory and thus here output depends only on current input.
Also, there is no need of clock here.
Examples of combinational circuits are full adder, multiplexer, decoder, encoder etc.
Now sequential circuits use memory and thus their output depends on current input plus previous
output. They employ a feedback loop to give output back to input.
Examples of sequential circuit are counter, shift registers etc.
7. Write about half adder and full adder
Half-Adder: A combinational logic circuit that performs the addition of two data bits, A and B, is
called a half-adder. Addition will result in two output bits; one of which is the sum bit, S, and the
other is the carry bit, C.
Full-Adder: The half-adder does not take the carry bit from its previous stage into account. This carry
bit from its previous stage is called carry-in bit. A combinational logic circuit that adds two data bits,
A and B, and a carry-in bit, Cin, is called a full-adder
8. Define multiplexer
A multiplexer (or mux) is a device that selects one of several analog or digital input signals and
forwards the selected input into a single line. A multiplexer of 2n inputs has n select lines, which are
used to select which input line to send to the output. Multiplexers are mainly used to increase the
amount of data that can be sent over the network within a certain amount of time and bandwidth.
A multiplexer is also called a data selector. Multiplexers can also be used to implement boolean
functions of multiple variables.
9. Define de-multiplexer
A demultiplexer (or demux) is a device taking a single input signal and selecting one of many data-
output-lines, which is connected to the single input.
10. Applications of mux and demux
Applications of Multiplexer

 Communication System: By using a multiplexer, the efficiency of the communication system can be
increased by allowing the transmission of data, such as audio, video data from different channels
through single line.
 Computer Memory: Multiplexers are used in computer memory to maintain a huge amount of
memory in the computers, and also to reduce the number of copper lines required to connect the
memory to other parts.
 Telephone network: multiple audio signals are integrated on a single line of transmission with
the help of a multiplexer.
 Transmission from computer system of a satellite: multiplexer is used to transmit the data signals
from compute system of a space craft or a satellite to the ground system by using a GSM.
Applications of De-Multiplexer
 Mux and De-Mux are both used in communication system to carry out the process of data
transmission. A De-multiplexer receives the output signals from the multiplexer and at the receiver
end it converts them back to the original form.
 Arithmetic Logic Unit: The output of the ALU is fed as an input to the de-multiplexer and the
output of the de-multiplexer is connected to a multiple register. The output of the ALU can be stored
in multiple registers.
11. What are Encoder and decoder? Give its representation.
Encoders are digital ICs used for encoding. By encoding, we mean generating a digital binary code
for every input. An Encoder IC generally consists of an Enable pin which is usually set high to
indicate the working. It consists of 2^n input lines and n output lines with each input line being
represented by a code of zeros and ones which is reflected at the output lines
Decoders are digital ICs which are used for decoding. In other words, the decoders decrypt or obtain
the actual data from the received code, i.e., convert the binary input at its input to a form, which is
reflected at its output. It consists of n input lines and 2^n output lines. A decoder can be used to
obtain the required data from the code or can also be used for obtaining the parallel data from the
serial data received.
12. What are the Applications of encoder and Decoder
Applications of the Encoder and Decoder
 Speed synchronization of multiple motors in industries

 War field flying robot with a night vision flying camera

 Robotic vehicle with the metal detector
 RF based home automation system
 Automatic health monitoring systems
13. Write the characteristic equation of a SR, JK, D and T flip flop
 Q(t+1) = R'(t)Q(t) + S(t),

 Q(t+1) = K'(t)Q(t) + J(t)Q'(t),
 Q(t+1) = D(t),
 Q(t+1) = T'(t)Q(t) + T(t)Q'(t) = T(t) ⊕ Q(t)
14. Distinguish between synchronous and asynchronous sequential logic circuits
15. Difference between flip-flop and latches

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Kammavari Sangham(R) 1952,

Digital Design and Computer

K.S. SCHOOL OF ENGINEERING AND MANAGEMENT

Course: Digital Design & Computer Organization Course Code: BCS302

 To explain the working of combinational and sequential logic system

 To realize the basic structure of computer system

 To illustrate the working of I/O operations and processing unit

Course Learning Outcomes: -

After completing the course, the students will be able to

CO3 Describe the fundamentals of machine instructions, addressing Understand (K2)

CO4 Explain the approaches involved in achieving communication Understand (K2)

Department of CS & BS, KSSEM Page 2 of 36

Department of CS & BS, KSSEM Page 3 of 36

INSTITUTION VISION & MISSION

 Establish state-of-art infrastructure to facilitate effective dissemination of technical and

Department of CS & BS, KSSEM Page 4 of 36

STEPS TO FOLLOW IN MULTISIM

Steps to follow in Multisim and to execute, verify the result:

Step 2: Place Components.

Step 3: Wire Components.

Step 4: Place a Simulation Source.

Step 5: Place Measurement Instruments.

Step 6: Run a Simulation

Department of CS & BS, KSSEM Page 5 of 36

4-variable expression: F (A, B, C, D) = Σm (0, 1, 2, 5, 7, 8, 9, 10, 13, 15)

 Since the given Boolean expression has 4 variables, so we draw a 4 x 4 K Map.

Now, F(A, B, C, D) = BD + C’D + B’D’

Thus, minimized Boolean expression is- F(A, B, C, D) = BD + C’D + B’D’

Implementation of the same using basic gates: -

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Circuit to be Built in Multisim: -

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2b. Full Subtractor: -

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• Select Verilog Module

STEPS TO CREATE TEST BENCH: -

 In the project window select simulation.

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module p3(y, a, b, c);

wire w1, w2;

Test Bench Code:

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Data Flow Model: -

Test Bench code and output is same as Structural model.

Test Bench code and output is same as Structural model.

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assign sum = a^b;

assign carry= a&b;

Test Bench Code: -

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Test Bench Code: -

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Test bench code: -

d) Full Subtractor Module: -

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#100 a=0; b=0;c=0;

#100 a=0; b=0;c=1;

#100 a=0; b=1;c=0;