INDEX

STUDENT’S NAME:………………… ROLL NO.:………………...

S.NO PROGRAM’S NAME DAT PAGE MARKS SIGNATURE/REMA
. E NO. OBTAINED RKS
1 To design and verify. Half
adder and Full adder using
basic and NAND gates.
2 To realize binary to gray
and gray to binary code
converters.
3 To verify the various
functions of IC
74153(MUX) and IC
74139(DEMUX).
4 To implement the circuit
and to verify the truth table
of the following Flip-
Flops.
5 To realize and study of Shift
Register.
6 To perform addition of two
8 bit numbers using 8085.
7 To perform the subtraction
of two 8 bit numbers using
8085.
8 To perform the
multiplication of two 8 bit
numbers using 8085
9 To perform the division of
two 8 bit numbers using
8085.

1
 EXPERIMENT: 1
Design and implementation of half adder & full adder using logic
gates/Universal gates
OBJECTIVE: To design and verify
i. Half adder and Full adder using basic and NAND gates.

COMPONENTS REQUIRED: IC 7400, IC 7408, IC 7486, and IC 7432, Patch cards and IC
Trainer Kit.

THEORY:
Half-Adder: A combinational logic circuit that performs the addition of two data bits, A and B,
is called a half-adder. Addition will result in two output bits; one of which is the sum bit, S, and
the other is the carry bit, C. The Boolean functions describing the half-adder are:
S =A ⊕ B C=AB

Full-Adder: The half-adder does not take the carry bit from its previous stage into account. This
carry bit from its previous stage is called carry-in bit. A combinational logic circuit that adds
two data bits, A and B, and a carry-in bit, Cin, is called a full-adder. The Boolean functions
describing the full-adder are:
S = (x ⊕ y) ⊕ Cin C = xy + Cin (x ⊕ y)

I. TO REALIZE HALF ADDER

II.
2
 FULL ADDER

TRUTH TABLE BOOLEAN EXPRESSIONS:

BASIC GATES

i) NAND GATES

3
Procedure:
  Check the components for their working.
 Insert the appropriate IC into the IC base.
 Rig up the circuit as shown in the logic circuit diagram.
 Apply various input data to the logic circuit via the input logic switches.
 Note down the corresponding output and verify the truth table.
Result:

VIVA-VOCE:
Q-1 What is ripple carry adder?
Q-2 What do you mean by universal gates?
Q-3What is half adder?
Q-4 What is full adder?
Q-5 What is look ahead adder?
Q-6 What is combinational circuit?
Q-7 What is the truth table of ex-or gate?
Q-8 What is 4 bit Adder?
Q-9 What do you mean by sequential Circuit?
Q-10 How to realize the SOP and POS?

4
 Experiment 2

BINARY TO GRAY CODE CONVERSION AND VICE VERSA

OBJECTIVE: To realize binary to gray and gray to binary code converters.

Components required: IC 7486, trainer kit, patch cords.

Theory:
The logical circuit which converts binary code to equivalent gray code is known as binary to
gray code converter. The gray code is a non-weighted code. The successive gray code differs in
one bit position only that means it is a unit distance code. It is also referred as cyclic code. It is
not suitable for arithmetic operations. It is the most popular of the unit distance codes. It is also a
reflective code. An n-bit Gray code can be obtained by reflecting an n-1 bit code about an axis
n-1
after 2 rows, and putting the MSB of 0 above the axis and the MSB of 1 below the axis.

Circuit implementation:

Binary to gray code converter:

Truth table:
Binary inputs Gray outputs
B3 B2 B1 B0 G3 G2 G1 G0
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 0 0 0 1 1
0 0 1 1 0 0 1 0
0 1 0 0 0 1 1 0
0 1 0 1 0 1 1 1
0 1 1 0 0 1 0 1
0 1 1 1 0 1 0 0
1 0 0 0 1 1 0 0
1 0 0 1 1 1 0 1
1 0 1 0 1 1 1 1
1 0 1 1 1 1 1 0
1 1 0 0 1 0 1 0
1 1 0 1 1 0 1 1
5
 1 1 1 0 1 0 0 1
1 1 1 1 1 0 0 0

Gray to binary code converter:

Truth table:

Gray inputs Binary outputs

G3 G2 G1 G0 B3 B2 B1 B0
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 0 0 0 1 1
0 0 1 1 0 0 1 0
0 1 0 0 0 1 1 1
0 1 0 1 0 1 1 0
0 1 1 0 0 1 0 0
0 1 1 1 0 1 0 1
1 0 0 0 1 1 1 1
1 0 0 1 1 1 1 0
1 0 1 0 1 1 0 0
1 0 1 1 1 1 0 1
1 1 0 0 1 0 0 0
1 1 0 1 1 0 0 1
1 1 1 0 1 0 1 1
1 1 1 1 1 0 1 0

6
Procedure:

  Check the components for their working.

 Insert the appropriate IC into the IC base.
 Rig up the circuit as shown in the logic circuit diagram.
 Apply various input data to the logic circuit via the input logic switches.
 Note down the corresponding output and verify the truth table.

Result:

VIVA-VOCE:
Q-1 What is gray code?
Q-2 What do you mean by BCD encoder?
Q-3What is encoder?
Q-4 What is decoder?
Q-5 What is multiplexer?
Q-6 Why clock pulse is required in the circuit?
Q-7 How to realize k map for 4 variables?
Q-8 What is de multiplexer ?
Q-9 What do you mean by number system?
Q-10 What is VLSI?

7
 EXPERIMENT: 3
MULTIPLEXER AND DEMULTIPLEXER
OBJECTIVE: To design and set up the following circuit
1) To verify the various functions of IC 74153(MUX) and IC 74139(DEMUX).
THEORY:
Multiplexers are very useful components in digital systems. They transfer a large
number of information units over a smaller number of channels, (usually one channel)
under the control of selection signals. Multiplexer means many to one. A multiplexer is
a circuit with many inputs but only one output. By using control signals (select lines)
we can select any input to the output. Multiplexer is also called as data selector because
the output bit depends on the input data bit that is selected. The general multiplexer
n
circuit has 2 input signals, n control/select signals and 1 output signal.
De-multiplexers perform the opposite function of multiplexers. They transfer a small
number of information units (usually one unit) over a larger number of channels under
the control of selection signals. The general de-multiplexer circuit has 1 input signal, n
n
control/select signals and 2 output signals. De-multiplexer circuit can also be realized
using a decoder circuit with enable.

COMPONENTS REQUIRED:
IC 7400, IC 7410, IC 7420, IC 7404, IC 74153, IC 74139, Patch Cords & IC Trainer Kit.

i) 4:1 MULTIPLEXER

4:1
Inputs MUX
Y

E’
Select
inputs
Output Y= E’S1’S0’I0 + E’S1’S0I1 + E’S1S0’I2 + E’S1S0I3

18

8
 TRUTH
REALIZATION USING NAND GATES TABLE

Select Enable Out

Inputs
Inputs Input puts

S1 S0 E I0 I1 I2 I3 Y
X X 1 X X X X 0
0 0 0 0 X X X 0
0 0 0 1 X X X 1
0 1 0 X 0 X X 0
0 1 0 X 1 X X 1
1 0 0 X X 0 X 0
1 0 0 X X 1 X 1
1 1 0 X X X 0 0
1 1 0 X X X 1 1

VERIFY IC 74153 MUX (DUAL 4:1 MULTIPLEXER)

9
 ii) DE-MUX USING NAND GATES
Enable Data Select
Outputs
Inputs Input Inputs

E D S1 S0 Y3 Y2 Y1 Y0
1 0 X X X X X X
0 1 0 0 0 0 0 1
0 1 0 1 0 0 1 0
0 1 1 0 0 1 0 0
0 1 1 1 1 0 0 0

VERIFICATION OF IC 74139 (DEMUX)

TRUTH TABLE

Inputs Outputs
Ea S1 S0 Y3 Y2 Y1 Y0
1 X X 1 1 1 1
0 0 0 1 1 1 0
0 0 1 1 1 0 1
0 1 0 1 0 1 1
0 1 1 0 1 1 1

PROCEDURE:
• Check all the components for their working.
• Insert the appropriate IC into the IC base.
• Make connections as shown in the circuit diagram.
• Verify the Truth Table and observe the outputs.

RESULT:

10
VIVA-VOCE:
Q-1 What is access code?
Q-2 What do you mean by BCD encoder?
Q-3What is encoder?
Q-4 What is decoder?
Q-5 What is multiplexer?
Q-6 Why clock pulse is required in the circuit?
Q-7 How to realize 8:1 multiplexer using NAND gate?
Q-8 What is de multiplexer ?
Q-9 What do you mean by number system?
Q-10 What is VLSI?

11
 EXPERIMENT 4
STUDY OF FLIPFLOPS
AIM: To implement the circuit and to verify the truth table of the following Flip-Flops.

LEARNING OBJECTIVE:
i) To learn about various Flip-Flops.
ii) To learn and understand the working of Master slave FF.

COMPONENTS REQUIRED:
7485, 7408, 8411, 7421, 7432, digital IC Trainer Kit, Patch Chord.

THEORY:
Basically Flip-Flops are the bistable multivibrators that stores logic 1 and logic
0.Shift registers, memory, and counters are built by using Flip – Flops. Any complex
sequential machines are build using Flip – Flops. Sequential circuit (machine) output
depends on the present state and input applied at that instant.
Mealy Machine is one whose output depends on both the present state and the input.
Moore machines one whose output depends only on the present state of the sequential
circuit. Note that the truth table of J – K Flip – Flop is same as the Master – Slave.
J – K Flip Flop and they must be remain same because IC – 7476is –ve edge
trigged flip – flop and we know that race around condition is eliminated by edge
triggered flip – flop. Another way of eliminating race around condition is by using
Master – Slave J –K Flip – Flop. When J = K = 1 (logic HIGH), J – K Flip – Flop
changes output many times for single clock pulse, it is Smaller than width of the clock
pulse.

CP

CP width of clock pulse

Pd < Cp = race around condition
Pd Propagation Delay
CP Clock Pulse Width
Race around condition is eliminated by using edge triggered clock pulse and
using Master – Slave J - K Flip Flops.
i)Implementation of J.K.Flip-Flop
Design:
IC – 74LS76: Dual –ve edge triggered J – K Flip – Flop

12
 Inputs Outputs
Q J K Qt + 1
0 0 0 0
0 0 1 0
0 1 0 1
0 1 1 1
1 0 0 1
1 0 1 0
1 1 0 1 Fig (4.1) Pin diagram of 7476
1 1 1 0
Truth Table of JK Flip – Flop:

Fig (4.2) J – K Flip – Flop Circuit

Where
Q Present State
Qt+1 Next State

Characteristic eqn Q t + 1 = J Q + K Q

ii) Master Slave J K Flip – Flop:

IC – 74107: Dual – Master – Slave J-K Flip - Flop

13
 Fig (4.3) Pin diagram
Circuit Implementation:

Fig (4.4) Master – Slave J –K Flip – Flop Circuit.

Truth Table of Master – Slave – JK Flip – Flop:

Where
Q Present state
Qt + 1 Next state
Inputs Outputs
Q J K Qt + 1
0 0 0 0
0 0 1 0
0 1 0 1
0 1 1 1
1 0 0 1
1 0 1 0
1 1 0 1
1 1 1 0 Characteristic eqn Q t + 1 = J Q + K Q
iii) D – Flip – Flop:
IC – 7474: Dual + ve edge triggered D- Flip Flop :

Fig (4.5) Pin Diagram

14
Circuit Implementation:

Inputs Outputs
Q J Qt + 1
0 0 0
Fig (4.6): D –Flip – Flop 0 1 1
Truth Table of D – Flip – Flop: 1 0 0
1 1 1

Where
Q Present State
D Data Input
Qt + 1 Next State

Characteristic eqn Q
t+1=D
From Characteristic equation it is clear that next state Qt + 1 is equal to the input data D
i.e. Q t + 1 = D
iv) T – Flip – Flop: Using J –K Flip –
Flop Truth Table of T – Flip – Flop:

15
 Inputs Outputs
Q J Qt + 1
0 0 0
0 1 1
1 0 0 Fig (4.7) : T – Flip - Flop
1 1 1 Circuit Where
Q Present State
D Data Input

Characteristic eqn Q t + 1 = DT + Q T (Ex – OR)

The next state of T Flip Flop is equal to Ex –OR of Present State (Q) and T input.
PROCEDURE:
1) Connections are made as per the circuit diagram.

2) Apply the –ve edge triggered, +ve edge triggered and level sensitive clock
pulses as required.

3) Verify the truth table of all the Flip – Flops.

4) Switch - off the power supply and disconnect the circuit.

RESULT:

Lab Manual EC37L Page 35

16
 EXPERIMENT: 5
SHIFT REGISTERS

AIM: To realize and study of Shift Register.

1) SISO (Serial in Serial out)
2) SIPO (Serial in Parallel out)
3) PIPO (Parallel in Parallel out)
4) PISO (Parallel in Serial out)
LEARNING OBJECTIVES:
To illustrate the operation of shift registers To
study different shift register configurations
COMPONENTS REQUIRED: IC 7495,IC 7474, Patch Cords & IC Trainer Kit.
Theory:
Shift registers are a type of sequential logic circuit, mainly for storage of
digital data. They are a group of flip-flops connected in a chain so that the output
from one flip-flop becomes the input of the next flip-flop. All the flip-flops are
driven by a common clock, and all are set or reset simultaneously.
The serial in/serial out shift register accepts data serially – that is, one bit at a
time on a single line. It produces the stored information on its output also in
serial form.
The serial in/parallel out shift register accepts data serially – that is, one bit at a
time on a single line. It produces the stored information on its output in parallel
form.
The parallel in/serial out shift register accepts data in parallel. It produces the
stored information on its output also in serial form.
The parallel in/parallel out shift register accepts data in parallel. It produces the
stored information on its output in parallel form.

Lab Manual EC37L Page 48

17
SERIAL IN SERIAL OUT:
LOGIC DIAGRAM:

OUTPUT WAVEFORM:

TRUTH TABLE:
CLK Serial in Serial out
1 1 0
2 0 0
3 0 0
4 1 1
5 X 0
6 X 0
7 X 1

18
SERIAL IN PARALLEL OUT:
LOGIC DIAGRAM:

OUTPUT WAVEFORM:

TRUTH TABLE:
OUTPUT
CLK DATA QA QB QC QD
1 1 1 0 0 0
2 0 0 1 0 0
3 0 0 0 1 1
4 1 1 0 0 1

19
PARALLEL IN SERIAL OUT:

LOGIC DIAGRAM:

OUTPUT WAVEFORM:

TRUTH TABLE:
CLK Q3 Q2 Q1 Q0 O/P
0 1 0 0 1 1
1 0 0 0 0 0
2 0 0 0 0 0
3 0 0 0 0 1

20
PARALLEL IN PARALLEL OUT:
LOGIC DIAGRAM:

TRUTH TABLE:
DATA INPUT OUTPUT
CLK DA DB DC DD QA QB QC QD
1 1 0 0 1 1 0 0 1
2 1 0 1 0 1 0 1 0

PROCEDURE:
1. Check the components for their working.
2. Insert the appropriate IC into the IC base.
3. Rig up the circuit as shown in the logic circuit diagram.
4. Apply various input data to the logic circuit via the input logic switches.
5. Note down the corresponding output and verify the truth table.

Note: Write the pin numbers of each gate and also write the intermediate expressions.

RESULT:

21
Shift Registers using IC 7495

PIN DIAGRAM of IC 7495:

22
PISO:

PROCEDURE:
Serial In Parallel Out (SIPO):-
23
1. Connections are made as per circuit diagram.
2. Keep the mode control in logic 0
3. Apply the data at serial input.
4. Apply one clock pulse at clock 1 observe this data at QA.
5. Apply the next data at serial input.
6. Apply one clock pulse at clock 2, observe that the data on QA will shift to QB and the new data applied
will appear at QA.
7. Repeat steps 2 and 3 till all the 4 bits data appear at the output of shift register.

Serial In Serial Out(SISO):-

1. Connections are made as per circuit diagram.
2. Keep the mode control in logic 0
3. Load the shift register with 4 bits of data one by one serially.
th
4. At the end of 4 clock pulse the first data ‘d0’ appears at QD.
5. Apply another clock pulse; the second data ‘d1’ appears at QD and so on.
6. Thus the data applied serially at the input comes out serially at QD
Parallel In Serial Out (PISO):-
1. Connections are made as per circuit diagram.
2. Apply the desired 4 bit data at A, B, C and D.
3. Keeping the mode control M=1 apply one clock pulse. The data applied
at A, B, C and D will appear at QA, QB, QC and QD respectively.
4. Now mode control M=0. Apply clock pulses one by one and observe
the Data coming out serially at QD
Parallel In Parallel Out (PIPO):-
1. Connections are made as per circuit diagram.
2. Apply the 4 bit data at A, B, C and D.
3. Apply one clock pulse at Clock 2 (Note: Mode control M=1).
4. The 4 bit data at A, B, C and D appears at QA, QB, QC and QD respectively.
RESULT:

24
 PROGRAM#6

ADDITION OF TWO 8 BIT NUMBERS

Objective To perform addition of two 8 bit numbers using 8085.

ALGORITHM:
1) Start the program by loading the first data into Accumulator.
2) Move the data to a register (B register).
3) Get the second data and load into Accumulator.
4) Add the two register contents.
5) Check for carry.
6) Store the value of sum and carry in memory location
7) Terminate the program.
PROGRAM:
MVI C, 00 Initialize C register to 00
LDA 4150 Load the value to Accumulator.
MOV B, A Move the content of Accumulator to B register.
LDA 4151 Load the value to Accumulator.
ADD B Add the value of register B to A
JNC LOOP Jump on no carry.
INR C Increment value of register C
LOOP: STA 4152 Store the value of Accumulator (SUM).
MOV A, C Move content of register C to Acc.
STA 4153 Store the value of Accumulator (CARRY)
HLT Halt the program.

OBSERVATION:
Input: 80 (4150) 80 (4251)
Output: 00 (4152)
01 (4153)
RESULT
:
Thus the program to add two 8-bit numbers was execute

25
 PROGRAM#7

SUBTRACTION OF TWO 8 BIT NUMBERS

Objective
To perform the subtraction of two 8 bit numbers using 8085.

ALGORITHM:
1. Start the program by loading the first data into Accumulator.
2. Move the data to a register ( register).
3. Get the second data and load into Accumulator.
4.Subtract the two register contents.
5.Check for carry.
6.If carry is present take 2’s complement of Accumulator.
7. Store the value of borrow in memory location.
8. Store the difference value (present in Accumulator) to a memory
9. location and terminate the program.

PROGRAM:
MVI C, 00 Initialize C to 00
LDA 4150 Load the value to Acc.
MOV B, A Move the content of Acc to B register.
LDA 4151 Load the value to Acc.
SUB B
JNC LOOP Jump on no carry.
CMA Complement Accumulator contents.
INR A Increment value in Accumulator.
INR C Increment value in register C
LOOP: STA 4152 Store the value of A-reg to memory address.
MOV A, C Move contents of register C to Accumulator.
STA 4153 Store the value of Accumulator memory address.
HLT Terminate the program

OBSERVATION:
Input:
06 (4150) 02 (4251)
Output:
04 (4152) 01 (4153)
RESULT:
Thus the program to subtract two 8-bit numbers was executed.

26
 PROGRAM#8

MULTIPLICATION OF TWO 8 BIT NUMBERS

Objective: To perform the multiplication of two 8 bit numbers using 8085.
ALGORITHM:
1) Start the program by loading HL register pair with address of memory location.
2) Move the data to a register (B register).
3) Get the second data and load into Accumulator.
4) Add the two register contents.
5) Check for carry.
6) Increment the value of carry.
7) Check whether repeated addition is over and store the value of product and carry in memory location.
8) Terminate the program.

PROGRAM:
MVI D, 00 Initialize register D to 00
MVI A, 00 Initialize Accumulator content to 00
LXI H, 4150
MOV B, M Get the first number in B - reg INX H
MOV C, M Get the second number in C- reg.
LOOP: ADD B Add content of A - reg to register B.
JNC NEXT Jump on no carry to NEXT.
INR D Increment content of register D
NEXT: DCR C Decrement content of register C
JNZ LOOP Jump on no zero to address
STA 4152 Store the result in Memory MOV A, D
STA 4153 Store the MSB of result in Memory
HLT Terminate the program

OBSERVATION:
Input:
FF (4150)
FF (4151)
Output:
01 (4152)
FE (4153)

RESULT:
Thus the program to multiply two 8-bit numbers was executed.

27
 PROGRAM#9

DIVISION OF TWO 8 BIT NUMBERS

Objective: To perform the division of two 8 bit numbers using 8085.

ALGORITHM:
1) Start the program by loading HL register pair with address of memory location.
2) Move the data to a register(B register).
3) Get the second data and load into Accumulator.
4) Compare the two numbers to check for carry.
5) Subtract the two numbers.
6) Increment the value of carry.
7) Check whether repeated subtraction is over and store the value of product and carry in memory
location.
8) Terminate the program.

PROGRAM:
LXI H, 4150
MOV B, M Get the dividend in B – reg.
MVI C, 00 Clear C – reg for qoutient
INX H MOV A, M Get the divisor in A – reg.
NEXT: CMP B Compare A - reg with register B.
JC LOOP Jump on carry to LOOP
SUB B Subtract A – reg from B- reg.
INR C Increment content of register C.
JMP NEXT Jump to NEXT
LOOP: STA 4152 Store the remainder in Memory
MOV A, C
STA 4153 Store the quotient in memory
HLT Terminate the program.

OBSERVATION:
Input:
FF (4150)
FF (4251)
Output:
01 (4152) ---- Remainder
FE (4153) ---- Quotient

RESULT:
Thus the program to multiply two 8-bit numbers was executed.

28