SRI SAI RAM ENGINEERING COLLEGE

SAI LEO NAGAR, WEST TAMBARAM, CHENNAI-44

NAME :

REGISTER NUMBER:

20EIPW401 DIGITAL ELECTRONICS WITH LAB

(II YEAR / IV SEM)
(BATCH: 2022 – 2026)

B.E ELECTRONICS AND INSTRUMENTATION

ENGINEERING
ACADEMIC YEAR: 2023 – 2024
EXPERIMENTS 10 Hrs

1. Implementation of SOP and POS using logic gates

2.Implementation of Half adder and Full adder using logic gates

3. Implementation of Multiplexer and De multiplexer using logic gates

4. Implementation of Code converter using logic gates

5. Implementation of flip flops

6. Implementation of Counters

7. VHDL simulation of Adder and Multiplexer

8. VHDL simulation of Flip flop & Counters

 Ex. No. : 1
Date :

IMPLEMENTATION OF BOOLEAN FUNCTIONS

AIM:

To implement the given function using SOP, POS form.

F(A,B,C,D) = ∑(0,1,2,5,8,9,10)

APPARATUS REQUIRED:

1. Digital trainer kit

2. IC7408
3. IC 7432
4. IC7404
5. IC7411
6. IC14075
7. Connecting wires

THEORY:

For various decision making functions a combination of AND, OR and NOT logic gates is
employed. The logic circuits so formed are known as Combinational logic circuits. Though there are
many varieties of circuit configurations for combinational circuits, two configurations are most
popular:
1. Sum of Products (SOP) and
2. Product of Sums (SOP)

The functions expressed in these forms are called Standard forms of Boolean algebra.

PROCEDURE:

1. Set up the circuit using the specified gates.

2. Set the inputs.

3. Check the needed Boolean function using truth table.

TRUTH TABLE

A B C D F= B’D’+ B’C’+ A’C’D

0 0 0 0 1
0 0 0 1 1
0 0 1 0 1
0 0 1 1 0
0 1 0 0 1
0 1 0 1 1
0 1 1 0 0
0 1 1 1 0
1 0 0 0 1
1 0 0 1 0
1 0 1 0 0
1 0 1 1 0
1 1 0 0 0
1 1 0 1 0
1 1 1 0 0
1 1 1 1 0
 PRODUCT OF SUM FORM

CIRCUIT DIAGRAM

THRUTH TABLE

A B C D F= (B’+D)(A’+B’)( C’+D’)
0 0 0 0 1
0 0 0 1 1
0 0 1 0 1
0 0 1 1 0
0 1 0 0 1
0 1 0 1 1
0 1 1 0 0
0 1 1 1 0
1 0 0 0 1
1 0 0 1 0
1 0 1 0 0
1 0 1 1 0
1 1 0 0 0
1 1 0 1 0
1 1 1 0 0
1 1 1 1 0

RESULT:
 HALF ADDER

CIRCUIT DIAGRAM

x 1 s
7486 3
2
y

1 c
3
2 7408

TRUTH TABLE

X Y C S
0 0 0 0
0 1 0 1
1 0 0 1
1 1 1 0
 Ex. No. : 2
Date :

IMPLEMENTATION OF ADDER/ SUBTRACTOR CIRCUITS

AIM:

To study and verify the following circuits.

1. half adder
2. Full adder
3. Half subtractor
4. Full subtractor

APPARATUS REQUIRED:

1. Digital trainer kit

2. IC7400, IC 7486, IC 7408
3. Connecting wires

THEORY:

HALF ADDER:
Adding two single-bit binary values, X, Y produces a sum S bit and a carryout C-out bit.This
operation is called half addition and the circuit to realize it is called ahalf adder.

FULL ADDER:
Adding three single-bit binary values, X,Y,Z producesa sum bit S and a carry out C-out bit.
This operation is called Full addition and the circuit to realize it is called a Full adder.

HALF SUBTRACTOR:
Subtracting a single-bit binary value Y from another X (I.e. X -Y ) producesa difference bit
Dand a borrow out bit B-out.This operation is called half subtraction and the circuit to realize it is
calleda half subtractor.

FULL SUBTRACTOR:
Subtracting two single-bit binary values, Y, Z from a single-bit value X produces adifference
bit D and a borrow out B-out bitthis is called full subtraction.

PROCEDURE:
1. Connections are made as per the circuit diagram.
2. Power supply is switched ON.
3. Truth table is verified.
 FULL ADDER

CIRCUIT DIAGRAM

TRUTH TABLE

X Y Z C S
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
Draw the K-MAP for C and S 1 0 0 0 1 and get the required expression
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1
 HAIF SUBTRATOR

CIRCUIT DIAGRAM

TRUTH TABLE

X Y B D
0 0 0 0
0 1 0 1
1 0 0 1
1 1 0 0
 FULL SUBTRACTOR

CIRCUIT DIAGRAM

TRUTH TABLE

x Y Z B D
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 1 0
1 0 0 0 1
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1

Draw the K-MAP for B and D and get the required expression
PROCEDURE:

1. The Encoder and Decoder circuit is designed and the Boolean function is found out.
2. The Low level input is Grounded and the HIGH level input is connected to the +5V
supply.
3. Connections are made as per the circuit given.
4. Observe the output for various combinations of inputs.
5. Thus the truth table is verified.

RESULT:
 4:1 MULTIPLEXER
CIRCUIT DIAGRAM

TRUTH TABLE

Inputs Control input Outputs (D0,D1,D2,D3)

D0 D1 D2 D3 X Y Z

1 0 0 0 0 0 D0

0 1 0 0 0 1 D1

0 0 1 0 1 0 D2

0 0 0 1 1 1 D3
 Ex. No. : 3
Date :

MULTIPLEXER AND DEMULTIPLEXER

AIM:

To construct and verify the truth table of multiplexer anddemultiplexer circuits

APPARATUS REQUIRED:

Particular Name SPECIFICATION QUANTITY

S.NO
1 Digital IC trainer kit ---- 1
2 IC7404, IC7432 IC7411 ---- 1 each
Connecting Wires 2
3

THEORY:

MULTIPLEXER:
Multiplexer means transmitting a large number of information units over a smaller
number of channels or lines. A digital multiplexer is a combinational circuit that selects binary
information from one of many input lines and directs it to a single output line. The selection of a
particular input line is controlled by a set of selection lines. Normally there are 2 n input line and
n selection lines whose bit combination determine which input is selected.
DEMULTIPLEXER:
The function of Demultiplexer is in contrast to multiplexer function. It takes information
from one line and distributes it to a given number of output lines. For this reason, the
demultiplexer is also known as a data distributor. Decoder can also be used as demultiplexer.
In the 1: 4 demultiplexer circuit, the data input line goes to all of the AND gates. The
data select lines enable only one gate at a time and the data on the data input line will pass
through the selected gate to the associated data output line.
 1:4 DE MULTIPLEXER

CIRCUIT DIAGRAM

TRUTH TABLE

INPUTS CONTROL INPUTS OUTPUTS

D X Y D0 D1 D2 D3
1 0 0 1 0 0 0
1 0 1 0 1 0 0
1 1 0 0 0 1 0
1 1 1 0 0 0 1
0 X X 0 0 0 0
PROCEDURE:

1. The Encoder and Decoder circuit is designed and the Boolean function is found out.
2. The Low level input is Grounded and the HIGH level input is connected to the +5V
supply.
3. Connections are made as per the circuit given.
4. Observe the output for various combinations of inputs.
5. Thus the truth table is verified.
BLOCK DIAGRAM FOR 4:1 MULTIPLEXER:

FUNCTION TABLE:

S1 S0 INPUTS Y
0 0 D0 → D0 S1’ S0’
0 1 D1 → D1 S1’ S0
1 0 D2 → D2 S1 S0’
1 1 D3 → D3 S1 S0

Y = D0 S1’ S0’ + D1 S1’ S0 + D2 S1 S0’ + D3 S1 S0

BLOCK DIAGRAM FOR 1:4 DEMULTIPLEXER:

FUNCTION TABLE:

S1 S0 INPUT
0 0 X → D0 = X S1’ S0’
0 1 X → D1 = X S1’ S0
1 0 X → D2 = X S1 S0’
1 1 X → D3 = X S1 S0

Y = X S1’ S0’ + X S1’ S0 + X S1 S0’ + X S1 S0

RESULT:
 CODE CONVERTER

CIRCUIT DIAGRAM OF BINARY TO GRAY CODE CONVERTER

Draw the K-MAP for B0, B1, B2 and B3 and get the required expression.

CIRCUIT DIAGRAM OFGRAY TO BINARY CODE CONVERTER

Draw the K-MAP for G0, G1, G2 and G3 and get the required expression.
 Ex. No. : 4
Date :

IMPLEMENTATION OF CODE CONVERTERS USING LOGIC GATES

Binary to Gray code convertor and Gray to Binary code convertor

AIM:

To design and verify the code converting circuits.

APPARATUS REQUIRED:

1. Digital trainer kit

2. IC7486

3. Connecting wires

THEORY:

There is a wide variety of binary codes that are used in digital systems to represent the
decimal digits 0 through 9. Some of the most commonly used codes are 8-4-2-1 binary code, excess-
3 code and gray code. Four bits are required to represent the decimal digits in these codes. Among
these codes the gray code is one important code which is often used in digital systems because it has
the advantage that only one bit in the numerical representation changes between any two successive
numbers.

PROCEDURE:

BINARY TO GRAY CODE CONVERTER:

1. Set up the circuit of a binary to gray code converter using IC7486 EX-OR gate.

2. Apply 4-bit binary inputs 0000 through 1111.

3. Observe the output in each case and verify the result.

GRAY TO BINARY CODE CONVERTER:

1. Set up the circuit of a gray to binary code converter using IC7486 EX-OR gate.

2. Apply 4-bit gray inputs 0000 through 1111.

3. Observe the output in each case and verify the result.

TRUTH TABLE FOR BINARY ↔ GRAY CODE CONVERTOR

Binary Gray
Decimal
B0 B1 B2 B3 G0 G1 G2 G3
0 0 0 0 0 0 0 0 0
1 0 0 0 1 0 0 0 1
2 0 0 1 0 0 0 1 1
3 0 0 1 1 0 0 1 0
4 0 1 0 0 0 1 1 0
5 0 1 0 1 0 1 1 1
6 0 1 1 0 0 1 0 1
7 0 1 1 1 0 1 0 0
8 1 0 0 0 1 1 0 0
9 1 0 0 1 1 1 0 1
10 1 0 1 0 1 1 1 1
11 1 0 1 1 1 1 1 0
12 1 1 0 0 1 0 1 0
13 1 1 0 1 1 0 1 1
14 1 1 1 0 1 0 0 1
15 1 1 1 1 1 0 0 0
CIRCUIT DIGRAM FOR BCD TO EXCESS-3 CODE CONVERTOR:
TRUTH TABLE

Draw the K-map for E3, E2, E1, and E0 and get the expression
 BCD to XS3 code convertor and XS3to BCD code converter

AIM:

To design and verify the code converting circuits.

APPARATUS REQUIRED:

1. Digital trainer kit

2. IC7486

3. Connecting wires

THEORY

The term BCD refers to representing the ten decimal digits in binary forms. The
Excess-3 system simply adds 3 to each number to make the codes look different. We will
not venture to discuss the importance of the Excess-3 BCD system because the discussion
would serve too great a distraction from our present purpose and the cost would outweigh
the benefit. Suffice it to say that the Excess-3 BCD system has some properties that made
it useful in early computers.

PROCEDURE:

1. Give the connections as per the circuit diagram.

2. Apply 4- bit binary inputs 0000 through 1111.
3. Observe the output in each case and verify the result.
CIRCUIT DIGRAM FOR EXCESS-3 TO BCD CODECONVERTOR:

TRUTH TABLE

Draw the K-map for B3, B2, B1, and B0 and get the expression
RESULT:
 Ex. No. : 5
Date :

IMPLEMENTATION OF FLIP FLOPS

Aim: -Verification of state tables of

R-S flip-flop
J - K flip-flop
T Flip-Flop
D Flip-Flop Using NAND and NOR gates.

APPARATUS REQUIRED:
IC 7400 (NAND Gate), IC 7402 (NOR Gate), IC 7408 (AND Gate).

Theory: -
In case of sequential circuits the effect of all previous inputs on the outputs is represented by a
state of the circuit. Thus, the output of the circuit at any time depends upon its current state and
the input. These also determine the next state of the circuit. The relationship that exists among
the inputs, outputs, present states and next states can be specified by either the state table or the
state diagram.

State Table: -
The state table representation of a sequential circuit consists of three sections labelledpresent
state next stateand output. T he p r e sen t s t a t e
d e s i gn a t e s t h e s t a t e o f f l i p - f l op s be f o re t h e occurrence of a clock pulse. The
next state shows the states of flip-flops after the clock pulse, and the output section lists the
value of the output variables during the present state.

Flip-Flop:-
The basic one bit digital memory circuit is known as flip-flop.It can store either 0or 1. Flip-flops
are classifieds according to the number of inputs.

R-S Flip-Flop:-
The circuit is similar to SR latch except enable signal is replaced by clock pulse.
Logic Diagram:

Characteristic table for S-R flip flop:

D Flip-Flop:-
The modified clocked SR flip-flop is known as D-flip-flop.From the truth tableof SR
flip-flop we see that the output of the SR flip-flop is in unpredictable state when the
inputsare same and high. In many practical applications, these input conditions are not
required. These inputconditions can be avoided by making then complement of each
other.
Logic Diagram:

Characteristic table for D flip flop

J-K Flip-Flop:-
In a RS flip-flop the input R=S=1 leads to an indeterminate output. The RSflip-flop
circuit may be re-joined if both inputs are 1 than also the outputs are complement of
each other.
 Logic Diagram

Characteristic table for J-K flip flop

T Flip-Flop:-
T flip-flop is known as toggle flip-flop. The T flip-flop is modification of the J-K f l i p -
f l op . Bot h t h e J K i np ut s of t h e J K f l i p - f l o p a r e h e l d a t l o gic 1 and t h e
c l oc k s i gn a l continuous to change.
 Logic Diagram

Characteristic table for T flip flop

Procedure:-
Connections are given as per the circuit diagram.
Verify truth-tables for various combinations of input.
 RESULT: -

COUNTER
PIN CONFIGURATION
BINARY 4-BIT SYNCHRONOUS COUNTER
 Ex. No. : 6A
Date :

DESIGN AND IMPLEMENTATION OF SYNCHRONOUS COUNTER

AIM:

To design and implement 4 bit asynchronous Ripple counter.

APPARATUS REQUIRED:

1. IC 7408, IC 7476, IC 7400,IC 7432

2. IC trainer kit
3. Connecting Wires.

THEORY:

It can be seen that the external clock pulses (pulses to be counted) are fed directly to
each J-K flip-flop in the counter chain and that both the J and K inputs are all tied together in
toggle mode, but only in the first flip-flop, flip-flop A (LSB) are they connected HIGH, logic
"1" allowing the flip-flop to toggle on every clockpulse. Then the synchronous counter follows
apredetermined sequence of states in response to the common clock signal, advancing one state
for each pulse.

The J and K inputs of flip-flop B are connected to the output "Q" of flip-flop A, but the J and K
inputs of flip-flops C and D are driven from AND gates which are also supplied with signals
from the input and output of the previous stage. If we enable each J-K flip-flop to toggle based
on whether or not all preceding flip-flop outputs (Q) are "HIGH" we can obtain the same
counting sequence as with the asynchronous circuit but without the ripple effect, since each flip-
flop in this circuit will be clocked at exactly the same time. As there is no propagation delay in
synchronous counters because all the counter stages are triggered in parallel the maximum
operating frequency of this type of counter is much higher than that of a similar asynchronous
counter. Because this 4-bit synchronous counter counts sequentially on every clock pulse the
resulting outputs count upwards from 0 ( "0000" ) to 15 ( "1111" ). Therefore, this type of
counter is also known as a 4-bit Synchronous Up Counter.
Pin diagram

4-bit Synchronous Counter Waveform Timing Diagram.

 TRUTH TABLE

COUN OUTPUTS
T
QD QC QB QA
0 0 0 0 0
1 0 0 0 1
2 0 0 1 0
3 0 0 1 1
4 0 1 0 0
5 0 1 0 1
6 0 1 1 0
7 0 1 1 1
8 1 0 0 0
9 1 0 0 1
10 1 0 1 0
11 1 0 1 1
12 1 1 0 0
13 1 1 0 1
14 1 1 1 0
15 1 1 1 1
Truth Table for JK flip-flop:

J K Qn+1
0 0 Qn
0
0 1
1
1 0
Qn
1 1
PROCEDURE:

1. Connections are made as per circuit diagram.

2. Clock pulses are applied one by one at the clock I/P and the O/P is observed at QA,
QB & QC for IC 7476.
3. Verify the Truth table.

DISCUSSION QUESTIONS:

1. What are the applications of counter?

2. State the types of counter.
3. Define bit, byte and word.
4. What is timing diagram?

RESULT:
PIN DIAGRAM FOR IC 7476:

LOGIC DIAGRAM FOR 4 BIT RIPPLE COUNTER:

 Ex. No. : 6B
Date :
DESIGN AND IMPLEMENTATION OF ASYNCHRONOUS COUNTER

AIM:

To design and implement 4 bit asynchronous Ripple counter .

APPARATUS REQUIRED:

Sl.No. COMPONENT SPECIFICATION QTY.

1. JK FLIP FLOP IC 7476 2
2. NAND GATE IC 7400 1
3. IC TRAINER KIT - 1
4. PATCH CORDS - 30

THEORY:

A counter is a register capable of counting number of clock pulse arriving at its clock input.
Counter represents the number of clock pulses arrived. A specified sequence of states appears as
counter output. This is the main difference between a register and a counter. There are two types of
counter, synchronous and asynchronous. In synchronous common clock is given to all flip flop and in
asynchronous first flip flop is clocked by external pulse and then each successive flip flop is clocked
by Q or Q output of previous stage. A soon the clock of second stage is triggered by output of first
stage. Because of inherent propagation delay time all flip flops are not activated at same time which
results in asynchronous operation. A simple implementation of a 4-bit counter is shown in Figure 1,
which consists of 4 stages of cascaded J-K flip-flops. This is a binary counter, since the output is in
binary system format, i.e., only two digits are used to represent the count, i.e., '1' and '0'. With only 4
bits, it can only count up to '1111', or decimal number 15. The J and K inputs of all the flip-flops are
tied to '1', so that they will toggle between states every time they are clocked. Also, the output of each
flip-flop in the counter is used to clock the next flip-flop. As a result, the succeeding flip-flop toggles
between '1' and '0' at only half the frequency as the flip-flop before it.
TRUTH TABLE:

CLK QA QB QC QD
0 0 0 0 0
1 1 0 0 0
2 0 1 0 0
3 1 1 0 0
4 0 0 1 0
5 1 0 1 0
6 0 1 1 0
7 1 1 1 0
8 0 0 0 1
9 1 0 0 1
10 0 1 0 1
11 1 1 0 1
12 0 0 1 1
13 1 0 1 1
14 0 1 1 1
15 1 1 1 1
PROCEDURE:

1. Connections are made as per circuit diagram.

2. Clock pulses are applied one by one at the clock I/P and the O/P is observed at QA, QB &
QC for IC 7476.
3. Verify the Truth table.

RESULT:
Ex. No. : 7
Date :

VHDL SIMULATION OF ADDERS AND MULTIPLEXERS

AIM: Write VHDL program for full adder,Multiplexer and verify the design

Procedure to work with Xilinx ISE 14.7 software:

PROCEDURE FOR HDL BASED DESIGN ENTRY AND

SIMULATION IN XILINX ISE

1. Start the Xilinx ISE by using start Program files  Xilinx ISE (8.2i) 
project navigator

2. File New Project

3. Enter the Project Name and location then click next

4. Select the Device and other category and click next twice and finish.

5. Click on the symbol of FPGA device and then right clickclick on new source.

6. Select the Verilog Module and give the file name click next and define ports
click next and finish.

7. Writing the behavioral Verilog Code in Verilog Editor.

8. Run the Check syntax Process windowsynthesize double

click check syntax and remove errors, if present, with proper
syntax & coding.

9. Click on the symbol of FPGA device and then right click click on new
source.
 10. Select the Test Bench Waveform and give the file name  select entity click
next and finish.

11. Select the desired parameters for simulating your design.

combinational circuit and simulation time click finish.

12. Assign all input signal using just click on graph and save file.

13. From the source process window. Click Behavioral simulation

from drop-down menu

14. Select the test bench file (.tbw) and click process buttondouble click the
Simulation Behavioral Model

15.Verify your design in wave window by seeing behavior of

output signal with respect to
input signal.

VHDL CODE FOR FULL ADDER DATA FLOW:

Full Adder
A EXPRESSIONS:
B
Ci S = A ⊕ B ⊕ Ci
S
Co CO = (A ⊕ B)Ci + AB
0
0
0
0
VHDL CODE FOR FULL ADDER
BEHAVIORAL:

library IEEE;
useIEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity fa1 is
Port ( a,b,ci : in STD_LOGIC; s,co : out
STD_LOGIC); end fa1;
architecture Behavioral of fa1 is
begin

begin s<=a xor b xor ci;

process(a,b,ci) co<=(a and b)or (b and ci)or (ci and a);
end process; end
Behavioral;

VHDL CODE FOR FULL ADDER STRUCTURAL:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use
IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity fa1 is
Port ( a,b,cin : in STD_LOGIC;
s,cout : out STD_LOGIC);
end fa1; architecture
struct of fa1 is
component and21
port(a,b:in std_logic; ---components, entity and architecture
c:out std_logic); --- must be declared separately
end component;
component xor21
port(a,b:in std_logic; ---components, entity and architecture
c:out std_logic); --- must be declared separately
end component;
component or31
port(a,b:in std_logic; ---components, entity and architecture
d:out std_logic); --- must be declared separately
end component;
signal s1,s2,s3:std_logic;
 begin
u1:xor21 port map(a,b,s1);
u2:xor21 port map(s1,cin,s);
u3:and21 port map(a,b,s2);
u4:and21 port map(s1,cin,s3);
u6:or31 port map(s2,s3,cout);
end struct;

SIMULATION OF FULL ADDER

VHDL CODE FOR MULTIPLEXER (8:1):

INPUTS SELECT LINES O/

P
d( d( d( d( d( d( d( d( s( s( s( f
7) 6) 5) 4) 3) 2) 1) 0) 2) 1) 0)
X X X X X X X 0 0 0 0 0
X X X X X X X 1 0 0 0 1
X X X X X X 0 X 0 0 1 0
X X X X X X 1 X 0 0 1 1
X X X X X 0 X X 0 1 0 0
X X X X X 1 X X 0 1 0 1
X X X X 0 X X X 0 1 1 0
X X X X 1 X X X 0 1 1 1
X X X 0 X X X X 1 0 0 0
X X X 1 X X X X 1 0 0 1
X X 0 X X X X X 1 0 1 0
X X 1 X X X X X 1 0 1 1
X 0 X X X X X X 1 1 0 0
X 1 X X X X X X 1 1 0 1
0 X X X X X X X 1 1 1 0
1 X X X X X X X 1 1 1 1
library IEEE;
use
IEEE.STD_LOGIC_1164.ALL;
use
IEEE.STD_LOGIC_ARITH.AL
L;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity mux1 is
Port ( d : in STD_LOGIC_VECTOR (7
downto 0); s : in STD_LOGIC_VECTOR
(2 downto 0);
f : out STD_LOGIC);
end mux1;
architecture Behavioral of mux1 is
begin
f<= d(0) when s="000" else
d(1) when s="001" else d(2)
when s="010" else d(3)
when s="011" else d(4)
when s="100" else d(5)
when s="101" else d(6)
when s="110" else d(7)
when s="111";
end Behavioral;
SIMULATION OF MULTIPLEXER
RESULT:
Ex. No. : 8
Date :

VHDL SIMULATION OF FLIP-FLOPS AND COUNTERS

AIM: To write VHDL program for Flip flops and counters verify the design

Procedure to work with Xilinx ISE 14.7 software:

PROCEDURE FOR HDL BASED DESIGN ENTRY AND

SIMULATION IN XILINX ISE

1. Start the Xilinx ISE by using start Program files  Xilinx ISE (8.2i) 
project navigator

2. File New Project

3. Enter the Project Name and location then click next

4. Select the Device and other category and click next twice and finish.

5. Click on the symbol of FPGA device and then right clickclick on new source.

6. Select the Verilog Module and give the file name click next and define ports
click next and finish.

7. Writing the behavioral Verilog Code in Verilog Editor.

8. Run the Check syntax Process windowsynthesize double

click check syntax and remove errors, if present, with proper
syntax & coding.

9. Click on the symbol of FPGA device and then right click click on new
source.

10. Select the Test Bench Waveform and give the file name  select entity click
 next and finish.

11. Select the desired parameters for simulating your design.

combinational circuit and simulation time click finish.

12. Assign all input signal using just click on graph and save file.

13. From the source process window. Click Behavioral simulation

from drop-down menu

14. Select the test bench file (.tbw) and click process buttondouble click the
Simulation Behavioral Model

15.Verify your design in wave window by seeing behavior of

output signal with respect to input signal.

VHDL CODE FOR D FLIP FLOP:

Cle D Clo Qn Qn
ar ck +1
+1
1 0 0 0 1
0 1 1 0

library IEEE;
use
IEEE.STD_LOGIC_1164.ALL;
use
IEEE.STD_LOGIC_ARITH.AL
L;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity dff is
Port ( d,res,clk : in
STD_LOGIC; q : out
STD_LOGIC);
end dff;
architecture Behavioral of dff is
begin
process(clk)
begin
if (res ='1')then q<='0';
elsif clk'event and clk='1'
then q<=d;
end if;
end process; end
Behavioral;
 VHDL CODE FOR T FLIP FLOP:

Cle T Clo Qn+ Qn

ar ck 1
+1
1 0 0 0 Qn
0 1 Q Qn
n

library IEEE;
use
IEEE.STD_LOGIC_1164.ALL;
use
IEEE.STD_LOGIC_ARITH.AL
L;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity tff is
Port ( t,clk,rst : in
STD_LOGIC; q : inout
STD_LOGIC);
end tff;
architecture Behavioral of tff is
signal div:std_logic_vector(22 downto 0);
signal clkd:std_logic;
begin
process(clk)
begin
l
k
end if; )
i t
f h
e
r n
i
s d
i i
n v
g <
_ =
e
d d
g i
e v
( +
c 1
;
end process;
clkd<=div(20);
process(clkd,rst) begin
t
h
e
n

end if; q
i <
f =
( '
r 0
s '
t ;
= elsif (clkd'event
' and clkd='1'
1 and t='1') then
' q<= not q;
) else q<=q;
end process; end
Behavioral;
BCD UP COUNTER:

Cl Q Q Q Q
oc D C B A
k
0 0 0 0 0
1 0 0 0 1
2 0 0 1 0
3 0 0 1 1
4 0 1 0 0
5 0 1 0 1
6 0 1 1 0
7 0 1 1 1
8 1 0 0 0
9 1 0 0 1
10 0 0 0 0

library IEEE;
use
IEEE.STD_LOGIC_1164.ALL;
use
IEEE.STD_LOGIC_ARITH.AL
L;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity bcdupcount is
Port ( clk,rst : in STD_LOGIC;
q : inout STD_LOGIC_VECTOR (3 downto
0)); end bcdupcount;
architecture Behavioral of bcdupcount is
signal div:std_logic_vector(22 downto 0);
signal clkd:std_logic;
begin
process(clkd)
begin
if rising_edge(clk)then
div<= div+1;
end if;
end process;
clkd<=div(22);
process(clkd,rst) begin
if rst='0' or q="1010" then
q<="0000";
elsif clkd'event and clkd='1' then
q<=q+1;
end if;
end process;
q<=q; end
Behavioral;
RESULT:
 Ex. No. : 9
Date :

WASHING MACHINE CONTROL USING BASIC AND & NOT GATES

Aim:
To construct logic circuit of washing machine control using a Virtual Labs and verify
its output.

Theory:

Introduction:
When logic gates are connected together to produce a specific output for certain specific
combinations of input variables, with no storage involved, the resulting circuit is called as
a Combinational logic circuit. The combination of basic gates can be used for a variety of applications
such as washing machine control, level monitoring and indicating applications in manufacturing
processes, elevator control applications, a warning indicating applications and binary addition -
subtraction and multiplication circuits.

APPLICATION: WASHING MACHINE CONTROLLER

For simplicity, consider a three-sensor based washing machine controller namely Door
Sensor, Water Level Sensor and Temperature Sensor that produce digital outputs. Let the controlling
action include control of Water Valve, Heater and Motor. All these are digitally controlled devices.

1.2 CONCEPT
The motor of the washing machine turns ON when the right temperature, the right water
level and obviously when the door of the machine is closed.
The system design involves three inputs: D, L & T representing Door position, Level &
Temperature respectively. It controls three output devices: W, H & M representing Water Valve,
Heater & Motor respectively. Let us decide the logics behind the system:

D = 0 ------- Door Open;

D = 1-------- Door Closed (desired)
L = 0 --------Water Level is LOW;
 L = 1 --------Water Level is HIGH (satisfactory)
T = 0 --------Temperature is LOW
T = 1 --------Temperature is HIGH (right value)
The truth table for this application can be developed by logical reasoning:

1. For turning ON of any of the output devices, the washing machine door/lid
should be closed at any point of time, so only last four cases of the truth table
should to be considered where D takes a value 1.
2. If door is closed & water level is LOW, the water valve should be turned ON.
3. If door is closed, water level is satisfactory (HIGH) & the temperature is low,
the heater should be turned ON.
4. Whereas when the door is closed, water level is satisfactory and the
temperature is right, the motor should turn ON.

Door(D) Level(L) Temper Valve(V) Heater Motor(M)

ature(T) (H)

0 0 0 0 0 0
0 0 1 0 0 0
0 1 0 0 0 0
0 1 1 0 0 0
1 0 0 1 0 0
1 0 1 1 0 1
1 1 0 0 1 0
1 1 1 0 0 1
Considering only those input conditions that produce a HIGH output, we get the reduced
Boolean expressions for controlling as follows:
Water Valve (V) = D.L'
Heater (H) = D.L.T'
Motor (M) = D.L.T
The corresponding combinational logic circuit is as shown in Figure 1.
Procedure:

1. Procedure: Turn On/OFF the inputs, D, L and T according to the truth table.
2. Note the output for various combinations of input.
3. Validate that the design works as per the problem statement:The motor of the washing
machine turns ON when the right temperature, the right water leveland obviously when
the door of the machine is closed.
4. Using simulator build the washing machine control circuit and verify the result.

Simulation:
Result: