NAME : BALAM VENKATA SAI BHARATH

REG.NO : 20MIS0102

COURSE : DIGITAL LOGIC AND MICROPROCESSOR

(LAB)

SLOT : L11+L12

FACULTY : SUGANYA P MAM

 Assessment 1: Combinational Logic Circuits

1)Verification of Logic gates

a).Verify the working of OR gate with its truth table
b)Verify the working of AND gate with its truth table
c) Verify the working of NOT gate with its truth table

d)Verify the working of NOR gate with its truth table

e)Verify the working of NAND gate with its truth table
f) Verify the working of X- OR gate with its truth table
g) Verify the working of X-NOR gate with its truth table
2)Verification of Boolean Expressions
a) X+X’Y=X+Y
x y x+x'y x+y

0 0 0 0

0 1 1 1

1 0 1 1

1 1 1 1
b) X’+XY=X’+Y
x y x'+xy x'+y
0 0 1 1
0 1 1 1
1 0 0 0
1 1 1 1
c) AB+A’C+BC=AB+A’C
A B C AB+A'C+BC AB+A'C
0 0 0 0 0
0 0 1 1 1
0 1 0 0 0
0 1 1 1 1
1 0 0 0 0
1 0 1 0 0
1 1 0 1 1
1 1 1 1 1
 d) PQ+Q’R+WPRQ=PQ+Q’R

p q r w Pq+q'r+wprq Pq+q'r
0 0 0 0 0 0
0 0 0 1 0 0
0 0 1 0 1 1
0 0 1 1 1 1
0 1 0 0 0 0
0 1 0 1 0 0
0 1 1 0 0 0
0 1 1 1 0 0
1 0 0 0 0 0
1 0 0 1 0 0
1 0 1 0 1 1
1 0 1 1 1 1
1 1 0 0 1 1
1 1 0 1 1 1
1 1 1 0 1 1
1 1 1 1 1 1
3) Simplify the following functions, and implement them using NAND and
NOR gates only:

F(A, B, C, D) = AC’D’ + A’C + ABC + AB’C + A’C’D'

-> F=D'+C;
C D D' F

0 0 1 1
0 1 0 0
1 0 1 1
1 1 0 1
a)implementation by using nand gate:

b)implementation by using nor gate:

4)Design a Half adder, Full adder, Half Subtractor and Full
Subtractor?

1)Half adder:{S=A XOR B;C=AB}

A B S C
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1
2)full adder:{S=A XOR B XOR C;Cout=AC+BC+AB}

A B C S Cout
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
3)Half subtractor:{D=A XOR B;Bout=A'B}

A B D Bout
0 0 0 0
0 1 1 1
1 0 1 0
1 1 0 0
4)full subtractor:{D=A XOR B XORC;Bout=BC+A'C+A'B}

A B C D Bout
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1
6).Implement the following function using 8x1 Multiplexer
F(A,B,C,D)=Σ (0,1,3,4,8,9,15)?

D0 D1 D2 D3 D4 D5 D6 D7

A' 0 1 2 3 4 5 6 7

A 8 9 10 11 12 13 14 15

D0 1

D1 1

D2 0

D3 A'

D4 A'

D5 0

D6 0

D7 A
8).You are asked to design the following circuit for your car. The
warning signal W should be set to high voltage (logical 1) if:
a) the engine is running and door is open; or
b) With the engine running, somebody is sitting in the driver‟s
seat and the belt is not fastened.
Otherwise output of the circuit is „0‟. The circuit should rely on
the following sensors:
sensors from engine(C=„1‟ if engine is running, otherwise it is
„0‟)
Seat sensor (S=1 if somebody is sitting on the seat, otherwise
„0‟)
Door sensor (D=1 if the door is open, otherwise „0‟)
Belt sensor (B=1 if the belt is fastened, otherwise „0‟)

A:-
>Let,A-'Engine sensor'-1/0;B-'Seat sensor'-1/0;C-'Door sensor'-
1/0;D-'belt sensor'-1/0&W-output.
->If A&C~1 then W~1 or If A&B~1&D~0 then W~1 &in all
othercases W~0.
A B C D W
0 0 0 0 0
0 0 0 1 0
0 0 1 0 0
0 0 1 1 0
0 1 0 0 0
0 1 0 1 0
0 1 1 0 0
0 1 1 1 0
1 0 0 0 0
1 0 0 1 0
1 0 1 0 1
1 0 1 1 1
1 1 0 0 1
1 1 0 1 0
1 1 1 0 1
1 1 1 1 1
->By the simplification of W o/p through K-map we get

W=AC+ABD'.By this we can design the circuit&verify it with

the truth table.

5).Find the sum and the difference of the following two binary

numbers.A=1101 B=1010 ?

A:->We can find both sum&difference of the given inputs in a

single design i;e by using 4bit parllel adder-subtractor circuit,by

changing the M value i;e M-0(for ADDER so that we'll get

sum)&M-1(for SUBTRACTOR so that we'll get difference).

1(A3) 1(A2) 0(A1) 1(A0)

SUM 1(B3) 0(B2) 1(B1) 0(B0)

1(X1) 0(X2) 1(X3) 1(X4) 1(X5)

 1(A3) 1(A2) 0(A1) 1(A0)

DIFF 0 1 1 0 (2's
comp of
B)
1(X1) 0(X2) 0(X3) 1(X4) 1(X5)
7)Design a combinational logic circuit that receives a BCD number

as a four bit binary variables whose output is input binary number

minus 3 using decoder. (Use Don't Care wherever necessary)

A:-

A B C D Minterms X3 X2 X1 X0

0 0 0 0 mo X X X X

0 0 0 1 m1 X X X X

0 0 1 0 m2 X X X X

0 0 1 1 m3 0 0 0 0

0 1 0 0 m4 0 0 0 1

0 1 0 1 m5 0 0 1 0

0 1 1 0 m6 0 0 1 1

0 1 1 1 m7 0 1 0 0

1 0 0 0 m8 0 1 0 1
1 0 0 1 m9 0 1 1 0

1 0 1 0 m10 X X X X

1 0 1 1 m11 X X X X

1 1 0 0 m12 X X X X

1 1 0 1 m13 X X X X

1 1 1 0 m14 X X X X

1 1 1 1 m15 X X X X
NAME:M S S HARSHITH.
REGNO:20MIS0133.