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Lab 5

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INTERNATIONAL UNIVERSITY

SCHOOL OF ELECTRICAL ENGINEERING

Digital Logic Design Laboratory

Lab 5

Demultiplexers

Full name: …………………………………………….


Student number: ………………………………….
Class: ……………………………………………….......
Date: …………………………………………………....

Digital Logic Design Laboratory 1-11


INTERNATIONAL UNIVERSITY
SCHOOL OF ELECTRICAL ENGINEERING

I. Objectives

In this laboratory, students will study:


- Understand and design a multiplexer.
- Use a demultiplexer and design/implement a circuit based on a function
definition.
- Design combinational circuits using DEMUX.

II. Procedure

1. Design demultiplexer using logic gates


a. Design 1-to-2 demultiplexer using logic gates:
A 1-to-2 demultiplexer has I is the input, S is the selector input, and Y 1 and Y2 are two
outputs. When S = 0 then Y0 = I but when S = 1 then Y 1 = I. The Figure 1 shows the
illustration of DEMUX 1-2.

Figure 1. The illustration of DEMUX 1-2.

Built the truth table:


Input Output
S I Y0 Y1
0 0 0 0
0 1 1 0
1 0 0 0
1 1 0 1

The expressions:Y 0=S I ,Y 1=SI

Digital Logic Design Laboratory 2-11


INTERNATIONAL UNIVERSITY
SCHOOL OF ELECTRICAL ENGINEERING

Implement the circuit via simulation software and paste the result in here

Make comment on the results


b. Design 1-to-4 DEMUX using logic gates.
Build the circuit. The inputs S0, S1, I, are driven by 6 switches. The outputs Y0, Y1,
Y2, Y3 are connected to LED.

Input Output
S1 S0 I Y0 Y1 Y2 Y3
0 0 0 0 0 0 0
0 0 1 1 0 0 0
0 1 0 0 0 0 0
0 1 1 0 1 0 0
1 0 0 0 0 0 0
1 0 1 0 0 1 0
1 1 0 0 0 0 0
1 1 1 0 0 0 1

The expressions: Y 0=S 1 S 0 I ; Y 1=S 1 S 0 I ; Y 2=S 1 S 0 I ; Y 3=S 1 S 0 I

Digital Logic Design Laboratory 3-11


INTERNATIONAL UNIVERSITY
SCHOOL OF ELECTRICAL ENGINEERING

Implement the circuit via simulation software and paste the result in here

Make comment on the results

c. Design 1-to-4 DEMUX using 3 DEMUX 1-2.


Implement the circuit via simulation software and paste the result in here

Digital Logic Design Laboratory 4-11


INTERNATIONAL UNIVERSITY
SCHOOL OF ELECTRICAL ENGINEERING

Make comment on the results

2. Investigate IC 1-to-8 DeMultiplexer (74HC238)


Construct the circuit as below:

Digital Logic Design Laboratory 5-11


INTERNATIONAL UNIVERSITY
SCHOOL OF ELECTRICAL ENGINEERING

Figure 2. IC 1-to-8 DeMultiplexer (74HC238)

- 8 outputs are connected by using LEDs.


- The inputs are controlled by switches.
- Observe the results and fulfill the truth table

INPUT OUTPUT
S2 S1 S0 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
0 0 0 1 0 0 0 0 0 0 0
0 0 1 0 1 0 0 0 0 0 0
0 1 0 0 0 1 0 0 0 0 0
0 1 1 0 0 0 1 0 0 0 0
1 0 0 0 0 0 0 1 0 0 0
1 0 1 0 0 0 0 0 1 0 0
1 1 0 0 0 0 0 0 0 1 0
1 1 1 0 0 0 0 0 0 0 1

Implement the circuit via simulation software and paste the result in here

Digital Logic Design Laboratory 6-11


INTERNATIONAL UNIVERSITY
SCHOOL OF ELECTRICAL ENGINEERING

Briefly describe the operation of the IC

3. Design 1-bit Full Subtractor


a. Using logic gates
Construct the circuit as below:
Three inputs are A, B, Bin. Two outputs are D and Bout.
Build the truth table and the expressions

Digital Logic Design Laboratory 7-11


INTERNATIONAL UNIVERSITY
SCHOOL OF ELECTRICAL ENGINEERING

Input Output
A B Bin D Bout
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1

The simplified expressions:


D = A B Bin + A B Bin + A B Bin + AB Bin
Simplified expressions : D = A B Bin + A B Bin + A B Bin + AB Bin

Bout = A B Bin + A B Bin + A B Bin + AB Bin


AB Bin 0 1
00 0 1
01 1 1
11 0 1
10 0 0
Simplified expressions: Bout = A B+B Bin+ A (Bin)

Implement the circuit via simulation software and paste the result in here

Digital Logic Design Laboratory 8-11


INTERNATIONAL UNIVERSITY
SCHOOL OF ELECTRICAL ENGINEERING

Make comment on the results

b. 1-to-8 DeMultiplexer (74HC238)


Implement the circuit via simulation software and paste the result in here

Digital Logic Design Laboratory 9-11


INTERNATIONAL UNIVERSITY
SCHOOL OF ELECTRICAL ENGINEERING

Make comment on the results

4. Design 4-bit Full Adder using 74HC283 and display to BCD Seg
Construct the circuit as below:
Four inputs for A(A3, A2, A1, A0) and B(B3, B2, B1, B0). The outputs are display by
BCD 7seg

Digital Logic Design Laboratory 10-11


INTERNATIONAL UNIVERSITY
SCHOOL OF ELECTRICAL ENGINEERING

Implement the circuit via simulation software and paste the result in here

Make comment on the results

Digital Logic Design Laboratory 11-11

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