Lab 5
Lab 5
Lab 5
Lab 5
Demultiplexers
I. Objectives
II. Procedure
Implement the circuit via simulation software and paste the result in here
Input Output
S1 S0 I Y0 Y1 Y2 Y3
0 0 0 0 0 0 0
0 0 1 1 0 0 0
0 1 0 0 0 0 0
0 1 1 0 1 0 0
1 0 0 0 0 0 0
1 0 1 0 0 1 0
1 1 0 0 0 0 0
1 1 1 0 0 0 1
Implement the circuit via simulation software and paste the result in here
INPUT OUTPUT
S2 S1 S0 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
0 0 0 1 0 0 0 0 0 0 0
0 0 1 0 1 0 0 0 0 0 0
0 1 0 0 0 1 0 0 0 0 0
0 1 1 0 0 0 1 0 0 0 0
1 0 0 0 0 0 0 1 0 0 0
1 0 1 0 0 0 0 0 1 0 0
1 1 0 0 0 0 0 0 0 1 0
1 1 1 0 0 0 0 0 0 0 1
Implement the circuit via simulation software and paste the result in here
Input Output
A B Bin D Bout
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1
Implement the circuit via simulation software and paste the result in here
4. Design 4-bit Full Adder using 74HC283 and display to BCD Seg
Construct the circuit as below:
Four inputs for A(A3, A2, A1, A0) and B(B3, B2, B1, B0). The outputs are display by
BCD 7seg
Implement the circuit via simulation software and paste the result in here