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    معمارية 2

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    Firas
    The document discusses basic computer organization and design including instruction codes, stored program organization, computer registers, common bus systems, computer instructions, instruction cycles, and timing and control. It describes the major components of a computer and how they work together through the instruction cycle.

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    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd

    معمارية 2

    Uploaded by

    Firas
    9 views13 pages
    The document discusses basic computer organization and design including instruction codes, stored program organization, computer registers, common bus systems, computer instructions, instruction cycles, and timing and control. It describes the major components of a computer and how they work together through the instruction cycle.

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    © © All Rights Reserved

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    The document discusses basic computer organization and design including instruction codes, stored program organization, computer registers, common bus systems, computer instructions, instruction cycles, and timing and control. It describes the major components of a computer and how they work together through the instruction cycle.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    9 views13 pages

    معمارية 2

    Uploaded by

    Firas
    The document discusses basic computer organization and design including instruction codes, stored program organization, computer registers, common bus systems, computer instructions, instruction cycles, and timing and control. It describes the major components of a computer and how they work together through the instruction cycle.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
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    Basic Computer Organization and Design

    Instruction code is a group of bits that instruct the computer to


    perform a specific operation. It is usually divided into parts,
    each having its own particular interpretation. The most basic
    part of an instruction code is its operation code operation part.
    Stored Program Organization

    -Computers that have a single-processor register usually assign


    to it the name accumulator (AC) and label it AC.

    Indirect Address: It is sometimes convenient to use the address


    bits of an instruction code not as an address but as the actual
    operand. When the second part of an instruction code specifies
    an operand, the instruction is said to have an immediate
    operand.
    The effective address to be the address of the operand in a
    computation-type instruction or the target address in a branch-
    type instruction.

    Computer Registers
    -Computer instructions are normally stored in consecutive
    memory locations and are executed sequentially one at a time.
    Common Bus System
    Paths must be provided to transfer information from one register
    to another and between memory and registers. The number of
    wires will be excessive if connections are made between the
    outputs of each register and the inputs of the other registers.

    - The input data and output data of the memory are connected to
    the common bus, but the memory address is connected to AR.
    - DR←AC and AC ←DR can be executed at the same time.
    This can be done by placing the content of AC on the bus (with
    𝑆2 𝑆1 𝑆0 = 100), enabling the LD (load) input of DR, transferring
    the content of DR through the adder and logic circuit into AC,
    and enabling the LD (load) input of AC, all during the same
    clock cycle. The two transfers occur upon the arrival of the
    clock pulse transition at the end of the clock cycle.
    Computer Instructions

    The operation code (opcode) part of the instruction contains


    three bits and the meaning of the remaining 13 bits depends on
    the operation code encountered. A memory-reference instruction
    uses 12 bits to specify an address and one bit to specify the
    addressing mode I.
    Instruction Set Completeness

    The set of instructions are said to be complete if the computer


    includes a sufficient number of instructions in each of the
    following categories:
    1. Arithmetic, logical, and shift instructions
    2. Instructions for moving information to and from memory and
    processor registers
    3. Program control instructions together with instructions that
    check status conditions
    4. Input and output instructions

    Timing and Control

    The clock pulses are applied to all flip-flops and registers in the
    system, including the flip-flops and registers in the control unit.
    The clock pulses do not change the state of a register unless the
    register is enabled by a control signal. The control signals are
    generated in the control unit and provide control inputs for the
    multiplexers in the common bus, control inputs in processor
    registers, and
    microoperations for the accumulator.

    - Two major types of control organization: hardwired control


    and microprogrammed control.

    - In the hardwired organization, the control logic is implemented


    with gates, flip-flops, decoders, and other digital circuits. It has
    the advantage that it can be optimized to produce a fast mode of
    operation. Any required control changes or modifications can be
    done by changing in the wiring among the various components.

    - In the microprogrammed control, the control information is


    stored in a control memory, the control memory is initiate the
    required sequence of microoperations. Any required control
    changes or modifications can be done by updating the
    microprogram in control memory.
    - The 4-bit sequence counter SC can count in binary from 0 to
    15, the output of counter are decoded in to 16 timing signals.
    The sequence counter SC can be incremented or cleared
    synchronously. Most of the time, the counter is incremented to
    provide the sequence of timing signals out of the 4 x 16 decoder.

    Ex.
    Instruction Cycle:

    • The steps that the control unit carries out in executing


    aprogram are:
    (1) Fetch the instruction to be executed from memory.
    (2) Decode the instruction (opcode).
    (3) Read effective address (operands) from main memory, if
    any.
    (4) Execute the instruction and store results, if any.

    Fetch and Decode:

    Initially, the program counter PC is loaded with the address of


    the first instruction in the program. The sequence counter SC is
    cleared to 0, providing a decoded timing signal T0 . After each
    clock pulse, SC is incremented by one, so that the timing signals
    go through a sequence T0 , T1 T2 , and so on.
    T0 : AR←PC
    T1 : IR←M[AR], PC←PC + 1
    T2 : D0 /..., D7 ←Decode IR(12-14), AR←IR(0-ll), I←IR(15)
    Since only AR is connected to the address inputs of memory, it
    is necessary to transfer the address from PC to AR during the
    clock transition associated with timing signal T0 .

    - To provide the data path for the transfer of PC to AR we must


    apply timing signal T0 to achieve the following connection:

    1. Place the content of PC onto the bus by making the bus


    selection inputs S2 S1 S0 equal to 010.

    2. Transfer the content of the bus to AR by enabling the LD


    input of AR.
    The next clock transition initiates the transfer from PC to AR
    since T0 = 1.
    T1 : IR←M[AR], PC←PC +1

    - The microoperation for the indirect address condition can be


    symbolized by the register transfer statement AR←M[AR].

    - The three instruction types are subdivided into four separate


    paths. The selected operation is activated with the clock
    transition associated with timing signal T3 . This can be
    symbolized as follows:
    D7 'IT3 : AR←M[AR]
    D7 'I'T3 : Nothing
    D7 I'T3 : Execute a register-reference instruction
    D7 IT3 : Execute an input-output instruction

    Register-Reference Instructions

    Register-reference instructions are recognized by the control


    when D7 = 1 and I = 0. These instructions use bits 0 through 11
    of the instruction code to specify one of 12 instructions. These
    12 bits are available in IR(0-ll). They were also transferred to
    AR during time T2 .
    Memory -Reference Instructions

    The effective address of the instruction is in the address register


    AR and was placed there during timing signal T2 when I = 0, or
    during timing signal T3 when I=1.

    AND to AC
    This is an instruction that performs the AND logic operation on
    pairs of bits in AC and the memory word specified by the
    effective address.
    D0 T4 : DR←M[AR]
    D0 T5 : AC←AC +DR, SC←O

    ADD to AC
    This instruction adds the content of the memory word specified
    by the effective address to the value of AC. The sum is
    transferred into AC and the output carry Cout is transferred to
    the E (extended accumulator) flip-flop.
    D1 T4 : DR ←M[AR]
    D1 T5 : AC ← AC + DR, E ←Cout, SC ← 0

    LDA: Load to AC
    This instruction transfers the memory word specified by the
    effective address to AC. The microoperations needed to execute
    this instruction are:
    D2 T4 : DR ←M[AR]
    D2 T5 : AC ← DR, SC ← 0

    STA: Store AC
    This instruction stores the content of AC into the memory word
    specified by the effective address.
    D3 T4 : M[AR] ← AC, SC ←0

    BUN: Branch Unconditionally


    D4 T4 : PC ←AR, SC ←0

    BSA: Branch and Save Return Address


    D5 T4 : M[AR] ←PC, AR ← AR + 1
    D5 T5 : PC ←AR, SC ← 0
    ISZ: Increment and Skip if Zero
    D6 T4 : DR ←M[AR]
    D6 T5 : DR ← DR + 1
    D6 T6 : M[AR] ← DR, if (DR = 0) then (PC ← PC + 1), SC ←0

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