1.

Introduction

The modern trend is to have a portable, faster and accurate device with more
functionality. This set of requirements put constraints on the chip area, power consumption,
and involved delay. Digital design techniques are more reliable, consumes less chip area and
also consumes less power and hence the task of processing complex signal is preferably carried
out in digital domain. It is aimed to build larger electronics systems mainly with digital
components but it is not easy to get rid of the analog components as signals emanating from
the physical world are fundamentally analog in nature. This results in the evolution of mixed-
signal circuits. The Analog-to-Digital converter (ADC) is the key to mixed signal circuits as it
provides the interface between the physical world and digital processing. ADC is one of the
fundamental electronic components of the modern heavily digitized world. Its function is to
map a continuous signal in time, i.e. with an infinite number of values, to a digital signal,
consisting of a stream of binary codes, which can only take two abstract values, `zero' or `one',
and is easily processed in the digital domain by microcontrollers and processors. This operation
is depicted in Fig. 1.1

Fig 1.1. ADC as an interface between physical world and digital processors

An overwhelming variety of ADCs exist on the market today, with differing resolutions,
bandwidths, accuracies, architectures, packaging, power requirements, and temperature ranges,
as well as hosts of specifications, covering a broad range of performance needs. And indeed,
there exists a variety of applications in data-acquisition, communications, instrumentation, and
interfacing for signal processing, all having a host of differing requirements. Considering
architectures, for some applications just about any architecture could work well; for others,
there is a “best choice.” In some cases, the choice is simple because there is a clear-cut
advantage to using one architecture over another.
The most popular ADC architectures available today are successive approximations
(sometimes called SAR because a successive approximations (shift) register is the key defining

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element), flash (all decisions made simultaneously), pipelined (with multiple flash stages), and
sigma-delta (), a charge-balancing type. All A/D converters require one or more steps
involving comparison of an input signal with a reference. Figure 1.2 shows qualitatively how
flash, pipelined, and SAR architectures differ with respect to the number of comparators used
vs. the number of comparison cycles needed to perform a conversion.

Fig 1.2. Trade-off between decision cycles and comparators

FLASH Converter

Conceptually, the flash architecture (illustrated in Figure 1.3) is quite straightforward: a set
of 2n–1 comparator is used to directly measure an analog signal to a resolution of n bits. For a
4-bit flash ADC, the analog input is fed into 15 comparators, each of which is biased to compare
the input to a discrete transition value. These values are spaced one least-significant bit (LSB
= FS/2n) apart.

Fig 1.3. Basic FLASH Converter architecture

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The comparator outputs simultaneously present 2n–1 discrete digital output state. If for
example the input is just above 1/4 of full scale, all comparators biased to less than 1/4 full
scale will output a digital “1,” and the others will output a digital “0.” Together, these outputs
can be read much like a liquid thermometer. The final step is to level-decode the result into
binary form.
Design Considerations and Implications: The flash architecture has the advantage of being
very fast, because the conversion occurs in a single ADC cycle. The disadvantage of this
approach is that it requires a large number of comparators that are carefully matched and
properly biased to ensure that the results are linear. Since the number of comparators needed
for an n-bit resolution ADC is equal to 2𝑛 − 1, limits of physical integration and input loading
keep the maximum resolution fairly low. For example, a 4-bit ADC requires 15 comparators,
an 8-bit ADC requires 255 comparators, and a 16-bit ADC would require 65,535 comparators.

PIPELINED Converter

The pipelined (or pipelined-flash) architecture effectively overcomes the limitations of the
flash architecture. A pipelined converter divides the conversion task into several consecutive
stages. Each of these stages, as shown in Figure 1.4, consists of a sample-and hold circuit, an
m-bit ADC (e.g., a flash converter), and an m-bit D/A converter (DAC). First the sample and
hold circuit of the first stage acquires the signal. The m-bit flash converter then converts the
sampled signal to digital data. The conversion result forms the most significant bits of the
digital output. This same digital output is fed into an m-bit digital-to-analog converter, and its
output is subtracted from the original sampled signal. The residual analog signal is then
amplified and sent on to the next stage in the pipeline to be sampled and converted as it was in
the first stage. This process is repeated through as many stages as are necessary to achieve the
desired resolution. In principle, a pipelined converter with p pipeline stages, each with an m-
bit flash converter, can produce a high-speed ADC with a resolution of n = p X m bits using p
X (2m–1) comparators. For example, a 2-stage pipelined converter with 8-bit resolution
requires 30 comparators, and a 4- stage 16-bit ADC requires only 60 comparators. In practice,

Fig 1.4. A single pipelined Converter architecture

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however, a few additional bits are generated to provide for error correction.
Design Considerations and Implications: Pipelined converters achieve higher resolutions than
flash converters containing a similar number of comparators. This comes at the price of
increasing the total conversion time from one cycle to p cycles. But since each stage samples
and holds its input, p conversions can be underway simultaneously. The total throughput can
therefore be equal to the throughput of a flash converter, i.e., one conversion per cycle. The
difference is that for the pipelined converter, we have now introduced latency equal to p cycles.
Another limitation of the pipelined architecture is that the conversion process generally
requires a clock with a fixed period. Converting rapidly varying non-periodic signals on a
traditional pipelined converter can be difficult because the pipeline typically runs at a periodic
rate.

SUCCESSIVE APPROXIMATION REGISTER (SAR) Converter

The successive-approximations architecture can be thought of as being orthogonal to the

flash architecture. While a flash converter uses many comparators to convert in a single cycle;
a SAR converter, shown in Figure 1.5, conceptually uses a single comparator over many cycles
to make its conversion. The SAR converter works like an old-fashioned balance scale. On one
side of the scale, we place the sampled unknown quantity. On the other side, we place a weight
(generated by the SAR and DAC) that has the value of 1/2 of full-scale and compare the two
values. This first weight represents the most significant bit (MSB). If the unknown quantity is
larger, the 1/2-scale weight is retained; if the unknown quantity is smaller, it is removed. This
series of steps is repeated n times, using successively smaller weights in binary progression
(e.g., 1/4, 1/8, 1/16, 1/32, . . . 1/2n of full scale) until the desired resolution, n, is attained. Each
weight represents a binary bit, with the largest representing the most significant bit, and the
smallest representing the least significant bit.

Fig 1.5 SAR Converter architecture

Design Considerations and Implications: A SAR converter can use a single comparator to
realize a high-resolution ADC. But it requires n comparison cycles to achieve n-bit resolution,
compared to p cycles for a pipelined converter and 1 cycle for a flash converter. Since a
successive-approximations converter uses a fairly simple architecture employing a single SAR,

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comparator, and DAC, and the conversion is not complete until all weights have been tested,
only one conversion is processed during n comparison cycles. For this reason, SAR converters
are more often used at lower speeds in higher-resolution applications. SAR converters are also
well suited for applications that have non-periodic inputs, since conversions can be started at
will. This feature makes the SAR architecture ideal for converting a series of time-independent
signals. A single SAR converter and an input multiplexer are typically less expensive to
implement than several sigma-delta converters. With dither noise present, SAR and pipelined
converters can use averaging to increase the effective resolution of the converter: for every
doubling of sample rate, the effective resolution improves by 3 dB or 1/2 bit.
One consideration when using a SAR or pipelined converter is aliasing. The process of
sampling a signal leads to aliasing—the frequency-domain reflection of signals about the
sampling frequency. In most applications, aliasing is an unwanted effect that requires a low-
pass anti-alias filter ahead of the ADC to remove high-frequency noise components, which
would be aliased into the passband. However, under sampling can put aliasing to good use,
most often in communications applications, to convert a high frequency signal to a lower
frequency. Under sampling is effective as long as the total bandwidth of a signal meets the
Nyquist criterion (less than one-half the sampling rate), and the converter has sufficient
acquisition and signal sampling performance at the higher frequencies where the signal resides.
While fast SAR converters are capable of under sampling, the faster pipelined converters tend
to be more effective at it.

SIGMA-DELTA Converter

The sigma-delta architecture takes a fundamentally different approach than those outlined
above. In its most basic form, a sigma-delta converter consists of an integrator, a comparator,
and a single bit DAC, as shown in Figure 1.6. The output of the DAC is subtracted from the
input signal. The resulting signal is then integrated, and the integrator output voltage is
converted to a single-bit digital output (1 or 0) by the comparator. The resulting bit becomes
the input to the DAC, and the DAC’s output is subtracted from the ADC input signal, etc. This
closed-loop process is carried out at a very high “oversampled” rate. The digital data coming
from the ADC is a stream of “ones” and “zeros,” and the value of the signal is proportional to
the density of digital “ones” coming from the comparator. This bit stream data is then digitally
filtered and decimated to result in a binary-format output.

Fig 1.6 SIGMA-DELTA Converter architecture

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Design Considerations and Implications: One of the most advantageous features of the sigma-
delta architecture is the capability of noise shaping, a phenomenon by which much of the low-
frequency noise is effectively pushed up to higher frequencies and out of the band of interest.
As a result, the sigma-delta architecture has been very popular for designing low-bandwidth
high-resolution ADCs for precision measurement. Also, since the input is sampled at a high
“oversampled” rate, unlike the other architectures described in this paper, the requirement for
external anti-alias filtering is greatly relaxed. A limitation of this architecture is its latency,
which is substantially greater than that of the other types. Because of oversampling and latency,
sigma-delta converters are not often used in multiplexed signal applications. To avoid
interference between multiplexed signals, a delay at least equal to the decimator’s total delay
must occur between conversions. These characteristics can be improved in sophisticated sigma-
delta ADC designs by using multiple integrator stages and/or multi-bit DACs.

In recent years Successive Approximation Register (SAR) analog to digital converter

is gaining more importance because of its power efficiency and improvement in conversion
speed with scaling down of technology. SAR ADC’s are suitable for the applications that
require medium resolution, medium to high sampling rate with low power consumption. In this
work, the successive approximation register analog-to-digital converter (SAR ADC) is of
concern. Its architecture and detailed operation will be explained in following chapter.

1.1 Motivation
In this thesis we aim to design a switched capacitor DAC for implementation inside the
SAR ADC. The performance requirement of SAR ADC can be represented in terms of static and
dynamic metrics. Static metrics include differential-non-linearity (DNL) and integral-non-linearity
(INL) while dynamic metric includes signal-to-noise-plus-distortion ratio (SNDR) and effective-
number of-bits (ENOB). All of these nonlinear parameters depend mainly on the structure of the
capacitive array of the feedback digital-to-analog converter (DAC). The capacitive array acts as both
sampling capacitance and feedback DAC and its linearity affects the overall performance of ADC. Thus,
design of DAC demands special attention and also requires proper design methodology. The following
design steps have been followed for designing DAC:

 Literature review
 Choice of the DAC capacitor topology
 System level study
 Estimation of non-linearity of DAC
 Investigation of calibration technique to reduce the non-linearity of DAC
 Circuit level implementation of the functional block of the DAC

1.2 Goal of the thesis

The goal of this thesis is to investigate the performance of the SAR ADC with a
switched capacitor implementation of the feedback DAC. Performance improvement will be
favoured by the capacitor array that is selected, which will improve speed and lower energy
waste. It has been tried to address the various issues which arise while designing the optimum
DAC and also the possible ways to overcome the same.

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1.3 Organization of the thesis

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 2. Successive Approximation Register (SAR) ADC
Speed, resolution, and power consumption are three critical parameters for an ADC.
Analysing and processing digital signals are dependent on specific demands. However, the
ADC operates continuously. Therefore, the power consumption is a very important factor in
the ADC circuit design. It is known that the successive approximation register ADC (SAR
ADC) architecture is well suitable for large-scale wireless sensor networks, physiological and
data acquisition applications, especially when multiple channels require input multiplexing due
to its moderate speed, moderate resolution and very low power consumption characteristics.

Fig 2.1 ADC architecture in comparison

2.1 Architecture of Differential SAR ADC

In the SAR ADC, the differential architecture (in which two identical halves convert
the difference between the two inputs into a differential output) is often employed to have a
good common-mode noise rejection and achieve high accuracy. However, it requires more chip
area and power. The fundamental blocks are the capacitive DACs, comparator, and SAR logic
circuits. A fully binary-weighted capacitor array is commonly used in SAR ADCs since it can
achieve better linearity than a CC-2C2Ccapacitor array or a split binary-weighted capacitor
array with an attenuation capacitor. In the capacitive DACs with inherent Sample and Hold,
the sampling operation is performed by the DAC itself. The comparator compares the analog
output of the differential capacitor array and generates the digital code, which will be used in
SAR logic. Then the differential DACs convert the output of the SAR logic to analog value by
switching the capacitors to different voltage references. The block diagram of differential
architecture of SAR ADC is given in Figure 2.2.

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 Fig 2.2 Architecture of Differential SAR ADC

2.2 SAR ADC Timing

The fundamental timing diagram for a typical SAR ADC is shown in Figure 4.2. The
end of conversion is generally indicated by an end-of-convert (EOC), data-ready (DRDY), or
a busy signal (actually, not-BUSY indicates end of conversion). The polarities and name of
this signal may be different for different SAR ADCs, but the fundamental concept is the same.
At the beginning of the conversion interval, the signal goes high (or low) and remains in that
state until the conversion is completed, at which time it goes low (or high). The trailing edge
is generally an indication of valid output data, but the data sheet should be carefully studied—
in some ADCs additional delay is required before the output data is valid. An N-bit conversion
takes N steps. It would seem on superficial examination that a 16-bit converter would have
twice the conversion time of an 8-bit one, but this is not the case. In an 8-bit converter, the
DAC must settle to 8-bit accuracy before the bit decision is made, whereas in a 16-bit converter,
it must settle to 16-bit accuracy, which takes a lot longer. In practice, 8-bit successive
approximation ADCs can convert in a few hundred nanoseconds, while 16-bit ones will
generally take several microseconds.
While there are some variations, the fundamental timing of most SAR ADCs is similar and
relatively straightforward. The conversion process is generally initiated by asserting a
CONVERT START signal. The CONVST signal is a negative-going pulse whose positive-
going edge actually initiates the conversion. The internal sample-and-hold (SHA) amplifier is
placed in the hold mode on this edge, and the various bits are determined using the SAR
algorithm. The negative-going edge of the CONVST pulse causes the EOC or BUSY line to
go high. When the conversion is complete, the BUSY line goes low, indicating the completion
of the conversion process. In most cases the trailing edge of the BUSY line can be used as an
indication that the output data is valid and can be used to strobe the output data into an external
register. An important characteristic of a SAR ADC is that at the end of the conversion time,
the data corresponding to the sampling clock edge is available with no "pipeline" delay. This
makes the SAR ADC especially easy to use in "single-shot" and multiplexed applications.

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 Fig 2.3 SAR ADC timing

2.3 Algorithm of SAR ADC

The input signal is first sampled, and the corresponding voltage stored on a capacitor.
It is then compared to a reference voltage which is equal to ½ the full-scale voltage. If it is
greater than the reference voltage, the MSB is registered as a "1," and an amount of charge
equal to ½ scale is subtracted from the storage capacitor. If the voltage on the capacitor is less
than ½ scale, then no charge is removed, and the bit is registered as a "0". After the MSB
decision is completed, the cycle continues for the second bit, but with the reference voltage
now equal to ¼ scale. The process continues until all bit decisions are completed.

Fig 2.4 Binary search algorithm of a 4-bit ADC

The balance scale analogy given in Figure2.5 is used to demonstrate the algorithm. In
this analogy problem, the object is to determine the least number of weights which would serve

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to weigh an integral number of pounds from 1 lb to 63 lb using a balance scale. One solution
put forth by the mathematician Tartaglia in 1556, was to use the series of weights 1 lb, 2 lb, 4
lb, 8 lb, 16 lb, and 32 lb. Assume unknown weight to be 45lb.

Fig 2.5 The balance scale analogy

2.4 Advantages of SAR ADC

 Very simple principle. SAR ADCs implement the binary search algorithm.
 Low power consumption. A SAR ADC does not contain an operational amplifier.
Operational amplifiers are generally power-hungry. The SAR ADC contains solely a
comparator; comparators consume much less power than operational amplifiers.
Pipelined and Sigma- Delta ADCs contain power-hungry operational amplifiers. From
SAR, Pipelined and Sigma- Delta ADCs, the SAR ADC is most likely low-power.
 No pipeline delay (latency). In a pipelined ADC, the pipeline delay is a multiple of the
sampling clock period. For low sampling frequencies, there will be a considerable
latency. The SAR ADC can use an internal clock that is independent of (and – if desired
– much faster than) the sampling clock; output codes can thus be delivered with a delay
negligible with respect to sampling clock period. Closing the loop requires that ADC
and DAC has no latency, a further argument in favour of the SAR ADC.

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2.5 Performance metrics of SAR ADC
Ideally, an ADC encodes a continuous-time analog input voltage, Vin, into a series of
discrete N-bit digital words that satisfy the relation,
𝑁−1
𝑏𝑘
𝑉𝑖𝑛 = 𝑉𝐹𝑆 ∑ +∈ … … … … … … … (2.1)
2𝑘+1
𝑘=0
Where VFS is the full-scale voltage, bk are the individual output bits and  is the quantization
error. This relation can also be written in terms of the least significant bit (LSB) or quantum
voltage level,
𝑉𝐹𝑆
𝑉𝐿𝑆𝐵 = 𝑁 = 1 𝐿𝑆𝐵 … … … … … … … (2.2)
2 −1
As
𝑁−1

𝑉𝑖𝑛 = 𝑉𝐿𝑆𝐵 ∑ 𝑏𝑘 2𝑘 +∈ … … … … … … … (2.3)

𝑘=0

A plot of this ideal characteristic for a 3-bit ADC is shown in Fig 2.4

Fig 2.6 Ideal behaviour of 3-bit ADC

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 Each unique digital code corresponds to a small range of analog input voltages. This
range is 1 LSB wide (the code width") and is centered around the code center. All input voltages
resolve to the digital code of the nearest code center. The difference between the analog input
voltage and the corresponding voltage of the nearest code is the quantization error. Since the
ADC has a finite number of output bits, even an ideal ADC produces some quantization error
with every sample. The number of output bits from an analog-to-digital converter do not fully
specify its behaviour. Real A/D converters can differ from ideal behaviour in many ways. A
variety of metrics exist in order to evaluate the performance of an ADC. These metrics can be
divided into two main categories: metrics for (a) static and (b) dynamic performance. We start
with the static errors and move on with the dynamic ones.

2.5.1 DC (or Static) metric:

The static metric for an ADC provides an understanding of the device behaviour for dc
or a very-low frequency input signal. Important DC specifications are explored in the following
sections.

Offset Error: Offset Error is also referred to as zero scale error. It is defined as the
difference between Ideal offset point (0.5 LSB) to actual offset and it can be a positive or
negative value. Offset Error value is usually specified using one of the following units: Volts,
Least Significant Bits (LSB), %Full Scale Value (%FSV), and parts per million (ppm).

Fig 2.7 (a) Positive Offset error (b) Negative Offset error

Gain error: It is also referred to as Full Scale Error. It represents the difference between
ideal voltage which provides Full scale output code versus the actual voltage for which the

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converter provides full scale output code. This measurement is done after calibrating the ADC
readings for the offset error. The error represents the difference in the ideal and actual slopes;
therefore, percentage error is same across all the ADC step. Gain Error value is usually
specified using one of the following units: %FSV or LSB or Volts. Gain error can also be
positive and negative. Fig 2.8 illustrates a positive gain error.

Fig 2.8 Gain error

Differential Nonlinearity (DNL): It is a measurement of how the width of a code

compares to the ideal width. The Fig 2.9 illustrates how some codes are longer than the ideal
width and others are shorter. The equation shown illustrates how DNL is calculated. The

Fig 2.9 Non ideal stair case output

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equation is really an error calculation using the measured code width, W[k], and the ideal code
width Q. The measured code width is calculated by subtracting the two adjacent code
transitions, T[k] and T[k-1]. If the measured code width is equal to the ideal code width, the
DNL is zero. If the measured code is longer than the ideal code, the DNL is positive. And if
the measured code is shorter, the DNL is negative.

𝑊(𝐾) − 𝑄
𝐷𝑁𝐿(𝑘) = … … … … … … … (2.4)
𝑄

𝑊(𝑘) = 𝑇(𝐾 + 1) − 𝑇(𝐾) … … … … … … … (2.5)

Where, W[k] is the measured code width, T[K] is the voltage level where code transition takes
place and Q is the ideal code width.
In some cases, non-linearity is large enough to cause a code transition to be completely
skipped. This is called a missing code. The example here shows a case where the digital output
of the ADC completely skips the code 1001. In this example, there is no analog input signal
that will ever cause the digital output to read 1001. Missing codes can be a serious issue for
many electronic systems, so most modern ADCs are designed and tested to ensure that they
will not have this problem. In fact, data sheets often provide a no missing code, or NMC,
specification to highlight that the converter will not have missing codes. Fig 2.10 shows an
example of the missing codes specification.

Fig 2.10 Missing code example

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 Fig 2.11 shows an example of how the differential nonlinearity specification is shown
in data sheets. For each code in the transfer function, we compare the measured code width to
the ideal code width. Thus, one way that this specification can be displayed is a graph of DNL
versus ADC output code. In our simplified example, one can see the DNL versus ADC code
for a 3-bit converter. The calculation for code 101 is shown. This bit is 0.031V wide which is
short compared to the ideal width of 0.125V so the DNL is negative. Fig 2.11(c) shows a more
practical example of an 18-bit converter. In this case thousands of DNL measurements are
being displayed and you can see that the DNL is typically less than 0.5 LSB.

Fig 2.11 Ways of representing DNL in datasheet

Integration Nonlinearity (INL): It is a measurement of how close the measured ADC transfer
function compares to a straight line. To eliminate errors from gain and offset error, the
measured transfer function is compared to an ideal straight line that is fit to the end points of
the ADC transfer function. The deviation between the ideal line and the measured function is
the INL error. In the simplified example shown in Fig 2.12, the green dashed line is the end
point fit of the transfer function. The reason it is called an end point fit is that the green line

Fig 2.12 Calculation of INL

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starts at the first code, 0000, and ends on the last code, 1111. For a perfectly linear ADC, the
straight-line fit would be directly down the middle of the ADC transfer function. In this case,
however, you can see that the measured function, shown in blue, deviates away from the linear
fit, so it is said to have a positive INL error. As with DNL error, the integral nonlinearity can
be displayed versus the ADC output code. Integral nonlinearity may be given units of LSB
codes or it may be given as a percentage of the full-scale range. Fig 2.13 shows a representation
of INL as in the datasheet of converter.

Fig 2.13 Representation of INL in datasheet

2.5.2 Dynamic metric

Many applications require digitizing a signal which varies quickly over time. An ADC's
performance has different important specifications for quickly varying signals. These different
parameters which define the ADC performance with Dynamic input are mostly specified using
single input frequency. The ADC output array is processed using FFT and analysed for
dynamic specifications. Each specification is usually associated with input signal specifications
in terms of frequency and amplitude. In subsequent section, we discuss the meaning and
significance of the various dynamic specifications for ADC.

Signal-to-Noise Ratio (SNR): The Signal-to-Noise Ratio specification provides information

regarding the noise energy excluding the fundamental and harmonic energy present in the
frequency spectrum for a particular input frequency. SNR is defined as the ratio of the output
signal voltage level to the output noise level, considering quantization noise. It is usually
represented in decibels (dB) and calculated using the following formula:
𝑃𝑠𝑖𝑔𝑛𝑎𝑙
𝑆𝑁𝑅 = 10 log ( ) … … … … … … … (2.6)
𝑃𝑛𝑜𝑖𝑠𝑒

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 2
𝑉𝐿𝑆𝐵
Assuming a quantization noise power equal to , the maximum SNR represented by a
12
digital word of N bits in a bandwidth of Fs /2 is,

𝑆𝑁𝑅 = 1.76 + 6.02𝑁 𝑑𝐵 … … … … … … … (2.7)

Total Harmonic Distortion (THD): Whenever an input signal of a particular frequency passes
through a non-linear device, additional content is added at the harmonics of the original
frequency. These harmonic frequencies usually distort the output and hence degrades the
performance of the system. This effect can be measured using the total harmonic distortion
(THD). THD is defined as the ratio of the sum of powers of the harmonic frequency
components to the power of the fundamental/original frequency component. In terms of RMS
voltage, the THD is given by,
√𝑉12 + 𝑉22 + ⋯ 𝑉𝑛2
𝑇𝐻𝐷 = … … … … … … … (2.7)
𝑉12

Signal-to-noise-and-distortion ratio (SINAD): The Signal-to-Noise and Distortion (SINAD)

specification provides information regarding the noise and harmonic energy present in the
frequency spectrum. It can be defined as the ratio of the signal power to all the unwanted
components i.e. quantization errors, thermal noise, distortion, etc.

𝑃𝑜𝑤𝑒𝑟 𝑜𝑓 𝑓𝑖𝑟𝑠𝑡 ℎ𝑎𝑟𝑚𝑜𝑛𝑖𝑐

𝑆𝐼𝑁𝐴𝐷 = 10 log ( ) … … … … … … … (2.8)
𝑃𝑜𝑤𝑒𝑟 𝑜𝑓 𝑎𝑙𝑙 𝑢𝑛𝑤𝑎𝑛𝑡𝑒𝑑 𝑐𝑜𝑚𝑝𝑜𝑛𝑒𝑛𝑡𝑠

Effective number of bits (ENOB): Effective number of bits (ENOB) is the number of bits
with which the ADC behaves like a perfect ADC and is used in order to characterize the
converter in a simple manner. It is calculated by reversing equation (2.7) as,

𝑆𝐼𝑁𝐴𝐷 − 1.76
𝐸𝑁𝑂𝐵 = … … … … … … … (2.8)
6.02
The ENOB allows an easy comparison of the real performance of a converter.

Spurious free dynamic range (SFDR): The Spurious Free Dynamic Range (SFDR)
specification provides information regarding the difference between maximum amplitude tone
in frequency spectrum and the fundamental input tone. In applications where high linearity is
required, the SFDR is the most important metric.

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 3. Digital to Analog Converter (DAC) for SAR ADC
In moderate to high speed, high resolution SAR ADCs, the exponentially growing analog
power consumption will quickly start to dominate. One of the main power-hungry components
is the DAC. Switched Capacitor (SC) topologies are usually preferred because they only
consume power during charging and discharging and hence consumes less power. In this
chapter, we will discuss in brief about the SC-DAC. Firstly, the various topologies of SC-DAC
will be discussed followed by the discussion of various switching procedures, which play major
role in the power reduction of DAC. At the end of the chapter, conclusion will be made
regarding the suitable topology and switching procedure of DAC for the implementation in
SAR ADC.

3.1 Switched Capacitor DACs

In switch capacitor DAC, switches of DAC are controlled to generate the voltage levels
that are needed for the comparisons with the sampled input voltage. Several topologies for the
SC-DAC exist. In this section, various topologies of switch capacitor DACs are discussed along
with their advantage and disadvantage.

3.1.1 Conventional Binary Weighted Capacitor Array: Binary weighted

capacitor array is the most common structure used as DAC. A traditional N-bit binary weighted
capacitor array consists of N capacitors. The capacitors in the network are binary weighted and
range from Cu (unit capacitance) for the LSB to 2N-1 Cu for the MSB. An additional Cu (dummy)
in parallel to the LSB capacitor gives a total capacitance of 2n Cu. Architecture of Binary
weighted capacitor array is depicted in Fig 3.1.

Fig 3.1. Conventional Binary Weighted Capacitor Array

The generation of the voltage levels is decided by the input code of the DAC, which
controls the switches that connect the bottom plate of the capacitors to Vref or ground,
respectively. The voltage division that is made each time represents the voltage level that is
used for the comparator decision. The output of DAC can be given as:
𝐶1 𝐶2 𝐶𝑁
𝑉𝐷𝐴𝐶 = 𝐷1 𝐶 + 𝐷2 𝐶 + ⋯ + 𝐷𝑁 𝐶 … … … … . . (3.1)
0 +𝐶1 +𝐶2 +⋯+𝐶𝑁 0 +𝐶1 +𝐶2 +⋯+𝐶𝑁 0 +𝐶1 +𝐶2 +⋯+𝐶𝑁

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Equation (3.2) can be simplified to,
𝑁
1
𝑉𝐷𝐴𝐶 = ∑ 𝐷𝑖 𝐶𝑖 … … . (3.3)
𝐶𝑇𝑜𝑡𝑎𝑙
𝑖=1
Where 𝐶𝑇𝑜𝑡𝑎𝑙 = 𝐶0 + 𝐶1 + 𝐶2 + ⋯ + 𝐶𝑁 , and Di represents the node voltages.

Binary weighted DAC topology is very simple to implement. However, the number of
unit capacitors required in the array increases exponentially with the increase in the number of
bits. For N bit resolution, it requires 2N unit capacitors. As a result, it consumes larger chip
area, huge power and also limits the frequency of operation (as larger capacitors require larger
settling time).

3.1.2 Binary Weighted with Attenuation Capacitor Array:

Binary Weighted with attenuation capacitor array is one of the solutions to reduce both
input capacitances and area. A single-ended BWA array is shown in Fig. 2.3. An attenuation
capacitor Catt divides the array into two binary weighted sub-arrays i.e. MSB and LSB DAC
array consisting of ‘m’ and ‘l’ number of capacitors respectively. However, we can split

Fig 3.2. Binary Weighted with Attenuation Capacitor Array

Fig 3.3. Binary Weighted with two Attenuation Capacitor

capacitive array into more than two halves (as shown in Fig 3.3) by using multiple attenuation
(or bridge) capacitance. This will even reduce the total capacitance by large amount but then
there will be a parasitic capacitance at each node and hence will add nonlinearity to the circuit.
Thus, architecture with more than one attenuation (or bridge) capacitor will add more
nonlinearity to the overall circuit.

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The value of attenuation capacitor should be such that the series combination of the attenuation
capacitor and the LSB array, assuming all lower terminal voltages of LSB side capacitor array
to zero, equals to the minimum capacitor of the MSB side i.e. Cu.

Fig 3.4. Equivalent circuit for calculation of equivalent capacitor in LSB

𝐶𝐿𝑆𝐵 𝐶𝑎𝑡𝑡
= 𝐶𝑒𝑞𝐿𝑆𝐵 … … . (3.4)
𝐶𝐿𝑆𝐵 + 𝐶𝑎𝑡𝑡
and
𝐶𝑒𝑞𝐿𝑆𝐵 = 𝐶𝑢 … … … … (3.5)

𝐶𝐿𝑆𝐵 𝐶𝑎𝑡𝑡 = 𝐶𝑒𝑞𝐿𝑆𝐵 𝐶𝐿𝑆𝐵 + 𝐶𝑒𝑞𝐿𝑆𝐵 𝐶𝑎𝑡𝑡

𝐶𝑒𝑞𝐿𝑆𝐵 𝐶𝐿𝑆𝐵
𝐶𝑎𝑡𝑡 = … … . . (3.6)
𝐶𝐿𝑆𝐵 − 𝐶𝑒𝑞𝐿𝑆𝐵

Calculation of total capacitance of N-bit Binary weighted with attenuation capacitor array
consisting of single attenuation capacitor and which divide array into two equal halves i.e.
m=l= N/2 can be done as follows:

Fig 3.5. Equivalent circuit for calculation of equivalent capacitor in MSB

Thus, total capacitance can be given as,

𝐶𝑇𝑜𝑡𝑎𝑙 = 𝐶𝑀𝑆𝐵 + 𝐶𝑢 … … . . (3.7)

Now we will calculate the output voltage of the Binary weighted with attenuation capacitor
array. At first equivalent Thevenin voltage (Vth) and equivalent capacitance looking into the
LSB side (as shown in Fig 3.6) is calculated. While calculating Ceq, all the lower terminal

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voltages of capacitor is connected to the ground. Finally, the output voltage is calculated using
circuit as depicted in Fig 3.7.

Fig 3.6. Circuit for calculation of Vth and Ceq

𝐶1 𝐶2 𝐶𝑁/2
𝑉𝑡ℎ = 𝐷1 𝐶 + 𝐷2 𝐶 +. . +𝐷𝑁/2 𝐶 ,
1 +𝐶2 +⋯+𝐶𝑁/2 1 +𝐶2 +⋯+𝐶𝑁/2 1 +𝐶2 +⋯+𝐶𝑁/2

𝑁/2
∑𝑖=1 𝐷𝑖 𝐶𝑖
𝑉𝑡ℎ = 𝐶 and 𝐶𝑒𝑞 = (𝐶1 + 𝐶2 + ⋯ + 𝐶𝑁 ) ||𝐶𝑎𝑡𝑡 . If 𝐶𝐿𝑆𝐵 = 𝐶1 + 𝐶2 + ⋯ + 𝐶𝑁/2 ,
1 +𝐶2 +⋯+𝐶𝑁/2 2

then Vth and Ceq can be given as,

∑𝑁/2 𝐷𝑖 𝐶𝑖
𝑉𝑡ℎ = 𝑖=1 … … … … … (3.8)
𝐶𝐿𝑆𝐵
And
𝐶𝑒𝑞 = 𝐶𝐿𝑆𝐵 ||𝐶𝑎𝑡𝑡 … … … … … (3.9)

Now the total array can be represented as,

Fig 3.7. Circuit for calculation of output voltage of DAC

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 𝐶𝑁 𝐶𝑁
𝐶𝑒𝑞 +1 +1
𝑉𝐷𝐴𝐶 = 𝑉𝑡ℎ 𝐶 + 𝐷𝑁+1 𝐶 2
+ ⋯ + 𝐷𝑁+1 𝐶 2
𝑒𝑞 +𝐶𝑁 +..+𝐶𝑁 2 𝑒𝑞 +𝐶𝑁 +..+𝐶𝑁 2 𝑒𝑞 +𝐶𝑁 +..+𝐶𝑁
+1 +1 +1
2 2 2

𝑉𝑡ℎ 𝐶𝑒𝑞 +∑𝑁

𝑖=1 𝐷𝑁 𝐶𝑁 +𝑖 +𝑖
𝑉𝐷𝐴𝐶 = 2 2
, if 𝐶𝑇𝑜𝑡𝑎𝑙 = 𝐶𝑒𝑞 + 𝐶𝑁+1 +. . +𝐶𝑁 , then
𝐶𝑒𝑞 +𝐶𝑁 +..+𝐶𝑁 2
+1
2

𝑉𝑡ℎ 𝐶𝑒𝑞 + ∑𝑁
𝑖=1 𝐷𝑁 +𝑖 𝐶𝑁 +𝑖
2 2
𝑉𝐷𝐴𝐶 = … … … . . (3.10)
𝐶𝑇𝑜𝑡𝑎𝑙

Binary weighted with attenuation capacitor array architecture requires less capacitor and hence
consumes less power and also requires less area. As we have seen, it requires an attenuation
capacitor two split array into two halves. Thus, two nodes were created and hence there will be
unwanted capacitor will be generated after fabrication. These parasitic capacitances will add
nonlinearity to the DAC. Also, this architecture is very sensitive to mismatch in capacitors.

3.2 Switching Procedures

In capacitive DAC, a majority of the total energy dissipation is due to repeated charging
and discharging of the large capacitor array. The energy dissipated in each switching step can
be calculated by studying the changes in voltage across each capacitor. Switching the bottom
plate of a capacitor from ground to Vref causes the voltage Vx on the top plate to change. In the
general case the voltage at the bottom plate of a capacitor Ci is changed by ∆Vb causing a
change ∆Vx at the top plate. The energy drawn from the reference voltage source Vref
connected to Ci, which is determined by the change in charge stored on the capacitor, is
described below.
𝑡 𝑡 𝑑𝑄(𝑡)
𝐸 = ∫𝑡 2 𝑉𝑟𝑒𝑓 𝐼𝑟𝑒𝑓 (𝑡)𝑑𝑡 = 𝑉𝑟𝑒𝑓 ∫𝑡 2 − 𝑑𝑡 = −𝑉𝑟𝑒𝑓 (𝑄(𝑡2 ) − 𝑄(𝑡1 ))
1 1 𝑑𝑡

E= −𝐶𝑖 𝑉𝑟𝑒𝑓 ((𝑉𝑥 (𝑡2 ) − 𝑉𝑏 (𝑡2 )) − (𝑉𝑥 (𝑡1 ) − 𝑉𝑏 (𝑡1 )))

𝐸 = 𝐶𝑖 𝑉𝑟𝑒𝑓 (∆𝑉𝑏 − ∆𝑉𝑥 )……………… (3.11)

Several new techniques using alternative switching algorithms have been proposed by the
researchers which dramatically decrease this power consumption. In this section different
switching procedures are described.

3.2.1 Conventional switching procedure:

In conventional switching procedure, the diff erential input voltage is sampled on the
bottom plates of the capacitors. During sampling all capacitors on the positive side of the DAC
1
are connected between the common-mode voltage 𝑉𝑐𝑚 = 2 𝑉𝑟𝑒𝑓 and Vinp. In the next clock
cycle the bottom plate of the MSB capacitor is switched to Vref and those of the remaining
capacitors to ground while the opposite procedure is done for the negative side. Figure 3.8
shows the conventional switching procedure for a 3-bit capacitive DAC and Fig 3.9 shows the
variation of DAC output voltages based on the change in capacitor bit values.

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 Fig 3.8. Conventional switching procedure

Fig 3.9. Waveform of conventional switching procedure

3.2.2 Monotonic switching procedure:

The Monotonic switching procedure takes advantage of the diff erential architecture by
making each comparison before the capacitive network is switched. In this way the unnecessary
steps used in the trial-and-error approach of a conventional ADC are eliminated. The input
voltage is sampled on the top plate which means that no switching energy is required before
the first comparison. This procedure is illustrated in figure 3.10 and its corresponding waveform
in Fig 3.11. Monotonic switching technique offer energy saving up to 81%.

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 Fig 3.10. Monotonic switching procedure

Fig 3.11. Waveform of monotonic switching procedure

In this chapter, we have seen that conventional Binary weighted DAC topology is
simple to implement but requires larger area. Thus, Binary weighted with attenuation capacitor
array topology will be used along with the monotonic switching procedure as t is found to be
more energy efficient. From now onwards we will discuss various design issues which we need
to overcome while designing this array in the following chapters.

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 4. Capacitor array design issues
In this work, Binary weighted with Attenuation Capacitor array structure having m=l=N/2
capacitors in both MSB and LSB array, as shown in figure 4.1 is used as DAC. Monotonic
capacitor switching procedure is adapted for switching the DAC unit as it has been found to be
more energy efficient. Because the MSB is already determined by the sign of the sampled
voltage due to monotonic switching, only 11 parallel capacitors are switched from ground to
the reference voltage and eventually back to ground during a conversion. However, an
additional parallel capacitor equal to the unit capacitor needs to be inserted to divide the
reference voltage by exactly two at each successive bit cycling step.

Fig 4.1. Used DAC structure

The output voltage of DAC can be expressed by simplifying equation 3.10 as,
𝑁⁄2
𝑉𝑟𝑒𝑓 𝐶𝑒𝑞𝐿𝑆𝐵 ⁄2 𝑁 2
∑𝑁
⁄
𝑉𝐷𝐴𝐶 = 𝐶𝑇𝑜𝑡
[∑ 𝐷𝑁+𝑖 𝐶𝑁+𝑖 + 𝐶𝐿𝑆𝐵 𝑖=1 𝐷𝑖 𝐶𝑖 ] ……………… (4.1), where 𝐶𝐿𝑆𝐵 = ∑𝑖=1 𝐶𝑖 ,
2 2
𝑖=1
𝑁⁄2

𝐶𝑀𝑆𝐵 = ∑ 𝐶𝑁+𝑖 , 𝐶𝑒𝑞𝐿𝑆𝐵 = 𝐶𝐿𝑆𝐵 ∥ 𝐶𝑎𝑡𝑡 , 𝐶𝑇𝑜𝑡 = 𝐶𝑒𝑞𝐿𝑆𝐵 + 𝐶𝑀𝑆𝐵 , 𝐷𝑖 is the binary bit value
2
𝑖=1
and using equation (3.6) we can write Catt as,
𝑁
−1
22
𝐶𝑎𝑡𝑡 = 𝑁 𝐶𝑢 ……………. (4.2), where Cu is the unit capacitor.
−1
2 2 −1

The fractional value of Catt is hard to be realized on the die itself. From (4.2), it is also
clear that as the number of bits increase Catt ≈ Cu. Thus, Catt is kept same as Cu which introduces
𝑁
2 ⁄2−1
a gain error,𝐺𝑎𝑖𝑛𝑒𝑟𝑟𝑜𝑟 |𝑚𝑎𝑥 = 𝑁 𝐶𝑢 . This gain error is predictable and it does not affect
2 ⁄2−1 −1
the linearity of the DAC. Fig. 4.2 shows the gain error contributed by each bit for a 14-bit
Binary weighted with attenuation capacitor DAC.

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 Fig 4.2. Gain error contributed by each bit for a 14-bit Binary
weighted with attenuation capacitor DAC

This chapter mainly deals with the various issues which must be taken into consideration
while designing the capacitor array to be used in SAR ADC. These issues are discussed briefly
in the following section.

4.1 Thermal Noise:

Let us consider a unit capacitor in the split binary-weighted capacitor array and its
neighbouring elements. The bottom plate of each parallel capacitor is connected to a separate
switch, while the top plates of unit capacitors in each sub binary-weighted capacitor arrays are
connected together. We look at one unitary cell consisting of one-unit capacitor and one switch.

Fig 4.3. Equivalent RC circuit

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When the switch is on, its transistor can be modelled as resistor. The resulting equivalent circuit
is a simple RC circuit (Figure 4.3). Thermal noise (Johnson noise) from the resistor affects the
voltage at the capacitor’s terminal; the capacitor itself does not introduce any noise. The output-
𝑘𝑇
referred RMS noise voltage in a RC circuit is given by, 𝑉𝑛𝑜𝑖𝑠𝑒,𝑅𝑀𝑆 = √𝐶 . Equivalently,
𝑢
𝑘𝑇
𝐶𝑢 = 𝑉 2 . As the peak-to-peak value of the thermal noise will be larger than the RMS
𝑛𝑜𝑖𝑠𝑒,𝑅𝑀𝑆

𝑟𝑒𝑓𝑘𝑇 𝑉
value, must be well below 0.5 VLSB i.e. √𝐶 ≤ 2𝑁+1 . Thermal noise imposes a fundamental
𝑢

limit on the size of unit capacitor. Higher the unit capacitor, lower the effect of thermal noise.

4.2 Capacitive Mismatch:

Mismatch in the capacitor array is introduced due to process variation during
fabrication. It affects the generated comparison level of the capacitive DAC. As for example
(shown in Fig 4.4), let us take the case where two equal capacitors are connected in series and
we are interested in finding the voltage across one of the capacitors. If both the capacitors are
ideal and equal, we will get half of the input voltage. But if we consider mismatch because of
process variation, then output will not be same as in the case of ideal one. Hence mismatch
among the capacitor in the DAC array effects the comparison level and as a result comparator
will give erroneous results.

Fig 4.4. Effect of capacitive mismatch on

the output voltage level

Mismatch of two similar capacitor can be modelled approximately as,

∆𝐶 𝑋
𝜎 ( 𝐶 ) = 𝐴 𝑐 …………………… (4.3)
𝐶,𝑡𝑜𝑡𝑎𝑙

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where Xc is the matching coefficient, depends upon capacitor type and technology and AC,total
depends on geometric dimensions of the capacitors expressed as,

𝐴𝐶,𝑡𝑜𝑡𝑎𝑙 = (√𝐴𝐶 + 𝐻𝐸). (√𝐴𝐶 + 𝑉𝐸) … … … … … … … . (4.4)

where 𝐴𝐶 = (𝑊. 𝐿) , HE & VE is the area overhead extended while doing the layout of

Fig 4.5. MIM capacitors layout with the extended area to mitigate DRC violation

capacitor to mitigate the DRC violation and W, L is the actual width and length of capacitor.

The standard deviation of single transistor is √2 times smaller than the standard deviation of
the difference of two capacitor and is given as
𝐶.𝑋𝑐
𝜎(𝐶) = ………………………. (4.5)
√2𝐴𝐶,𝑡𝑜𝑡𝑎𝑙

Standard deviation of capacitor Cn, consisting of ‘n’ parallel unit capacitance (Cu) can be given
by,

𝜎(𝐶𝑛 ) = √𝑛 𝜎(𝐶𝑢 )…………………………… (4.6)

It is evident from the equation 4.5, the effect of mismatch between capacitors can be minimized
using the capacitor having larger width and length i.e. high capacitance.

4.3 Sampling frequency:

Desired sampling frequency also imposes limit on the total size of capacitor array.
Larger capacitor array requires large settling time and thus limits the frequency of operation.
Given in Fig 4.6 is the equivalent model of DAC using which we can calculate the time-

29 | P a g e
 Fig 4.6. Figure showing the DAC model during sampling

constant () and hence estimate the bandwidth limitation of the DAC. For an accurate sampling
𝑇
𝑡𝑠𝑎𝑚𝑝𝑙𝑖𝑛𝑔 ≈ 𝑐𝑙𝑜𝑐𝑘⁄2 ≫ 𝜏 . As capacitor increases, 𝜏 increase which untimely limits the
bandwidth. Again,
𝑡
𝑉𝑐 (𝑡) = 𝑉𝑖𝑛 (1 − 𝑒 −𝜏 )
𝑉𝑖𝑛 − 𝑉𝑐 (𝑡)
𝑡 = − ln ( ).𝜏
𝑉𝑖𝑛
1 𝑉𝑟𝑒𝑓
(𝑉𝑖𝑛 − 𝑉𝐶 (𝑡))|𝑡 = 𝑡_𝑠𝑒𝑡𝑡𝑙𝑖𝑛𝑔 ≤ 𝐿𝑆𝐵 ≈ 𝑁+2
4 2
𝑉𝑟𝑒𝑓
𝑡𝑠𝑒𝑡𝑡𝑙𝑖𝑛𝑔 = − ln(𝑉 𝑁+2
)𝑅𝑆𝑤𝑖𝑡𝑐ℎ 𝐶𝑇𝑜𝑡𝑎𝑙 ……………………. (4.7)
𝑖𝑛 2

Equation (4.7) can validate that settling time can be reduced by choosing low value of unit
capacitance.

These are the major issues covered which should be taken care of while designing the DAC.
Apart from all these issues one more issue is the effect of the parasitic capacitance which is
prominent in the binary weighted with attenuation capacitor architecture. This parasitic
capacitance effect along with the capacitive mismatch is covered much in details in the
following chapters.

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 5. Analytical Model for the estimation of non-linearity
in capacitive DAC in SAR ADC
As discussed in previous chapters, the efficiency in terms of accuracy, power
consumption, and on-chip area of Successive Approximation Register (SAR) Analog to Digital
Converter (ADC) depends on the charge redistribution Digital to Analog Converter (DAC).
Thus, the optimal design of SAR ADC demands accurate design and analysis of the DAC unit.
In this chapter, a MATLAB model of charge-redistribution DAC based on Binary Weighted
with attenuation capacitor array has been presented for the design of a SAR ADC. This
MATLAB based model performs statistical as well as parametric simulations including the
effects of parasitic capacitances and capacitor mismatch which help in the accurate estimation
of static and dynamic non-linearity of the DAC unit.

5.1 Modelling the effect of parasitic capacitance:

In order to model the effect of parasitic capacitance on DAC output voltage, we need
to introduce the parasitic node capacitances and then have to compute the DAC output voltage
by considering the parasitic capacitance. The non-ideal model of Catt consists of three parts Cpl,
Cpm, and Cp as shown in Fig. 5.1, where Cpl is the net parasitic capacitance of the LSB array,
Cpm is the net parasitic capacitance of the MSB array and Cp is the parasitic between LSB and
MSB array. Now we need to calculate the DAC output voltage, taking into account the parasitic
capacitances. The output voltage is computed in the same manner as mentioned in the previous
chapter.

Fig 5.1. Non-ideal model of Binary Weighted DAC architecture with attenuation capacitor

The DAC output voltage considering all the parasitic capacitance’s is given as,
𝑁⁄2
𝑉𝑟𝑒𝑓 𝐶𝑒𝑞𝐿𝑆𝐵,𝑝𝑎𝑟 ⁄2
𝑉𝐷𝐴𝐶 = 𝐶 [∑ 𝐷𝑁+𝑖 𝐶𝑁+𝑖 + ∑𝑁
𝑖=1 𝐷𝑖 𝐶𝑖 ] …………………. (5.1)
𝑇𝑜𝑡,𝑝𝑎𝑟 2 2 𝐶𝐿𝑆𝐵,𝑝𝑎𝑟
𝑖=1

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 𝑁
⁄2
Where, 𝐶𝐿𝑆𝐵,𝑝𝑎𝑟 = ∑𝑁𝑖=1 𝐶𝑖 + 𝐶𝑝𝑙 = 2 2 −1 𝐶𝑢 + 𝐶𝑝𝑙 ,
𝑁 ⁄2 𝑁
𝐶𝑀𝑆𝐵,𝑝𝑎𝑟 = ∑ 𝐶𝑁+𝑖 + 𝐶𝑝𝑚 = (2 2 − 1) 𝐶𝑢 + 𝐶𝑝𝑚 ,
𝑖=1 2

𝐶𝑒𝑞𝐿𝑆𝐵,𝑝𝑎𝑟 = 𝐶𝐿𝑆𝐵,𝑝𝑎𝑟 ∥ (𝐶𝑎𝑡𝑡 + 𝐶𝑝 ), and 𝐶𝑇𝑜𝑡,𝑝𝑎𝑟 = 𝐶𝑒𝑞𝐿𝑆𝐵,𝑝𝑎𝑟 + 𝐶𝑀𝑆𝐵,𝑝𝑎𝑟

Replacing these values in equation (8), DAC output voltage consisting of all parasitic can be
expressed as,
𝑁⁄2
𝑁 𝑁⁄2
−1
𝑉𝑟𝑒𝑓 [(2 2 +1) ∑ 𝐷𝑁 2𝑖−1 +(∑ 𝐷𝑖 2𝑖−2 +𝐷1 )+𝛥𝑁𝑝𝑎𝑟 ]
+𝑖 𝑖=2
𝑖=1 2
𝑉𝐷𝐴𝐶,𝑝𝑎𝑟 = 𝑁 ……… (5.2)
[(2𝑁−1 +2 2 −1)+𝛥𝐷𝑝𝑎𝑟 ]

𝑁 𝑁 𝑁 𝑁
𝛥𝐷𝑝𝑎𝑟 = [(2 2 + 2 2 −1 − 1) 𝛼 + 2 2 𝛽 + (2 2 −1 + 1) 𝛾 + (𝛼. 𝛽 + 𝛼. 𝛾 + 𝛽. 𝛾)]… (5.3)

𝑁 ⁄2
𝐶𝑝 +𝐶𝑝𝑙 𝐶𝑝 𝑁 ⁄2
and,𝛥𝑁𝑝𝑎𝑟 = [( )∑ 𝐷𝑁+𝑖 2𝑖−1 + (∑𝑖=1 𝐷𝑖 2𝑖−2 + 𝐷1 )]……………. (5.4)
𝐶𝑢 𝑖=1 2 𝐶𝑢

Cp C pl C pm
considering,   ,  and   ………………………… (5.5)
Cu Cu Cu

From (5.3) and (5.4) it is clear that ∆Dpar is a constant value depending on the parasitic
and unit capacitance. Thus, it introduces a gain error without affecting the linearity of the DAC.
However, ∆Npar depends not only on the parasitic and unit capacitance but also on the bit values
(Di), thus, introducing non-linearity. This can further degrade the dynamic and static metric of
the DAC and subsequently of the converter. It is also seen from (5.5) that total parasitic
capacitance contributed by LSB and MSB array must be less than the unit capacitance to
minimize the non-linearity.

5.2 Modelling the effect of capacitive mismatch:

Mismatch in capacitor array because of the process variation effects the generated
comparison level of the DAC. As a result, linearity of DAC is affected and subsequently
converter’s linearity is distorted. UMC 0.18𝜇𝑚 CMOS technology comes with a Metal/Metal
Capacitor (MMC) module, also referred to as Metal Insulator Metal (MIM) capacitor module.
MIM Cap model is implemented in MATLAB provided by the UMC 0.18𝜇𝑚 technology.
Based on this the nominal value is computed. In order to introduce the flavour of mismatch, a
small random value of the same unit is added with the nominal value. This random value is
randomly selected within ±3σ variation with a Gaussian profile. Standard deviation of capacitor
Cn, consisting of ‘n’ parallel unit capacitance (Cu) can be given by,

𝜎(𝐶𝑛 ) = √𝑛 𝜎(𝐶𝑢 )…………………………… (5.6)

32 | P a g e
In this manner, each element of the capacitor array is computed. Using this array, DAC output
is computed.

MSB capacitance is the largest, thus it has the highest uncertainty of matching, affecting the
DAC output voltage the most. Hence while designing the DAC, care should be taken that the
maximum error due to MSB at the DAC output voltage should not exceed half LSB. i.e. ∆VDAC
≤ 0.5LSB.

It can be seen from (4.5) that the mismatch is inversely proportional to the area of unit
capacitance. Hence in order to achieve better matching higher unit capacitance is desired,
which in results a higher chip area and power consumption. Thus, there is a trade-off between
the improvement in nonlinearity due to mismatch and performance in terms of area and power
consumption which makes the design of DAC complex.

5.3 Modelling the effect of both parasitic capacitance and capacitive

mismatch:
In this section a generalized equation has been developed which can be used to analyse
the effect of both parasitic capacitance and capacitor mismatch. This equation is derived using
the charge conservation principle i.e. charge stored in the capacitor array during the sampling
is equal to the charge on the capacitor array when the input is disabled i.e. conversion phase.
MATLAB model of 14-bit Fully Differential SAR ADC as shown in figure (5.2) is used for
deriving the equation. In this, DAC is the only non-ideal unit comprising both the effects of

Fig 5.2. Block diagram of 14 bit Fully Differential SAR ADC

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parasitic and mismatch. All the other units are kept ideal.
During sampling phase, top plate of the MSB capacitor array is connected to the input whereas
bottom plate is connected to Vrefp. The charge stored Qi during sampling can be expressed as,

𝑄𝑖 = 𝑄𝑖,𝑀𝑆𝐵 + 𝑄𝑖,𝑒𝑞𝐿𝑆𝐵 = (𝑉𝑖𝑛 − 𝑉𝑟𝑒𝑓𝑝 )𝐶𝑀𝑆𝐵 + 𝑉𝑖𝑛 𝐶𝑝𝑚 + (𝑉𝑖𝑛 − 𝑉𝑡ℎ )𝐶𝑒𝑞𝐿𝑆𝐵 , where

𝑁/2 𝐶𝑖 𝑉𝑖 𝐶𝐿𝑆𝐵 (𝐶𝐴𝑡𝑡 +𝐶𝑝 ).(𝐶𝐿𝑆𝐵 +𝐶𝑝𝑙 )

𝑉𝑡ℎ = [∑𝑖=1 ] = 𝑉𝑟𝑒𝑓𝑝 and 𝐶𝑒𝑞𝐿𝑆𝐵 = . Replacing
(𝐶𝐿𝑆𝐵 +𝐶𝑝𝑙 ) (𝐶𝐿𝑆𝐵 +𝐶𝑝𝑙 ) (𝐶𝐿𝑆𝐵 +𝐶𝐴𝑡𝑡 +𝐶𝑝 +𝐶𝑝𝑙 )
these values, we will get
(𝐶𝐴𝑡𝑡 +𝐶𝑝 )(𝐶𝐿𝑆𝐵 +𝐶𝑝𝑙 ) 𝐶𝐿𝑆𝐵 (𝐶𝐴𝑡𝑡 +𝐶𝑝 )
𝑄𝑖 = 𝑉𝑖𝑛 [𝐶𝑝𝑚 + 𝐶𝑀𝑆𝐵 + (𝐶 ] − 𝑉𝑟𝑒𝑓𝑝 [𝐶𝑀𝑆𝐵 + (𝐶 ] …… (5.7)
𝐿𝑆𝐵 +𝐶𝐴𝑡𝑡 +𝐶𝑝 +𝐶𝑝𝑙 ) 𝐴𝑡𝑡 +𝐶𝑝 +𝐶𝐿𝑆𝐵 +𝐶𝑝𝑙 )

After sampling is done, input signal is disabled. The bottom plate of all the elements in the
capacitor array is determined using the decision made by SAR Logic. Assuming bottom plate
voltages as Vi, where i = 1, 2...N. The final charge stored Qf at any conversion instant can be
calculated as,
𝑄𝑓 = 𝑄𝑓,𝑀𝑆𝐵 + 𝑄𝑓,𝑒𝑞𝐿𝑆𝐵

𝑄𝑓 = (𝑉𝐷𝐴𝐶 − 𝑉𝑁 )𝐶𝑁 + (𝑉𝐷𝐴𝐶 − 𝑉𝑁−1 )𝐶𝑁−1 + ⋯ + (𝑉𝐷𝐴𝐶 − 𝑉𝑁+1 ) 𝐶𝑁+1 + 𝑉𝐷𝐴𝐶 𝐶𝑝𝑚
2 2
+ (𝑉𝐷𝐴𝐶 − 𝑉𝑡ℎ )𝐶𝑒𝑞𝑙𝑆𝐵

𝑁⁄2
(𝐶𝐴𝑡𝑡 +𝐶𝑝 )(𝐶𝐿𝑆𝐵 +𝐶𝑝𝑙 ) 𝑁/2 (𝐶𝐴𝑡𝑡 +𝐶𝑝 ) ∑𝑖=1 𝐶𝑖 𝑉𝑖
𝑄𝑓 = 𝑉𝐷𝐴𝐶 [𝐶𝑀𝑆𝐵 + 𝐶𝑝𝑚 + (𝐶 ] − ∑𝑖=1 𝐶𝑁+𝑖 𝑉𝑁+𝑖 − .. (5.8)
𝐿𝑆𝐵 +𝐶𝐴𝑡𝑡 +𝐶𝑝 +𝐶𝑝𝑙 ) 2 2
(𝐶𝐴𝑡𝑡 +𝐶𝑝 +𝐶𝐿𝑆𝐵 +𝐶𝑝𝑙 )

where 𝑉𝑁 = 𝐷𝑁 𝑉𝑟𝑒𝑓𝑝

Using charge conservation principle Qi = Qf, the DAC output voltage can be expressed as,
𝑁⁄2
𝑁⁄2
𝑉𝑟𝑒𝑓 (𝐾1 𝐶𝑀𝑆𝐵 +𝐶𝐿𝑆𝐵 𝐾2 )−𝐾1 ∑ 𝐶𝑁 𝑉𝑁 −𝐾2 ∑𝑖=1 𝐶𝑖 𝑉𝑖
+𝑖 +𝑖
2 2
𝑉𝐷𝐴𝐶 = 𝑉𝑖𝑛 − [ 𝑖=1
] …………… (5.9)
𝐾3 𝐾1 +𝐾2 𝐾4
where

𝐾1 = 𝐶𝑎𝑡𝑡 + 𝐶𝐿𝑆𝐵 + 𝐶𝑝 + 𝐶𝑝𝑙 , 𝐾2 = 𝐶𝑎𝑡𝑡 + 𝐶𝑝 , K3  CMSB  C pm and K4  CLSB  C pl

In the above equation (5.9), to show the parasitic effect, different combination of
𝛼, 𝛽 𝑎𝑛𝑑 𝛾 is chosen. Based on the relationship developed in equation (5.5), C pl , C p and C pm
is calculated and substituted in the above equation (5.9).
However, in order to include the mismatch, a statistical analysis has been performed
for all the capacitance between their respective ranges i.e. Ci ±σ(Ci), where i = 1, 2...14. Once
the total element of the capacitor array is obtained, CMSB and CLSB is calculated and substituted
in the above equation.

34 | P a g e
Thus, DAC voltages of both DAC-P and DAC-N for fully differential architecture including
both parasitic capacitance and capacitive mismatch is obtained. Comparison among these
voltages is made by the comparator. Based on the results obtained by comparator, SAR logic
decides further switching of the DAC. The obtained results include the effect of both mismatch
and parasitic. From the obtained result static and dynamic non-linearity is calculated

5.4 Modelling methodology

The converter’s characteristic can be easily derived once all the transition levels of the input
voltage are known. These levels can be assessed through a voltage capacitive divider, thus by
means of a simple capacitive ratio, eventually taking into consideration the parasitic and the
statistical variation of the array capacitances. This approach allows to drastically lighten the
computation of the nonlinearity metrics. Fig 5.3. shows the block diagram of modelling
methodology which has been adapted. It includes the following steps:
 Implementation of the DAC capacitance model, eventually adding the parasitics and/or
mismatch contribution
 Evaluation of DAC output vector (VDAC), i.e. the DAC output voltages corresponding
to all the possible switch configurations, which represents all the transition levels
between adjacent codes.
 Assessment of the ADC input-to-output characteristic from the DAC output vector.
 evaluation of the static metrics (DNL and INL)
 evaluation of the dynamic metrics (SNDR and ENoB)

Fig 5.3. Block diagram of modelling methodology

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5.5 Results and Discussion
In this section, various results obtained is shown as well as discussed. The performance of
the ADC has been measured with Vrefp = 1.8V and Vrefn = 0V. The reconstructed analog value
from 14-bit digital output, has been used to compute static and dynamic characteristic of the
converter.

In order to compute the static metric which comprises of DNL and INL, a ramp signal is
provided at the input. Obtained digital value is again reconstructed and thus a staircase output
is obtained. From this DNL and INL is calculated. However, to compute dynamic metric which
mainly comprises SNDR and ENOB, differential sinusoidal signal is applied ate the input and
14-bit digital output is obtained. Digital output is reconstructed using ideal DAC. Power
spectrum is calculated for the reconstructed analog signal and hence SNDR & ENOB is
calculated.

Fig 5.4. Procedure for calculating static and dynamic metric

Fig 5.5 and Fig 5.6 is the curves of obtained DNL and INL considering only parasitic
capacitance effect. Here for different value of 𝛼, 𝛽 𝑎𝑛𝑑 𝛾 DNL and INL is obtained
considering unit capacitance as 900fF.

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 Fig 5.5. DNL and its normal distribution considering only parasitic (Cp, Cpl and Cpm)

Fig 5.6. INL and its normal distribution considering only parasitic (Cp, Cpl and Cpm)

It can be seen from the Fig 5.5 and Fig 5.6 that, with increase in the value of 𝛼, 𝛽 𝑎𝑛𝑑 𝛾 , DNL
and INL of the converter degrades. Lower the value of 𝛼, 𝛽 𝑎𝑛𝑑 𝛾 ,the curve converges to small
DNL and INL. In order to have better linearity, less parasitic capacitance is desired. Better
layout practices may help in minimizing these parasitic capacitances.

Now, only the mismatches are considered and DNL and INL is plotted in Fig 5.7 and
Fig 5.8. Here, different values of unit capacitor are chosen. Maximum allowed MIM metal area
is 150*150um. However, in order to obtain a better control of the bottom plate to substrate
parasitic capacitance, it is recommended to not draw MIM area greater than 30*30 um. Thus,
maximum unit capacitor considered here is 909fF corresponding to area 30*30 um.

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 Fig 5.7. DNL and its normal distribution considering only mismatch

Fig 5.8. INL and its normal distribution considering only mismatch

Now using the same procedure, dynamic metric (SNDR, ENOB) is calculated considering the

Fig 5.9. Power Spectrum of the ADC for (a) different parasitic value (Cp, Cpl and Cpm) (b)
mismatch of capacitor

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 effect of both parasitic capacitance and capacitive mismatch respectively and obtained
frequency response is shown in Fig 5.9. Here input signal is a sinusoidal wave of frequency
500Hz and is sampled at 1Msps.

Now, effect of both parasitic capacitance and mismatch is considered together. Various
results thus obtained are depicted in the Table 1.
Table 1: Effect of parasitic and mismatches on Static and Dynamic characteristic of DAC unit

Cu Mismatch Std.    DNL INL SNDR ENOB

(LSB) (LSB) (dB) (bit)
(fF) Dev
No - 0 0 0  0.2  0.2 78.67 12.78
Yes 3 0 0 0 9 7 59.67 9.62
No - 0.1 0.1 0.1 -0.2, 3 64.46 10.42
103 +0.18
No - 0.25 0.25 0.25 -0.2, 8 55.85 8.94
+4.6
No - 0.5 0.5 0.5 -0.2,  15 50.17 8.04
+8
Yes 3 0.1 0.1 0.1  10 7 57.40 9.24
Yes 3 0.25 0.25 0.25  11 8 53.64 8.62
Yes 3 0.5 0.5 0.5  13  15 49.52 7.93
No - 0 0 0  0.2  0.2 78.67 12.78
Yes 3 0 0 0 3  2.2 69.42 11.23
No - 0.1 0.1 0.1 -0.2, 3 64.46 10.42
+0.18
229 No - 0.25 0.25 0.25 -0.2, 8 55.85 8.94
+4.6
No - 0.5 0.5 0.5 -0.2,  15 50.17 8.04
+8
Yes 3 0.1 0.1 0.1  3.6 3 63.1 10.19
Yes 3 0.25 0.25 0.25 6 8 55.60 8.94
Yes 3 0.5 0.5 0.5 8  15 50.02 8.05
No - 0 0 0  0.2  0.2 78.67 12.78
Yes 3 0 0 0 1  0.8 74.86 12.14
No - 0.1 0.1 0.1 -0.2,  1.5 64.98 10.50
404 +0.8
No - 0.25 0.25 0.25 -0.2, 3 59.63 9.61
+1.8
No - 0.5 0.5 0.5 -0.2, 6 53.09 8.53
+3.6
Yes 3 0.1 0.1 0.1 -1, 3 64.08 10.35
+2.2
Yes 3 0.25 0.25 0.25 -1.2, 8 55.84 8.98
+5.2
Yes 3 0.5 0.5 0.5 -0.8,  15 50.21 8.05
+8
No - 0 0 0  0.2  0.2 78.67 12.78
Yes 3 0 0 0  0.6  0.4 77.50 12.58
No - 0.1 0.1 0.1 -0.2, 3 64.46 10.42
+0.18

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 632 No - 0.25 0.25 0.25 -0.2, 8 55.85 8.94
+4.6
No - 0.5 0.5 0.5 -0.2,  15 50.17 8.04
+8
Yes 3 0.1 0.1 0.1 -0.6, 3 64.33 10.39
+2
Yes 3 0.25 0.25 0.25 -0.4, 8 55.87 8.99
+4.6
Yes 3 0.5 0.5 0.5 -0.4,  15 50.21 8.05
+8
No - 0 0 0  0.2  0.2 78.67 12.78
Yes 3 0 0 0  0.2  0.2 78.56 12.76
No - 0.1 0.1 0.1 -0.2, 3 64.46 10.42
+0.18
909 No - 0.25 0.25 0.25 -0.2, 8 55.85 8.94
+4.6
No - 0.5 0.5 0.5 -0.2,  15 50.17 8.04
+8
Yes 3 0.1 0.1 0.1 -0.2, 3 64.35 10.39
+1.8
Yes 3 0.25 0.25 0.25 -0.2, 8 55.85 8.98
+4.6
Yes 3 0.5 0.5 0.5 -0.2,  15 50.21 8.05
+8

Above results shows the degradation of the linearity of the DAC unit on parasitic and
mismatches. Mismatch effect can be minimizedby choosing larger capacitance value as the
mismatch is inversely proportional with the area of the capacitor. MSB capacitance is the
largest, thus it has the highest uncertainty of matching, affecting the DAC output voltage the
most. Hence while designing the DAC, care should be taken that the maximum error due to
MSB at the DAC output voltage should not exceed half LSB. i.e. ∆VDAC ≤ 0.5LSB. Parasitic
effect can be minimized by using proper layout techniques. So, to achieve high resolution with
good accuracy mere split array DAC cannot be sufficient. Different calibration techniques must
be adopted to solve this trade-off between the improvement in non-linearity due to mismatch
and performance in terms of area and power consumption. In next chapter, calibration
technique is discussed in detail.

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 6. Calibration technique to reduce nonlinearity
In high resolution DAC’s or DAC with low Cu value a little mismatch could result in large
voltage variations at the output. Thus, it is important to calibrate mismatch in such circuits.
Here self-calibration technique is utilized in the DAC circuit to reduce the capacitance
mismatch. This is a foreground calibration technique hence it will be initiated automatically
whenever the circuitry is turned on for first time and after using certain clock periods for
calibration it will work with its normal operation as DAC.

The non-ideal model of Catt consists of three parts Cpl, Cpm, and Cp was shown in Fig. 5.1,
where Cpl is the net parasitic capacitance of the LSB array, Cpm is the net parasitic capacitance
of the MSB array and Cp is the parasitic between LSB and MSB array. Using this model, Ceff
(the effective contribution of LSB- side to DAC output node) is calculated as shown in Fig 6.1.
To ensure perfect linearity, Ceff must equal to the unit capacitor Cu.

Fig 6.1. Figure showing calculation of Ceff

(𝐶𝑎𝑡𝑡 + 𝐶𝑝𝑙 )(𝐶𝐿𝑆𝐵 + 𝐶𝑝𝑙 )

𝐶𝑒𝑓𝑓 = … … … …. (6.1),
𝐶𝑎𝑡𝑡 + 𝐶𝑝𝑙 + 𝐶𝐿𝑆𝐵 + 𝐶𝑝𝑙
where CLSB is summation of all LSB capacitors.
We have used attenuation capacitor same as unit capacitor. It is evident from equation 6.1
that Ceff is not equal to unit capacitor. To keep Ceff always equal to the lowest bit capacitor of
MSB segment (Cu), a linear tunable array CV is placed on the LSB segment for calibration as
shown in Fig 6.2. It aims to adjust Ceff equal to Cu regardless of the mismatch and parasitic
effect of Catt. Implementation of CV is shown in Fig 6.3.

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 Fig 6.2. Non-ideal model along with tunable capacitor CV

Fig 6.3. Implementation of tunable capacitor CV

6.1 Calibration logic

The calibration is done in three phases Precharging, Charge Redistribution and
Mismatch calibration. Calibration is done for both DAC-P and DAC-N one after another.
Phases of calibration are explained much in details in the following section:

 Precharging Phase: In this phase, all the MSB-side capacitances connected to ground
and all the LSB -side capacitances connected to Vref. VCM (common mode voltage) is
also connected and hence total capacitor array charged to potential equals to VCM.

 Charge Re-distribution Phase: During this mode, VCM is disconnected and voltages
of lowest value capacitor on MSB-side and voltages on the LSB-side are swapped. Net
capacitance of the LSB-side should have been equal to the lowest valued capacitor on
the MSB-side, but because of the mismatch and parasitic capacitance, it is not equal.
Thus, redistribution of charge takes place and because of that the output voltage of DAC
is not equal to VCM.

 Mismatch Calibration Phase: In this phase, the mismatch in the LSB side is
calibrated. The output of DAC should have been ideally equal to VCM, but practically

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 it is not so. The DAC output is monitored and compared with the VCM. In order to
compensate for the change in the output voltage of the DAC, linear tunable capacitor
CV is added on the LSB side. Proper tuning of C V, compensates for the change in the
voltage during charge redistribution phase. Hence mismatch in the LSB side is
calibrated. The value of Cv is freezed and hence will not change.

Fig 6.4. DAC-P in precharge phase

Fig 6.5. DAC-P in charge-redistribution phase

Fig 6.6. DAC-P in mismatch calibration phase

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 Now we will calibrate the DAC-P and DAC-N one by one. At first the DAC-P is calibrated
followed by DAC-N. Initially DAC-P is in precharge phase and state of DAC-N is not bothered
because comparator which compares the DAC-P and DAC-N output voltage, is disabled. Once
the DAC-P is precharged to VCM, it is shifted to charge redistribution phase. Now the DAC-N
is connected in precharge phase. Once the charge redistribution is done, comparator is enabled.
It compares the output voltage of DAC-P and DAC-N. Based on the results of the comparison,
Cv is tuned by proper control mechanism. Once the DAC-P voltage just exceeds Vcm, it
indicates that the DAC-P calibration is done. Cv corresponding to DAC-P is freezed and then
DAC-P is connected to Vcm. Now DAC-N is brought into the charge redistribution phase.
Same procedure is adapted for DAC-n also. Thus, both DAC-P and DAC-N is calibrated one
after another. Here, we need to ensure that the offset of comparator should be less than the LSB
and precision of Cv determines the accuracy of calibration. In Fig 6.7 illustrates the calibration
setup of DAC-P and DAC-N.

Fig 6.7. Calibration setup of DAC-P and DAC-N

6.2 Circuit implementation:

In this section, a brief overview regarding the circuit implementation of all peripherals
of DAC along with the calibration control circuit is described. These circuits have been
implemented in cadence virtuoso.
Calibration control circuit: This circuit is mainly responsible for the generation of all control
signals necessary for the calibration. Along with the power signal, RST, outp, outn and external
clock are the major inputs. Outp and outn are the comparator’s output, which is by default set
to zero. Using all this signal, it generates s, sb, the inputs of the DAC switches and the input
of the control circuitry of C-DACP and C-DACN are generated. ‘S’ is the output which mainly

44 | P a g e
signifies the end of DAC calibration. Fig 6.8 illustrates the circuit diagram of Calibration
control circuit.

Fig 6.8. Calibration control circuit

Implementation of DAC switch controller: DAC switch controls the bottom plate voltage of
all the capacitors in the DAC array. These have different configuration in calibration phase and
conversion phase. Thus, we need a separate control circuit which can maintain the capacitor
potentials as per the requirement. Initially, it operates DAC in calibration mode just after it gets
one RESET signal. After the calibration is done, it operates the DAC in conversion mode. It
controls the DAC potentials based on the decision made by comparator. Fig 6.9 shows the
individual DAC switch controller and Fig 6.10 shows the total array.

Fig 6.9. Individual DAC switch controller circuit

45 | P a g e
46 | P a g e
Fig 6.10. DAC switch controller array circuit
Implementation of control circuit of Calibration DAC (C-DAC): These are basically Flip-
Flops, which control the calibration DAC. Depending on the amount of mismatch, it is mainly
responsible for tuning the C-DAC after getting input from the Calibration control unit. Fig 6.11
sows the circuit diagram of the C-DAC switch controller.

Fig 6.11. C-DAC switch controller array circuit

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6.3 Simulation results
The waveform of calibration of DAC-P shown in Fig 6.7 was simulated in cadence
with all peripherals of DAC connected. Here we can clearly see the DAC going through all the
three phases needed for the calibration. Initially, after the clock became active, DAC goes into
precharge phase and is charged to 900 mv. After that it goes into the charge redistribution
phase. We can clearly notice that, the voltage of DAC rises above the 900mv owing to the
mismatch in the LSB-side and the MSB-side. Lastly to resolve this issue, it goes into calibration
phase where by proper tuning action of the C-DACP, it compensates for the extra voltage rise
because of mismatch. This has been done for both DAC-P and DAC-N. In Fig 6.12, timing
diagram for the calibration of both DAC-P and DAC-N is shown.

Fig 6.12. Waveform of calibration of DAC-P

Fig 6.13. Waveform of calibration of both DAC-P and DAC-N

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 Here the results for the dynamic metric are given for both before and after calibration.
We can illustrate from Fig 6.14 and Fig 6.15, that we are getting some improvements because
of calibration.

Fig 6.14. Power spectrum before calibration

Fig 6.15. Power spectrum after calibration

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Dynamic metrics were calculated for input frequency 100Hz. Sampling frequency were varied
from 1KSPS to 25KSPS. Various data before and after calibration is shown in Table 6.1.
Improvements can be seen from this table also. However, due to resource constraint we were
unable to provide data relating to static metric.

Table 6.1: Data relating to dynamic metric before and after calibration
Input KSPS SINAD SFDR SNDR ENOB THD
Freq.
(Hz)

Before After Before After Before After Before After Before After
Calib Calib Calib Calib Calib Calib Calib Calib Calib Calib
100 1 61.29 71.75 63.72 74.18 58.87 69.33 9.88 11.62 61.29 71.75
100 5 61.75 72.20 63.94 74.40 60.51 70.97 9.96 11.70 61.75 72.20
100 10 61.94 72.40 64.10 74.56 60.78 71.24 9.99 11.73 61.94 72.40
100 25 62.05 72.50 64.19 74.65 60.92 71.38 10.02 11.75 62.05 72.45

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REFERENCES:

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Meinerzhagen, EPFL
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