HMC 832 A

25 MHz to 3000 MHz
Fractional-N PLL with Integrated VCO

Data Sheet HMC832A
FEATURES FUNCTIONAL BLOCK DIAGRAM
LD/SDO SCK SDI
RF bandwidth: 25 MHz to 3000 MHz
3.3 V supply HMC832A LOCK
DETECT
Maximum phase detector rate: 100 MHz
Ultralow phase noise CONTROL
SPI
PROGRAMMING SEN
INTERFACE
−110 dBc/Hz in band (typical), fO at 1600 MHz
EN
Fractional figure of merit (FOM): −226 dBc/Hz MODULATOR CAL RF_P
24-bit step size, 3 Hz typical resolution

Exact frequency mode with 0 Hz frequency error EN RF_N
Fast frequency hopping ÷1, 2, 4, 6, ...62
40-lead, 6 mm × 6 mm LFCSP package: 36 mm2

÷N
APPLICATIONS VCO
CP CP PFD VTUNE
Cellular infrastructure
Microwave radios ÷R
WiMax, WiFi
13110-001
Communications test equipment XREFP
CATV equipment Figure 1.

DDS replacement
Military
Tunable reference sources for spurious-free performance
GENERAL DESCRIPTION
The HMC832A is a 3.3 V, high performance, wideband, frac- The HMC832A is footprint compatible to the HMC830 PLL
tional-N, phase-locked loop (PLL) that features an integrated with an integrated VCO. It features 3.3 V supply and innovative
voltage controlled oscillator (VCO) with a fundamental programmable performance technology that enables the
frequency of 1500 MHz to 3000 MHz and an integrated VCO HMC832A to tailor current consumption and corresponding
output divider (divide by 1, 2, 4, 6, … 62) that enables the noise floor performance to individual applications by selecting
HMC832A to generate continuous frequencies from 25 MHz to either a low current consumption mode or a high performance
3000 MHz. The integrated phase detector (PD) and Σ-Δ mode for improved noise floor performance.
modulator, capable of operating at up to 100 MHz, permit wider Additional features of the HMC832A include 12 dB of RF
loop bandwidths and faster frequency tuning with excellent output gain control in 1 dB steps; an output mute function to
spectral performance. automatically mute the output during frequency changes when
Industry leading phase noise and spurious performance, across the device is not locked; selectable output return loss;
all frequencies, enable the HMC832A to minimize blocker programmable differential or single-ended outputs, with the
effects, and to improve receiver sensitivity and transmitter ability to select either output in single-ended mode; a Σ-Δ
spectral purity. A low noise floor (−160 dBc/Hz eliminates any modulator exact frequency mode that enables users to generate
contribution to modulator/mixer noise floor in transmitter output frequencies with 0 Hz frequency error; and a register
applications. configurable 3.3 V or 1.8 V serial port interface (SPI).
Rev. B Document Feedback

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HMC832A Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1 ID, Read Address, and Reset (RST) Registers ........................ 35
Applications ....................................................................................... 1 Reference Divider (REFDIV), Integer, and Fractional
Functional Block Diagram .............................................................. 1 Frequency Registers ................................................................... 35
General Description ......................................................................... 1 VCO SPI Register ....................................................................... 36
Revision History ............................................................................... 2 Σ-Δ Configuration Register ...................................................... 36
Specifications..................................................................................... 3 Lock Detect Register .................................................................. 37
Timing Specifications .................................................................. 6 Analog Enable (EN) Register .................................................... 37
Absolute Maximum Ratings ............................................................ 7 Charge Pump Register ............................................................... 38
Recommended Operating Conditions ...................................... 7 Autocalibration Register............................................................ 38
ESD Caution .................................................................................. 7 Phase Detector (PD) Register ................................................... 39
Pin Configuration and Function Descriptions ............................. 8 Exact Frequency Mode Register ............................................... 39
Typical Performance Characteristics ............................................. 9 General-Purpose, SPI, and Reference Divider

(GPO_SPI_RDIV) Register ...................................................... 40
Theory of Operation ...................................................................... 15
VCO Tune Register .................................................................... 41
PLL Subsystem Overview .......................................................... 15
Sucessive Approximation Register ........................................... 41
VCO Subsystem Overview ........................................................ 15
General-Purpose 2 Register ...................................................... 41
SPI Configuration of PLL and VCO Subsystems ................... 15
Built-In Self Test (BIST) Register ............................................. 41
VCO Subsystem .......................................................................... 17
VCO Subsystem Register Map ...................................................... 42
PLL Subsystem ............................................................................ 21
VCO Enable Register ................................................................. 42
Soft Reset and Power-On Reset ................................................ 28
VCO Output Divider Register .................................................. 43
Power-Down Mode .................................................................... 28
VCO Configuration Register .................................................... 43
General-Purpose Output (GPO) .............................................. 28
VCO Calibration/Bias, Center Frequency Calibration
Chip Identification ..................................................................... 29 (CF_CAL), and MSB Calibration Registers ............................ 44
Serial Port Interface (SPI) .......................................................... 29 VCO Output Power Control ..................................................... 44
Applications Information .............................................................. 32 Evaluation Printed Circuit Board (PCB) ..................................... 45
Power Supply ............................................................................... 33 Changing Evaluation Board Reference Frequency and CP
Programmable Performance Technology................................ 33 Current Configuration .............................................................. 46
Loop Filter and Frequency Changes ........................................ 33 Evaluation Kit Contents ............................................................ 46
RF Programmable Output Return Loss................................... 34 Outline Dimensions ....................................................................... 47
Mute Mode .................................................................................. 34 Ordering Guide .......................................................................... 48
PLL Register Map ........................................................................... 35
REVISION HISTORY
11/15—Revision B: Initial Version
Rev. B | Page 2 of 48
Data Sheet HMC832A
SPECIFICATIONS
VPPCP, VDDLS, VCC1, VCC2, RVDD, AVDD, DVDD, VCCPD, VCCHF, VCCPS = 3.3 V minimum and maximum specified across the
temperature range of −40°C to +85°C.
Table 1.
Parameter Test Conditions/Comments Min Typ Max Unit
RF OUTPUT CHARACTERISTICS
Output Frequency 25 3000 MHz
VCO Frequency at PLL Input 1500 3000 MHz
RF Output Frequency at fVCO 1500 3000 MHz
OUTPUT POWER
RF Output Power Across all frequencies (see Figure 25), high
performance mode (VCO_REG 0x03[1:0] = 3d)
Maximum gain setting (VCO_REG 0x07[3:0] = 7 dBm
0xB), single-ended
Gain Setting 6 (VCO_REG 0x07[3:0] = 6d), 2 dBm
differential
Output Power Control Range 1 dB steps 12 dB
HARMONICS FOR FUNDAMENTAL MODE
fO Mode at 2 GHz Second/third/fourth harmonics −20/−29/−45 dBc
fO/2 Mode at 2 GHz/2 = 1 GHz Second/third/fourth harmonics −26/−10/−34 dBc
fO/30 Mode at 3 GHz/30 = 100 MHz Second/third/fourth harmonics −33/−10/−40 dBc
fO/62 Mode at 1550 MHz/62 = 25 MHz Second/third/fourth harmonics −40/−6/−43 dBc
VCO OUTPUT DIVIDER
VCO RF Divider Range 1, 2, 4, 6, 8, … 62 1 62
PLL RF DIVIDER CHARACTERISTICS
19-Bit N-Divider Range (Integer) Maximum = 219 − 1 16 524,287
19-Bit N-Divider Range (Fractional) Fractional nominal divide ratio varies (±4) 20 524,283
dynamically maximum
REFERENCE (XREFP PIN) INPUT
CHARACTERISTICS
Maximum XREFP Input Frequency 350 MHz
XREFP Input Level AC-coupled1 −6 +12 dBm
XREFP Input Capacitance 5 pF
14-Bit R-Divider Range 1 16,383
PHASE DETECTOR (PD)2
PD Frequency Fractional Mode3 DC 100 MHz
PD Frequency Integer Mode DC 100 MHz
CHARGE PUMP
Output Current 0.02 2.54 mA
Charge Pump Gain Step Size 20 µA
PD/Charge Pump Single Sideband (SSB) 50 MHz reference, input referred
Phase Noise
1 kHz −143 dBc/Hz
10 kHz Add 2 dB for fractional mode −150 dBc/Hz
100 kHz Add 3 dB for fractional mode −152 dBc/Hz
LOGIC INPUTS 1.8 V and 3.3 V modes
Input Voltage
Low (VIL) 0.75 V
High (VIH) 1.15 V
SCK Clock Frequency Rate 6 50 MHz
HMC832A Data Sheet
LD/SDO LOGIC OUTPUT
Output High Voltage
High (VOH) CMOS 1.8 V mode (Register 0x0F[9:8] = 00b, 1.3 2.3 V
Register 0x0B[22] = 0)
CMOS 3.3 V mode (Register 0x0F[9:8] = 00b, VDD − VDD V
Register 0x0B[22] = 1) 0.2
Open-drain mode (Register 0x0F[9:8] = 01b)4 1.8 V
Low (VOL) CMOS mode (Register 0x0F[9:8] = 00b) 0.1 V
Open-drain mode (Register 0x0F[9:8] = 01b)5 0.4
SCK Clock Frequency Rate CMOS mode (Register0x0F[9:8] = 00b)6 6 50 MHz
Open-drain mode (Register0x0F[9:8] = 01b)7 5 10 MHz
Capacitive Load CMOS mode (Register0x0F[9:8] = 00b) 10 20 pF
Open-drain mode (Register0x0F[9:8] = 01b)8 10 pF
Load Current CMOS mode (Register0x0F[9:8] = 00b)9 3.6 mA
Open-drain mode (Register0x0F[9:8] = 01b)10 7.2 mA
Output Resistance When Driver Is Low (RON) Open-drain mode (Register0x0F[9:8] = 01b) 100 200 Ω
Pull-Up Resistor (RUP) Open-drain mode (Register0x0F[9:8] = 01b) 500 1000 Ω
Rise Time CMOS mode (Register0x0F[9:8] = 00b)11 0.5 + 0.3(CLOAD) 7 ns
Fall Time CMOS mode (Register0x0F[9:8] = 00b)11 1.5 + 0.2(CLOAD) 10 ns
SCK to SDO Turnaround Time CMOS mode (Register0x0F[9:8] = 00b)11 0.9 + 0.1(CLOAD) 12 ns
Output Impedance (ROUT) 1.8 V mode (Register 0x0B[22] = 0) 100 200 Ω
POWER SUPPLY VOLTAGES
3.3 V Supplies AVDD, VCCHF, VCCPS, VCCPD, RVDD, DVDD, 3.1 3.3 3.5 V
VPPCP, VDDLS, VCC1, VCC2
POWER SUPPLY CURRENTS
High Performance Mode VCO_REG 0x03[1:0] = 3d12
2500 MHz, 11 dB Gain 11 dB gain (VCO_REG 0x07[3:0] = 11d), 219 mA
single-ended output (VCO_REG 0x03[3:2] = 2d)
800 MHz, 11 dB Gain Single-ended output 230 mA
differential output (VCO_REG 0x03[3:2] = 3d)
800 MHz, 6 dB Gain Differential output 237 mA
Low Current Mode VCO_REG 0x03[1:0] = 1d12
Power-Down
Crystal Off Register 0x01 = 0, crystal not clocked 10 µA
Crystal On, 100 MHz Register 0x01 = 0, crystal clocked at 100 MHz 5 mA
POWER-ON RESET
Typical Reset Voltage on DVDD 700 mV
Minimum DVDD Voltage for No Reset 1.5 V
Power-On Reset Delay 250 µs
VCO CLOSED-LOOP PHASE NOISE
fO at 1600 MHz, 10 kHz Offset See Figure 3 −110 dBc/Hz
Data Sheet HMC832A
VCO OPEN-LOOP PHASE NOISE
fO at 2 GHz13
10 kHz Offset −88 dBc/Hz
1 MHz Offset −139 dBc/Hz
fO at 2 GHz/2 = 1 GHz13
fO at 3 GHz/30 = 100 MHz13
250 kHz Offset fO13 Over manufacturing process variations with

3.3 V power supply at 25°C
fO = 1584 MHz −124.5 dBc/Hz
fO = 1998 MHz −122.5 dBc/Hz
fO = 2416 MHz −122.0 dBc/Hz
fO = 2812 MHz −121.0 dBc/Hz
PLL
Phase Noise at 20 kHz Offset, 50 MHZ Over process with 3.3 V power supply at 25°C,
PFD Rate measured with >200 kHz loop bandwidth
fO = 1582.896 MHz −113.5 dBc/Hz
fO = 1998.25 MHz −113.5 dBc/Hz
fO = 2415.735 MHz −112.5 dBc/Hz
fO = 2811.21 MHz −109.5 dBc/Hz
Lock Time Depends on loop filter bandwidth, PFD rate, 500 µs
and definition of lock (to within ±Hz or
±degrees of settling)
Frequency Resolution Depends on PFD rate and VCO output divider
setting
Fundamental Mode 1.5 GHz to 3 GHz output; at typical phase fPD/224 Hz
detector frequency (fPD) of 50 MHz, typical
resolution = 3 Hz
Divider Mode <1.5 GHz output, resolution depends on VCO fPD/(224 × Hz
output divider setting output divider)
Reference Spurs −85 dBc/Hz
FIGURE OF MERIT (FOM) Normalized to 1 Hz (see Figure 24)
Floor Integer Mode −229 dBc/Hz
Floor Fractional Mode −226 dBc/Hz
Flicker (Both Modes) −268 dBc/Hz
HMC832A Data Sheet
VCO CHARACTERISTICS
VCO Tuning Sensitivity Measured with 1.5 V on VTUNE (see Figure 29)
2800 MHz 24.6 MHz/V
2400 MHz 25.8 MHz/V
2000 MHz 25.2 MHz/V
1600 MHz 24.3 MHz/V
VCO Supply Pushing14 Measured with 1.5 V on VTUNE 2.8 MHz/V
1
Measured with 100 Ω external termination. See the Reference Input Stage section for more details.
2
Slew rate of ≥0.5 ns/V is recommended. See the Reference Input Stage section for more details. Frequency is guaranteed across process voltage and temperature from
−40°C to +85°C.
3
This maximum PD frequency can only be achieved if the minimum N value is respected. For example, in the case of fractional mode, the maximum PD frequency =
fVCO/20 or 100 MHz, whichever is less.
4
External 1 kΩ pull-up resistor to 1.8 V.
5
Limited by the 1 kΩ pull-up resistor and NMOS RON.
6
10 pF load capacitor.
7
10 pF load capacitor, 1 kΩ pull-up resistor. In general, open-drain mode can support higher frequencies at the expense of maximum VOL. The maximum frequency for a
given pull-up resistor and load capacitor is approximately 1/(10 × RPULL-UP × CLOAD). For example, a 10 pF load capacitor and 1 kΩ pull-up resistor can support up to
10 MHz, where VOL maximum = VDD × RON/(1 kΩ + RON) ≈ 164 mV. With a 500 Ω pull-up resistance and a 10 pF load, a 20 MHz maximum frequency is possible, and the
maximum VOL increases to 300 mV.
8
1 kΩ pull-up resistor.
9
The minimum resistive load to ground in CMOS mode is 1 kΩ.
10
The LD/SDO pin does not have short-circuit protection. The maximum current of 7.2 mA must not be exceeded under any condition.
11
CLOAD in pF. CLOAD maximum = 20 pF.
12
For detailed current consumption information, refer to Figure 33 and Figure 36.
13
Gain setting = 6 (VCO_REG 0x07[3:0] = 6d) in high performance mode (VCO_REG 0x03[1:0] = 3d).
14
Pushing refers to a change in VCO frequency due to a change in the power supply voltage.
TIMING SPECIFICATIONS
SPI Write Timing Characteristics
AVDD = DVDD = 3 V, exposed pad (EP) = 0 V. See Figure 47.
Table 2.
t1 SDI setup time to SCK rising edge 3 ns
t2 SCK rising edge to SDI hold time 3 ns
t3 SEN low duration 10 ns
t4 SEN high duration 10 ns
t5 SCK 32nd rising edge to SEN rising edge 10 ns
t6 Recovery time 20 ns
fSCK Maximum serial port clock speed 50 MHz
SPI Read Timing Characteristics
AVDD = DVDD = 3 V, exposed pad (EP) = 0 V. See Figure 48.
Table 3.
t1 SDI setup time to SCK rising edge 3 ns
t2 SCK rising edge to SDI hold time 3 ns
t3 SEN low duration 10 ns
t4 SEN high duration 10 ns
t51 SCK rising edge to SDO time 8.2 ns + 0.2 ns/pF ns
t6 Recovery time 10 ns
t7 SCK 32nd rising edge to SEN rising edge 10 ns
1
An extra 0.2 ns delay is required for every 1 pF load on SDO.
Data Sheet HMC832A
ABSOLUTE MAXIMUM RATINGS

RECOMMENDED OPERATING CONDITIONS
Table 4.
Parameter Rating Table 5. Recommended Operating Conditions
AVDD, RVDD, DVDD, VCCPD, VCCHF, VCCPS −0.3 V to +3.6 V Parameter Min Typ Max Unit
VPPCP, VDDLS, VCC1 −0.3 V to +3.6 V Temperature
VCC2 −0.3 V to +3.6 V Junction Temperature1 125 °C
Operating Temperature Range −40°C to +85°C Ambient Temperature −40 +85 °C
Storage Temperature Range −65°C to +150°C Supply Voltage
Maximum Junction Temperature 150°C AVDD, RVDD, DVDD, VCCPD, 3.1 3.3 3.5 V
Thermal Resistance (θJC) (Junction to Case, EP) 9°C/W VCCHF, VCCPS, VPPCP, VDDLS,
Reflow Soldering VCC1, VCC2
Peak Temperature 260°C 1
Using the layout design guidelines set out in the Qualification Test Report is
Time at Peak Temperature 40 sec strongly recommended.
ESD Sensitivity, Human Body Model (HBM) Class 1B
Stresses at or above those listed under Absolute Maximum ESD CAUTION
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
HMC832A Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
LD/SDO
VCCPD
VCCPS
VCCHF
BIAS
SCK
NIC
NIC
NIC
SDI
40
39
38
37
36
35
34
33
32
31
AVDD 1 30 SEN
NIC 2 29 RF_P
VPPCP 3 28 RF_N
CP 4 27 VCC1
NIC 5 HMC832A 26 NIC
NIC 6 TOP VIEW 25 VCC2
VDDLS 7 (Not to Scale) 24 NIC
NIC 8 23 VTUNE
NIC 9 22 NIC
RVDD 10 21 NIC
11
12
13
14
15
16
17
18
19
20
XREFP
NIC
NIC
NIC
NIC
NIC
NIC
NIC
CEN
DVDD
NOTES
1. NIC = NOT INTERNALLY CONNECTED.
13110-002
2. THE EXPOSED GROUND PAD MUST BE
CONNECTED TO RF/DC GROUND.
Figure 2. Pin Configuration
Table 6. Pin Function Descriptions

Pin Number Mnemonic Description
1 AVDD DC Power Supply for Analog Circuitry.
2, 5, 6, 8, 9, 11 to NIC Not Internally Connected. These pins are not connected internally; however, it is recommended to
14, 18 to 22, 24, 26, connect these pins to RF/dc ground externally.
34, 37, 38
3 VPPCP Power Supply for the Charge Pump Analog Section.
4 CP Charge Pump Output.
7 VDDLS Power Supply for the Charge Pump Digital Section.
10 RVDD Reference Supply.
15 XREFP Reference Oscillator Input.
16 DVDD DC Power Supply for Digital (CMOS) Circuitry.
17 CEN PLL Subsystem Enable. Note that CEN has no effect on the VCO subsystem. Connect CEN to logic high
for normal operation.
23 VTUNE VCO Varactor. VTUNE is the tuning port input.
25 VCC2 VCO Analog Supply 2.
27 VCC1 VCO Analog Supply 1.
28 RF_N RF Negative Output.
29 RF_P RF Positive Output.
30 SEN PLL Serial Port Enable (CMOS) Logic Input.
31 SDI PLL Serial Port Data (CMOS) Logic Input.
32 SCK PLL Serial Port Clock (CMOS) Logic Input.
33 LD/SDO Lock Detect/Serial Data Output. This pin can also function as a general-purpose (CMOS) logic output
(GPO). See the General-Purpose Output (GPO) section for more information. The drive voltage level on
this pin can be either 1.8 V or 3.3 V and is set via Register 0x0B[22].
35 VCCHF DC Power Supply for Analog Circuitry.
36 VCCPS DC Power Supply for Analog Prescaler.
39 VCCPD DC Power Supply for Phase Detector.
40 BIAS External Bypass Decoupling for Precision Bias Circuits. The 1.920 V ± 20 mV reference voltage (BIAS) is
generated internally and cannot drive an external load. It must be measured with a 10 GΩ meter, such
as the Agilent 34410A; a 10 MΩ digital voltage meter reads erroneously.
EP Exposed Pad. The exposed pad must be connected to RF/dc ground.
Data Sheet HMC832A
TYPICAL PERFORMANCE CHARACTERISTICS

–100 –100
–110 –110
LOOP BW = 75kHz
PHASE NOISE (dBc/Hz)

–120 –120
LOOP BW = 75kHz LOOP BW = 127kHz
–130 –130
LOOP BW = 127kHz
–140 –140
–150 –150
750MHz, EVM = –62.5dB, OR 0.075% 880MHz, EVM = –61.3dB OR 0.086%
1600MHz, EVM = –57dB OR 0.141% 1605MHz, EVM = –57.5dB OR 0.133%
–160 2500MHz, EVM = –53.3dB OR 0.216% –160 2505MHz, EVM = –52dB OR 0.251%
875MHz, EVM = –64.8dB OR 0.058% 880MHz, EVM = –61.8dB OR 0.081%
–170 –170
13110-003
13110-006
1k 10k 100k 1M 10M 100M 1k 10k 100k 1M 10M 100M
OFFSET (Hz) OFFSET (Hz)
Figure 3. Typical Closed-Loop Integer Phase Noise, 50 MHz PD Frequency, Output Figure 6. Typical Closed-Loop Fractional Phase Noise, 50 MHz PD Frequency,
Gain = 6 (VCO_REG 0x07[3:0] = 6d), High Performance Mode (VCO_REG 0x03[1:0] Output Gain = 6 (VCO_REG 0x07[3:0] = 6d), High Performance Mode
= 3d), Phase Noise Integrated from 1 kHz to 100 MHz, See Table 13 (VCO_REG 0x03[1:0] = 3d), Phase Noise Integrated from 1 kHz to 100 MHz,
See Table 13
–60 –100
–110 ÷1
–80
÷2
–120 ÷4
–100
÷8
–130
LOW CURRENT MODE ÷16
–120
(VCO_REG 0x03[10] = 1d)
–140 ÷32
÷62
–140
–150
–160
HIGH PERFORMANCE MODE –160
(VCO_REG 0x03[10] = 3d)
–180 –170
13110-004
13110-007
1k 10k 100k 1M 10M 100M 1k 10k 100k 1M 10M 100M
Figure 4. Open-Loop VCO Phase Noise at 1800 MHz Figure 7. Closed-Loop Phase Noise at 1800 MHz, Divided by 1 to 62, PD
Frequency, Loop Filter Bandwidth = 75 kHz (Type 2 from Table 13), High Perfor-
mance Mode (VCO_REG 0x03[1:0] = 3d), Subset of Available Output Divide Ratios
Shown; Full Range of Output Divide Values Includes 1, 2, 4, 6, 8, … 58, 60, 62
–40 –100
÷1
–60 –110 ÷2
÷4
–80 –120
÷8
–100 –130 ÷16
LOW CURRENT MODE ÷32

–120 (VCO_REG 0x03[10] = 1d)
–140 ÷62
–140 –150
–160 HIGH PERFORMANCE MODE –160

(VCO_REG 0x03[10] = 3d)
–180 –170
13110-005
13110-008
1k 10k 100k 1M 10M 100M 1k 10k 100k 1M 10M 100M

Figure 5. Free Running VCO Phase Noise at 3000 MHz Figure 8. Closed-Loop Phase Noise at 3000 MHz, Divided by 1 to 62, PD
Frequency, Loop Filter Bandwidth = 75 kHz (Type 2 from Table 13), High Perfor-
mance Mode (VCO_REG 0x03[1:0] = 3d), Subset of Available Output Divide Ratios
is Shown; Full Range of Output Divide Values Includes 1, 2, 4, 6, 8, … 58, 60, 62
HMC832A Data Sheet
–60 –60
–80 –80
LOW CURRENT MODE (VCO_REG 0x03[10] = 1d)
LOW CURRENT MODE (VCO_REG 0x03[10] = 1d) SSB INTEGRATED PHASE NOISE = –58.7dBc
SSB INTEGRATED PHASE NOISE = –64.3dBc INTEGRATION BANDWIDTH = 1kHz TO 100MHz

INTEGRATION BANDWIDTH = 1kHz TO 100MHz SNR = 55.7dB, EVM = 0.164%, PHASE NOISE
–100 SNR = 61.3dB, EVM = 0.086%, PHASE NOISE –100 INTEGRATION BANDWIDTH 1kHz TO 100MHz
INTEGRATION BANDWIDTH 1kHz TO 100MHz
–120 –120
–140 –140
–160 HIGH PERFORMANCE MODE (VCO_REG 0x03[10] = 3d) –160 HIGH PERFORMANCE MODE (VCO_REG 0x03[10] = 3d)
SSB INTEGRATED PHASE NOISE = –65.5dBc SSB INTEGRATED PHASE NOISE = –59dBc
INTEGRATION BANDWIDTH = 1kHz TO 100MHz INTEGRATION BANDWIDTH = 1kHz TO 100MHz
SNR = 62.5dB, EVM = 0.075% PHASE NOISE SNR = 56dB, EVM = 0.158%, PHASE NOISE
INTEGRATION BANDWIDTH 1kHz TO 100MHz INTEGRATION BANDWIDTH 1kHz TO 100MHz
–180 –180
13110-009
13110-012
1k 10k 100k 1M 10M 100M 1k 10k 100k 1M 10M 100M
Figure 9. Fractional Spurious Performance at 904 MHz, Exact Frequency Figure 12. Fractional Spurious Performance at 1804 MHz, Exact Frequency
Mode On, 122.88 MHz XTAL, PFD = 61.44 MHz, Channel Spacing = 200 kHz, Mode On, 122.88 MHz XTAL, PFD = 61.44 MHz, Channel Spacing = 200 kHz,
Loop Filter Type 2 (See Table 13) Loop Filter Type 2 (See Table 13)
–60 –60
SSB INTEGRATED PHASE NOISE = –57dBc
INTEGRATION BANDWIDTH = 1kHz TO 100MHz
–80 –80 LOW CURRENT MODE (VCO_REG 0x03[10] = 1d)
SNR = 54dB, EVM = 0.199%, PHASE NOISE SSB INTEGRATED PHASE NOISE = –57dBc
INTEGRATION BANDWIDTH 1kHz TO 100MHz INTEGRATION BANDWIDTH = 1kHz TO 100MHz
SNR = 54, EVM = 0.199%, PHASE NOISE

–100 –100
–120 –120
–140 –140
HIGH PERFORMANCE MODE (VCO_REG 0x03[10] = 3d)

–160 SSB INTEGRATED PHASE NOISE = –57.45dBc –160 HIGH PERFORMANCE MODE (VCO_REG 0x03[10] = 3d)
SSB INTEGRATED PHASE NOISE = –57.45dBc
INTEGRATION BANDWIDTH = 1kHz TO 100MHz INTEGRATION BANDWIDTH = 1kHz TO 100MHz
SNR = 54.45dB, EVM = 0.189%, PHASE NOISE SNR = 54.45dB, EVM = 0.189%, PHASE NOISE
–180 –180
13110-010
13110-013
1k 10k 100k 1M 10M 100M 1k 10k 100k 1M 10M 100M
Figure 10. Fractional Spurious Performance at 2118.24 MHz, Figure 13. Fractional Spurious Performance at 2118.24 MHz,
Exact Frequency Mode On, 122.88 MHz XTAL, PFD = 61.44 MHz, Identical Configuration to Figure 10 with Exact Frequency Mode Off
Channel Spacing = 240 kHz, Loop Filter Type 2 (See Table 13)
–60 –60

–80 SSB INTEGRATED PHASE NOISE = –55.6dBc –80
INTEGRATION BANDWIDTH = 1kHz TO 100MHz LOW CURRENT MODE (VCO_REG 0x03[10] = 1d)
SNR = 52.6dB, EVM = 0.234%, PHASE NOISE SSB INTEGRATED PHASE NOISE = –55.6dBc

SNR = 52.6dB, EVM = 0.234%, PHASE NOISE

–100 –100 INTEGRATION BANDWIDTH 1kHz TO 100MHz
–120 –120
–140 –140
HIGH PERFORMANCE MODE (VCO_REG 0x03[10] = 3d)

–160 SSB INTEGRATED PHASE NOISE = –56dBc –160 HIGH PERFORMANCE MODE (VCO_REG 0x03[10] = 3d)
INTEGRATION BANDWIDTH = 1kHz TO 100MHz SSB INTEGRATED PHASE NOISE = –56dBc
SNR = 53dB, EVM = 0.224%, PHASE NOISE SNR = 53dB, EVM = 0.224%, PHASE NOISE
–180 –180
13110-014
13110-011
1k 10k 100k 1M 10M 100M 1k 10k 100k 1M 10M 100M

Figure 11. Fractional Spurious Performance at 2646.96 MHz, Exact Frequency Figure 14. Fractional Spurious Performance at 2646.96 MHz,
Mode On, 122.88 MHz XTAL, PFD = 61.44 MHz, Channel Spacing = 240 kHz, Identical Configuration to Figure 11 with Exact Frequency Mode Off
Loop Filter Type 2 (See Table 13)
Data Sheet HMC832A
–120 –60
–80
–130

–100
–140 100MHz OUTPUT
–120
–150 55.55MHz OUTPUT

–140
–160
–160
25MHz OUTPUT
–170 –180
13110-018
13110-015
100 1k 10k 100k 1M 10M 100M 1k 10k 100k 1M 10M 100M
Figure 15. Low Frequency Performance, 100 MHz XTAL, PD Frequency = Figure 18. Typical Spurious Emissions at 2000.1 MHz, 50 MHz Fixed
50 MHz, Loop Filter Type 3 (See Table 13), Integer Mode, 50 MHz Low-Pass Reference, 50 MHz PD Frequency, Integer Boundary Spur Inside the Loop
Filter at the Output of HMC832A for the 25 MHz Curve Only, Charge Pump Set Filter Bandwidth (See the Loop Filter and Frequency Changes Section)
to Maximum Value
–60 –60
TYPICAL SPURIOUS vs. OFFSET FROM 2GHz,
FIXED REFERENCE = 50MHz
–80 –70

–100 –80
–120 –90
–140 –100
TYPICAL SPURIOUS vs. OFFSET FROM 2GHz,
TUNABLE REFERENCE ~47.5MHz
–160 –110
–180 –120
13110-019
13110-016
1k 10k 100k 1M 10M 100M 2000.01 2000.1 2001

OFFSET (Hz) OUTPUT FREQUENCY (kHz)
Figure 16. Typical Spurious Emissions at 2000.1 MHz, Tunable 47.5 MHz Figure 19. Typical Spurious vs. Offset from 2 GHz, Fixed 50 MHz Reference vs.
Reference, Loop Filter Type 2 (see Table 13 and the Loop Filter and Frequency Tunable 47.5 MHz Reference (See the Loop Filter and Frequency Changes
Changes Section) Section)
–40 –100
HIGH PERFORMANCE MODE ON –40°C
+27°C
(VCO_REG 0x03[1:0] = 3d) 100kHz OFFSET +85°C
–60 –110 ALL MODES
1MHz OFFSET
ALL MODES
–80 –120 100MHz OFFSET

LOW CURRENT MODE
100MHz OFFSET
–100 –130 HIGH PERFORMANCE
MODE
–120 –140
–140 –150
2854MHz –160
–160 2453MHz
2013MHz
1587MHz
–180 –170
13110-020
13110-017
1k 10k 100k 1M 10M 100M 30 100 300 1000 3000

OFFSET (Hz) FREQUENCY (MHz)
Figure 17. Open-Loop Phase Noise Figure 20. Open-Loop Phase Noise vs. Frequency at Various Temperatures
HMC832A Data Sheet
–50 0.4460 –200
–40°C
+27°C
+85°C
ERROR VECTOR MAGNITUDE (EVM) (%)

SSB INTEGRATED PHASE NOISE (dBc)
–55
NORMALIZED PHASE NOISE (dBc/Hz)

–60 0.1410 –210
–65
TYP FOM vs. OFFSET
–70 0.0447 –220
FOM FLOOR
–75 FOM 1/f NOISE
–80 0.0141 –230
–85
PHASE NOISE INTEGRATED FROM 10kHz TO 20MHz

–90 0.0045 –240
13110-024
13110-021
100 1000 100 1k 10k 100k 1M
OUTPUT FREQUENCY (MHz) OFFSET (Hz)
Figure 21. Single Sideband (SSB) Integrated Phase Noise, High Performance Figure 24. Figure of Merit (FOM)
Mode, Loop Filter Type 2 (See Table 13)
15 20
RETURN LOSS (VCO_REG 0x03[5] = 0)
RETURN LOSS (VCO_REG 0x03[5] = 1)
15
10
HIGH PERFORMANCE MODE GAIN SETTING = 11
(VCO_REG 0x03[1:0] = 3d) 10 (VCO_REG 0x07[3:0] = 11d)
OUTPUT POWER (dBm)
OUTPUT POWER (dBm)
5
5 GAIN SETTING = 5
(VCO_REG 0x07[3:0] = 5d)
0 0 GAIN SETTING = 0
(VCO_REG 0x07[3:0] = 0d)
–5
–5
LOW CURRENT MODE
(VCO_REG 0x03[1:0] = 1d) –10
–10
–15
HIGH PERFORMANCE MODE
PHASE NOISE INTEGRATED FROM 10kHz TO 20MHz LOW CURRENT MODE
–15 –20
13110-025
13110-022
25 100 1000 3000 25 100 1000 3000

FREQUENCY (MHz) FREQUENCY (MHz)
Figure 22. Typical Single-Ended Output Power vs. Frequency Figure 25. Typical Output Power vs. Frequency and Gain (Single-Ended)
(Mid Gain Setting 6 (VCO_REG 0x07[3:0] = 6d))
10 0
–40°C
+27°C
8 +85°C RETURN LOSS 0 (VCO_REG 0x03[5] = 0)
–5
6 RETURN LOSS 1 (VCO_REG 0x03[5] = 1)
OUTPUT POWER (dBm)
RETURN LOSS (dB)
–10
4
2 –15
0
–20
–2
–25
–4
–6 –30
13110-023
13110-026
0 2 4 6 8 10 25 100 1000 8000

GAIN SETTING OUTPUT FREQUENCY (MHz)
Figure 23. Typical RF Output Power at 2 GHz (Single-Ended) vs. Temperature Figure 26. RF Output Return Loss
Data Sheet HMC832A
3.2 200
SETTLING TIME TO <10°
PHASE ERROR SETTLING TIME TO <10°
150 PHASE ERROR
3.0
100
PHASE ERROR (Degrees)

FREQUENCY (GHz)
50
2.8
2.6
–50
–100
2.4
–150
2.2 –200
13110-030
13110-027
0 20 40 60 80 100 120 140 160 0 20 40 60 80 100 120 140 160
TIME (µs) TIME (µs)
Figure 27. Frequency Settling After Frequency Change, Autocalibration Figure 30. Phase Settling After Frequency Change, Autocalibration Enabled,
Enabled, Loop Filter Bandwidth = 127 kHz (Type 1, See Table 13) Loop Filter Bandwidth = 127 kHz (Type 1, See Table 13)
2.510 200

150 PHASE ERROR

PHASE ERROR 100
PHASE ERROR (Degrees)

FREQUENCY (GHz)
2.505
50
–50
2.500
–100
NOTE: LOOP FILTER BANDWIDTH = 127kHz, LOOP NOTE: LOOP FILTER BANDWIDTH = 127kHz,
LOOP FILTER PHASE MARGIN = 61°.
FILTER PHASE MARGIN = 61°. THIS RESULT IS DIRECTLY THIS RESULT IS DIRECTLY AFFECTED B Y LOOP
AFFECTED BY LOOP FILTER DESIGN. FASTER SETTLING –150 FILTER DESIGN. FASTER SETTLING TIME IS
TIME IS POSSIBLE WITH WIDER LOOP FILTER POSSIBLE WITH WIDER LOOP FILTER
BANDWIDTH AND LOWER PHASE MARGIN. BANDWIDTH AND LOWER PHASE MARGIN.
2.495 –200
13110-031
13110-028
0 20 40 60 80 100 120 140 160 0 20 40 60 80 100 120 140 160

TIME (µs) TIME (µs)
Figure 28. Frequency Settling After Frequency Change, Manual Calibration, Figure 31. Phase Settling After Frequency Change, Manual Calibration
Loop Filter Bandwidth = 127 kHz (Type 1 in Table 13)
90 4.0
VCO_REG 0x00[5:1] = 15d 2854MHz
TUNING VOLTAGE AFTER CALIBRATION (V)
2453MHz
80 2013MHz 3.5
1587MHz CALIBRATED AT +85°C, MEASURED AT +85°C
CALIBRATED AT +85°C, MEASURED AT –40°C
CALIBRATED AT –40°C, MEASURED AT –40°C
70 3.0 CALIBRATED AT –40°C, MEASURED AT +85°C
CALIBRATED AT +27°C, MEASURED AT +27°C
60 2.5
kVCO (MHz/V)
50 2.0
40 1.5
30 1.0
20 0.5
fMIN fMAX
10 0
13110-029
13110-032
0 0.66 1.30 2.00 2.60 3.30 1330 1520 1710 1900 2090 2280 2470 2660 2850 3040
TUNING VOLTAGE (V) VCO FREQUENCY (MHz)
Figure 29. Typical VCO Sensitivity (kVCO) Figure 32. Typical Tuning Voltage After Calibration (See the Loop Filter and
Frequency Changes Section)
HMC832A Data Sheet
240 260
fO/62 OUTPUT GAIN 0dB fO/62 OUTPUT GAIN 0dB
OUTPUT GAIN 6dB OUTPUT GAIN 6dB
230 fO/4 fO/4
fO/2
CURRENT CONSUMPTION (mA)

CURRENT CONSUMPTION (mA)
240 fO/2
220
fO HIGH PERFORMANCE MODE
(VCO_REG 0x03[1:0] = 3d) fO
210
220 HIGH PERFORMANCE MODE
200 (VCO_REG 0x03[1:0] = 3d)
190 LOW CURRENT

CONSUMPTION MODE 200
(VCO_REG 0x03[1:0] = 1d)
180 LOW CURRENT
CONSUMPTION MODE
(VCO_REG 0x03[1:0] = 1d)
170
180
160
13110-036
13110-033
0 500 1000 1500 2000 2500 3000 0 500 1000 1500 2000 2500 3000
OUTPUT FREQUENCY (MHz) OUTPUT FREQUENCY (MHz)
Figure 33. Current Consumption in Single-Ended Output Configuration, Figure 36. Current Consumption in Differential Output Configuration,
Output Gain Configured in VCO_REG 0x07[3:0], Differential or Single-Ended Output Gain Configured in VCO_REG 0x07[3:0], Differential or Single-Ended
Mode Programmed in VCO_REG 0x03[3:2] Mode Programmed in VCO_REG 0x03[3:2]
232 235
14MHz SINUSOIDAL
25MHz SINUSOIDAL
230 50MHz SQUARE
230 100MHz SQUARE
225
228
FOM (dBc/Hz)
FOM (dBc/Hz)
220
226
215
224
210
222 14MHz SQUARE WAVE 205

25MHz SQUARE WAVE
50MHz SQUARE WAVE
100MHz SQUARE WAVE
220 200
13110-038
13110-034
–15 –12 –9 –6 –3 0 3 –20 –15 –10 –5 0 5

REFERENCE POWER (dBm) REFERENCE POWER (dBm)
Figure 34. Reference Input Sensitivity, Square Wave, Measured from a 50 Ω Figure 37. Reference Input Sensitivity, Sinusoidal Wave, Measured from a
Source with a 100 Ω External Resistor Termination 50 Ω Source with a 100 Ω External Resistor Termination
–10
SIGNAL ON RF_N PIN WHEN RF_N PIN OFF,
RF_P PIN ON (VCO_REG 0x03[3:2] = 1d),
MUTE OFF (ON ONLY DURING VCO
–30 CALIBRATION VCO_REG 0x03[8:7] = 1d)
ISOLATION (dB)
–50
BOTH RF_N AND RF_P PINS OFF,
(VCO_REG 0x03[3:2] = 0d),
MUTE OFF (ON ONLY DURING VCO
CALIBRATION VCO_REG 0x03[8:7] = 1d)
–70
–90
MUTE ON (VCO_REG 0x03[8:7] = 3d)
–110
13110-035
100 1000 3000

FRQUENCY (MHz)
Figure 35. Mute Mode Isolation, Measured at Output
Data Sheet HMC832A
THEORY OF OPERATION
SEN
SDI 4
CONTROL REF BUFF
SCK RF BUFFER EN
RF_N
LD/SDO RF_P
3 VSPI
CHARGE MODULATOR CAL VSPI CNTRL
CP fO OR ÷N OR ×2
PUMP
PLL BUFF EN
CAL VCO EN
N
PHASE DIVIDER
FREQUENCY
DETECTOP
R PLL BUFF
XREFP DIVIDER
VTUNE
CEN PLL ONLY
13110-043
Figure 38. PLL and VCO Subsystems
The HMC832A PLL with integrated VCO is composed of two VCO SUBSYSTEM OVERVIEW
subsystems: PLL subsystem and VCO subsystem, as shown in The VCO subsystem consists of a capacitor switched step tuned
Figure 38. VCO and an output stage. In typical operation, the VCO
PLL SUBSYSTEM OVERVIEW subsystem is programmed with the appropriate capacitor switch
The PLL subsystem divides down the VCO output to the desired setting that is executed automatically by the PLL subsystem
comparison frequency via the N-divider (integer value set in autocalibration state machine when autocalibration is enabled
Register 0x03, fractional value set in Register 0x04), compares (Register 0x0A[11] = 0; see the VCO Calibration section for
the divided VCO signal to the divided reference signal more information). The VCO tunes to the fundamental
(reference divider set in Register 0x02) in the phase detector frequency (1500 MHz to 3000 MHz), and is locked by the CP
(PD), and drives the VCO tuning voltage via the charge pump output from the PLL subsystem. The VCO subsystem controls
(CP) (configured in Register 0x09) to the VCO subsystem. the output stage of the HMC832A, enabling configuration of
Some of the additional PLL subsystem functions include  User defined performance settings (see the Programmable
Performance Technology section) that are configured via
 Σ-Δ configuration (Register 0x06). VCO_REG 0x03[1:0].
 Exact frequency mode (configured in Register 0x0C,  VCO output divider settings that are configured in
Register 0x03, and Register 0x04). VCO_REG 0x02 (divide by 2 to 62 to generate frequencies
 Lock detect (LD) configuration (use Register 0x07 to from 25 MHz to 1500 MHz, or divide by 1 to generate
configure LD and Register 0x0F to configure the LD/SDO fundamental frequencies between 1500 MHz and
output pin). 3000 MHz).
 External CEN pin used for the hardware PLL enable pin.  Output gain settings (VCO_REG 0x07[3:0]).
The CEN pin does not affect the VCO subsystem.  Output return loss setting (VCO_REG 0x03[5]). See
Typically, only writes to the divider registers (integer part uses Figure 26 for more information.
Register 0x03, fractional part uses Register 0x04) of the PLL  Single-ended or differential output operation
subsystem are required for HMC832A output frequency (VCO_REG 0x03[3:2]).
changes.  Mute (VCO_REG 0x03[8:7]).
The divider registers of the PLL subsystem (Register 0x03 and SPI CONFIGURATION OF PLL AND VCO
Register 0x04) set the fundamental frequency (1500 MHz to SUBSYSTEMS
3000 MHz) of the VCO subsystem. Output frequencies ranging
The two subsystems (PLL subsystem and VCO subsystem) have
from 25 MHz to 1500 MHz are generated by tuning to the
their own register maps as shown in the PLL Register Map and
appropriate fundamental VCO frequency (1500 MHz to
VCO Subsystem Register Map sections. Typically, writes to both
3000 MHz) by programming the N divider (Register 0x03 and
register maps are required for initialization and frequency
Register 0x04) and programming the output divider (divide by
tuning operations.
1 to 62, in VCO_REG 0x02) in the VCO subsystem.
As shown in Figure 38, the PLL subsystem is connected directly
For detailed frequency tuning information and an example, see
to the SPI of the HMC832A, whereas the VCO subsystem is
the Frequency Tuning section.
connected indirectly through the PLL subsystem to the
HMC832A Data Sheet
HMC832A SPI. As a result, writes to the PLL register map are Register 0x05[6:3], respectively. Autocalibration requires that
written directly and immediately, whereas the writes to the VCO these values be zero (Register 0x05[6:0] = 0); otherwise, when
subsystem register map are written to the PLL Register 0x05 they are not zero (Register 0x05[6:0] ≠ 0), autocalibration does
and forwarded via the internal VCO SPI (VSPI) to the VCO not function.
subsystem. This is a form of indirect addressing. To ensure that the autocalibration functions, it is critical to
VCO subsystem registers are write only and cannot be read. For write Register 0x05[6:0] = 0 after the last VCO subsystem write
more information, see the VCO Serial Port Interface (VSPI) but prior to an output frequency change that is triggered by a
section. write to either Register 0x03 or Register 0x04.
VCO Serial Port Interface (VSPI) However, it is impossible to write only Register 0x05[6:0] = 0
The HMC832A communicates with the internal VCO (VCO_ID and VCO_REGADDR) without writing VCO_DATA
subsystem via an internal 16-bit VCO SPI. The internal serial (Register 0x05[15:7]). Therefore, to ensure that VCO_DATA
port controls the step tuned VCO and other VCO subsystem (Register 0x05[15:7]) is not changed, it is required to read the
functions. switch settings provided in Register 0x10[7:0], and then rewrite
them to Register 0x05[15:7], as follows:
The internal VSPI runs at the rate of the autocalibration finite
state machine (FSM) clock, tFSM (see the VCO Autocalibration 1. Read Register 0x10.
section), where the FSM clock frequency cannot be greater than 2. Write to Register 0x05[15:14] = Register 0x10[7:6];
50 MHz. The VSPI clock rate is set by Register 0x0A[14:13]. Register 0x05[13] = 1 (reserved bit); Register 0x05[12:8] =
Register 0x10[4:0]; and Register 0x05[7:0] = 0.
Writes to the control registers of the VCO are handled indi-
rectly via writes to Register 0x05 of the HMC832A. A write to Changing the VCO subsystem configuration (see the VCO
Register 0x05 causes the internal PLL subsystem to forward the Subsystem Register Map section) without following this
packet, MSB first, across its internal serial link to the VCO procedure results in a failure to lock to the desired frequency.
subsystem, where it is interpreted. For applications not using the read functionality of the
VSPI Use of Register 0x05 HMC832A SPI, in which Register 0x10 cannot be read, it is
possible to write Register 0x05 = 0x0 to set Register 0x05[6:0] =
The packet data written into Register 0x05 is subparsed by logic
0, which also sets the VCO subband setting equal to zero
at the VCO subsystem into the following three fields:
(Register 0x05[15:7] = 0), effectively programming incorrect
Field 1—Bits[2:0]: 3-bit VCO_ID, target subsystem address = VCO subband settings and causing the HMC832A to lose lock.
000b. This procedure is then immediately followed by a write to
Field 2—Bits[6:3]: 4-bit VCO_REGADDR, the internal register • Register 0x03, if in integer mode
address inside the VCO subsystem. • Register 0x04, if in fractional mode
Field 3—Bits[15:7]: 9-bit VCO_DATA, the data field to write to
This write effectively retriggers the autocalibration state
the VCO register.
machine, forcing the HMC832A to relock whether in integer or
For example, to write 0 1111 1110 into Register 2 of the VCO fractional mode.
subsystem (VCO_ID = 000b), and set the VCO output divider
This procedure causes the HMC832A to lose lock and relock
to divide by 62, the following must be written to Register 0x05 =
after every VCO subsystem change. Typical output frequency
0 1111 1110b, 0010b, 000b or, equivalently, Register 0x05 =
and lock time is shown in Figure 27 and Figure 30, respectively.
0x7F10.
Lock time is typically in the order of 100 μs for a phase settling
During autocalibration, the autocalibration controller writes of 10°, and is dependent on loop filter design (loop filter band-
into the VCO register address specified by the VCO_ID width and loop filter phase margin).
and VCO_REGADDR, as stored in Register 0x05[2:0] and
Data Sheet HMC832A
VCO SUBSYSTEM
SPI
(SEN, SDI, SCK)
LD/SDO
VCO_REG 0x03[1:0] VCO SUBSYSTEM

VCO_REG 0x01[0]
PERFORMANCE VDD
MASTER ENABLE TUNING
VCO SUBSYSTEM
VCO_REG 0x01[5]
VSPI EN VCO_REG 0x03[3]
VCO
CONTROL
RF_P
÷1, ÷2, ÷4, ÷6, ... ÷62

VCO_REG 0x01[3]
EN RF_N
VCO_REG 0x02[5:0] VCO_REG 0x03[2]
CONTROL CAL
VCO_REG 0x07[3:0]
MODULATOR VCO_REG 0x01[2]

EN
VCO
N VTUNE
DIVIDER
VCO_REG 0x01[1], EN
VCO CAL VCO_REG 0x00[0]
VCO_REG 0x00[8:1] VOLTAGE
PHASE CP LOOP
FREQUENCY CHARGE
XREFP R PUMP FILTER
DETECTOR
13110-044
DIVIDER
Figure 39. PLL and VCO Subsystems
SCK VSCK DTUNE

VCO
SUBBAND
SDI VSDO VCO SELECT
HOST VSPI
SEN VSLE
SYNTHESIZER
CP LOOP VTUNE
FILTER
VCO INPUT
RFOUT
VCO
13110-045
Figure 40. Simplified Step Tuned VCO
The HMC832A contains a VCO subsystem that can be VCO Calibration

configured to operate in VCO Autocalibration
• Fundamental frequency (fo) mode (1500 MHz to The HMC832A uses a step tuned type VCO. A simplified step
3000 MHz). tuned VCO is shown in Figure 40. A step tuned VCO is a VCO
• Divide by N mode, where N = 2, 4, 6, 8 … 58, 60, 62 with a digitally selectable capacitor bank allowing the nominal
(25 MHz to 1500 MHz). center frequency of the VCO to be adjusted or stepped by
All modes are VCO register programmable, as shown in switching in and out of the VCO tank capacitors. More than
Figure 39. One loop filter design can be used for the entire one capacitor can be switched in at a time.
frequency of operation of the HMC832A.
A step tuned VCO allows the user to center the VCO on the
required output frequency while keeping the varactor tuning
voltage optimized near the midvoltage tuning point of the
HMC832A Data Sheet
HMC832A charge pump. This enables the PLL charge pump to Autocalibration can also be disabled, thereby allowing manual
tune the VCO over the full range of operation with both a low VCO tuning. Refer to the Manual VCO Calibration for Fast
tuning voltage and a low tuning sensitivity (kVCO). Frequency Hopping section for more information about manual
The VCO switches are normally controlled automatically by the tuning.
HMC832A using the autocalibration feature. The autocalibration Autocalibration Using Register 0x05
feature is implemented in the internal state machine. It manages Autocalibration transfers switch control data to the VCO
the selection of the VCO subband (capacitor selection) when a subsystem via Register 0x05. The address of the VCO subsystem
new frequency is programmed. The VCO switches can also be in Register 0x05 is not altered by the autocalibration routine.
controlled directly via Register 0x05 for testing or for special The address and ID of the VCO subsystem in Register 0x05
purpose operations. Other control bits specific to the VCO are must be set to the correct value before autocalibration is
also sent via Register 0x05. executed. For more information, see the VCO Serial Port
To use a step tuned VCO in a closed loop, the VCO must be Interface (VSPI) section.
calibrated such that the HMC832A knows which switch
Automatic Relock on Lock Detect Failure
position on the VCO is optimum for the desired output
frequency. The HMC832A supports autocalibration of the step It is possible, by setting Register 0x07[13], to have the VCO subsys-
tuned VCO. The autocalibration fixes the VCO tuning voltage tem automatically rerun the calibration routine and relock itself
at the optimum midpoint of the charge pump output, then if the lock detect indicates an unlocked condition for any reason.
measures the free running VCO frequency while searching for With this option, the system attempts to relock only once.
the setting, which results in the free running output frequency VCO Autocalibration on Frequency Change
that is closest to the desired phase-locked frequency. This
Assuming Register 0x0A[11] = 0, the VCO calibration starts
procedure results in a phase-locked oscillator that locks over a
automatically whenever a frequency change is requested. To
narrow voltage range on the varactor. A typical tuning curve for
rerun the autocalibration routine for any reason at the same
a step tuned VCO is shown in Figure 41. Note that the tuning
frequency, rewrite the frequency change with the same value,
voltage stays in a narrow range over a wide range of output
and the autocalibration routine executes again without
frequencies.
changing the final frequency.
4.0
VCO Autocalibration Time and Accuracy
TUNING VOLTAGE AFTER CALIBRATION (V)
CALIBRATED AT +85°C, MEASURED AT +85°C

3.5 CALIBRATED AT +85°C, MEASURED AT –40°C
CALIBRATED AT –40°C, MEASURED AT –40°C
CALIBRATED AT –40°C, MEASURED AT +85°C
The VCO frequency is counted for tMMT, the period of a single
3.0 CALIBRATED AT +27°C, MEASURED AT +27°C autocalibration measurement cycle.
2.5 tMMT = tXTAL × R × 2n (1)
2.0 where:
tXTAL is the period of the external reference (crystal) oscillator.
1.5
R is the reference path division ratio currently in use, set in
1.0 Register 0x02.
n is set by Register 0x0A[2:0] and results in measurement
0.5
fMIN fMAX periods that are multiples of the PD period, tXTAL × R.
0
The VCO autocalibration counter, on average, expects to register
13110-046
1330 1520 1710 1900 2090 2280 2470 2660 2850 3040
VCO FREQUENCY (MHz) N counts, rounded down (floor) to the nearest integer, for every
Figure 41. Typical VCO Tuning Voltage After Calibration PD cycle.
The calibration is normally run automatically, once for every N is the ratio of the target VCO frequency, fVCO, to the frequency of
change of frequency. This autocalibration ensures optimum the PD, fPD, where N can be any rational number supported by
selection of VCO switch settings vs. time and temperature. The the N divider.
user does not normally need to be concerned about which N is set by the integer and fractional register contents using
switch setting is used for a given frequency because this is Equation 2.
handled by the autocalibration routine.
N = NINT + NFRAC/224 (2)
The accuracy required in the calibration affects the amount of
where:
time required to tune the VCO. The calibration routine searches
NINT is the integer set in Register 0x03.
for the best step setting that locks the VCO at the current
NFRAC is the fractional part set in Register 0x04.
programmed frequency and ensures that the VCO stays locked
and performs well over its full temperature range without
additional calibration, regardless of the temperature at which
the VCO was calibrated.
Data Sheet HMC832A
The autocalibration state machine and the data transfers to the VCO Autocalibration Example
internal VCO VSPI run at the rate of the FSM clock, tFSM, where The VCO subsystem must satisfy the maximum fPD limited by
the FSM clock frequency cannot be greater than 50 MHz. the two following conditions:
tFSM = tXTAL × 2m (3) N ≥ 16 (fINT), N ≥ 20.0 (fFRAC)
where m is 0, 2, 4, or 5 as determined by Register 0x0A[14:13]. where:
The expected number of VCO counts, V, is given by N = fVCO/fPD. fPD ≤ 100 MHz.
V = floor (N × 2n) (4) fINT is integer mode.
fFRAC is fractional-N mode. The minimum N values changes
The nominal VCO frequency measured, fVCOM, is given by
depending on the operating mode.
fVCOM = V × fXTAL/(2n × R) (5)
For example, if the VCO subsystem output frequency is to
where the worst case measurement error, fERR, is operate at 2.01 GHz and the crystal frequency is fXTAL = 50 MHz,
fERR ≈ ±fPD/2n + 1 (6) R = 1, and m = 0 (see Figure 42), then tFSM = 20 ns (50 MHz).
A 5-bit step tuned VCO, for example, nominally requires five When using autocalibration, the maximum autocalibration
measurements for calibration or in the worst case, six measure- FSM clock cannot exceed 50 MHz (see Register 0x0A[14:13]).
ments, and therefore, seven VSPI data transfers of 20 clock cycles The FSM clock does not affect the accuracy of the measure-
each. The measurement has a programmable number of wait ment; it only affects the time to produce the result. This same
states, k, of 128 FSM cycles defined by Register 0x0A[7:6] = k. clock clocks the 16-bit VCO serial port.
Total calibration time, worst case, is given by If the time to change frequencies is not a concern, the
n
tCAL = k128 tFSM + 6tPD 2 + 7 × 20 tFSM (7) calibration time for maximum accuracy can be set and,
therefore, the measurement resolution is of no concern.
or equivalently
Using an input crystal of 50 MHz (R = 1 and fPD = 50 MHz), the
tCAL = tXTAL (6R × 2n + (140 + (k × 128)) × 2m) (8)
times and accuracies for calibration using Equation 6 and
For guaranteed hold of lock, across temperature extremes, the Equation 8 are listed in Table 7, where minimal tuning time is
resolution must be better than 1/8th of the frequency step caused 1/8th of the VCO band spacing.
by a VCO subband switch change. Better resolution settings
show no improvement.
tPD
CALIBRATION WINDOW
REG 0x02
XREF tMMT = tXTAL × R × 2n
÷R ÷ 2n
START STOP
REG 0x0A[14:13] ÷ 2m REG 0x0A[2:0]
m = [0, 2, 4, 5] n = [0, 1, 2, 3, 5, 6, 7, 8]
50MHz MAX FOR

FSM + VSPI CLOCKS V
13110-047
VCO CTR
FSM
Figure 42. VCO Calibration
Table 7. Autocalibration Example with fXTAL = 50 MHz, R = 1, m = 0

Control Value Register 0x0A[2:0] n 2n tMMT (µs) tCAL (µs) fERR Maximum
0 0 1 0.02 4.92 ±25 MHz
1 1 2 0.04 5.04 ±12.5 MHz
2 2 4 0.08 5.28 ±6.25 MHz
3 3 8 0.16 5.76 ±3.125 MHz
4 5 32 0.64 8.64 ±781 kHz
5 6 64 1.28 12.48 ±390 kHz
6 7 128 2.56 20.16 ±95 kHz
7 8 256 5.12 35.52 ±98 kHz
HMC832A Data Sheet
Across all VCOs, a measurement resolution better than 800 kHz Register 0x0A[11] = 1, the fractional frequency change is
produces correct results. Setting m = 0 and n = 5 provides loaded immediately into the modulator when the register is
781 kHz of resolution and adds 8.6 μs of autocalibration time to written with no adjustment to the VCO.
a normal frequency hop. After the autocalibration sets the final
Small steps in frequency in fractional mode, with autocalibration
switch value, 8.64 μs after the frequency change command, the
enabled (Register 0x0A[11] = 0), usually require only a single
fractional register is loaded, and the loop locks with a normal
write to the fractional register. In a worst case scenario, three
transient predicted by the loop dynamics. Therefore, as shown
main serial port transfers to the HMC832A may be required to
in this example, autocalibration typically adds about 8.6 μs to
change frequencies in fractional mode. If the frequency step is
the normal time to achieve frequency lock. Use autocalibration
small and the integer part of the frequency does not change, the
for all but the most extreme frequency hopping requirements.
integer register is not changed. In all cases, in fractional mode,
Manual VCO Calibration for Fast Frequency Hopping it is necessary to write to the fractional register, Register 0x04,
When switching frequencies quickly is needed, it is possible to for frequency changes.
eliminate the autocalibration time by calibrating the VCO in Registers Required for Frequency Changes in Integer
advance and storing the switch number vs. frequency infor- Mode
mation in the host, which is accomplished by initially locking In integer mode (Register 0x06[11] = 0), a change of frequency
the HMC832A on each desired frequency using autocalibration, requires main serial port writes to the following registers:
then reading and storing the selected VCO switch settings. The
VCO switch settings are available in Register 0x10[7:0] after • VCO SPI register, Register 0x05. This write is required only
every autocalibration operation. The host must then program for manual control of the VCO when Register 0x0A[11] = 1
the VCO switch settings directly when changing frequencies. (autocalibration disabled) or when the VCO output divider
value must change (VCO_REG 0x02).
Manual writes to the VCO switches are executed immediately as
• Integer register, Register 0x03. In integer mode, an
are writes to the integer and fractional registers when autocalibra-
integer register write triggers autocalibration when
tion is disabled. Therefore, frequency changes with manual
Register 0x0A[11] = 0 and it is loaded into the prescaler
control and autocalibration disabled requires a minimum of two
automatically after autocalibration runs. If autocalibration
serial port transfers to the PLL, once to set the VCO switches
is disabled, Register 0x0A[11] = 1, the integer frequency
and once to set the PLL frequency.
change is loaded into the prescaler immediately when
When autocalibration is disabled (Register 0x0A[11] = 1), the written with no adjustment to the VCO. Normally, changes
VCO updates its registers immediately with the value written to the integer register cause large steps in the VCO
via Register 0x05. The VCO internal transfer requires 16 VSCK frequency; therefore, the VCO switch settings must be
clock cycles after the completion of a write to Register 0x05. adjusted. Autocalibration enabled is the recommended
VSCK and the autocalibration controller clock are equal to the method for integer mode frequency changes. If auto-
input reference divided by 0, 4, 16, or 32 as controlled by calibration is disabled (Register 0x0A[11] = 1), a prior
Register 0x0A[14:13]. knowledge of the correct VCO switch setting and the
For settling time requirements faster than 1 ms, contact Analog corresponding adjustment to the VCO is required before
Devices, Inc., applications support. Settling times under 100 µs executing the integer frequency change.
are possible but certain conditions on performance do exist. VCO Output Mute Function
Registers Required for Frequency Changes in Fractional The HMC832A features an intelligent output mute function
Mode with the capability to disable the VCO output while maintaining
In fractional mode (Register 0x06[11] = 1), a large change of fully functional PLL and VCO subsystems. The mute function is
frequency may require main serial port writes to one of the automatically controlled by the HMC832A and provides a
three following registers: variety of mute control options including
• The integer register, Register 0x03. This write is required • Automatic mute. This option automatically mutes the
only if the integer part changes. outputs during VCO calibration during output frequency
• The VCO SPI register, Register 0x05. This write is required changes. This mode can be useful in eliminating any out of
only for manual control of VCO if Register 0x0A[11] = 1, band emissions during frequency changes, and ensuring
autocalibration is disabled, or to change the VCO output that the system emits only the desired frequencies. It is
divider value (VCO_REG 0x02). See Figure 39 for more enabled by writing VCO_REG 0x03[8:7] = 1d.
information. • Always mute (VCO_REG 0x03[8:7] = 3d). This mode is
• The fractional register, Register 0x04. The fractional register used for manual mute control.
write triggers autocalibration when Register 0x0A[11] = 0,
and it is loaded into the modulator automatically after the
autocalibration runs. If autocalibration is disabled,
Data Sheet HMC832A
Typical isolation when the HMC832A is muted is always better at a constant average phase offset with respect to each other.
than −50 dB, and is approximately −40 dB better than disabling The frequency of operation of the PD is fPD. Most formulas
the individual outputs of the HMC832A via VCO_REG related to, for example, step size, Σ-Δ modulation, and timers,
0x03[3:2], as shown in Figure 35. are functions of the operating frequency of the PD, fPD. fPD is
The VCO subsystem registers are not directly accessible. They also referred to as the comparison frequency of the PD.
are written to the VCO subsystem via PLL Register 0x05. See The PD compares the phase of the RF path signal with that of
Figure 39 and the VCO Serial Port Interface (VSPI) section for the reference path signal and controls the charge pump output
more information about the VCO subsystem SPI. current as a linear function of the phase difference between the
VCO Built-In Self Test (BIST) with Autocalibration two signals. The output current varies linearly over a full ±2π
radians (±360°) of input phase difference.
The frequency limits of the VCO can be measured using the
BIST features of the autocalibration machine by setting Charge Pump
Register 0x0A[10] = 1, which freezes the VCO switches in one A simplified diagram of the charge pump is shown in Figure 43.
position. VCO switches can then be written manually with the The CP consists of four programmable current sources: two
varactor biased at the nominal midrail voltage used for controlling the CP gain (up gain, Register 0x09[13:7], and down
autocalibration. For example, to measure the VCO maximum gain, Register 0x09[6:0]) and two controlling the CP offset,
frequency, use Switch 0, written to the VCO subsystem via where the magnitude of the offset is set by Register 0x09[20:14],
Register 0x05 = 000000001 0000 VCO_ID, where VCO_ID = and the direction is selected by Register 0x09[21] = 1 for up
000b. offset and Register 0x09[22] = 1 for down offset.
When autocalibration is enabled (Register 0x0A[11] = 0), and CP gain is used at all times, whereas CP offset is recommended
a new frequency is written, autocalibration runs. The VCO for fractional mode of operation only. Typically, the CP up and
frequency error relative to the command frequency is measured down gain settings are set to the same value (Register 0x09[13:7] =
and the results are written to Register 0x11[19:0], where Register 0x09[6:0]).
Register 0x11[19] is the sign bit. The result is written in terms of
Charge Pump Gain
VCO count error (see Equation 4).
Charge pump up and down gains are set by Register 0x09[13:7]
For example, if the expected VCO is 2 GHz, the reference is
and Register 0x09[6:0], respectively. The current gain of the
50 MHz, and n is 6, expect to measure 2000/(50/26) = 2560 counts.
pump in amps/radian is equal to the gain setting of this register
If a difference of −5 counts is measured in Register 0x11, it means
(Register 0x09) divided by 2π.
2555 counts were actually measured. Therefore, the actual fre-
quency of the VCO is 5/2560 low (negative), or 1.99609375 GHz. The typical CP gain setting is set from 2 mA to 2.5 mA;
With a 2 GHz VCO, 50 MHz reference, and n = 6, one count is however, lower values can also be used. Note that values less
approximately ±781 kHz. than 1 mA may result in degraded phase noise performance.
PLL SUBSYSTEM For example, if both Register 0x09[13:7] and Register 0x09[6:0]
are set to 50 decimal, the output current of each pump is 1 mA,
Charge Pump (CP) and Phase Detector (PD)
and the phase frequency detector gain is kP = 1 mA/2π radians,
The phase detector (PD) has two inputs, one from the reference or 159 μA/rad. See the Charge Pump (CP) and Phase Detector
path divider and one from the RF path divider. When in lock, (PD) section for more information.
these two inputs are at the same average frequency and are fixed
UP OFFSET REG 0x09[21]

UP GAIN 0µA TO 635µA
REG 0x09[13:7] 5µA STEP
0mA TO 2.54mA REG 0x09[20:14]
20µA STEP
UP
PD
REF PATH
LOOP
VCO PATH FILTER
DN
DOWN OFFSET REG 0x09[22]

DOWN GAIN 0µA TO 635µA
REG 0x09[6:0] 5µA STEP
REG 0x09[20:14]
13110-048
0mA TO 2.54mA
20µA STEP
Figure 43. Charge Pump Gain and Offset Control
HMC832A Data Sheet
Charge Pump Phase Offset Phase Detector Functions
In integer mode, the phase detector operates with zero offset. Register 0x0B, the phase detector register, allows manual access
The divided reference signal and the divided VCO signal arrive to control special phase detector features.
at the phase detector inputs at the same time. Integer mode Setting Register 0x0B[5] = 0 masks the PD up output, which
does not require any CP offset current. When operating in prevents the charge pump from pumping up.
integer mode, disable the CP offset in both directions (up and
down) by writing Register 0x09[22:21] = 00b, and set the CP Setting Register 0x0B[6] = 0 masks the PD down output, which
offset magnitude to zero by writing Register 0x09[20:14] = 0. prevents the charge pump from pumping down.
In fractional mode, CP linearity is of paramount importance. Clearing both Register 0x0B[5] and Register 0x0B[6] tristates
Any nonlinearity degrades phase noise and spurious perfor- the charge pump while leaving all other functions operating
mance. These nonlinearities are eliminated by operating the PD internally.
with an average phase offset, either positive or negative (either The PD force CP up (Register 0x0B[9] = 1) and force CP down
the reference or the VCO edge always leads, that is, arrives first (Register 0x0B[10] = 1) bits allow the charge pump to be forced
at the PD). up or down, respectively. This forces the VCO to the ends of the
A programmable CP offset current source adds dc current to tuning range, which is useful in testing the VCO.
the loop filter and creates the desired phase offset. Positive Reference Input Stage
current causes the VCO to lead, whereas negative current RVDD
causes the reference to lead.

The CP offset is controlled via Register 0x09. Increasing the offset AC COUPLE XREFP 20Ω
current causes the phase offset to scale from 0° to 360°. 80Ω
100Ω
13110-050
The specific level of charge pump offset current (Register 0x09, VBIAS
Bits[20:14]) is calculated using Equation 9 and shown in Figure 44.
Figure 45. Reference Path Input Stage
Required CP Offset = min ((4.3 × 10−9 × fPD × ICP), 0.25 × ICP) (9)
The reference buffer provides the path from an external refer-
where:
ence source (generally crystal-based) to the R divider, and
fPD is the comparison frequency of the phase detector (Hz).
eventually to the phase detector. The buffer has two modes
ICP is the full-scale current setting (A) of the switching charge
of operation controlled by Register 0x08[21]. High gain
pump (set in Register 0x09[6:0] and Register 0x09[13:7]).
(Register 0x08[21] = 0) is recommended below 200 MHz,
700
CP CURRENT = 2.5mA
and high frequency (Register 0x08[21] = 1) for 200 MHz to
350 MHz operation. The buffer is internally dc biased with
RECOMMENDED OFFSET CURRENT (µA)
600
100 Ω internal termination. For a 50 Ω match, add an external
CP CURRENT = 2mA
500 100 Ω resistor to ground followed by an ac coupling capacitor
(impedance less than 1 Ω).
400
At low frequencies, a relatively square reference is recommended to
300 maintain a high input slew rate. At higher frequencies, use a
CP CURRENT = 1mA
square or sinusoid. Table 8 shows the recommended operating
200
regions for different reference frequencies. If operating outside
100
these regions, the device usually still operates, but with degraded
reference path phase noise performance.
0
When operating at 50 MHz, the input referred phase noise of
13110-049
0 20 40 60 80 100
PHASE DETECTOR FREQUENCY (MHz) the PLL is between −148 dBc/Hz and −150 dBc/Hz at a 10 kHz
Figure 44. Recommended CP Offset Current vs. Phase Detector Frequency for offset, depending on the mode of operation. To avoid degra-
Typical CP Gain Currents, Calculated Using Equation 9 dation of the PLL noise contribution, the input reference signal
Do not allow the required CP offset current to exceed 25% must be 10 dB better than this floor. Such low levels are only
of the programmed CP current. It is recommended to necessary if the PLL is the dominant noise contributor and
enable the up offset and disable the down offset by writing these levels are required for the system goals.
Register 0x09[22:21] = 01b. Reference Path R Divider
Operation with CP offset influences the required configuration The reference path R divider is based on a 14-bit counter and
of the lock detect function. See the description of the lock can divide input signals by values from 1 to 16,383 and is
detect function in the Lock Detect section. controlled via Register 0x02.
Data Sheet HMC832A
RF Path, N Divider The HMC832A supports two lock detect modes.
The main RF path divider is capable of average divide ratios • Analog LD supports a fixed window size of 10 ns. Analog
between 219 − 5 (524,283) and 20 in fractional mode, and LD mode is selected by writing Register 0x07[6] = 0.
between 219 − 1 (524,287) and 16 in integer mode. The VCO • Digital LD supports a user configurable window size,
frequency range divided by the minimum N divider value programmed in Register 0x07[11:7]. Digital LD is selected
places practical restrictions on the maximum usable PD by writing Register 0x07[6] = 1.
frequency. For example, a VCO operating at 1.5 GHz in
fractional mode with a minimum N divider value of 20 has a Lock Detect Configuration
maximum PD frequency of 75 MHz. Optimal spectral performance in fractional mode requires CP
Lock Detect current and CP offset current configuration, described in detail
in the Charge Pump (CP) and Phase Detector (PD) section.
The lock detect (LD) function verifies that the HMC832A is
generating the desired frequency. It is enabled by writing The settings in Register 0x09 impact the required LD window
Register 0x07[3] = 1. The HMC832A provides an LD indicator size in fractional mode of operation. To function, the required
in one of two ways. lock detect window size is provided by Equation 10 in fractional
mode and Equation 11 in integer mode.
• As an output available on the LD/SDO pin of the HMC832A
(configuration is required to use the LD/SDO pin for LD LD Window (sec) =
purposes; for more information, see the Serial Port and the  I CP _ OFFSET (A) 1 
 + 2.66 × 10 − 9 (sec) + 
Configuring the LD/SDO Pin for LD Output sections).  f (Hz) × I (A) f (Hz ) 
 PD CP PD  (10)
• Reading from Register 0x12[1], where Bit 1 = 1 indicates a 2
locked condition and Bit 1 = 0 indicates an unlocked
condition. 1
LD Window (sec) = (11)
2 × f PD
The LD circuit expects the divided VCO edge and the divided
reference edge to appear at the PD within a user specified time where:
period (window), repeatedly. Either signal may arrive first. Only fPD is the comparison frequency of the phase detector.
the difference in arrival times is significant. The arrival of the ICP_OFFSET is the charge pump offset current (Register 0x09[20:14]).
two edges within the designated window increments an internal ICP is the full-scale current setting of the switching charge pump
counter. When the count reaches and exceeds a user specified (Register 0x09[6:0] or Register 0x09[13:7]).
value (Register 0x07[2:0]), the HMC832A declares lock. If the result provided by Equation 10 is equal to 10 ns, analog
Failure in registering the two edges in any one window resets LD can be used (Register 0x07[6] = 0); otherwise, digital LD is
the counter and immediately declares an unlocked condition. necessary (Register 0x07[6] = 1).
Lock is deemed to be reestablished when the counter reaches Table 9 lists the required Register 0x07 settings to appropriately
the user specified value (Register 0x07[2:0]) again. program the digital LD window size. From Table 9, select the
closest value in the digital LD window size columns to the ones
calculated in Equation 10 and Equation 11, and program
Register 0x07[11:10] and Register 0x07[9:7] accordingly.
Table 8. Reference Sensitivity1
Square Input Sinusoidal Input
Reference Input Slew > 0.5 V/ns Recommended Swing (V p-p) Recommended Power Range (dBm)
Frequency (MHz) Recommended Minimum Maximum Recommended Minimum Maximum
<10 Yes 0.6 2.5 No No No
10 Yes 0.6 2.5 No No No
25 Yes 0.6 2.5 Okay 8 15
50 Yes 0.6 2.5 Yes 6 15
100 Yes 0.6 2.5 Yes 5 15
150 Okay 0.9 2.5 Yes 4 12
200 Okay 1.2 2.5 Yes 3 8
1
Okay means the setting works. For example, 150 MHz input square wave is sufficient but 100 MHz may provide improved performance.
HMC832A Data Sheet
Digital Window Configuration Example Cycle Slip Prevention (CSP)
For this example, assume the device is in fractional mode, with When changing the VCO frequency and the VCO is not yet
a 50 MHz PD and the following conditions: locked to the reference, the instantaneous frequencies of the two
PD inputs are different, and the phase difference of the two
• Charge pump gain of 2 mA (Register 0x09[13:7] = 0x64,
inputs at the PD varies rapidly over a range much greater than
Register 0x09[6:0] = 0x64),
±2π radians. Because the gain of the PD varies linearly with
• Up offset (Register 0x09[22:21] = 01b)
phase up to ±2π, the gain of a conventional PD cycles from high
• Offset current magnitude of 400 μA (Register 0x09[20:14] gain, when the phase difference approaches a multiple of 2π, to
= 0x50) low gain, when the phase difference is slightly larger than a
Apply Equation 10 to calculate the required LD window size. multiple of 0 radians. The output current from the charge pump
cycles from maximum to minimum, even though the VCO has
LD Window (sec) =
not yet reached its final frequency.
 0.4 × 10 −3 (A) 1 
 + 2.66 × 10 −9 (sec) +  The charge on the loop filter small capacitor may actually
6 −3
 50 × 10 (Hz) × 2 × 10 (A) 50 × 10 6 (Hz) 
discharge slightly during the low gain portion of the cycle. This
2
= 13.33 ns
discharge can make the VCO frequency reverse temporarily
during locking. This phenomenon is known as cycle slipping.
Locate the Table 9 value that is closest to this result, which is, in Cycle slipping causes the pull-in rate during the locking phase
this case, 13.3 ≈ 13.33. To set the digital LD window size, to vary cyclically. Cycle slipping increases the time to lock to a
program Register 0x07[11:10] = 10b and Register 0x07[9:7] = value greater than that predicted by normal small signal Laplace
010b, according to Table 9. For a given operating point, there is transform analysis.
always a good solution for the lock detect window. However,
The HMC832A PD features an ability to reduce cycle slipping
one solution does not fit all operating points. As observed from
during acquisition. The cycle slip prevention (CSP) feature
Equation 10 and Equation 11, if the charge pump offset or PD
increases the PD gain during large phase errors. The specific
frequency is changed significantly, the lock detect window may
phase error that triggers the momentary increase in PD gain is
need to be adjusted.
set via Register 0x0B[8:7].
Configuring the LD/SDO Pin for LD Output
Frequency Tuning
Setting Register 0x0F[7] = 1 and Register 0x0F[4:0] = 1 displays The HMC832A VCO subsystem always operates in the
the lock detect flag on the LD/SDO pin of the HMC832A. When fundamental frequency of operation (1500 MHz to 3000 MHz).
locked, LD/SDO is high. As the name suggests, the LD/SDO pin The HMC832A generates frequencies below its fundamental
is multiplexed between the LD and the serial data output (SDO) frequency (25 MHz to 1500 MHz) by tuning to the appropriate
signals. Therefore, LD is available on the LD/SDO pin at all fundamental frequency and selecting the appropriate output
times except when a serial port read is requested, in which case divider setting (divide by 2 to 62) in VCO_REG 0x02[5:0].
the pin reverts temporarily to the serial data output pin, and
returns to the lock detect flag after the read is completed. The HMC832A automatically controls frequency tuning in the
fundamental band of operation. For more information, see the
LD can be made available on the LD/SDO pin at all times by VCO Autocalibration section.
writing Register 0x0F[6] = 1. In that case, the HMC832A does
not provide any readback functionality because the SDO signal To tune to frequencies below the fundamental frequency range
is not available. (<1500 MHz), it is required to tune the HMC832A to the appropri-
ate fundamental frequency, and then select the appropriate output
divider setting (divide by 2 to 62) in VCO_REG 0x02[5:0].
Table 9. Typical Digital Lock Detect Window

Digital Lock Detect Window Size Nominal Value (ns)
LD Timer Speed, LD Timer Divide Setting, Register 0x07[9:7]
Register 0x07[11:10] 000 001 010 011 100 101 110 111
00 (Fastest) 6.5 8 11 17 29 53 100 195
01 7 8.9 12.8 21 36 68 130 255
10 7.1 9.2 13.3 22 38 72 138 272
11 Slowest 7.6 10.2 15.4 26 47 88 172 338
Data Sheet HMC832A
Integer Mode VCO_REG 0x02[5:0]).
The HMC832A is capable of operating in integer mode. For NINT is the integer division ratio (set in Register 0x03), an
integer mode, set the following registers: integer number between 20 and 524,284.
NFRAC is the fractional part, from 0.0 to 0.99999…, NFRAC =
 Disable the fractional modulator, Register 0x06[11] = 0 Register 0x04/224.
 Bypass the modulator circuit, Register 0x06[7] = 1 R is the reference path division ratio (set in Register 0x02).
In integer mode, the VCO step size is fixed to that of the PD fXTAL is the frequency of the reference oscillator input.
frequency. Integer mode typically has a 3 dB lower phase noise For example, fOUT = 1402.5 MHz, k = 2, fVCO = 2805 MHz, fXTAL =
than fractional mode for a given PD operating frequency. 50 MHz, R = 1, fPD = 50 MHz, NINT = 56, and NFRAC = 0.1. fPD is
Integer mode, however, often requires a lower PD frequency to the PD operating frequency, fXTAL/R.
meet step size requirements. The fractional mode advantage is Register 0x04 = round(0.1 × 224) = round(1,677,721.6) =
that higher PD frequencies can be used; therefore, lower phase 1,677,722.
noise can often be realized in fractional mode. Disable the
charge pump offset when in integer mode. 50  106  1677722 
fVCO  56    2805 MHz  1.192 Hz error (14)
Integer Frequency Tuning 1  224 
In integer mode, the digital Σ-Δ modulator is shut off and the fVCO
f OUT   1402.5 MHz  0.596 Hz error (15)
N divider (Register 0x03) can be programmed to any integer 2
value in the range of 16 to 219 − 1. To run in integer mode, In this example, the output frequency of 1402.5 MHz is achieved by
configure Register 0x06 (as described in the Integer Mode programming the 19-bit binary value of 56d = 0x38 into the
section), then program the integer portion of the frequency as INTG_REG bit in Register 0x03, and the 24-bit binary value of
explained by Equation 12, ignoring the fractional part. 1677722d = 0x19999A into the FRAC bit in Register 0x04. Elimi-
1. Disable the fractional modulator, Register 0x06[11] = 0. nate the 0.596 Hz quantization error using the exact frequency
2. Bypass the Σ-Δ modulator Register 0x06[7] = 1. mode, if required. In this example, the output fundamental is
3. To tune to frequencies (<1500 MHz), select the appropriate divided by 2. Specific control of the output divider is required.
output divider value VCO_REG 0x02[5:0]. See the VCO Subsystem Register Map section and description
for details.
Writing to the VCO subsystem registers (VCO_REG 0x02[5:0]
and VCO_REG 0x03[0] in this case) is accomplished indirectly Exact Frequency Tuning
through PLL Register 0x05. More information on communi- Due to quantization effects, the absolute frequency precision of
cating with the VCO subsystem through PLL Register 0x05 is a fractional PLL is normally limited by the number of bits in the
available in the VCO Serial Port Interface (VSPI) section. fractional modulator. For example, the frequency resolution of a
Fractional Mode 24-bit fractional modulator is set by the PD comparison rate
divided by 224. The 224 value in the denominator is sometimes
Set the following registers to place the HMC832A in fractional
referred to as the modulus. Analog Devices PLLs use a fixed
mode:
modulus, which is a binary number. In some types of fractional
 Enable the fractional modulator, Register 0x06[11] = 1. PLLs, the modulus is variable, allowing exact frequency steps to be
 Connect the Σ-Δ modulator in circuit, Register 0x06[7] = 0. achieved with decimal step sizes. Unfortunately, small steps
using small modulus values result in large spurious outputs at
Fractional Frequency Tuning
multiples of the modulus period (channel step size). For this
This is a generic example with the goal of explaining how to reason, Analog Devices PLLs use a large fixed modulus.
program the output frequency. Actual variables are dependent Normally, the step size is set by the size of the fixed modulus. In
on the reference in use. the case of a 50 MHz PD rate, a modulus of 224 results in a 2.98 Hz
The HMC832A in fractional mode achieves frequencies at step resolution, or 0.0596 ppm. In some applications, it is
fractional multiples of the reference. The frequency of the necessary to have exact frequency steps, and even an error of
HMC832A, fVCO, is given by 3 Hz cannot be tolerated.
f XTAL Fractional PLLs are able to generate exact frequencies (with

fVCO  (N INT  N FRAC )  f INT  f FRAC (12) zero frequency error) if N can be exactly represented in binary
R
(for example, N = 50.0, 50.5, 50.25, 50.75, …). Some common
fOUT = fVCO/k (13) frequencies cannot be exactly represented. For example, NFRAC =
where: 0.1 = 1/10 must be approximated as round((0.1 × 224)/224 ) ≈
fOUT is the output frequency after any potential dividers. 0.100000024. At fPD = 50 MHz, this translates to a 1.2 Hz error.
k is 1 for fundamental, or k = 2 to 62 depending on the selected The exact frequency mode of the HMC832A addresses this
output divider value (Register 0x05[6:0] indirectly addressed to issue and can eliminate quantization error by programming the
HMC832A Data Sheet
channel step size to fPD/10 in Register 0x0C to 10 (in this example). each target frequency or be set up for a fixed fGCD that applies to
More generally, this feature can be used whenever the desired all channels.
frequency, fVCO, can be exactly represented on a step plan where Configuring Exact Frequency Mode for a Particular
there is an integer number of steps (<214) across integer-N
Frequency
boundaries. Mathematically, this situation is satisfied if
1. Calculate and program the integer register setting.
fVCOk mod(fGCD) = 0 (16)
Register 0x03 = NINT = floor(fVCO/fPD)
where:
fVCOk is the channel step frequency. 0 < k < 224 − 1, as shown in where the floor function is the rounding down to the
Figure 46. nearest integer.
GCD is the greatest common divisor. 2. Then calculate the integer boundary frequency.
f  fN = NINT × fPD
f GCD = GCD( f VCO1 , f PD ) and f GCD ≥  PD
14 
2  3. Calculate and program the exact frequency register value.
where fPD is the frequency of the phase detector. Register 0x0C = fPD/fGCD
Some fractional PLLs are able to achieve these exact frequencies where fGCD = GCD(fVCO, fPD).
by adjusting (shortening) the length of the phase accumulator 4. Calculate and program the fractional register setting.
(the denominator or the modulus of the Σ-Δ modulator) so that
 224 ( fVCOk − f N ) 
the Σ-Δ modulator phase accumulator repeats at an exact Register 0x04 N FRAC = ceil 

period related to the interval frequency (fVCOk − fVCO(k − 1)) in  f PD 
Figure 46. Consequently, the shortened accumulator results in
where ceil is the ceiling function, that is, round up to the
more frequent repeating patterns and, as a result, often leads to
nearest integer.
spurious emissions at multiples of the repeating pattern period,
or at harmonic frequencies of fVCOk − fVCO(k − 1). For example, in To configure the HMC832A for exact frequency mode at fVCO =
some applications, these intervals may represent the spacing 2800.2 MHz, where the PD rate (fPD) = 61.44 MHz, proceed as
between radio channels, with the spurious occurring at multiples follows:
of the channel spacing. 1. Check Equation 16 to confirm that the exact frequency
In comparison, the Analog Devices method is able to generate mode for this fVCO is possible.
exact frequencies between adjacent integer-N boundaries while f 
still using the full 24-bit phase accumulator modulus, thus fGCD = GCD( fVCO , f PD ) and fGCD ≥  PD
14 
2 
achieving exact frequency steps with a high phase detector
comparison rate, which allows Analog Devices PLLs to maintain fGCD = GCD(2800.2 × 106, 61.44 × 106) =
excellent phase noise and spurious performance in the exact 61.44 × 106
120 × 103 > = 3750
frequency mode. 214
Using Exact Frequency Mode Because Equation 16 is satisfied, configure the HMC832A
for exact frequency mode at fVCO = 2800.2 MHz by
If the constraint in Equation 16 is satisfied, the HMC832A is
continuing with the remaining steps.
able to generate signals with zero frequency error at the desired
VCO frequency. Exact frequency mode can be reconfigured for
fVCO = fVCO2
INTEGER INTEGER
BOUNDARY BOUNDARY
fN fVCO1 fVCO2 fVCO3 fVCO4 fVCO14 – 2 fVCO14 – 1 fVCO14 fN + 1

13110-051
fN + 1 – fN = fPD
Figure 46. Exact Frequency Tuning
Data Sheet HMC832A
2. Calculate NINT. To switch between various equally spaced intervals (channels),
NINT = Register 0x03 = only the fractional register (Register 0x04) must be programmed
to the desired VCO channel frequency (fVCOk), as follows:
 f   2800.2 × 106 
floor  VCO1  = floor  6
 = 45d = 0x2D Register 0x04 =
 f PD   61.44 × 10 
 2 24 ( f VCOk − f N ) 
3. Calculate the value for Register 0x0C N FRAC = ceil 

 f PD 
Register 0x0C =
f PD where fN = floor(fVCO1/fPD), and fVCO1, as shown in Figure 46,
=
GCD(( f VCOk + 1 − f VCOk ), f PD ) represents the smallest channel VCO frequency that is greater
than fN.
61.44 × 10 6
= To configure the HMC832A for the exact frequency mode for
GCD(100 × 10 3 , 61.44 × 10 6 )
equally spaced intervals of 100 kHz, where the first channel
61.44 × 10 6 (Channel 1) = fVCO1 = 2800.200 MHz and the PD rate (fPD) =
= 3072d = 0 xC00
20000 61.44 MHz, proceed as follows:
4. To program Register 0x04, calculate the closest integer-N 1. Check that the exact frequency mode for fVCO1 =
boundary frequency (fN) that is less than the desired VCO 2800.2 MHz (Channel 1) and fVCO2 = 2800.2 MHz +
frequency (fVCO): fN = fPD × NINT. Using the current example, 100 kHz = 2800.3 MHz (Channel 2) is possible.
fN = fPD × NINT = 45 × 61.44 × 106 = 2764.8 MHz f GCD1 = GCD( f VCO1 , f PD ) and
then f 
f GCD1 ≥  PD
14  and f GCD2 = GCD( f VCO2 , f PD ) (17)
Register 0x04 = 2 
 224 ( fVCO − f N )   f PD 
ceil = and f GCD2 ≥  14 
f PD  2 
 
 224 (2800.2 × 10 6 − 2764.8 × 10 6 )  f GCD1 = GCD(2800.2 × 10 6 , 61.44 × 10 6 ) =
ceil  =
 61.44 × 10 6  61.44 × 10 6
120 × 10 3 > = 3750
9666560d = 0 x938000 214
Exact Frequency Channel Mode f GCD2 = GCD(2800.3 × 10 6 , 61.44 × 10 6 ) =
When multiple, equally spaced, exact frequency channels are 61.44 × 10 6
needed that fall within the same interval (that is, fN ≤ fVCOk < 20 × 10 3 > = 3750
214
fN + 1), where fVCOk is shown in Figure 46 and 1 ≤ k ≤ 214, it is
possible to maintain the same integer-N (Register 0x03) and 2. If Equation 16 is satisfied for at least two of the equally
exact frequency register (Register 0x0C) settings and only spaced interval (channel) frequencies, fVCO1, fVCO2, fVCO3, …
update the fractional register (Register 0x04) setting. The exact fVCON, as it is in Equation 17, the HMC832A exact
frequency channel mode is possible when Equation 16 is frequency channel mode is possible for all desired channel
satisfied for at least two equally spaced adjacent frequency frequencies, and can be configured as follows:
channels, that is, the channel step size. Register 0x03 =
To configure the HMC832A for exact frequency channel mode, f   2800.2 × 10 6 
floor  VCO1  = floor   = 45d = 0 x2D
initially program the integer (Register 0x03) and the exact  f PD   61.44 × 10
6

frequency (Register 0x0C) for the smallest fVCO frequency (fVCO1
in Figure 46), as follows: Register 0x0C =
f PD
1. Calculate and program the integer register setting Regis- =
GCD(( f VCOk + 1 − f VCOk ), f PD )
ter 0x03 = NINT = floor(fVCO1/fPD), where fVCO1 is shown in
Figure 46 and corresponds to the minimum channel VCO 61.44 × 10 6
=
frequency. Then, the lower integer boundary frequency is GCD(100 × 10 3 , 61.44 × 10 6 )
given by fN = NINT × fPD.
61.44 × 10 6
2. Calculate and program the exact frequency register value = 3072d = 0xC00
20000
Register 0x0C = fPD/fGCD, where fGCD = GCD((fVCOk + 1 − fVCOk),
fPD) = greatest common divisor of the desired equidistant where (fVCOk + 1 − fVCOk) is the desired channel spacing
channel spacing (fVCOk + 1 − fVCOk) and the PD frequency, fPD. (100 kHz in this example).
HMC832A Data Sheet
3. To program Register 0x04, the closest integer-N boundary POWER-DOWN MODE
frequency, fN, that is less than the smallest channel VCO The VCO subsystem is not affected by the CEN pin or soft
frequency, fVCO1, must be calculated (fN = floor(fVCO1/fPD)). reset. Therefore, device power-down is a two-step process.
Using the current example:
1. Power down the VCO by writing 0 to VCO Register 1 via
 2800.2 × 10 6  Register 0x05.
f N = f PD × floor  6 
=
 61.44 × 10  2. Power-down the PLL by pulling the CEN pin (Pin 17) low
45 × 61.44 × 10 6 = 2764.8 MHz (assuming there are no SPI overrides (Register 0x01[0] = 1)).
Pulling the CEN pin low disables all analog functions and
Then, for Channel 1,
internal clocks. Current consumption typically drops below
 2 24 ( f VCO1 − f N )  10 μA in the power-down state. The serial port still
Register 0x04 = ceil  ,

 f PD  responds to normal communication in power-down mode.
where fVCO1 = 2800.2 MHz. It is possible to ignore the CEN pin by setting Register 0x01[0]
= 0. Control of the power-down mode then comes from the
 2 24 (2800.2 × 10 6 − 2764.8 × 10 6 )  serial port register, Register 0x01[1].
= ceil  = 9666560d = 0 x938000
 61.44 × 10 6  It is also possible to leave various blocks turned on when in
4. To change from Channel 1 (fVCO1 = 2800.2 MHz) to power-down (see Register 0x01), as listed in Table 10.
Channel 2 (fVCO2 = 2800.3 MHz), only Register 0x04 needs
Table 10. Bit and Block Assignments for Register 0x01
to be programmed, as long as all of the desired exact
Bit Assignment Block Assignment
frequencies, fVCOk (see Figure 46), fall between the same
Bit 2 Internal bias reference sources
integer-N boundaries (fN < fVCOk < fN + 1). In that case,
Bit 3 PD block
Register 0x04 = Bit 4 CP block
 2 24 (2800.3 × 10 6 − 2764.8 × 10 6 )  Bit 5 Reference path buffer
ceil  =
 61.44 × 10 6  Bit 6 VCO path buffer
9693867 d = 0 x93EAAB, and so on Bit 7 Digital I/O test pads
To mute the output but leave the PLL and VCO locked, see the
Seed Register
VCO Output Mute Function section.
The start phase of the fractional modulator digital phase
accumulator (DPA) can be set to one of four possible default GENERAL-PURPOSE OUTPUT (GPO)
values via the seed bits, Register 0x06[1:0]. The HMC832A The PLL shares the LD/SDO (lock detect/serial data output) pin
automatically reloads the start phase (seed value) into the DPA to perform various functions. Although the pin is most commonly
every time a new fractional frequency is selected. Certain zero used to read back registers from the chip via the SPI, it is also
or binary seed values may cause spurious energy correlation at capable of exporting a variety of signals and real-time test wave-
specific frequencies. For most cases, a random (not zero and forms (including lock detect). It is driven by a tristate CMOS
not binary) start seed is recommended (Register 0x06[1:0] = 2). driver with ~200 Ω ROUT. It has logic associated with it to dynami-
cally select whether the driver is enabled, and to decide which
SOFT RESET AND POWER-ON RESET
data to export from the chip.
The HMC832A features a hardware power-on reset (POR). All
In its default configuration, after power-on reset, the output
chip registers are reset to default states approximately 250 μs
driver is disabled, and drives only during appropriately
after power-up.
addressed SPI reads. This configuration allows the HMC832A
The PLL subsystem SPI registers can also be soft reset by an SPI to share its output with other devices on the same bus.
write to Register 0x00. Note that the soft reset does not clear the
The pin driver is enabled if the chip is addressed; that is, the last
SPI mode of operation referred to in the Serial Port section. The
three bits of the SPI cycle = 000b before the rising edge of SEN.
VCO subsystem is not affected by the PLL soft reset; the VCO
If SEN rises before SCK has clocked in an invalid (nonzero)
subsystem registers can only be reset by removing the power
chip address, the HMC832A starts to drive the bus.
supply.
To monitor any of the GPO signals, including lock detect, set
If external power supplies or regulators have rise times slower
Register 0x0F[7] = 1 to keep the SDO driver always on. This
than 250 μs, write to the SPI soft reset bit (Register 0x00[5] = 1)
setting stops the LDO driver from tristating and means that the
immediately after power-up, before any other SPI activity. This
SDO line cannot be shared with other devices.
write procedure ensures starting from a known state.
The HMC832A naturally switches from the GPO data and
exports the SDO signal during an SPI read. To prevent this
automatic data selection and always select the GPO signal, set
Data Sheet HMC832A
Bit 6 of Register 0x0F to 1 to prevent automuxing of the LD/SDO SPI Protocol Features
pin. The phase noise performance at this output is poor and The SPI protocol has the following general features:
uncharacterized. Also, do not toggle the GPO output during
normal operation because toggling may degrade the spectral • 3-bit chip address, can address up to eight devices
performance. connected to the serial bus.
• Wide compatibility with multiple protocols from multiple
Additional controls are available that may be helpful when
vendors.
sharing the bus with other devices.
• Simultaneous write/read during the SPI cycle.
• To disable the driver completely, set Register 0x08[5] = 0 • 5-bit address space.
(this bit takes precedence over all other LD/SDO driver bit • 3-wire for write only capability, 4-wire for read/write
settings). capability.
• To disable either the pull-up or pull-down sections of the
driver, set Register 0x0F[8] = 1 or Register 0x0F[9] = 1, Typical serial port operation can be run with SCK at speeds of
respectively. up to 50 MHz.
• To drive 3.3 V CMOS logic, set Register 0x0B[22] = 1. Serial Port Write Operation
Example scenarios are listed in Table 11. The signals that are SPI write specifications are listed in Table 2 in the SPI Write
available on the GPO are selected by changing the GPO_ Timing Characteristics section and a typical write cycle is
SELECT bit, Register 0x0F[4:0]. shown in Figure 47. The SPI write operation is as follows:
1. The master (host) places 24-bit data, D[23:0], MSB first, on
CHIP IDENTIFICATION
SDI on the first 24 falling edges of SCK.
Identify the PLL subsystem version information by reading the 2. The slave (HMC832A) shifts in data on SDI on the first
content of the read only register, CHIP_ID, in Register 0x00. It 24 rising edges of SCK.
is not possible to read the VCO subsystem version. 3. The master places a 5-bit register address to be written to,
SERIAL PORT INTERFACE (SPI) R[4:0], MSB first, on the next five falling edges of SCK (25th
to 29th falling edges).
The HMC832A SPI supports both 1.8 V and 3.3 V voltage
4. The slave shifts the register bits on the next five rising
levels. Input pins including SDI, SCK, and SEN support both
edges of SCK (25th to 29th rising edges).
voltage levels without the need for any configuration.
5. The master places a 3-bit chip address, A[2:0], MSB first,
The SPI output, the LD/SDO pin, also supports both 1.8 V and on the next three falling edges of SCK (30th to 32nd falling
3.3 V levels in both CMOS and open-drain configurations. edges). Analog Devices reserves Chip Address A2 to
Both the voltage levels and configuration (CMOS or open Chip Address A0 = 000 for all RF PLLs with integrated
drain) are register programmable via Register 0x0B[22] and VCOs.
Register 0x0F[9:8], respectively, as shown in Table 12. Open-drain 6. The slave shifts the chip address bits on the next three
mode in both 1.8 V and 3.3 V levels requires an external pull-up rising edges of SCK (30th to 32nd rising edges).
resistor. See the electrical specifications in Table 1 for more 7. The master asserts SEN after the 32nd rising edge of SCK.
information. 8. The slave registers the SDI data on the rising edge of SEN.
Table 11. Driver Scenarios
Scenario Action
Drive SDO During Reads, Tristate Otherwise (Allow Bus Sharing), 1.8 V Output None required
Drive SDO During Reads, Lock Detect Otherwise, 1.8 V Output Set GPO select, Register 0x0F[4:0] = 00001b (default)
Set Register 0x0F[7] = 1, prevent GPO driver disable
Always Drive Lock Detect, 3.3 V Output Set Register 0x0F[6] = 1, prevent automux of SDO
Set the GPO select, Register 0x0F[4:0] = 00001 (default)
Set Register 0x0F[7] = 1, prevent GPO driver disable
Set Register 0x0B[22] = 1, output drive set to 3.3 V logic
Table 12. SPI Voltage

Register 0x0B[22] SPI Register 0x0F[8] Internal Register 0x0F[9] Internal
Voltage Level Pull-Up Disable Pull-Down Disable LD/SDO Pin Configuration
Don’t care Don’t care Don’t care LD/SDO pin tristated
1 1 0 3.3 V open-drain mode
0 1 0 1.8 V open-drain mode
1 0 0 3.3 V CMOS mode
0 0 0 1.8 V CMOS mode
HMC832A Data Sheet
t5
1 2 3 22 23 24 25 26 30 31 32
SCK
t1 t2
t6
SDI x D23 D22 D2 D1 D0 R4 R3 R0 A2 A1 A0 x
SEN
13110-052
t3 t4
Figure 47. Serial Port Write Timing Diagram
Serial Port Read Operation 5. The master places the 3-bit chip address, A[2:0], MSB first,
In general, the LD/SDO line is always active during the on the next three falling edges of SCK (30th to 32nd falling
write cycle. During any SPI cycle, LD/SDO contains the edges). The chip address is always 000b.
data from the current address written in Register 0x00[4:0]. 6. The slave shifts the chip address bits on the next three
If Register 0x00[4:0] is not changed, the same data is always rising edges of SCK (30th to 32nd rising edges).
present on LD/SDO during a SPI cycle. 7. The master asserts SEN after the 32nd rising edge of SCK.
8. The slave registers the SDI data on the rising edge of SEN.
If a read is required from a specific address, it is necessary to
9. The master clears SEN to complete the address transfer of
write the required address to Register 0x00[4:0] in the first SPI
the two-part read cycle.
cycle. Then, in the next SPI cycle, the desired data becomes
10. If a write data to the chip is not needed at the same time as
available on LD/SDO. A typical read cycle is shown in Figure 48.
the second cycle occurs, it is recommended to simply
An example of the two-cycle procedure to read from any rewrite the same contents on SDI to Register 0x00 on the
random address is as follows: readback portion of the cycle.
1. The master (host), on the first 24 falling edges of SCK, 11. The master places the same SDI data as the previous cycle
places 24-bit data, D[23:0], MSB first, on SDI, as shown in on the next 32 falling edges of SCK.
Figure 48. Set D[23:5] to zero. D[4:0] = address of the 12. The slave (HMC832A) shifts the SDI data on the next
register to be read on the next cycle. 32 rising edges of SCK.
2. The slave (HMC832A) shifts in data on SDI on the first 13. The slave places the desired read data (that is, data from
24 rising edges of SCK. the address specified in Register 0x00[4:0] of the first
3. The master places the 5-bit register address, R[4:0] (the cycle) on LD/SDO, which automatically switches to SDO
read address register), MSB first, on the next five falling mode from LD mode, disabling the LD output.
edges of SCK (25th to 29th falling edges). R[4:0] = 00000. 14. The master asserts SEN after the 32nd rising edge of SCK to
4. The slave shifts the register bits on the next five rising complete the cycle and to revert back to lock detect on
edges of SCK (25th to 29th rising edges). LD/SDO.
Data Sheet HMC832A
FIRST CYCLE
1 18 19 20 24 25 29 30 31 32
SCK
t7
t1 t2 t6
SDI x D5 D4 D0 R4 R3 R0 A2 A1 A0 x
READ ADDRESS REGISTER ADDRESS = 00000 CHIP ADDRESS = 000

t5
LD/SDO
OR LD/GPO x x x x x x x x x x x LD/GPO
TRISTATE
SEN
t3 t4
SECOND CYCLE
1 18 19 20 24 25 29 30 31 32
SCK
t7
t1 t6
SDI x D23 D5 D4 D0 R4 R3 R0 A2 A1 A0 x
LD/SDO LD/GPO D23 D22 D2 D1 D0 R4 R0 A2 A1 A0 LD/GPO1
SEN
t3
1FOR MORE INFORMATION ON USING THE GPO FUNCTION SEE THE SERIAL PORT INTERFACE SECTION. 13110-053
Figure 48. Serial Port Read Timing Diagram
HMC832A Data Sheet
APPLICATIONS INFORMATION
A large bandwidth (25 MHz to 3000 MHz), industry leading Using the HMC832A with a tunable reference, as shown in
phase noise and spurious performance, excellent noise floor Figure 51, it is possible to drastically improve spurious emissions
(−160 dBc/Hz), and a high level of integration make the performance across all frequencies.
HMC832A ideal for a variety of applications, including as an RF
or IF stage local oscillator (LO).
PLL
HMC832A
DAC
PLL ÷2
HMC1044LP3E
HMC832A
DAC
13110-040
HMC900LP5E HMC795LP5E
Figure 49. HMC832A in a Typical Transmit Chain
PLL
HMC832A
HMCAD1520
ADC
CMIO
0
90
PLL
CMQO
HMC1044LP3E HMC832A
HMCAD1520
ADC
13110-041
HMC960LP4E HMC900LP5E
Figure 50. HMC832A in a Typical Receive Chain
TUNABLE REFERENCE
25MHz TO 100MHz
PLL PLL
13110-042
CRYSTAL HMC832A HMC832A

OSCILLATOR
Figure 51. HMC832A Used as a Tunable Reference for HMC832A
Data Sheet HMC832A
POWER SUPPLY divide ratios are changed in the opposite direction accordingly
The HMC832A is a high performance, low noise device. In so that the HMC832A generates an identical output frequency,
some cases, phase noise and spurious performance may be as shown in Figure 18, without the spurious emissions inside
degraded by noisy power supplies. To achieve maximum the loop bandwidth. Using these same procedures, Figure 19 is
performance and ensure that power supply noise does not generated by observing and plotting only the magnitude of the
degrade the performance of the HMC832A, use the Analog largest spur, at any offset and at each output frequency, while
Devices low noise, high power supply rejection ratio (PSRR) using a fixed 50 MHz reference and a tunable 47.5 MHz
regulator, the HMC1060LP3E. Using the HMC1060LP3E lowers reference.
the design risk and cost, and ensures that the performance shown The HMC832A features an internal autocalibration process that
in the Typical Performance Characteristics section can be achieved. seamlessly calibrates the HMC832A when a frequency change
is executed (see Figure 27 and Figure 30). The typical frequency
PROGRAMMABLE PERFORMANCE TECHNOLOGY
settling time that can be expected after any frequency change
For low power applications that do not require maximum noise (writes to Register 0x03 or Register 0x04 ) is shown in Figure 27
floor performance, the HMC832A features the ability to reduce with autocalibration enabled (Register 0x0A[11] = 0). A fre-
current consumption by 50 mA (power consumption by 165 mW) quency hop of 5 MHz is shown in Figure 27; however the settling
at the cost of decreasing phase noise floor performance by ~5 dB. time is independent of the size of the frequency change. Any size
High performance is enabled by writing VCO_REG 0x03[1:0] = frequency hop has a similar settling time with autocalibration
3d, and it is disabled (low current consumption mode enabled) enabled. Figure 32 shows the typical tuning voltage after calibration
by writing VCO_REG 0x03[1:0] = 1d. High performance mode where, when the HMC832A is calibrated at any temperature,
improves noise floor performance at the cost of increased current the calibration setting holds across the entire operating range of
consumption. The resulting current consumption is shown in the HMC832A (−40°C to +85°C). Figure 32 shows that the
Figure 33 and Figure 36. tuning voltage is maintained within a narrow operating range
LOOP FILTER AND FREQUENCY CHANGES for worst case scenarios where calibration is executed at one
R3 R4 temperature extreme and the device is operating at the other
CP VTUNE
C1 R2 C3 C4 extreme.
13110-037
C2
For applications that require fast frequency changes, the HMC832A
supports manual calibration that enables faster settling times
Figure 52. Loop Filter Design
(see Figure 28 and Figure 31). Manual calibration must be
All PLLs with integrated VCOs exhibit integer boundary spurs executed only once for each individual HMC832A device, at
at harmonics of the reference frequency. Figure 18 shows the any temperature, and is valid across all temperature operating
worst case spurious scenario where the harmonic of the ranges of the HMC832A. For more information about manual
reference frequency (50 MHz) is within the loop filter calibration, see the Manual VCO Calibration for Fast Frequency
bandwidth of the fundamental frequency of the HMC832A. Hopping section. A frequency hop of 5 MHz is shown in Figure 28
The tunable reference changes the reference frequency from and Figure 31; however, the settling time is independent of the
50 MHz in Figure 18 to 47.5 MHz in Figure 16 to distance the size of the frequency change. Any size frequency hop has a similar
harmonic of the reference frequency (spurious emissions) from settling time with autocalibration disabled (Register 0x0A[11] = 1).
the fundamental output frequency of the HMC832A so that it is
filtered by the loop filter. The internal HMC832A setup and
Table 13. Loop Filter Designs Used in Typical Performance Characteristics Graphs
Loop Filter Loop Filter Loop Filter Phase C1 C2 C3 C4 R2 R3 R4 Loop Filter
Type Bandwidth (kHz) Margin (pF) (nF) (pF) (pF) (Ω) (Ω) (Ω) Design
Type 11 127 61° 390 10 82 82 750 300 300 See Figure 52
Type 22 75 61° 270 27 200 390 430 390 390 See Figure 52
Type 33 214 71° 56 1.8 N/A4 N/A4 2200 0 0 See Figure 52
1
Loop Filter Type 1 is for best integrated phase noise. The loop filter bandwidth is designed for 50 MHz PD frequency, CP = 1.6 mA at 2.2 GHz output in fractional mode.
2
Loop Filter Type 2 is suggested for best far out phase noise. The loop filter bandwidth is designed for 50 MHz PD frequency, CP = 1.6 mA at 2.2 GHz output in fractional
mode.
3
Loop Filter Type 3 is suggested for best integrated phase noise in integer mode. The loop filter bandwidth is designed for 50 MHz PD frequency, CP = 2.5 mA at 3 GHz
output in integer mode.
4
N/A means not applicable.
HMC832A Data Sheet
RF PROGRAMMABLE OUTPUT RETURN LOSS MUTE MODE
The HMC832A features a programmable RF output return loss The HMC832A features a configurable mute mode, as well as
(VCO_REG 0x03[5]) and 0 dB to 11 dB of programmable gain the ability to independently turn off outputs on both the RF_N
(VCO_REG 0x07[3:0]), as shown in Figure 26 and Figure 25, and RF_P output pins. Figure 35 shows isolation measured at the
respectively. Maximum output power is achieved with a high output when the mute mode is on (VCO_REG 0x03[8:7] = 3d),
return loss setting (VCO_REG 0x03[5] = 0), as shown in Figure 22. and when the mute mode is off (VCO_REG 0x03[8:7] = 1d),
Setting VCO_REG 0x03[5] = 1 improves return loss for applica- with either or both outputs disabled (VCO_REG 0x03[3:2] = 0d) or
tions that require it at the cost of reduced RF output power (see one output enabled and the other disabled (VCO_REG 0x03[3:2] =
Figure 22). 1d).
Data Sheet HMC832A
PLL REGISTER MAP

ID, READ ADDRESS, AND RESET (RST) REGISTERS
The ID register is read only, the read address/RST strobe register is write only, and the RST register is read/write.
Table 14. Register 0x00, ID Register (Read Only)

Bits Type Name Width Default Description
23:0 R CHIP_ID 24 J7275 HMC832A chip ID
Table 15. Register 0x00, Read Address/RST Strobe Register (Write Only)
Bits Type Name Width Default1 Description
4:0 W Read address 5 N/A Read address for next cycle. This is a write only register.
5 W Soft reset 1 N/A Soft reset for both SPI modes (set to 0 for proper operation).
23:6 W Not defined 18 N/A Not defined (set to 0 for proper operation).
1
N/A means not applicable.
Table 16. Register 0x01, RST Register (Default 0x000002)

0 R/W RST_CHIPEN_PIN_SELECT 1 0 1 = power down the PLL via the CEN pin (see the Power-Down Mode
section)
0 = power down the PLL via the SPI (RST_CHIPEN_FROM_SPI),
Register 0x01[1]
1 R/W RST_CHIPEN_FROM_SPI 1 1 PLL enable bit of the SPI
9:2 R/W Reserved 8 0 Reserved
REFERENCE DIVIDER (REFDIV), INTEGER, AND FRACTIONAL FREQUENCY REGISTERS

Table 17. Register 0x02, REFDIV Register (Default 0x000001)
13:0 R/W RDIV 14 1 Reference divider R value (see Equation 12). Using the divider requires the reference path
buffer to be enabled (Register 0x08[3] = 1). 1d ≤ RDIV ≤ 16,383d.
Table 18. Register 0x03, Frequency Register, Integer Part (Default 0x000019)
18:0 R/W INTG_REG 19 25d Integer divider register. These bits are the VCO divider integer part, used in
all modes (see Equation 12).
Fractional mode.
Maximum 219 − 4 = 0x7FFFC = 524,284d.
Integer mode.
Minimum 16d.
Maximum 219− 1 = 0x7FFFF = 524,287d.
Table 19. Register 0x04, Frequency Register, Fractional Part (Default 0x000000)
23:0 R/W FRAC 24 0 VCO divider fractional part (24-bit unsigned); see the Fractional Frequency Tuning section.
These bits are used in fractional mode only (NFRAC = Register 0x04/224). Minimum = 0d;
maximum = 224 − 1.
HMC832A Data Sheet
VCO SPI REGISTER Register 0x05 is a read/write register. However, Register 0x05
Register 0x05 is a special register used for indirect addressing of holds only the contents of the last transfer to the VCO subsystem.
the VCO subsystem. Writes to Register 0x05 are automatically Therefore, it is not possible to read the full contents of the VCO
forwarded to the VCO subsystem by the VCO SPI state subsystem. Only the content of the last transfer to the VCO
machine controller. subsystem can be read. For autocalibration, Register 0x05[6:0]
must be set to 0.
Table 20. Register 0x05, VCO SPI Register (Default 0x000000)
2:0 R/W VCO_ID 3 0 Internal VCO subsystem ID.
6:3 R/W VCO_REGADDR 4 0 VCO subsystem register address. These bits are for interfacing with the VCO. See the
VCO Serial Port Interface (VSPI) section.
15:7 R/W VCO_DATA 9 0 VCO subsystem data. These bits are used to write the data to the VCO subsystem.
Σ-Δ CONFIGURATION REGISTER

Table 21. Register 0x06, Σ-Δ Configuration Register (Default 0x200B4A)
Bit Type Name Width Default Description
1:0 R/W Seed 2 2 Selects the seed in fractional mode. Writes to this register are stored in the
HMC832A and are loaded into the modulator only when a frequency change is
executed and when Register 0x06[8] = 1.
0: 0 seed.
1: LSB seed.
2: 0xB29D08 seed.
3: 0x50F1CD seed.
6:2 R/W Reserved 5 18d Reserved.
7 R/W FRAC_BYPASS 1 0 Bypass fractional mode. In the bypass fractional modulator, the output is ignored,
but fractional modulator continues to be clocked when SD enable = 1. Use this
bit to test the isolation of the digital fractional modulator from the VCO output in
integer mode.
0: use modulator, required for fractional mode
1: bypass modulator, required for integer mode.
10:8 R/W Initialization 3 3d Program to 7d.
11 R/W SD enable This bit controls whether autocalibration starts on an integer or a fractional write.
1 1 0: disables fractional core, use for integer mode or integer mode with CSP.
1: enables fractional core (required for fractional mode), or integer isolation
testing.
20:12 R/W Reserved 9 0 Reserved.
21 R/W Automatic clock 1 1 Program to 0.
configuration
22 R/W Reserved 1 0 Reserved.
Data Sheet HMC832A
LOCK DETECT REGISTER
Table 22. Register 0x07, Lock Detect Register (Default 0x00014D)
2:0 R/W LKD_WINCNT_MAX 3 5d The lock detect window sets the number of consecutive counts of the
divided VCO that must be within the lock detect window to declare lock
0: 5
1: 32
2: 96
3: 256
4: 512
5: 2048
6: 8192
7: 65,535
3 R/W Enable internal lock 1 1 See the Serial Port section
detect
6 R/W Lock detect window 1 1 Lock detection window timer selection
type 1: digital programmable timer
0: analog one shot, nominal 10 ns window
9:7 R/W LD digital window 3 2 Lock detection, digital window duration
duration 0: half cycle
1: one cycle
2: two cycles
3: four cycles
4: eight cycles
5: 16 cycles
6: 32 cycles
7: 64 cycles
11:10 R/W LD digital timer 2 0 Lock detect digital timer frequency control (see the Lock Detect section for
frequency control more information)
00: fastest
11: slowest
12 R/W Reserved 31 0 Reserved
13 R/W Automatic relock: one 1 0 1: attempts to relock if the lock detect fails for any reason; tries one time
try only
ANALOG ENABLE (EN) REGISTER

Table 23. Register 0x08, Analog EN Register (Default 0xC1BEFF)
0 R/W BIAS_EN 1 1 Enables main chip bias reference
1 R/W CP_EN 1 1 Charge pump enable
2 R/W PD_EN 1 1 PD enable
3 R/W REFBUF_EN 1 1 Reference path buffer enable
4 R/W VCOBUF_EN 1 1 VCO path RF buffer enable
5 R/W GPO_PAD_EN 1 1 0: disables the LD/SDO pin
1: enables the GPO port or allows a shared SPI
When Bit 5 = 1 and Register 0xF[7] = 1, the LD/SDO pin is always driven, which
is required for use of the GPO port
When Bit 5 = 1 and Register 0xF[7] = 0, SDO is off when an unmatched chip
address is seen on the SPI, allowing a shared SPI with other compatible
devices
9:6 R/W Reserved 4 11d Reserved
HMC832A Data Sheet
10 R/W VCO buffer and 1 1 VCO buffer and prescaler bias enable
prescaler bias enable
21 R/W High frequency 1 0 Program to 1 for 200 MHz to 350 MHz operation; program to 0 for <200 MHz
reference
CHARGE PUMP REGISTER

Table 24. Register 0x09, Charge Pump Register (Default 0x403264)
6:0 R/W CP down gain 7 100d, Charge pump down gain control, 20 µA per step. Affects fractional
0x64 phase noise and lock detect settings.
0d = 0 µA.
1d = 20 µA.
2d = 40 µA.
…
127d = 2.54 mA.
13:7 R/W CP up gain 7 100d, Charge pump up gain control, 20 µA per step. Affects fractional phase
0x64 noise and lock detect settings.
0d = 0 µA.
1d = 20 µA.
2d = 40 µA.
…
127d = 2.54 mA.
20:14 R/W Offset magnitude 7 0 Charge pump offset control, 5 µA per step. Affects fractional phase
noise and lock detect settings.
0d = 0 µA.
1d = 5 µA.
2d = 10 µA.
…
127d = 635 µA.
21 R/W Offset up enable 1 0 Recommended setting = 1 in fractional mode, 0 otherwise.
22 R/W Offset down enable 1 1 Recommended setting = 0.
AUTOCALIBRATION REGISTER
Table 25. Register 0x0A, VCO Autocalibration Configuration Register (Default 0x002205)
2:0 R/W VTUNE resolution 3 5 R divider cycles
0: 1 cycle
1: 2 cycles
2: 4 cycles
…
7: 256 cycles
9:3 R/W Reserved 7 64d Program 8d
10 R/W Force curve 1 0 Program 0
11 R/W Autocalibration disable 1 0 Program 0 for normal operation using VCO autocalibration
12 R/W No VSPI trigger 1 0 0: normal operation
1: this bit disables the serial transfers to the VCO subsystem (via
Register 0x05)
Data Sheet HMC832A
14:13 R/W FSM/VSPI clock select 2 1 These bits set the autocalibration FSM and VSPI clock (50 MHz
maximum)
0: input crystal reference
1: input crystal reference divide by 4
PHASE DETECTOR (PD) REGISTER

Table 26. Register 0x0B, PD Register (Default 0x0F8061)
2:0 R/W PD_DEL_SEL 3 1 Sets the PD reset path delay (recommended setting is 001).
4:3 R/W Reserved 2 0 Reserved.
5 R/W PD_UP_EN 1 1 Enables the PD up output.
6 R/W PD_DN_EN 1 1 Enables the PD down output.
8:7 R/W CSP mode 2 0 Cycle slip prevention mode. This delay varies by ±10% with temperature and ±12%
with process. Extra current is driven into the loop filter when the phase error is larger
than the following:
0 = disabled.
1 = 5.4 ns.
2 = 14.4 ns.
3 = 24.1 ns.
9 R/W Force CP up 1 0 Forces CP up output to turn on; use for test only.
10 R/W Force CP 1 0 Forces CP down output to turn on; use for test only.
down
21:11 R/W Reserved 13 496d Reserved.
(0x1F0)
22 R/W SPI voltage 1 0 LD/SDO pin voltage drive level.
level 0: 1.8 V SPI mode.
1: 3.3 V SPI mode.
EXACT FREQUENCY MODE REGISTER

Table 27. Register 0x0C, Exact Frequency Mode Register (Default 0x000000)
13:0 R/W Number of 14 0 The comparison frequency divided by the correction rate must be an integer.
Channels per fPD Frequencies at exactly the correction rate have zero frequency error.
0: disabled.
1: disabled.
2:16383d (0x3FFF).
HMC832A Data Sheet
GENERAL-PURPOSE, SPI, AND REFERENCE DIVIDER (GPO_SPI_RDIV) REGISTER
Table 28. Register 0x0F, GPO_SPI_RDIV Register (Default 0x000001)
4:0 R/W GPO_SELECT 5 1d The signal selected by this bit is an output to the LD/SDO pin when
the LD/SDO pin is enable via Register 0x08[5]
0: data from Register 0x0F[5]
1: lock detect output
2: lock detect trigger
3: lock detect window output
4: ring oscillator test
5: pull-up resistor is ~230 Ω from CSP
6: pull-down resistor is ~230 Ω from CSP
7: reserved
8: reference buffer output
9: reference divider output
10: VCO divider output
11: modulator clock from VCO divider
12: auxiliary clock
13: auxiliary SPI clock
14: auxiliary SPI enable
15: auxiliary SPI data output
16: PD down
17: PD up
18: internal clock path (SD3) clock delay
19: SD3 core clock
20: autostrobe integer write
21: autostrobe fractional write
22: autostrobe auxiliary SPI
23: SPI latch enable
24: VCO divider sync reset
25: seed load strobe
26 to 29: not used
30: SPI output buffer enable
31: soft reset, RST
5 R/W GPO test data 1 0 1: GPO test data
6 R/W Prevent automux SDO 1 0 1: outputs GPO data only
0: automuxes between SDO and GPO data
7 R/W LDO driver always on 1 0 1: LD/SDO pin driver always on
0: LD/SDO pin driver only on during SPI read cycle
8 R/W Disable PFET 1 0 0: enable LD/SDO pin high drive
1: disable LD/SDO pin high drive
9 R/W Disable NFET 1 0 0: enable LD/SDO pin low drive
1: disable LD/SDO pin low drive
Data Sheet HMC832A
VCO TUNE REGISTER
The VCO tune register is a read only register.
Table 29. Register 0x10, VCO Tune Register (Default 0x000020)

7:0 R VCO switch 8 32 Indicates the VCO switch setting selected by the autocalibration state machine to
setting yield the nearest free running VCO frequency to the desired operating frequency. Not
valid when Register 0x10[8] = 1, autocalibration busy. When a manual change is made
to the VCO switch settings, this register does not indicate the current VCO switch
position. VCO subsystems may not use all the MSBs, in which case the unused bits are
don’t care bits.
0 = highest frequency.
1 = second highest frequency.
…
255 = lowest frequency.
8 R Autocalibration 1 0 Busy when the autocalibration state machine is searching for the nearest switch
busy setting to the requested frequency.
SUCESSIVE APPROXIMATION REGISTER

The successive approximation register (SAR) is a read only register.
Table 30. Register 0x11, Successive Approximation Register (Default 0x07FFFF)

18:0 R SAR error magnitude counts 19 219 to 1 SAR error magnitude counts
19 R SAR error sign 1 0 SAR error sign
0 = error is positive
1 = error is negative
GENERAL-PURPOSE 2 REGISTER
The GPO2 register is a read only register.
Table 31. Register 0x12, GPO2 Register (Default 0x000000)

0 R GPO 1 0 GPO state
1 R Lock detect 1 0 Lock detect status
1 = locked
0 = unlocked
BUILT-IN SELF TEST (BIST) REGISTER

The BIST register is a read only register.
Table 32. Register 0x13, BIST Register (Default 0x001259)

16:0 R Reserved 17 4697d Reserved
HMC832A Data Sheet
VCO SUBSYSTEM REGISTER MAP

The VCO subsystem uses indirect addressing via Register 0x05. For more detailed information on how to write to the VCO subsystem,
see the VCO Serial Port Interface (VSPI) section.
The VCO tuning register is write only.
Table 33. VCO_REG 0x00, Tuning Register

0 W CAL 1 0 VCO tune voltage is redirected to a temperature compensated
calibration voltage
8:1 W CAPS 8 16 VCO subband selection
0000 0000: maximum frequency
1111 1111: minimum frequency
VCO ENABLE REGISTER

The VCO enable register is a write only register.
Table 34. VCO_REG 0x01, Enable Register

0 W Master enable VCO subsystem 1 1 0: all VCO subsystem blocks are turned off.
1 W VCO enable 1 1 Enables VCOs.
2 W PLL buffer enable 1 1 Enables PLL buffer to N divider.
3 W Input/output master enable 1 1 Enables output stage and the output divider. It does not enable/disable
the VCO.
4 W Reserved 1 1 Reserved.
5 W Output stage enable 1 1 Output stage enable.
7:6 W Reserved 2 3 Reserved.
Example: Disabling the Output Stage of the VCO Subsystem

To disable the output stage of the VCO subsystem of the HMC832A, clear Bit 5 in VCO_REG 0x01. If the other bits are left unchanged,
write 1 1101 1111 into VCO_REG 0x01. The VCO subsystem register is accessed via a write to PLL subsystem Register 0x05 = 1 1101
1111 0001 00 = 0xEF88.
Register 0x05[2:0] = 000b; VCO subsystem ID 0.
Register 0x05[6:3] = 0001b; VCO subsystem register address.
Register 0x05[7] = 1b; master enable.
Register 0x05[8] = 1b; VCO enable.
Register 0x05[9] = 1b; PLL buffer enable.
Register 0x05[10] = 1b; I/O master enable.
Register 0x05[11] = 1b; reserved.
Register 0x05[12] = 0b; disable the output stage.
Register 0x05[14:13] = 11b; reserved.
Register 0x05[15] = 1b; don’t care.
Data Sheet HMC832A
VCO OUTPUT DIVIDER REGISTER
This is a write only register. To write 0 1111 1110 into VCO_REG 0x02 (VCO_ID = 000b) and set the VCO output divider to divide by 62,
the following must be written to Register 0x05 = 0 1111 1110 0010 000:
Register 0x05[2:0] = 000; Subsystem ID 0
Register 0x05[6:3] = 0010; VCO Register Address 2d.
Register 0x05[16:7] = 0 1111 1110; divide by 62, maximum output RF gain.
Table 35. VCO_REG 0x02, Output Divider Register

5:0 W RF divide ratio 6 1 0: mutes the output when VCO_REG 0x03[8:7] = 0d
1: fO
2: fO/2
3: invalid, defaults to 2
4: fO/4
6: fO/6
…
60: fO/60
62: fO/62 > 62 invalid, defaults to 62
8:6 W Reserved 3 0 Reserved
VCO CONFIGURATION REGISTER

The VCO configuration register is a write only register.
Table 36. VCO_REG 0x03, Configuration Register

1:0 W Programmable 2 2 Selects the output noise floor performance level at a cost of increased
performance mode current consumption.
01: low current consumption mode.
11: high performance mode.
Other states (00 and 10) not supported.
2 W RF_N output enable 1 0 Enables the output on RF_N pin. Required for differential operation, or
single-ended output on the RF_N pin.
3 W RF_P output enable 1 0 Enables the output on RF_P pin. Required for differential operation, or
single-ended output on the RF_P pin.
5 W Return loss 1 0 0: return loss = −5 dB typical (highest output power).
1: return loss = −10 dB typical.
8:7 W Mute mode 2 1 Defines when the mute function is enabled (the output is muted), see
the VCO Output Mute Function section and Figure 35 for more
information.
00: enables mute when the divide ratio, VCO_REG 0x02[5:0] = 0. This
enables the HMC832A to be backward compatible to the HMC830 mute
function.
01: during VCO calibration (see the VCO Calibration section for more
details).
10: not supported.
11: mute all RF outputs (unconditional).
HMC832A Data Sheet
VCO CALIBRATION/BIAS, CENTER FREQUENCY CALIBRATION (CF_CAL), AND MSB CALIBRATION REGISTERS
These registers are write only. Specified performance is only guaranteed with the required settings in Table 37 only; other settings are not
supported.
Table 37. VCO_REG 0x04, Calibration/Bias Register

0 W Initialization 9 201d Reserved
Table 38. VCO_REG 0x05, CF_CAL Register

8:0 W Reserved 9 170d Reserved
Table 39. VCO_REG 0x06, MSB Calibration Register

8:0 W Reserved 9 255d Reserved
VCO OUTPUT POWER CONTROL

The VCO power control register is write only.
Table 40. VCO_REG 0x07, Output Power Control Register

3:0 W Output stage gain control 4 1 Output stage gain control in 1 dB steps
0d: 0 dB gain
1d: 1 dB gain
2d: 2 dB gain
…
10d: 10 dB gain
11d: 11 dB gain
4 W Initialization 1 0 Program to 1d
8:5 W Reserved 4 4d Program to 4d
Data Sheet HMC832A
EVALUATION PRINTED CIRCUIT BOARD (PCB)

The circuit board used in the application uses RF circuit design Figure 54. Use a sufficient number of via holes to connect the
techniques. Signal lines have 50 Ω impedance, whereas the top and bottom ground planes. The evaluation circuit board
package ground leads and exposed pad are connected directly shown Figure 53 and Figure 54 is available from Analog Devices
to the ground plane similar to that shown in Figure 53 and upon request.
GND 5.5V C40 R1 USB
TP3 C5 R28
TP2 C47
C8
R27 C54 R46
AD4
R11 C48
SDI
SDO
C53
R29 C39
R12
C56 R49
SEN
SCK
R41
U4
C51
R47
R40
C11
C6
U1
C12 R5 TP1
R13 C41 LOCK DETECT
R9 R8
R14
R6 C55
P C9
R7
R10
R48
R45 C49
C42 C52
C50
C16
C14
C15
JP5 JP4 JP3 JP2
C10
R15
C13 J3
C19 U2
C18
R50 C17
C46
HMC832A
VCCCP
+3.3V
VCC1
C7
TPLL/TCXO L1
LOT XXX
R16
SW1 C21 C26
D0 C25
C23
C24
C20
R37 C27
R39
R22 C22
R43
D1 C28
N
R35 C33
R44
C34 R18 J4
C31
C32
R19
R42
C29 R33 R26 R21 JP1
C44 R32 C35
600-00581-00-1
TP4
C45 Y1
R17
J5 REF IN U3 C30 R34 R23 C37

GND
R20
R36
R25
R24
C38
R38
R31
TP5
13110-039
D1
Figure 53. Silkscreen and PCB Traces Top Layer
J7
C1
C4
C2
R2
R3
C3
R4
R30
A1
C43
C36
13110-139
Figure 54. Silkscreen and PCB Traces Bottom Layer
HMC832A Data Sheet
CHANGING EVALUATION BOARD REFERENCE For evaluation purposes, the HMC832A evaluation board is
FREQUENCY AND CP CURRENT CONFIGURATION shipped with an on-board, low cost, low noise (100 ppm),
50 MHz VCXO, enabling evaluation of most parameters
The evaluation board is provided with a 50 MHz on-board
including phase noise without any external references.
reference oscillator, and Type 1 loop filter configuration, as
shown in Figure 52 (~127 kHz bandwidth, see Table 13). Exact phase or frequency measurements require the HMC832A
to use the same reference as the measuring instrument. To
The default register configuration file included in the Analog
accommodate this requirement, the HMC832A evaluation
Devices PLL evaluation software sets the comparison frequency
board includes the HMC1031; a simple low current integer-N
to 50 MHz (R = 1, that is, Register 0x02 = 1).
PLL that can lock the on-board VCXO to an external 10 MHz
As with all PLLs and PLL with integrated VCOs, modifying the reference input commonly provided by most test equipment. To
comparison frequency or CP current results in changes to the lock the HMC832A to an external 10 MHz reference, connect
loop dynamics and ultimately, phase noise performance. When the external reference output to the J5 input of the HMC832A
making these changes, keep in mind the following: evaluation board and change the HMC1031 integer divider value
• CP offset current setting. Refer to the Charge Pump (CP) to 5 by changing the switch settings, D1 = 1 (SW1 to SW4
and Phase Detector (PD) section. closed), and D0 = 0 (SW2 to SW3 open). For more information,
• LD configuration. Refer to the Lock Detect section. see the HMC1031 data sheet.
To redesign the loop filter for a particular application, EVALUATION KIT CONTENTS
download the PLL design software tool, ADIsimPLL™. The The evaluation kit contains one EV1HMC832ALP6G
Analog Devices PLL design enables users to accurately model evaluation PCB, a USB interface board, a six-foot USB Type A
and analyze performance of all Analog Devices PLLs, PLLs with male to USB Type B female cable, a CD ROM that contains the
integrated VCOs, and clock generators. It supports various loop user manual, evaluation PCB schematic, evaluation software,
filter topologies, and enables users to design custom loop filters and Analog Devices PLL design software. To order the evaluation
and accurately simulate resulting performance. For more kit, see the Ordering Guide section for the product number.
information, see the Loop Filter and Frequency Changes
section.
Data Sheet HMC832A
OUTLINE DIMENSIONS
6.10 0.30
6.00 SQ 0.25
PIN 1 5.90 0.20 PIN 1
INDICATOR INDICATOR
31 40
30 1
0.50
BSC 4.75
EXPOSED
PAD 4.70 SQ
4.65
21
10
11
0.35 20
0.20 MIN
TOP VIEW 0.30 BOTTOM VIEW
0.25 4.50 REF
0.90
0.85 FOR PROPER CONNECTION OF
0.05 MAX THE EXPOSED PAD, REFER TO
0.80
0.02 NOM THE PIN CONFIGURATION AND
COPLANARITY FUNCTION DESCRIPTIONS
0.08 SECTION OF THIS DATA SHEET.
SEATING 0.20 REF
PLANE
03-31-2015-A
COMPLIANT TO JEDEC STANDARDS MO-220
Figure 55. 40-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

6 mm × 6 mm Body, Very Thin Quad
(HCP-40-1)
Dimensions shown in millimeters
04-01-2015-A
Figure 56. Tape and Reel Outline Dimensions

Dimensions shown in millimeters
HMC832A Data Sheet
ORDERING GUIDE
Lead MSL Temperature Package
Model1 Finish Rating Range Package Description Option Qty. Brand2
HMC832ALP6GE 100% MSL1 −40°C to +85°C 40-Lead Lead Frame Chip Scale HCP-40-1 H 832 A
matte Sn Package [LFCSP_VQ] XXXX
HMC832ALP6GETR 100% MSL1 −40°C to +85°C 40-Lead Lead Frame Chip Scale HCP-40-1 500 H 832 A
matte Sn Package [LFCSP_VQ], 7” Tape and Reel XXXX
EK1HMC832ALP6G Evaluation Kit
EV1HMC832ALP6G Evaluation Board
1
E = RoHS Compliant Part.
2
Four-digit lot number XXXX.
©2015 Analog Devices, Inc. All rights reserved. Trademarks and

registered trademarks are the property of their respective owners.
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25 MHz to 3000 MHz

Fractional-N PLL with Integrated VCO

24-bit step size, 3 Hz typical resolution

Fast frequency hopping ÷1, 2, 4, 6, ...62

40-lead, 6 mm × 6 mm LFCSP package: 36 mm2

CATV equipment Figure 1.

Rev. B Document Feedback

General Description ......................................................................... 1 VCO SPI Register ....................................................................... 36

Revision History ............................................................................... 2 Σ-Δ Configuration Register ...................................................... 36

Specifications..................................................................................... 3 Lock Detect Register .................................................................. 37

Timing Specifications .................................................................. 6 Analog Enable (EN) Register .................................................... 37

Absolute Maximum Ratings ............................................................ 7 Charge Pump Register ............................................................... 38

Recommended Operating Conditions ...................................... 7 Autocalibration Register............................................................ 38

ESD Caution .................................................................................. 7 Phase Detector (PD) Register ................................................... 39

Typical Performance Characteristics ............................................. 9 General-Purpose, SPI, and Reference Divider

250 kHz Offset fO13 Over manufacturing process variations with

ABSOLUTE MAXIMUM RATINGS

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

Figure 2. Pin Configuration

Table 6. Pin Function Descriptions

TYPICAL PERFORMANCE CHARACTERISTICS

PHASE NOISE (dBc/Hz)

PHASE NOISE (dBc/Hz)

PHASE NOISE (dBc/Hz)

–100 –130 ÷16

LOW CURRENT MODE ÷32

–160 HIGH PERFORMANCE MODE –160

1k 10k 100k 1M 10M 100M 1k 10k 100k 1M 10M 100M

PHASE NOISE (dBc/Hz)

PHASE NOISE (dBc/Hz)

HIGH PERFORMANCE MODE (VCO_REG 0x03[10] = 3d)

LOW CURRENT MODE (VCO_REG 0x03[10] = 1d)

INTEGRATION BANDWIDTH = 1kHz TO 100MHz

SNR = 52.6dB, EVM = 0.234%, PHASE NOISE

HIGH PERFORMANCE MODE (VCO_REG 0x03[10] = 3d)

1k 10k 100k 1M 10M 100M 1k 10k 100k 1M 10M 100M

PHASE NOISE (dBc/Hz)

–150 55.55MHz OUTPUT

PHASE NOISE (dBc/Hz)

1k 10k 100k 1M 10M 100M 2000.01 2000.1 2001

–80 –120 100MHz OFFSET

1k 10k 100k 1M 10M 100M 30 100 300 1000 3000

ERROR VECTOR MAGNITUDE (EVM) (%)

NORMALIZED PHASE NOISE (dBc/Hz)

–80 0.0141 –230

PHASE NOISE INTEGRATED FROM 10kHz TO 20MHz

25 100 1000 3000 25 100 1000 3000

RETURN LOSS (dB)

0 2 4 6 8 10 25 100 1000 8000

PHASE ERROR (Degrees)

SETTLING TIME TO <10°

SETTLING TIME TO <10°

PHASE ERROR (Degrees)

0 20 40 60 80 100 120 140 160 0 20 40 60 80 100 120 140 160

CURRENT CONSUMPTION (mA)

190 LOW CURRENT

222 14MHz SQUARE WAVE 205

–15 –12 –9 –6 –3 0 3 –20 –15 –10 –5 0 5

MUTE ON (VCO_REG 0x03[8:7] = 3d)