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MOHAMMED SATHAK A J COLLEGE OF ENGINEERING
Siruseri IT park, OMR, Chennai - 603103
LESSON PLAN Department of CSE and IT Name of the Name of the DIGITAL PRINCIPLES AND handling JAYANTHI.E & Mrs.S.ANUSUYA Subject COMPUTER Faculty ORGANIZATION Subject Code CS3351 Year / Sem II/ III Acad Year 2022-2023 Batch 2021- 2025 Course Objective To analyze and design combinational circuits
To analyze and design sequential circuits
To understand the basic structure and operation of a digital computer To study the design of data path unit, control unit for processor and to familiarize with the hazards To understand the concept of various memorieas and I/O interfacing Course Outcome CO1:Design various combinational digital circuits using logic gates CO2:Design sequential circuits and analyze the design procedures CO3:State the fundamentals of computer systems and analyze the execution of an instruction CO4:Analyze different types of control design and identify hazards CO5:Identify the characteristics of various memory systems and I/O communication Lesson Plan T / R* Perio Mode of ds Teaching (BB / Blooms Level Sl. No. Topic(s) CO PO Book Requ PPT / NPTEL / (L1-L6) ired MOOC / etc ) UNIT I - COMBINATIONAL LOGIC 1 Combinational Circuits T1 1 BB L2 CO1 PO1,PO2,PO3,PO4,PO5 2 K-map simplifications T1 1 BB L3 CO1 PO1,PO2,PO3,PO4,PO5
implementation of 15 T1 4 DEMO L3 CO1 PO1,PO2,PO3 combinational circuits using gates for arbitrary functions. Lab session-Implementation of 4- bit binary adder/subtractor circuits. 19 T1 4 DEMO L3 CO1 PO1,PO2,PO3
Lab Session-Implementation 21 T1 2 DEMO L3 CO1 PO1,PO2,PO3 of code converters. Lab Session-Implementation of 25 BCD adder, encoder and T1 4 DEMO L3 CO1 PO1,PO2,PO3 decoder circuits Lab Session-Implementation 27 T1 2 DEMO L3 CO1 PO1,PO2,PO3 of functions using Multiplexers. Suggested Activity: Assignment / Case Studies / Tutorials/ Quiz / Mini Projects / Model Developed/others Planned if any DESIGN AND CRITICAL THINKING Evaluation method : MARKS WILL BE GIVEN BASED ON THEIR PRESENTATION UNIT II -SYNCHRONOUS SEQUENTIAL LOGIC
28 Introduction to sequential circuits T1 1 BB L2 CO2 PO1,PO2,PO3,PO4,PO5
Flip flops- operation and excitation
29 T1 1 BB L2 CO2 PO1,PO2,PO3,PO4,PO5 table 30 Triggering of FF T1 1 BB L2 CO2 PO1,PO2,PO3 Analysis and design of clocked 31 T1,R1 1 BB L2 CO2 PO1,PO2,PO3,PO4,PO5 sequential circuits 32 Design- moore/ mealy models T1 1 BB L4 CO2 PO1,PO2,PO3,PO4,PO5 State minimization and State 33 T1 1 BB L3 CO2 PO1,PO2,PO3,PO4,PO5 assignment 34 Circuit implementation T1,R1 1 BB L3 CO2 PO1,PO2,PO3,PO4,PO5 35 Registers T1 1 BB L2 CO2 PO1,PO2,PO3,PO4,PO5
36 Counters T1 1 BB L2 CO2 PO1,PO2,PO3,PO4,PO5
Lab session-Implementation of the
42 T1 6 DEMO L3 CO2 PO1,PO2,PO3 synchronous counters Lab sessiojn-Implementation of a 46 T1 4 DEMO L3 CO2 PO1,PO2,PO3 Universal Shift register Suggested Activity: Assignment / Case Studies / Tutorials/ Quiz / Mini Projects / Model Developed/others Planned if any ASSIGNMENT-PROBLEMS BASED ON COUNTER DESIGN. Evaluation method : Marks will be awarded based on their performance. UNIT III- COMPUTER FUNDAMENTALS Functional units of a digital 47 T1 1 BB L2 CO3 PO1,PO2 computer 48 Von Neumann Architecture T1,R1 1 BB L2 CO3 PO1,PO2 operation and operands of 49 T1 1 BB L2 CO3 PO1,PO2,PO4,PO5 computer hardware instructions 50 Instruction set architecture(ISA) T1 1 BB L2 CO3 PO1,PO2,PO4,PO5,PO10 Memmory location, Address and 51 T1 1 BB L2 CO3 PO1,PO2 operation Instruction and Instruction PO1,PO2,PO4,PO5,PO9,PO10,PO 52 T1,R1 1 BB L2 CO3 sequencing 11,PO12 53 Addressing modes T1 1 BB L2 CO3 PO1,PO2 PO1,PO2,PO4,PO5,PO9,PO10,PO 54 Encoding of machine instruction T1 1 BB L2 CO3 11,PO12 Interaction between Assembly and PO1,PO2,PO4,PO5,PO9,PO10,PO 55 T1 1 BB L2 CO3 high level language 11,PO12 Lab session-Simulator based study 57 T2 2 PPT L2 CO3 PO1,PO2 of Computer Architecture Suggested Activity: Assignment / Case Studies / Tutorials/ Quiz / Mini Projects / Model Developed/others Planned if any QUIZ
Evaluation method : Marks will be given based on their responses
66 Control Hazards R2 1 BB L2 CO4 PO1,PO2,PO3,PO4,PO5
Suggested Activity: Assignment / Case Studies / Tutorials/ Quiz / Mini Projects / Model Developed/others Planned if any MIND MAPPING Evaluation method : Marks will be awarded based on their responses.
PO1,PO2,PO4,PO5,PO9,PO10,PO 73 parallel and serial interface R1 1 BB L2 CO5 11,PO12 74 Interrupt I/O R1 1 BB L2 CO5 PO1,PO2,PO3,PO4,PO5 Interconnection standards:USB PO1,PO2,PO4,PO5,PO9,PO10,PO 75 R1 1 BB L2 CO5 ,SATA 11,PO12 Suggested Activity: Assignment / Case Studies / Tutorials/ Quiz / Mini Projects / Model Developed/others Planned if any CASE STUDY
Evaluation method : Marks will be given based on their presentation
Content Beyond the Syllabus Planned
1 Combinational circuits using Verilog HDL
2 ARM Processor Text Books arson Education, 2018 1 M. Morris Mano, Michael D. Ciletti, “Digital Design : With an Introduction to the Verilog HDL, VHDL, and System Verilog”, Sixth Edition, 2 Pe . David A. Patterson, John L. Hennessy, “Computer Organization and Design, The Hardware/Software Interface”, Sixth Edition, Morgan Reference Books aw-Hill, 2012. 1 Carl Hamacher, Zvonko Vranesic, Safwat Zaky, Naraig Manjikian, “Computer Organization and Embedded Systems”, Sixth Edition, Tata 2 McGr William Stallings, “Computer Organization and Architecture – Designing for Performance”, Tenth Edition, Pearson Education, 2016. 3 M. Morris Mano, “Digital Logic and Computer Design”, Pearson Education, 2016. Website / URL References 1 https://nptel.ac.in/courses/117106086
2 https://ieeexplore.ieee.org/document/1463186
3 https://www.youtube.com/watch?v=AtfXJ0PNesk
Blooms Level Fixed Level 1 ( L1 ) : Remembering Lower Level 4 (L4) : Analysing Order Lower Hour Level 5 (L5) : Evaluating Order Higher Order Projects / Mini Projects Level 2 (L2) : Understanding Thinkin Exa Thinki Thinking g Level 3 (L3) : Applying ms Level 6 (L6) : Creating ng Mapping syllabus with Bloom’s Taxonomy LOT and HOT Unit No Unit Name L1 L2 L3 L4 L5 L6 LOT HOT Total Unit 1 COMBINATIONAL LOGIC 0 7 20 0 0 0 27 0 27
CO PO Mapping PO1 PO2 PO3 PO4 PO5 PO6 PO7 PO8 PO9 PO10 PO11 PO12 PSO1 PSO2 PSO3 CO1 3 2 1 1 2 - - - 1 1 2 1 2 2 1 CO2 2 2 1 2 2 - - - 1 1 1 2 2 2 2 CO3 2 1 - 1 1 - - - 2 1 1 2 2 3 1 CO4 2 2 1 2 2 1 1 - 1 2 1 3 2 2 3 CO5 3 2 2 1 2 - - - 1 1 2 2 3 3 2 Avg 2 2 1 1 2 1 1 - 1 1 1 2 2 2 2 Justification for CO-PO mapping PO1(3) Graduates will learn the basic knowledge of Boolean theorems,PO2(2) Graduates will able to analyze the k-map CO1 in the combinational circuits,PO12(1),Graduates will be able to upgrades their knowledge in design of digital circuits by life long learning PO1(2) Graduates will be learn the concept of synchronous sequential circuits,PO3(1) Graduates will able to analyze the CO2 design of counters and registers ,PO5(2),Graduates will be able to use modern tools usage in Verilog HDL. PO3(1) Graduates will be able identify the architedctures in computer , PO9(2) Graduates will able to slightly gain CO3 the contextual knowledge.PO11(2) Graduates will be able to demonstarte knowledge between high level and assembly level language program. PO4(2) Graduates will be able analyse the processor.PO6(1) Graduates will be able to understand the contextual CO4 knowledge in control unit. PO2(2) Graduates will be able to formulate the memory and their hierarchy . PO7(1) Graduates will able to know the need of CO5 memory management in a processor..PO12(1) Graduates will be able to learn interconnection standards by life long learning. 3 High level 2 Moderate level 1 Low level
Name & Sign of Faculty Incharge :Jayanthi.E & Mrs.S.Anusuya
Name & Sign of Subject Expert : Head of the Department : Format No :231
