ZCU670 Evaluation Board

IBERT Example Design

XTP693 (v1.0) April 27, 2022

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Table of Contents
Table of Contents ...................................................................................................................................... 2
Introduction .............................................................................................................................................. 3
Overview ................................................................................................................................................... 3
Navigating Content by Design Process...................................................................................................... 4
Additional Resources ................................................................................................................................ 4
ZCU670 Block Diagram ............................................................................................................................. 5
IBERT Overview ........................................................................................................................................ 6
ZCU670 Board Component Location ........................................................................................................ 9
Board Setup and Configuration............................................................................................................... 10
Standard ESD Measures ...................................................................................................................... 10
Switch Setup........................................................................................................................................ 11
Power .................................................................................................................................................. 11
JTAG .................................................................................................................................................... 11
Software Setup ........................................................................................................................................ 12
Vivado Download ................................................................................................................................ 12
Vivado Installation .............................................................................................................................. 12
Design Files ............................................................................................................................................. 12
Extract Archive .................................................................................................................................... 12
Review the provided design ................................................................................................................ 12
Design Arguments ............................................................................................................................... 13
Steps to Execute Design ...................................................................................................................... 14
Testing the Design ............................................................................................................................... 15
Appendix A .............................................................................................................................................. 20
Appendix B Xilinx Design Constraints...................................................................................................... 21
Appendix C .............................................................................................................................................. 22
Appendix D .............................................................................................................................................. 23
Appendix E Additional Resources and Legal Notices .............................................................................. 24
Xilinx Resources ...................................................................................................................................... 24
Documentation Navigator and Design Hubs........................................................................................... 24
References .............................................................................................................................................. 24
Revision History....................................................................................................................................... 25
Please Read: Important Legal Notices .................................................................................................... 26

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Introduction
Overview
The ZCU670 is an evaluation board featuring the ZU67DR Zynq® UltraScale+™ RFSoC DFE device. This
board enables the evaluation of applications requiring multi-band (sub-7 GHz, mmWave), multi-std
(5G, LTE, etc.), and multi-mode (TDD, FDD) radios, including Milcom and Satcom applications. The
ZCU670 board is equipped with all the common board-level features needed for design development,
such as DDR4 memory, networking interfaces, an FMC+ expansion port, as well as access to the RFMC
2.0 interface.

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Navigating Content by Design Process
Xilinx® documentation is organized around a set of standard design processes to help you find
relevant content for your current development task. This document covers the following design
processes:

• Board System Design: Designing a PCB through schematics and board layout. Also involves
power, thermal, and signal integrity considerations. For more information, see Versal ACAP
Design Process Documentation Board System Design.

Additional Resources
See Appendix E Additional Resources and Legal Notices for references to documents, files, and
resources relevant to the ZCU670 evaluation board.

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ZCU670 Block Diagram

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 IBERT Overview
The IBERT for UltraScale™ Architecture GTY Transceivers core provides a broad-based physical medium
attachment (PMA) evaluation and demonstration platform for UltraScale/UltraScale+™ architecture GTY
transceivers. Parameterizable to use different GTY transceivers and clocking topologies, the core can
also be customized to use different line rates, reference clock rates, and logic widths. Data pattern
generators and checkers are included for each GTY transceiver, giving several different pseudo-random
binary sequence (PRBS) and clock patterns to be sent over the channels.

After the script has been properly executed, the project for the IP customization (XCI) can be inspected
or manipulated. If this is modified, new scripts will need to be generated as this will invalidate any
generated designs. If your intention is to only inspect or manipulate the provided example design, it is
suggested to utilize the bd_only=true argument. This will cause the design to exit execution just
after the IP has been customized and XCI scripting has been created. More information can be found in
the Design Arguments and Steps to Execute Design sections.

The below design, generated by the scripting is a multipart design. This is done in this way to create a
clean and efficient separation between the IP and the Board level effort. This can be clearly understood.
To dive deeper into this design, in the ZCU670_IBERT Vivado instance, right click the
ibert_ultrascale_gty_0 design source and choose Re-customize IP…

Each tab contains various configuration options for the customized IP. The ZCU670 has a 156.25 Mhz
clock which is connected to the MGTREFCLK1 on Quad 127. Refer to the ZCU670 schematic pages 6,
35,38 for details.

Within the Protocol Definition tab, the IP has been customized with 25 Gbps LineRate as that utilizes
the default clocks properly. This IP has also been configured for multiple protocols to ease future
customization. Throughout this design, options will be selected for all lanes to utilize the same outputs.

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Note selections in Advanced Settings. The default values suffice for driving the design on the ZCU670.

Next, inspect the Protocol Selection tab.

The most important piece of this is the Refclk selection. Note that the IP has been selected to utilize the
same MGTREFCLK1 from Quad 127. This is possible as in this chip architecture, adjacent Quads can
utilize clocks from adjacent inputs. Refer to UltraScale Architecture GTY Transceivers User Guide
(UG578) for more information.

Next inspect the Clock Settings tab. Of note in this is the clock source selection. It has been selected to
utilize the MGTREFCLK1 from Quad 127. For other frequencies supported by the ZCU670 using the
included clock mux and generators, selecting the appropriate input clock is done here.

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For further information see the IBERT for UltraScale GTY Transceivers LogiCORE IP Product Guide
(PG196), which can also be accessed through DocNav as well as from the IP customization wizard

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ZCU670 Board Component Location

J29 Quad zSFP/zSFP+ connector

J24 JTAG micro-USB J50 Power connector

SW15 Power ON/OFF
J28 FMCP HSPC connector

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 Board Setup and Configuration
Standard ESD Measures

To prevent ESD damage:

• Attach a wrist strap to an unpainted metal surface of your hardware to prevent electrostatic
discharge from damaging your hardware.
• When you are using a wrist strap, follow all electrical safety procedures. A wrist strap is for static
control. It does not increase or decrease your risk of receiving electric shock when you are using or
working on electrical equipment.
• If you do not have a wrist strap, before you remove the product from ESD packaging and installing or
replacing hardware, touch an unpainted metal surface of the system for a minimum of five seconds.
• Do not remove the device from the antistatic bag until you are ready to install the device in the
system.
• With the device still in its antistatic bag, touch it to the metal frame of the system.
• Grasp cards and boards by the edges. Avoid touching the components and gold connectors on the
adapter.
• If you need to lay the device down while it is out of the antistatic bag, lay it on the antistatic bag.
Before you pick it up again, touch the antistatic bag and the metal frame of the system at the same
time.
• Handle the devices carefully to prevent permanent damage.

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Switch Setup
The Zynq UltraScale+ ZCU670 boot process is described in the “Boot Modes” section of the Zynq
UltraScale+ Device Technical Reference Manual (UG1085). The ZCU670 board supports a subset of the
modes documented in the technical reference manual via onboard boot options. The mode switch /
jumper configuration options for SW2is listed in the ZCU670 Evaluation Board User Guide (UG1532).
Jumpers / switches need to be configured in the default locations. Refer to the “Default Jumper and
Switch Settings” topic in ZCU670 Evaluation Board User Guide (UG1532) for the default jumper /
switch setting.

Power
12VDC Power needs to be provided using J50. Use only the suggested power supply to ensure
compatibility and to avoid damage.

Refer to ZCU670 Evaluation Board User Guide (UG1532) for Board Component Locations

JTAG
Using the included micro-USB 2.0 type-A cable, connect J24 to your PC. It is suggested to avoid USB
Hubs as well as extender cables. If using another JTAG interface, refer to that product user guide, as
well as ZCU670 Evaluation Board User Guide (UG1532) for configuration options.

Refer to ZCU670 Evaluation Board User Guide (UG1532) for Board Component Locations.

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Software Setup
Vivado Download
This design requires an install of Vivado. Vivado can be located at the AMD/Xilinx Support Downloads
site. This design REQUIRES version v2022.1. This design can be run from Vivado and Vivado ML
Edition. This design can also be run from Vivado included within other installations, such as a full Vitis
Installation.

Vivado Installation
For help with installation and licensing, refer to the Vivado Design Suite User Guide (UG973).

Design Files
Extract Archive
The source scripts are archived in rdf0624-zcu670-ibert-c-2021-2.zip. Extract these files to your hard
drive. It is advised to use C:\vivprj

Note: Under Windows, there is a possibility to run into a path length error. The directory names
suggested throughout are specifically chosen to maintain an organized design structure, yet work
within that limit. Caution is advised if you deviate from these instructions.
For further information see Answer Record 52787
Linux does not have this path limitation.

Review the provided design

Vivado provides multiple methods of executing a design. The design script has these functions in
mind, as it provides multiple paths of execution built in. This includes detecting if the design is being
executed from within the Vivado GUI, shell, or command line. Vivado acts as a middle layer
interpreting each of these across both Windows and Linux environments.

The design consists of multiple scripts that handle specific features. This can be summarized as a
donut structure.

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 VPK120_IBERT ZCU670_IBERT
make_[design]
VPK120_NoC ZCU670_DDR

VPK120_IPI ZCU670_IPI

etc etc

design design design design

support support support support
files files files files

This donut consists of a framework and a project design. This framework creates a uniform customer
experience across all designs giving a form/fit/function interface be the design IBERT, NOC/DDR, IPI,
etc. across any evaluation board. Customers can leverage this design as a guide to create scripted
flows along with other AMD/Xilinx guides. In some cases, the design incorporates a scripted interface
to the scripting flow for Vitis. This allows a seamless single command execution that provides in the
end a useable design, of course based on the arguments provided.

Within the script, there are many arguments that can augment the behavior of the script.

For this design, there are three files:

• make_ibert.tcl
o contains all the logic necessary to drive IBERT designs. This includes argument
checking, design flow as well as other administrative duties
o detects available processor capabilities to maximize design creation performance
o arguments listed below
• zcu670_ibert.tcl
o contains the scripting necessary to reproduce the Vivado design
o no arguments

Design Arguments
Arguments are not case sensitive. Arguments can be provided in any order.
• help
o Prints help to the screen
• prod=<product_short_name>
o This design defaults to ZCU670
• bd_only=true/{false}
o defaults to false
o Create design up to XCI Design and STOP
o Useful if manually setting values or customizing the design without waiting for
remainder of bitstream generation steps
• clean=true/{false}
o defaults to false
o Cleans design by effectively deleting the design
• version_override=true/{false}

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 o defaults to false
o Used to override the Version Check
o It is STRONGLY recommended to NOT use this
Note: See below for an example use of arguments when launching the design

Steps to Execute Design

Note: A base level of understanding is necessary to use any tool. Vivado is no exception. For
assistance with terminology or use of Vivado, it is suggested to read and understand the Vivado
Design Suite User Guide (UG910)
Vivado TCL Console
1. Open Vivado GUI by clicking on the Vivado icon to launch the tool

a.
2. Once open, in the TCL console, change directory to the c:\vivprj folder
a. cd {c:\vivprj}

b.
c.
3. Generating the entire design requires setting an argument. In batch mode, this is normally
accomplished through the -tclargs flag. While in the Vivado GUI, we need to set the argv
directly
set argv {prod=zcu670}

4. Execute the design

source ./make_ibert.tcl -notrace
i. Note: -notrace is used to keep the console reporting to a minimum
It can be beneficial to remove that for troubleshooting

5. Note as the script creates a new design targeting the ZCU670 Evaluation Platform
a. It is normal to see a wait box, such as the below indicating Vivado is busy

b. Once the Customized IP Design is complete, all necessary IP scripting is generated

Note: If bd_only=true argument is provided, the script will stop here allowing you
to manipulate the various pieces of the design

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 The script will create a new example IP located
./zcu670_ibert
If bd_only=true is not set, the script will also generate an example design located
./zcu670_ibert/ibert_ultrascale_gty_0_ex

c. Once the IP scripts are created, the Example Design script will command Vivado to
run the IP Generated script in a new Vivado instance, working through all steps in the
Navigation Flow, to bitstream generation. During this last stage, expect to see a
similar indicator until the bitstream has been created

Note: if background is selected, navigation is possible between the two Vivado

instances
d. Once the bitstream is complete, the default is for Vivado to open up the Device Image
Generation Completed Dialog (unless you have requested this to not be shown)

e. Without this, you can also tell the image is complete with the message in the upper
right, or feedback in the TCL console

Testing the Design

Once the design is completely built, JTAG will be used to download the design to the ZCU670
Evaluation Platform.
• Insert zSFP+ Loopback adapter and FMC+ Loopback adapter as desired
o 4x MultiLane ML-4026-28-0dB Loopback adapter suggested for J29
o Samtec Searay REF-210144-01 suggested for J28
• Power UP the ZCU670 Evaluation Kit by flipping SW15
• Wait until after the cooling fan has slowed (typically 15-30 seconds)
• The last step in the Vivado Flow Navigator will be Open Hardware Manager
• Select Open Hardware Manager from the Device Image Generation Completed Dialog

or select the “Open Hardware Manager” step from the Flow Navigator

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• In the Hardware Manager flow from the Flow Navigator, click on Open Target and Auto
Connect

• You will see the TCL commands execute to connect to the hw_server and then connect to
the JTAG chain

• Now program the device, Vivado will prepopulate the Bitstream file field on the open design
dialog

• While you wait, notice the device is also displayed in the Hardware dialog

• Once completed, notice the change in the Hardware dialog

• Be aware that transceivers will not link until you populate a loopback adapter to the zSFP+
connector (J29), or the FMCP HSPC connector (J28)
• From here, you can view and adjust the various features of the GTY transceivers
• You can also select Auto-detect Links or for manual selection, select Create Links

For manual selection, choose the two channels you would like to pair, then click the + button,
repeat as necessary

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 Tip: If the onboard JTAG is used, it can be helpful to change the FREQUENCY to 7500000

• Notice the commands being executed in the TCL console, these actions can also be scripted!

• The ZCU670 Evaluation Board has been wired as indicated by the schematic, however with
the use of a loopback adapter, the channels are looped back on the same Quad and Lane
• To ensure that the design is looping data through the loopback adapter, scroll to the right in
the Serial I/O Links tab until Loopback Mode is discovered
• If None is selected, click the pull-down menu for each desired lane, and select None
o Note: Each mode allows for testing of different areas of interest – internal to the
device, analog, digital, etc.
o Note: DFE has been enabled in this design. This further enhances the performance of
the transceiver. Refer to UltraScale Architecture GTY Transceivers User Guide (UG578)
“RX Equalizer (DFE and LPM)” topic

• In the Serial I/O Links tab, you can see the various metrics around each link
o Here you can change and tune your lane, changing to various patterns, injecting
errors, etc.
o For example, changing the transmit and receive Patterns to MISMATCH demonstrates
a drop in link. Matching the pattern resumes link

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• Link down, pattern mismatch

• Link up, matching pattern

• Clicking Reset will reset the link (notice Errors are now 0)

• IBERT GTY Serial I/O Scans, you can view specific performance measurements, open area,
range and other metrics for specific GTY channels
• In order to run a scan, right click the lane of choice, and select Create Scan…

• In the next dialog, keep the defaults and select Create Scan
• A new scan will appear in the Serial I/O Scans tab

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Things to note. The open area, range as well as BER coloring. This useful depiction can be
utilized to tune your transceivers for optimal performance.

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Appendix A

Intentionally Left Blank

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Appendix B Xilinx Design Constraints
The Xilinx® design constraints (XDC) file template for the ZCU670 board provides for designs targeting
the ZCU670 evaluation board. Net names in the constraints listed correlate with net names on the
latest ZCU670 evaluation board schematic. Identify the appropriate pins and replace the net names
with net names in the user RTL.

See the Vivado Design Suite User Guide: Using Constraints (UG903) for more information.

Note: The IBERT Example Design generates an XDC based on design parameters and using the board
awareness of Vivado. Once generated, this can be inspected.

IMPORTANT! See the ZCU670 board documentation ("Board Files" check box) for the XDC File

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Appendix C

Intentionally Left Blank

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Appendix D

Intentionally Left Blank

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Appendix E Additional Resources and
Legal Notices
Xilinx Resources
For support resources such as Answers, Documentation, Downloads, and Forums, see Xilinx
Support.

Documentation Navigator and Design Hubs

Xilinx® Documentation Navigator (DocNav) provides access to Xilinx documents, videos, and support
resources, which you can filter and search to find information. To open DocNav:

• From the Vivado® IDE, select Help → Documentation and Tutorials.

• On Windows, select Start → All Programs → Xilinx Design Tools → DocNav.
• At the Linux command prompt, enter docnav.

Xilinx Design Hubs provide links to documentation organized by design tasks and other topics, which
you can use to learn key concepts and address frequently asked questions. To access the Design Hubs:

• In DocNav, click the Design Hubs View tab.

• On the Xilinx website, see the Design Hubs page.

Note: For more information on DocNav, see the Documentation Navigator page on the Xilinx website.

References
The most up to date information related to the ZCU670 board and its documentation is available on
these websites:

ZCU670 Evaluation Kit— Master Answer Record 33801

These documents provide supplemental material useful with this guide:

1. ZCU670 Evaluation Board User Guide (UG1532)

2. Zynq UltraScale+ RFSoC Data Sheet: Overview (DS889)
3. Zynq UltraScale+ RFSoC DFE Data Sheet: Overview (DS883)
4. Zynq UltraScale+ RFSoC Data Sheet: DC and AC Switching Characteristics (DS926)
5. Zynq UltraScale+ Device Technical Reference Manual (UG1085)
6. UltraScale Architecture PCB Design User Guide (UG583)
7. UltraScale Architecture-Based FPGAs Memory IP LogiCORE IP Product Guide (PG150)
8. UltraScale Architecture GTY Transceivers User Guide (UG578)
9. IBERT for UltraScale GTY Transceivers LogiCORE IP Product Guide (PG196)

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 10. Vivado Design Suite User Guide: Using Constraints (UG903)
11. Tera Term Terminal Emulator Installation Guide (UG1036)
12. UltraScale Architecture System Monitor User Guide (UG580)
13. ZCU670 System Controller Tutorial (XTP698)
14. ZCU670 Software Install and Board Setup Tutorial (XTP699)
15. Silicon Labs CP210x USB-to-UART Installation Guide (UG1033)

Revision History
The following table shows the revision history for this document.

Section Revision Summary

10/25/2021 Version 0.1
Initial release. N/A

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Please Read: Important Legal Notices
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Copyright

© Copyright 2022 Xilinx, Inc. Xilinx, the Xilinx logo, Alveo, Artix, Kintex, Kria, Spartan, Versal,
Vitis, Virtex, Vivado, Zynq, and other designated brands included herein are trademarks of Xilinx
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