h264 Cabac Prodbrief Ds602

- THIS IS A DISCONTINUED IP CORE 0
H.264 CABAC Core v1.0

DS602 (v1.0) May 15, 2007
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Product Brief
Features
H.264/MPEG-4 Part 10 Main/High/High Ext. Profiles Level 4.2+ Support for up to HD 1080i and 1080p/60 fps at 75 Mbps. Output stream is compliant with International Standard ISO/IEC 14496-10:2005 (E) Rec. H.264 (E) Frame or Field processing 4:2:0 supported. Fixed context model initialization supported Interlaced streams supported Output stream granularity at single slice level. Output control signals provided for rate control and rate distortion optimization Self-sustaining internal state machine supported for user interface
Documentation Design File Formats Verification Spartan-3 Virtex-4
LogiCORE Facts Core Specifics

Resources Used 1080i/p 720i/p CIF 49 block RAMs, 8860 slices 49 block RAMs, 8860 slices 37 block RAMs, 8627 slices
ITU-R-BT.601 41 block RAMs, 8727 slices
ITU-R-BT.601 43 block RAMs, 7942 slices
CIF
39 block RAMs, 7831 slices Provided with Core Data Sheet, User Guide VHDL, EDIF JM10 Reference C-Code vs. VHDL Test Bench and HW Tests VHDL Wrapper
Instantiation Template Design Tool Requirements Synthesis
Resource Summary
LogiCORE Facts Core Specifics
Supported Device Families Virtex-5, Virtex-4, Spartan-3
Synplicity Synplify_Pro 8.6.2 Xilinx ISE 8.2.03i (from ngd_build) ModelSim 6.1c SE, MicroSoft Visual C++ V6.0, ActivePerl 5.8.3. Annapolis Micro Systems WildCard4 platform API 3.0, Driver 4.0, Firmware 1.0 ModelSim 6.1c SE Support
Xilinx Implementation Tools Verification
Resources Used 1080i/p 5083 Slice Flip Flops 10258 Slice LUTS 8 RAMB18x2, 20 RAMB36 5083 Slice Flip Flops 10258 Slice LUTS 8 RAMB18x2, 20 RAMB36 10270 Slice LUTS 8 RAMB18x2, 16 RAMB36 CIF 5022 Slice Flip Flops 10240 Slice LUTS 8 RAMB18x2, 14 RAMB36
Simulation
720i/p
Virtex-5
ITU-R-BT.601 5072 Slice Flip Flops
Xilinx provides technical support for this LogiCORE product when used as described in the product documentation. Xilinx cannot guarantee timing functionality, or support of product if implemented in devices not listed in the documentation, or if customized beyond that allowed in the product documentation, or if any changes are made in sections of the design marked DO NOT MODIFY.
2007 Xilinx, Inc. All rights reserved. XILINX, the Xilinx logo, and other designated brands included herein are trademarks of Xilinx, Inc. All other trademarks are the property of their respective owners. Xilinx is providing this design, code, or information "as is." By providing the design, code, or information as one possible implementation of this feature, application, or standard, Xilinx makes no representation that this implementation is free from any claims of infringement. You are responsible for obtaining any rights you may require for your implementation. Xilinx expressly disclaims any warranty whatsoever with respect to the adequacy of the implementation, including but not limited to any warranties or representations that this implementation is free from claims of infringement and any implied warranties of merchantability or fitness for a particular purpose.
DS602 (v1.0) May 15, 2007 Product Brief
www.xilinx.com
- THIS IS A DISCONTINUED IP CORE H.264 CABAC Core v1.0
Introduction
The Xilinx H.264 Context Adaptive Binary Arithmetic Coder (CABAC) Version 1.0 core is a fully functional VHDL design implemented on a Xilinx FPGA. For each slice to encode, the CABAC core generates a compressed bitstream as specified by the ITU-T Video Coding Experts Group (VCEG) together with the ISO/IEC Moving Picture Experts Group (MPEG) as the product of a collective partnership effort known as the Joint Video Team (JVT). The collaborative effort is also known as H.264/AVC/MPEG4 Part 10. A high-level block diagram of the CABAC core is shown in Figure 1. The two main components are the control state machines (Main SM and Pre-Processing SM) and the encoding engine. As shown in Figure 1, the CABAC core is fully self-sustained with its complex state machines able to effectively generate and feed the appropriate Synthax Element (SE) into its internal Arithmetic Coding (AC) engine. For a given slice (pre-defined partition of a frame), the necessary input data is fed on a macroblock (MB) basis and consists mainly of the integer transform coefficients absolute levels, the motion vector differences (MVD) and other related information such as MB type and MB prediction mode. The length and size of the MB data given as input to the core is adaptively determined on both the users side and inside the core itself. For instance, in the case of an MB that does not contain any MVDs, the core has prior knowledge of this and does not waist cycles waiting for MVDs. Correspondingly, the user does not send any MVDs. Another example is with the transform coefficients of a given MB, which are skipped by both the core and the users sides when the coded block pattern value is zero. This adaptiveness translates into significant savings of MB data transfer bandwidth between the users side and the core. The generated SEs are passed to the AC engine block which consists of the AC encoder, the binarizer, and the context management block. After binarization of the input SE, each resulting bit (or bin) is sequentially processed by the encoding engine in a single clock cycle. The ability to process each bin in a single clock cycle coupled with the fast state machines enables real-time HD encoding.
Figure Top x-ref 1
CABAC Core
currFrame
currSlice
Encoding Engine
currMB
SE Pre-Processing
SE
Main SM
Context Magmt.
Binarizer
bin
Binari-Arith Encoder
Byte_out(7:0)
ds602_01_011207
Figure 1: CABAC Functional Block Diagram
www.xilinx.com
- THIS IS A DISCONTINUED IP CORE H.264 CABAC Core v1.0
Applications
The CABAC Encoder core can be utilized in H.264 standards applications where hardware acceleration is needed to achieve real time operation. Typical video applications are video surveillance, video conferencing, and video broadcast. The CABAC core can also be used in military and medical applications in a standalone application where lossless arithmetic coding is desired.
Performance
Table 1 shows the performance of the CABAC core for different device families and the corresponding output data rate supported.
Table 1: Performance Summary
FPGA Family
Spartan-3E Virtex-4 Virtex-5
Clock FMax
50 MHz 133 MHz 165 MHz
Approximate 4:2:0 Output Bit Rate (Mbps)

25 66 80
Notes
Supports up to SD, 601i, 4CIF Supports up to HD, 1080P/30, 1080i/60, 720P/60 Supports up to 1080P/60, 1080i/60, 720P/60
Revision History
The following table shows the revision history for this document. Date
05/15/07
Version
1.0 Initial Xilinx release.
Revision
www.xilinx.com

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- THIS IS A DISCONTINUED IP CORE 0

H.264 CABAC Core v1.0

LogiCORE Facts Core Specifics

ITU-R-BT.601 41 block RAMs, 8727 slices

ITU-R-BT.601 43 block RAMs, 7942 slices

Instantiation Template Design Tool Requirements Synthesis

Xilinx Implementation Tools Verification

ITU-R-BT.601 5072 Slice Flip Flops

DS602 (v1.0) May 15, 2007 Product Brief

- THIS IS A DISCONTINUED IP CORE H.264 CABAC Core v1.0

Figure 1: CABAC Functional Block Diagram

DS602 (v1.0) May 15, 2007 Product Brief

- THIS IS A DISCONTINUED IP CORE H.264 CABAC Core v1.0

Approximate 4:2:0 Output Bit Rate (Mbps)

DS602 (v1.0) May 15, 2007 Product Brief

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