A4950

Full-Bridge DMOS PWM Motor Driver

Features and Benefits Description

• Low RDS(on) outputs
Designed for pulse width modulated (PWM) control of DC
• Overcurrent protection (OCP)
motors, the A4950 is capable of peak output currents to ±3.5 A
▫ Motor short protection
and operating voltages to 40 V.
▫ Motor lead short to ground protection
▫ Motor lead short to battery protection Input terminals are provided for use in controlling the speed and
• Low Power Standby mode direction of a DC motor with externally applied PWM control
• Adjustable PWM current limit signals. Internal synchronous rectification control circuitry is
• Synchronous rectification provided to lower power dissipation during PWM operation.
• Internal undervoltage lockout (UVLO)
Internal circuit protection includes overcurrent protection,
• Crossover-current protection
motor lead short to ground or supply, thermal shutdown with
hysteresis, undervoltage monitoring of VBB, and crossover-
Package: 8-pin SOICN with exposed current protection.
thermal pad (suffix LJ) The A4950 is provided in a low-profile 8-pin SOICN package
with exposed thermal pad (suffix LJ) that is lead (Pb) free, with
100% matte tin leadframe plating.

Not to scale

Functional Block Diagram

Load Supply

Charge
OSC Pump VBB

IN1
Control
Logic

Disable OUT1
TSD
IN2 UVLO OUT2
7V

GND

LSS

VREF ÷ 10 (Optional)

A4950-DS, Rev. 2
A4950 Full-Bridge DMOS PWM Motor Driver

Selection Guide
Part Number Packing
A4950ELJTR-T 3000 pieces per 13-in. reel

Absolute Maximum Ratings

Characteristic Symbol Notes Rating Unit
Load Supply Voltage VBB 40 V
Logic Input Voltage Range VIN –0.3 to 6 V
VREF Input Voltage Range VREF –0.3 to 6 V
Sense Voltage (LSS pin) VS –0.5 to 0.5 V
Motor Outputs Voltage VOUT –2 to 42 V
Output Current IOUT Duty cycle = 100% 3.5 A
Transient Output Current iOUT TW < 500 ns 6 A
Operating Temperature Range TA Temperature Range E –40 to 85 °C
Maximum Junction Temperature TJ(max) 150 °C
Storage Temperature Range Tstg –55 to 150 °C

Thermal Characteristics may require derating at maximum conditions, see application information
Characteristic Symbol Test Conditions* Value Unit
On 2-layer PCB with 0.8 in2. exposed 2-oz. copper each side 62 ºC/W
Package Thermal Resistance RθJA
On 4-layer PCB based on JEDEC standard 35 ºC/W

*Additional thermal information available on the Allegro website.

Terminal List Table

Number Name Function
Pin-out Diagram 1 GND Ground
2 IN2 Logic input 2
GND 1 8 OUT2 3 IN1 Logic input 1
IN2 2 7 LSS
PAD 4 VREF Analog input
IN1 3 6 OUT1
VREF 4 5 VBB
5 VBB Load supply voltage
6 OUT1 DMOS full bridge output 1
7 LSS Power return – sense resistor connection
8 OUT2 DMOS full bridge output 2
– PAD Exposed pad for enhanced thermal dissipation

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A4950 Full-Bridge DMOS PWM Motor Driver

ELECTRICAL CHARACTERISTICS Valid at TJ = 25°C, unless otherwise specified

Characteristics Symbol Test Conditions Min. Typ. Max. Unit
General
Load Supply Voltage Range VBB 8 – 40 V
IOUT = |2.5 A|, TJ = 25°C – 0.6 0.8 Ω
RDS(on) Sink + Source Total RDS(on)
IOUT = |2.5 A|, TJ = 125°C – 0.96 1.3 Ω
fPWM < 30 kHz – 10 – mA
Load Supply Current IBB
Low Power Standby mode – – 10 μA
Source diode, If = –2.5 A – – 1.5 V
Body Diode Forward Voltage Vf
Sink diode, If = 2.5 A – – 1.5 V
Logic Inputs
VIN(1) 2.0 – – V
Logic Input Voltage Range VIN(0) – – 0.8 V
VIN(STANDBY) Low Power Standby mode – – 0.4 V
IIN(1) VIN = 2.0 V – 40 100 μA
Logic Input Current
IIN(0) VIN = 0.8 V – 16 40 μA
Logic Input Pull-Down Resistance RR RLOGIC(PD) VIN = 0 V = IN1 = IN2 – 50 – kΩ
Input Hysteresis VHYS – 250 550 mV
Timing
Crossover Delay tCOD 50 – 500 ns
VREF Input Voltage Range VREF 0 – 5 V
VREF / ISS , VREF = 5 V 9.5 – 10.5 V/V
Current Gain AV VREF / ISS , VREF = 2.5 V 9.0 – 10.0 V/V
VREF / ISS , VREF = 1 V 8.0 – 10.0 V/V
Blank Time tBLANK 2 3 4 μs
Constant Off-time toff 16 25 34 μs
Standby Timer tst IN1 = IN2 < VIN(STANDBY) – 1 1.5 ms
Power-Up Delay tpu – – 30 μs
Protection Circuits
UVLO Enable Threshold VBBUVLO VBB increasing 7 7.5 7.95 V
UVLO Hysteresis VBBUVLOhys – 500 – mV
Thermal Shutdown Temperature TJTSD Temperature increasing – 160 – °C
Thermal Shutdown Hysteresis TTSDhys Recovery = TJTSD – TTSDhys – 15 – °C

Allegro MicroSystems, Inc. 3

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A4950 Full-Bridge DMOS PWM Motor Driver

Characteristic Performance

PWM Control Timing Diagram

VIN(1)

IN1

GND

VIN(1)

IN2

GND

+IREG

IOUT(x)
0A

-IREG

Forward/ Reverse/ Forward/ Reverse/

Fast Decay Fast Decay Slow Decay Slow Decay

PWM Control Truth Table

IN1 IN2 10×VS > VREF OUT1 OUT2 Function

0 1 False L H Reverse
1 0 False H L Forward
0 1 True H/L L Chop (mixed decay), reverse
1 0 True L H/L Chop (mixed decay), forward
1 1 False L L Brake (slow decay); after a Chop command
0 0 False Z Z Coast, enters Low Power Standby mode after 1 ms
Note: Z indicates high impedance.

Allegro MicroSystems, Inc. 4

115 Northeast Cutoff
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A4950 Full-Bridge DMOS PWM Motor Driver

Functional Description

Device Operation ITripMAX (A), which is set by:

The A4950 is designed to operate DC motors. The output drivers
are all low-RDS(on) , N-channel DMOS drivers that feature inter- VREF
ITripMAX =
nal synchronous rectification to reduce power dissipation. The 10 RS
current in the output full bridge is regulated with fixed off-time
pulse width modulated (PWM) control circuitry. The IN1 and IN2 where VREF is the input voltage on the VREF pin (V) and RS is
inputs allow two-wire control for the bridge. the resistance of the sense resistor (Ω) on the LSS terminal.

Protection circuitry includes internal thermal shutdown, and pro- Overcurrent Protection
tection against shorted loads, or against output shorts to ground A current monitor will protect the IC from damage due to output
or supply. Undervoltage lockout prevents damage by keeping the shorts. If a short is detected, the IC will latch the fault and disable
outputs off until the driver has enough voltage to operate nor- the outputs. The fault latch can only be cleared by coming out of
mally. Low Power Standby mode or by cycling the power to VBB. Dur-
ing OCP events, Absolute Maximum Ratings may be exceeded
Standby Mode
for a short period of time before the device latches.
Low Power Standby mode is activated when both input (INx)
pins are low for longer than 1 ms. Low Power Standby mode Shutdown
disables most of the internal circuitry, including the charge pump If the die temperature increases to approximately 160°C, the full
and the regulator. When the A4950 is coming out of standby bridge outputs will be disabled until the internal temperature falls
mode, the charge pump should be allowed to reach its regulated below a hysteresis, TTSDhys , of 15°C. Internal UVLO is present
voltage (a maximum delay of 200 μs) before any PWM com- on VBB to prevent the output drivers from turning-on below the
mands are issued to the device. UVLO threshold.
Internal PWM Current Control Braking
Initially, a diagonal pair of source and sink FET outputs are The braking function is implemented by driving the device in
enabled and current flows through the motor winding and the Slow Decay mode, which is done by applying a logic high to both
optional external current sense resistor, RS . When the voltage inputs, after a bridge-enable Chop command (see PWM Control
across RS equals the comparator trip value, then the current sense Truth Table). Because it is possible to drive current in both direc-
comparator resets the PWM latch. The latch then turns off the tions through the DMOS switches, this configuration effectively
sink and source FETs (Mixed Decay mode). shorts-out the motor-generated BEMF, as long as the Chop com-
VREF mand is asserted. The maximum current can be approximated by
The maximum value of current limiting is set by the selection of VBEMF / RL . Care should be taken to ensure that the maximum
RSx and the voltage at the VREF pin. The transconductance func- ratings of the device are not exceeded in worse case braking situ-
tion is approximated by the maximum value of current limiting, ations: high speed and high-inertia loads.

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A4950 Full-Bridge DMOS PWM Motor Driver

Synchronous Rectification Mixed Decay Operation

When a PWM off-cycle is triggered by an internal fixed off-time The bridges operate in Mixed Decay mode. Referring to the
cycle, load current will recirculate. The A4950 synchronous rec- lower panel of the figure below, as the trip point is reached, the
tification feature turns-on the appropriate DMOSFETs during the device goes into fast decay mode for 50% of the fixed off-time
current decay, and effectively shorts out the body diodes with the period. After this fast decay portion the device switches to slow
low RDS(on) driver. This significantly lowers power dissipation. decay mode for the remainder of the off-time. During transitions
When a zero current level is detected, synchronous rectification is from fast decay to slow decay, the drivers are forced off for the
turned off to prevent reversal of the load current. Crossover Delay, tCOD . This feature is added to prevent shoot-
through in the bridge. During this “dead time” portion, synchro-
nous rectification is not active, and the device operates in fast
decay and slow decay only.

Mixed Decay Mode Operation

VPHASE

See Enlargement A
IOUT
0

Enlargement A
Fixed Off-Time, toff = 25 μs

0.50 × toff 0.50 × toff

ITrip

IOUT

Fast Decay Slow Decay

tCOD tCOD tCOD

Allegro MicroSystems, Inc. 6

115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
A4950 Full-Bridge DMOS PWM Motor Driver

Application Information

Sense Pin (LSS) of the device makes a good location for the star ground point. The
In order to use PWM current control, a low-value resistor is exposed pad can be connected to ground for this purpose.
placed between the LSS pin and ground for current sensing pur-
poses. To minimize ground-trace IR drops in sensing the output Layout
current level, the current sensing resistor should have an indepen- The PCB should have a thick ground plane. For optimum
dent ground return to the star ground point. This trace should be electrical and thermal performance, the A4950 must be soldered
as short as possible. For low-value sense resistors, the IR drops in directly onto the board. On the underside of the A4950 package is
the PCB can be significant, and should be taken into account. an exposed pad, which provides a path for enhanced thermal dis-
sipation. The thermal pad must be soldered directly to an exposed
When selecting a value for the sense resistor be sure not to
exceed the maximum voltage on the LSS pin of ±500 mV at surface on the PCB in order to achieve optimal thermal conduc-
maximum load. During overcurrent events, this rating may be tion. Thermal vias are used to transfer heat to other layers of the
exceeded for short durations. PCB.

Ground The load supply pin, VBB, should be decoupled with an electro-
A star ground should be located as close to the A4950 as possible. lytic capacitor (typically 100 μF) in parallel with a lower valued
The copper ground plane directly under the exposed thermal pad ceramic capacitor placed as close as practicable to the device.

Solder
GND GND A4950
Trace (2 oz.)
Signal (1 oz.)
Ground (1 oz.)
PCB
Thermal (2 oz.)
OUT2

RS Thermal Vias

OUT1
C1
A4950
1 GND
C2 VBB OUT2
BULK LSS
CAPACITANCE PAD RS
IN2
IN1 OUT1
VREF VBB
VBB
C1 C2

GND GND

Bill of Materials
Item Reference Value Units Description
0.25 2512, 1 W, 1% or better,
1 RS Ω
(for VREF = 5 V, IOUT = 2 A) carbon film chip resistor
2 C1 0.22 μF X5R minimum, 50 V or greater
3 C2 100 μF Electrolytic, 50 V or greater

Allegro MicroSystems, Inc. 7

115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
A4950 Full-Bridge DMOS PWM Motor Driver

Package LJ, 8-Pin SOICN

with exposed thermal pad

4.90 ±0.10
8° 0.65
0° 8 1.27
8
0.25 1.75
0.17
B
2.41 NOM 3.90 ±0.10 6.00 ±0.20 2.41 5.60
A 1.04 REF

1 2
1.27 1 2
3.30 NOM 0.40
3.30
0.25 BSC
C PCB Layout Reference View
SEATING PLANE
Branded Face
GAUGE PLANE
8X C
SEATING
0.10 C PLANE For Reference Only; not for tooling use (reference MS-012BA)
Dimensions in millimeters
1.70 MAX Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
0.51
0.31 0.15 Exact case and lead configuration at supplier discretion within limits shown
0.00
1.27 BSC A Terminal #1 mark area
B Exposed thermal pad (bottom surface); dimensions may vary with device
C Reference land pattern layout (reference IPC7351
SOIC127P600X175-9AM); all pads a minimum of 0.20 mm from all
adjacent pads; adjust as necessary to meet application process
requirements and PCB layout tolerances; when mounting on a multilayer
PCB, thermal vias at the exposed thermal pad land can improve thermal
dissipation (reference EIA/JEDEC Standard JESD51-5)

Allegro MicroSystems, Inc. 8

115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
A4950 Full-Bridge DMOS PWM Motor Driver

Revision History
Revision Revision Date Description of Revision
Rev. 2 November 9, 2011 Update PWM timing, AV

Copyright ©2011, Allegro MicroSystems, Inc.

Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to per-
mit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the
information being relied upon is current.
Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the
failure of that life support device or system, or to affect the safety or effectiveness of that device or system.
The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use;
nor for any infringement of patents or other rights of third parties which may result from its use.

For the latest version of this document, visit our website:

www.allegromicro.com

Allegro MicroSystems, Inc. 9

115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com