Book 1 Module 5

CATEGORY B1 B2
DIGITAL TECHNIQUES

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AUTHORITY

It is IMPORTANT to note that the information in this book is for study/training

purposes only.

When carrying out a procedure/work on aircraft/aircraft equipment you MUST

always refer to the relevant aircraft maintenance manual or equipment
manufacturer’s handbook.

You should also follow the requirements of your national regulatory authority (the
CAA in the UK) and laid down company policy as regards local procedures, recording,
report writing, documentation etc.

For health and safety in the workplace you should follow the regulations/guidelines
as specified by the equipment manufacturer, your company, national safety
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CONTENTS

Page

Numbering systems 1
The Decimal system 1
The Binary system 2
The Octal system 8
The Hexadecimal system 11
The Binary coded decimal system 14
Mathematical functions on Binary numbers 15
Digital circuits 18
Logic gates 19
Electronic gate operation 25
De Morgan’s rules 34
Adders 35
Comparators 37
Logic circuits – examples 39
Sequential/combinational logic 42
Flip-flops 42
The SR flip-flop 43
Clocks 44
The D type SR flip-flop 45
The JK flip-flop 45
Counters 46
Shift registers 48
Encoders and decoders 49
Encoders 49
Analogue to digital converters 51
The digital ramp converter 51
The successive approximation ADC 52
The integrated duel slope converter 53
The charge balancing converter 54
Terminology 55
Decoders 56
The digital to analogue converter 56
The R-2R type D to A converter 58
Multiplexers and demultiplexers 59
Passenger entertainment system 63
Assignment 64
Solutions to activities 64
HOW TO TACKLE THIS BOOK

Basically, very slowly! Make sure you understand each part before going onto
the next. It is important you can recognise logic gates, be able to draw relevant
truth tables and be able to interpret aircraft schematic diagrams in relation to
logic circuits.

It is important that you have a full appreciation of the involvement of logic

circuitry in aircraft computer and related systems.

This series of study books for module 5 is written for the B1/B2 engineer. The
A line mechanic should study our books for module 5 specifically written to
that level. This book is written to the B2 level for all subjects which is a
slightly higher level than the B1 requirement.

The B2 engineer needs to study this book (as well as the other books in this
module) in its/their entirety with all subjects to level 2 except for Electronic
Instrument Systems which should be studied to level 3.

For the B1.1 and B1.3 (jet engine aircraft) engineer some subjects need not be
studied at all and some subjects need to be studied at a level one below that of
the B2. For the B1.2 and B1.4 engineer (piston engine aircraft) none of this
book is applicable.

Any references to scientists are for interest only and details need not be
committed to memory.

There are 6 books in the LBP module 5 series.

IMPORTANT

The B1 engineer should check the syllabus whilst studying these books to
ensure that he/she studies only those subjects listed. A copy of the 2011
syllabus is included as an appendix to this book.

We have also included the definitions of the difficulty levels. Not easy for the
individual to interpret and sometimes the CAA (in their examinations) tend to
interpret them liberally anyway.
 NUMBERING SYSTEMS

Most digital transmission in today’s modern aircraft uses various types of

number systems. Typically these would be decimal, binary, octal and
hexadecimal, or a form of these systems.

THE DECIMAL SYSTEM

This is the system in everyday use; there are 10 digits (0 to 9 inclusive) so it

has a ‘base’ or ‘radix’ (number of digits used in the system) of 10. Taking the
number 72306 can be written as:

(7 x 10,000) + (2 x 1000) + (3 x 100) + (0 x 10) + 6 x 1

= (7 x 104) + (2 x 103) + (3 x 102) + (0 x 101) + (6 x 100)

= 72306

Each digit is effectively multiplied by a power of 10.

Note. To write 19.526 in powers of 10 then proceed as follows:

1 x 101 + 9 x 100 + 5 x 10-1 + 2 x 10-2 + 6 x 10-3

= (10) + (9) + (5 x 1 = .5) + ( 2 = .02) + ( 6 = .006)

10 100 1000

= 10 + 9 + . 5 + . 02 + . 006

= 19.526

Note that 100 = 1. In fact any number to the power of nought equals 1.
Proof. Using as an example the number 3. That is 30 = 1.

1 = 9 = 32 = 32 x 3-2 = 32+(-2) = 30
9 32

Note that 3 was used because it is an easy number to show that any number
to the power of nought is equal to 1.

It can be seen that the decimal system is based on successive powers of 10,
the number with the smallest value (100) is known as the Least Significant
Digit (LSD) and the number with the highest value (104 in the example above)
is known as the Most Significant Digit (MSD).

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The disadvantage of the decimal system for use in a digital computer is that
the circuits which would be used, using transistors, would have to have 10
discrete levels of collector current. For example 0mA (0 milliamps) would equal
0, 1mA would equal 1, 2mA = 2, 3mA = 3 etc. Such a system would be
extremely difficult to operate because:

(a) Any variation of power supply would cause errors.

(b) Component tolerance would have to be virtually zero, and be
unaffected by temperature variations.
(c) Component resistance values will change with age.

Any errors from the above may cause an error increment of one or two, giving
an incorrect output (eg instead of 8 [correct reading] for example it might be 7
or 9).

Precision is important, and to expect a circuit to be infallible in distinguishing

between 10 different magnitudes of current is a bit much.

Where accuracy and speed are important it would be better to use a system
that has just two states. Reliance is higher because the circuit is either HIGH
(high voltage level) or LOW (low voltage level), or ON or OFF.

This would mean component characteristic variations would be less important.

So the system that is the basis of today’s digital processing is the ‘two states’
BINARY SYSTEM.

THE BINARY SYSTEM

This has a base or radix of 2. As in the decimal system we can represent any
number in successive powers of 2.

For example:

27 = 24 + 23 + 21 + 20

= 16 + 8 + 2 + 1

expanded further:

= 1 x 24 + 1 x 23 + 0 x 22 + 1 x 21 + 1 x 20

↓ ↓ ↓ ↓ ↓

1 1 0 1 1

means the binary number for 27 = 110112

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To avoid confusion between systems with different radix this would be written
as 110112 to identify it as a binary number.

What are fractions expressed as powers of 2? Examples:

1 = 0.5 = 2-1 = .12

2

1 = 1 = 0.25 = 2-2 = .012

4 22

1 = 1 = 0.125 = 2-3 = .0012

8 23

1 = 1 = 0.0625 = 2-4 = .00012

16 24

Example. Change 17.75 decimal to binary. Take the 17 first then add on the
.75.

17 = 24 + 20 + 2-1 + 2-2 and .75 = .5 + .25 = .11

expanded gives

1 x 24 + 0 x 23 + 0 x 22 + 0 x 21 + 1 x 20 + 1 x 2-1 + 1 x 2-2

↓ ↓ ↓ ↓ ↓ ↓ ↓

1 0 0 0 1 . 1 1

So 17.75 = 10001.112

Note. Each binary digit is termed a bit.

The table below shows the relationship between Binary and Decimal numbers
up to Decimal 21. It could be continued indefinitely.

blank

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 Decimal 5-bit Binary Decimal 5-bit Binary No
Number Number (word) Number Number (word)

24 23 22 21 20 24 23 22 21 20

0 0 0 0 0 0 11 0 1 0 1 1

1 0 0 0 0 1 12 0 1 1 0 0

2 0 0 0 1 0 13 0 1 1 0 1

3 0 0 0 1 1 14 0 1 1 1 0

4 0 0 1 0 0 15 0 1 1 1 1

5 0 0 1 0 1 16 1 0 0 0 0

6 0 0 1 1 0 17 1 0 0 0 1

7 0 0 1 1 1 18 1 0 0 1 0

8 0 1 0 0 0 19 1 0 0 1 1

9 0 1 0 0 1 20 1 0 1 0 0

10 0 1 0 1 0 21 1 0 1 0 1

TABLE 1 BINARY/DECIMAL EQUIVALENTS

From the table it can be seen that the binary number is longer than the
decimal number but because of the fast switching speeds of modern circuits
this does not present a problem. Also because of the reliability of the two-state
system, the practical advantages gained by using binary numbers are
considerable.

ACTIVITY 1 Write the successive powers of 2 for the following decimal

numbers and then expand to give the binary number.

(a) 19 (c) 15.125

(b) 29 (d) 22.0625

This method is fine as far as it goes, but when larger numbers are involved it
becomes cumbersome. To convert from decimal to binary, the successive
division by two method may be employed (see below), the ‘remainder’ of any
division (which must be either 0 or 1) is then recorded successively in a
separate column. The following examples show the method.

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Example a Example b

Convert 796 to binary Write 217 in binary form

2 796 2 217

2 398 remainder 0 2 108 remainder 1

2 199 ’’ 0 2 54 ’’ 0

2 99 ’’ 1 2 27 ’’ 0

2 49 ’’ 1 2 13 ’’ 1

2 24 ’’ 1 2 6 ’’ 1

2 12 ’’ 0 2 3 ’’ 0

2 6 ’’ 0 2 1 ’’ 1

2 3 ’’ 0 2 0 ’’ 1

2 1 ’’ 1 READ UP READ UP
to obtain to obtain
0 ’’ 1 binary binary
equivalent form
1100011100 11011001

So for 796. First divide by 2. The answer is 398 with remainder 0. The divide
398 by 2. The answer is 199 with remainder 0. Divide 199 by 2. The answer is
99 with remainder 1. Continue this until all divisions are complete. Read UP
the remainder column to give the binary number 1100011100.

ACTIVITY 2 Convert the following decimal numbers to binary:

(a) 846
(b) 317
(c) 147

You should practice converting the smaller numbers using powers of 2 which
is a quicker method.

Example

Convert 4510 to Binary

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Write down the successive powers of 2:

(25) (24) (23) (22) (21) (20)

32 16 8 4 2 1

Then make up the number, ie

(1 x 32) + (0 x 16) + (1 x 8) + (1 x 4) + (0 x 2) + (1 x 1) = 4510

So 32 16 8 4 2 1 equals:

1 0 1 1 0 1

So 4510 equals binary 1011012

ACTIVITY 3 So the idea is to write down the powers of 2 and put 1’s in the
powers you need to make up the number. Try these:

(a) 47
(b) 32
(c) 21

The following example shows the process of converting decimal fractions to

binary. The number (in this case 0.615) is multiplied by two, which equals
1.230. The 1 goes in the left hand column. Then multiply 230 by 2 which
equals 0.460. Put the 0 in the left hand column. Continue the process then
read DOWN the carries (left hand) column to give the binary number.

Convert 0.615 to binary form

0 . 615 x 2

1 230 x 2
READ DOWN
And write from left to right 0 460 x 2
to give binary fraction:
0 920 x 2
0.1001112
1 840 x 2

1 680 x 2

1 360 x 2 -------- until required accuracy

is obtained.

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Conversion of a Decimal Fraction to a Binary Fraction

The next example shows how to convert a mixed decimal number to binary.
Note that it must be treated in two parts as shown.

Example
Convert 14.625 to binary

First separate into whole and fractional parts, ie:

14 . 625 = 14 . 000 + 0 . 625

(WHOLE) (FRACTION)

WHOLE FRACTION

2 14 0 . 625 x 2

2 7 remainder 0 1 250 x 2
READ
2 3 ’’ 1 UP READ 0 500 x 2
DOWN
2 1 ’’ 1 1 000

0 ’’ 1

1410 = 11102 0.62510 = 0.1012

Recombine the whole and fraction parts to give: 14.62510 = 1110.1012

Conversion of Binary to Decimal

The easiest way to convert Binary to Decimal is to write the powers of 2 above
each bit position starting from the right and working towards the left. Then by
inspection calculate the Decimal number. For example, take the binary
number 1011012 and convert to decimal.

32 16 8 4 2 1 ← the powers

1 0 1 1 0 1

It can be seen that the number 45 is made up from:

32 + 8 + 4 + 1 = 4510 (there are no 16s and no 2s but one of each of

the other values 32, 8, 4 & 1)

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Examples:

Remember to write the powers of 2 above each bit position and the calculate
the Denary number.

1. Convert 1101101 binary to decimal

64 32 16 8 4 2 1

1 1 0 1 1 0 1

So 64 + 32 + 8 + 4 + 1 = 10910

2. Convert 1101.1 binary to decimal

8 4 2 1 .5

1 1 0 1 .1

= 13 .510

3. Convert 1001110.112 to decimal

64 32 16 8 4 2 1 .5 .25

1 0 0 1 1 1 0 .1 1

= 64 + 8 + 4 + 2 + .5 + .25

= 78.7510

ACTIVITY 4 Try these yourself – convert to decimal:

(a) 110011 (c) 1011.1

(b) 1110011 (d) 1100.001

THE OCTAL SYSTEM

In the binary system the number of bits in a word can be quite lengthy and
problems can occur such as the possibility of an error in manipulating so
many digits.

The octal system (numbering 0 to 7, 10 to 17 etc) helps lessen these

difficulties, being more compact and easily converted back to decimal or
binary.

-8-
The system uses the base or radix 8, this means to convert from decimal to
octal we divide by 8 and record the remainders as before and read UP to get
the octal number.

To convert this number to binary split each octal number into it’s three figure
binary numbers and join together.

Example 1

Convert 796 to Octal and then convert to Binary

a. Conversion of Decimal to Octal b. Conversion of Octal to Binary

8 796 (to convert 14348 to binary)

8 99 remainder 4 The binary number is obtained by

taking each Octal digit and converting
8 12 remainder 3 READ it to a three figure Binary number:

8 1 remainder 4 UP
1 4 3 4
0 remainder 1 001 100 011 100

∴ 79610 = 14348 so 14348 = 0011000111002 = 11000111002

and 79610 = 14348 = 11000111002

To convert from binary to octal, start from the right and group into threes, if
the final group does not have three bits then add noughts to make up to the
three.

Example 2

Convert 10101002 to Octal

1 01 0 1 0 0

add 2 noughts 001 010 100

Convert to Octal digit 1 2 4

read left to right

10101002 = 1248

-9-
Example 3
01000002 to Octal

0 1 0 0 0 0 0

000 100 000

0 4 0

01000002 = 408

To convert from 0ctal to Binary (just a recap) the reverse procedure is used.

Example - convert 12638 to Binary

1 2 6 3

Put into groups

of three 001 010 110 011

12638 = 10101100112

ACTIVITY 5 Convert the following Binary numbers to Octal:

(a) 101010100 (b) 1110100000 (c) 111010001

Convert the following Octal numbers to Binary:

(d) 426 (e) 5625 (f) 65217

Fractions in Decimal to Binary are dealt with by the method of multiplication

by 2 and Decimal to Octal uses the multiplication by 8 method.

Example

Convert 0.9062510 to Binary.

0.90625 x 2 = 1.81250 1
0.8125 x 2 = 1.6250 1
0.625 x 2 = 1.250 1 READ
0.25 x 2 = 0.5 0 DOWN
0.5 x 2 = 1.0 1

0.9062510 = 0.111012

- 10 -
To convert 0.9062510 to Octal

0.90625 x 8 = 7.25 7 READ

.25 x 8 = 2.00 2 DOWN

0.9062510 = 0.728

or we could have used the Binary number split into threes. For example:

0.11101

Starting after the decimal point going left to right:

0 . 1 1 1 0 1
add a nought

. 111 010

. 7 2

= .728

The reverse procedure is used to obtain a Binary fraction from an Octal

fraction.

ACTIVITY 6 Convert the following Binary numbers to Octal.

(a) 111.111 (b) 101.1 (c) 110.0111

Convert the following Octal numbers to Binary:

(d) .64 (e) .77 (f) .43

THE HEXADECIMAL SYSTEM

This system has a base or radix of 16 (numbers 0 to 9 then lettered A to F) and

is used again where large binary numbers are handled to cut down possible
errors. Since we have only ten different digit symbols (0 to 9 inclusive) six
other symbols have to be used and these are the letters A to F inclusive. The
table below shows the three numbering systems already considered and the
hexadecimal system.

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 Decimal Octal Binary Hexadecimal

0 0 0000 0
1 1 0001 1
2 2 0010 2
3 3 0011 3
4 4 0100 4
5 5 0101 5
6 6 0110 6
7 7 0111 7
8 10 1000 8
9 11 1001 9
10 12 1010 A
11 13 1011 B
12 14 1100 C
13 15 1101 D
14 16 1110 E
15 17 1111 F

TABLE 2 COMPARISON 0F NUMBERING SYSTEMS

Conversion from Decimal to Hexadecimal (Hex)

Divide the Decimal number by 16 (to give a result) and convert the remainder
to Hex. Take the result and divide by 16 and convert the remainder to Hex. For
example, converting 76210 to Hex (see the workings below) divide 762 by 16.
This gives 47 with the remainder equal to 10 (in Hex = A). The next stage is to
divide 47 by 16 and so in. So:

16 762

16 47 remainder A

16 2 remainder B READ UP

0 remainder 2
∴76210 = 2FA16

Conversion from Hexadecimal to Binary

Take each Hex character and convert to its four bit binary word and join each
four bit word together. Example, convert 2BC16 to Binary:

- 12 -
 2 B C

group into }
4 digits } 0010 1011 1100

∴2BC16 = 10101111002

ACTIVITY 7 Convert the following Binary numbers to Hexadecimal:

(a) 11100010 (b) 1111111 (c) 111001

Convert the following Hexadecimal codes to Decimal:

(d) 2D (e) 1AF (f) 21A

Convert the following Decimal numbers to Hexadecimal:

(g) 1632 (h) 494 (i) 5174

(j) Convert 17816 to Decimal, Binary and Octal.

(k) Convert EF16 to Decimal, Binary and Octal:

Fractions in Hexadecimal

Not too unlike the process of converting whole numbers. Example, convert
0.9062510 to Hexadecimal:

0.90625 x 16 = 14.5 E READ

0.5 x 16 = 8.0 8 DOWN

So 0.9062510 = 0.E8

To convert to Binary

Also not too unlike the procedure for whole numbers, for example:

0.E8

Group into four digits 0.1110 1000

= 0.111010002

- 13 -
ACTIVITY 8 Convert the following decimal fractions to Hexadecimal:

(a) 0.6250 (b) 0.81250

Convert the following Hexadecimal numbers to Binary:

(c) 0.A8 (d) 0.F6

Comparing the lengths a Binary number to Octal and Hexadecimal

111100001111101100011.00010011012
= 7417543.04648
= 1E1F63.13416

Note from the above how concise (and therefore less prone to error) the Octal
and Hex systems are compared to the Binary system.

THE BINARY CODED DECIMAL (BCD) SYSTEM

There are several forms of this system but we shall concentrate on the 8421
code. It is used in display read-out systems, decoders and counters.

DECIMAL BCD
23 22 21 20
8 4 2 1
0 0 0 0 0
1 0 0 0 1
2 0 0 1 0
3 0 0 1 1
4 0 1 0 0
5 0 1 0 1
6 0 1 1 0
7 0 1 1 1
8 1 0 0 0
9 1 0 0 1

TABLE 3 DECIMAL BCD EQUIVALENT

It is called 8421 code as each digit is weighted from left to right in powers of 2.
You might be thinking that this is the same as the binary code; however, with
numbers from 10 upwards each number is represented by the 4 bit code. For
example 1110 to BCD is 0001 0001 leaving a space between each group of four
digits.

- 14 -
Another example 42910 to BCD

is 0100 0010 1001

Converting from BCD to Decimal is again quite easy. Split into four groups and
convert each group into BCD, eg convert 10000101 to BCD

Split into groups of four 1000 0101

8 5

so 10000101 = 8510

ACTIVITY 9 Convert the following Decimal numbers to BCD

(a) 94 (b) 529 (c) 2947

Convert the following BCD numbers to Decimal

(d) 011100001001 (e) 001101100100

Summary

By way of a summary and to enable a comparison to be made between a

number representation in the various systems and codes, consider the decimal
number 347. In its various forms:

DECIMAL 347
BINARY 101011011
8421 BCD 0011 0100 0111
OCTAL 533
HEXADECIMAL 15B

Any group of Binary digits is known as a WORD. Each word is formed by a

number of BITS (BINARY DIGITS) and this represents the word length.

MATHEMATICAL FUNCTIONS ON BINARY NUMBERS

Adding. The rules are similar to those when adding decimal numbers, eg 5 + 5
= 0 and carry 1 to the next higher ‘power’ column, and 1 + 1 in binary results
in 0 carry 1.

- 15 -
Rules

0 + 0 = 0
0 + 1 = 1
1 + 0 = 1
1 + 1 = 0 and carry 1
1 + 1 + 1 = 1 and carry 1

Example. Add 1011 and 1110

1011
1110
11001
111 Carry

= 11001

Subtraction. Similar to the rules for decimal subtraction except 0 – 1 = 1 and

borrow 1. Rules:

0 – 0 = 0
1 – 0 = 1
1 – 1 = 0
0 – 1 = 1 and borrow 1

Example. Subtract 10101 from 11011

11011
10101 –
00110
1 borrowed

Multiplication. This is very similar to Decimal multiplication. Rules:

0 x 0 = 0
0 x 1 = 0
1 x 0 = 0
1 x 1 = 1

Example. Multiply 1100 x 11

1100
11
1100
1100 ADD
100100

- 16 -
Multiplication in a computer is achieved by repeated addition (eg in Decimal 2
x 4 is computed as 2 + 2 + 2 + 2 = 8).

Division. Again not too unlike Decimal division. Rules:

1 0
1) 1 1) 0

Example. Divide 111100 by 110 (60 divide by 6)

1010
110) 111100
110
0011
110
00000

Check this by converting binary 1010 to see if the answer is correct.

Computers cannot divide; they carry out division by repeated subtraction,

which is in itself done by an addition process.

Positive and Negative Numbers

The computer needs to distinguish between positive and negative numbers for
data storage purposes. To do this there is usually an additional bit added
which identifies whether the number is positive or negative, eg ‘0’ for positive
numbers and ‘1’ for negative numbers.

Example – using an 8 bit binary word with the sign bit added on the front.

Decimal Binary
- 4.5 100100.100

sign bit
-ve
+ 10.25 001010.010

sign bit
+ve

This is a convenient method for storing numbers but does not allow direct
subtraction of one number from another. Computers, in fact, go through a
process of addition and do not subtract. By inverting each digit and adding 1
the negative of the number is obtained. This process is called TWO’s
COMPLEMENT. The Twos Complement process involves inverting each bit in a
word and adding 1.

- 17 -
Once the twos compliment of a number is found it can be added to any other
Binary number to give a result the same as subtraction.

Example. Find the negative binary number of +5 decimal.

+5 as a 4 bit word = 0101

invert (change ‘0’s to ‘1’s and ‘1’s to ‘0’s) = 1010
Add 1 1
1011

1011 is known as the Twos Compliment of 0101.

Note. Negative numbers have a 1 in the most significant bit position whilst the
positive number has a 0.

When numbers are represented as negative, subtraction is achieved by

addition (adding a negative number being the same as subtracting a positive
number) eg:

5 – 7 = 5 + (-7) +7 = 0111
Invert = 1000
Add 1 = 1001
so = 0101 + 1001

= 0101
1001 +
1110

1110 effectively = - 2

take +2 which = 0010

Invert 1101
Add 1 1
1110

Alternatively the two’s compliment of 1110 = 0010 = 2.

This means that both addition and subtraction can be done by the same
circuits in a computer, as well as multiplication and division.

DIGITAL CIRCUITS

Made up of conductors, digital to analogue converters, analogue to digital

converters, resistors, diodes, logic gates, various other devices and using low
dc voltages (about 5V).

- 18 -
LOGIC GATES

Used in logic networks to control the flow of data through the system. They are
called logic gates since the ‘gates’ are opened and closed by the binary inputs
in order to perform a logical function.

Logic gates are the basic building blocks from which many different kinds of
logical outputs can be obtained. The gates we shall consider are the AND,
NOT, OR, NAND, NOR and XOR gates.

They are made up of electronic components and the outputs can be

represented by Boolean algebra (named after George Boole English
mathematician 1815 –1864).

Logic gates have binary inputs of 1 or 0 and they may represent (in a circuit)
ON, CLOSED (logic 1) or OFF, OPEN (logic 0). We shall be using the American
symbols for the gates in this and all other LBP books. (There are British
Standard symbols but they are not in common use in the aircraft industry).

The AND Gate

This gate can have two or more inputs and only one output. It will give an
output if all inputs are on. If any one input is not available the output will be
zero. The symbol for a 2 input AND gate is shown below.

Fig. 1 ‘AND’ GATE SYMBOL

Fig. 2 ELECTRICAL ‘AND’ GATE CIRCUIT

The AND gate can be made up electrically by two switches in series. The lamp
will only light when switches A AND B are both made. If any one switch is
open the lamp will not light.

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The operation of the logic gate can be described by means of a TRUTH TABLE.

When switch A is open (logic 0) and switch B is open (logic 0) there is no

output to the lamp (logic 0). When switch A is made (logic 1) and switch B is
open (logic 0) there is still no output to lamp (logic 0).

When switch A is open (logic 0) and switch B is made (logic 1) – there still no
output to the lamp (logic 0). When switch A is made (logic 1) and switch B is
made (logic 1) there is an output to the lamp (logic 1). So when A AND B are
logic 1 then there is an output. This is summarised in the truth table:

A B S
0 0 0
1 0 0
0 1 0
1 1 1

The table shows A and B as the inputs and S as the output. There are only 2
inputs but there may be more, eg A, B, C, D, E etc.
.
The Boolean expression for this gate is written A B = S. The dot means AND,
and the expression is read as ‘A AND B equals S’ (the S is sometimes called z).

You should remember the symbols and the truth table.

ACTIVITY 10 Sketch a circuit for a three input AND gate and draw it’s symbol
and derive it’s truth table.

The OR Gate

Can have two or more inputs and will give an output if any one input is logic
1.

Fig. 3 ‘OR’ GATE SYMBOL

An OR gate electrical circuit can be made up by two switches in parallel (figure

4). The lamp will light if switch A OR B is closed.

- 20 -
 Fig. 4 ELECTRICAL ‘OR’ GATE CIRCUIT

So the truth table will be:

A B S
0 0 0 Both switches open
1 0 1 Switch A closed
0 1 1 Switch B closed
1 1 1 Switches A and B closed

The Boolean expression is:

A + B = S

The + means OR and the expression is read as ‘A OR B equals S’.

The NOT Gate

This gate has one input and one output.

Fig. 5 SYMBOL FOR A ‘NOT’ GATE

This gate produces an inversion of the input signal, so when the input is A the
output is NOT A, which is symbolised by a bar on top of the A = A. So the
output of this gate is the opposite to it’s input. So input logic 1, output logic 0.
Input logic 0, output logic 1. The truth table:

A S
1 0
0 1

- 21 -
The Boolean expression is:

S=A

The NAND Gate

This is short for NOT AND and works similar to a NOT gate except that it has
more than one input.

Fig. 6 SYMBOL FOR A NAND GATE

The bubble on the end of what is an AND gate has the same function as in the
NOT gate – it inverts the signal, except that in this case more than one input is
involved. In this gate when A is 0 AND B is 0 then the output is 1. In the AND
gate this would be 0. So the NAND gate is an inverted AND gate.

The truth table is:

A B S
0 0 1
1 0 1
0 1 1
1 1 0

The Boolean expression is:

.
A B = S .
The bar over A B gives NOT AND
and is read as ‘NOT (A AND B)
EQUALS S’.

The NOR Gate

This is short for NOT OR and is simply a negated OR gate.

Fig. 7 SYMBOL FOR A NOR GATE

- 22 -
Again an input A = 0 and B = 0 would, for a OR gate, give 0 as an output, but
for the NOR gate it would give a 1 as an output.

The truth table is:

A B S
0 0 1
0 1 0
1 0 0
1 1 0

The Boolean expression is:

A+B=S The bar over A + B gives NOT OR and is

read as ‘NOT (A OR B) equals S’.

The XOR Gate

You may have noticed that the OR gate gives an output when A OR B = 1 and
when A AND B = 1. The XOR gate only gives an output when A OR B are 1 not
when A AND B are 1, so it is exclusively an OR gate and will not work under
the AND function. It is read as a two syllable word x then or.

Fig. 8 SYMBOL FOR XOR GATE

The truth table is:

A B S
0 0 0
1 0 1
0 1 1
1 1 0

The Boolean expression is:

AB+AB =S

which is read as ‘NOT A AND B OR A AND NOT B EQUALS S’.

It should be appreciated that for all the gates so far discussed we have
assumed logic 1 is positive (+5 volts) and logic 0 is zero (0 volts). This is called
POSITIVE LOGIC and is the notation most frequently used. However,
NEGATIVE LOGIC may be used, and this means that logic 0 is positive (+5
volts) and logic 1 is zero (0 volts). We shall use positive logic throughout this
book.

- 23 -
To consolidate your knowledge of logic gates we shall put a few together to
make up some simple logic circuits. Note that bubbles on inputs (or outputs)
to/from gates negates or inverts the signal.

Fig. 9 LOGIC CIRCUIT 1

With reference to logic circuit 1 figure 9, what is the output logic level S if A =
logic 1, B = logic 0 and C = logic 0?

With A = 1 and B = 0 (remember this 0 is changed to 1 by the bubble) the

output of gate 1 = 1. The input to gate 2 is 0 (the 1 from gate 1 is inverted, and
input C = 0) so the output is 0.

What would be the Boolean expression for this circuit?

.
The output of gate 1 is A B (read as ‘A AND NOT B’).

..
The output of gates 1 and 2 is A B C (read as ‘NOT [A AND NOT B] AND C’).

ACTIVITY 11 Study the following circuits (figures 10 and 11) and determine
the logic level of the output from each.

(a)

Fig. 10 LOGIC CIRCUIT 2

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- 24 -
 (b)

Fig. 11 LOGIC CIRCUIT 3

ELECTRONIC GATE OPERATION

The earliest examples of logic mechanisms were those using mechanical levers
(the key in a lock for example – which is AND logic), gear wheels etc. Other
systems used low-pressure highly filtered air in accurately engineered logic
gates to control machines (commonly machines used in production
engineering). These devices were slow, heavy and prone to failure due to their
moving parts.

Electrics have played a part in logic circuits as shown in the drawings above
on AND and OR circuits. Micro switches, suitably wired are still used on many
aircraft to perform logic functions. With the introduction of electronics, solid-
state circuitry can perform the most complex logic functions with the
advantages of minimal size and weight; very low power consumption, and very
fast operation.

We shall be concentrating on electronic systems in this book.

The simplest logic system using discrete components was the diode-resistor
(DR) logic and figure 12 shows an AND gate made from these components.

Fig. 12 DR ‘AND’ GATE CIRCUIT

- 25 -
Note that the 0V line is shown as an earth or ground line as the AND circuit
will be connected to an earthed circuit at the S output.

When A or B = 0 then current will flow from the +ve 5V supply line through the
resistor and the diodes. This means that all the voltage is dropped across the
resistor and no voltage is on the output line, so the output (S) is 0V (logic state
0).

When A and B are logic 1 (+5V), no current flows, voltage is the same both
sides of resistor R and the output is +5V (logic state 1).

The diagram below shows an OR gate.

Fig. 13 DR ‘OR’ LOGIC CIRCUIT

When A or B are logic 1 (+5V) current will flow and S will be high (logic 1).
When A and B have no voltage supply (0V) then there will be no output voltage
at S (S = logic 0).

The next advance was resistor transistor logic (RTL) and diode transistor logic
(DTL). The diagrams below show some typical circuits.

Fig. 14 RTL NOR GATE

- 26 -
 Fig. 15 DTL NAND GATE

Today since the integrated circuit (IC) became possible the logic gates work by
transistor-transistor logic (TTL), metal oxide semiconductors (MOS) and
complementary metal oxide semiconductor (CMOS) group of families.

The integrated circuit (IC) is a complete electronic circuit, transistors, diodes,

resistors, capacitors, all made from one ‘chip’ of silicon, typically 5mm square
and 0.5mm thick.

The following diagram shows a typical IC with its plastic case partly cut- away
to show the ‘chip’.

Fig. 16 AN IC PACKAGE

Note the metal pins – for inserting into a suitable IC socket or to be soldered
into a PCB (Printed Circuit Board). Note also the metal connections from the
chip to the pins. The reason for this form of construction is so as to allow the
chip to be connected to other circuits. It is too small, in it’s original form, to be
handled and/or to be connected to anything.

The scales of integration refer to the number of gates contained in a single IC

package:

- 27 -
eg:

* Small-scale integration (SSI) – containing no more than 11 gates.

* Medium scale integration (MSI) – containing up to 100 gates.
* Large-scale integration (LSI) – containing between 100 to 1000 gates.
* Very large scale integration (VLSI) – containing over 1000 gates.

The diagrams below show the some TTL and CMOS gates.

Fig. 17 TTL ‘AND’ GATE

Fig. 18 TTL NAND GATE

blank

- 28 -
 Fig. 19 CMOS NOR GATE

Fig. 20 CMOS NAND GATE

Properties of TTL and CMOS Gates

TTL uses bi-polar transistors along with diodes and transistors formed to
microscopic dimensions on a slice of silicon (chip). TTL must have a steady 5V
dc supply, while CMOS will work on dc voltages between 3 and 15V and
usually requires much less power. CMOS uses unipolar Field Effect
Transistors (FETs) with metal-oxide-silicon technology, this lends itself to VLSI
as they take up less room on a chip, compared to the TTL. CMOS has a much
higher input impedance.

One important point with CMOS is that if static electric charges are allowed to
build up on it’s input pins, these voltages can break down the thin layer of
silicon oxide insulation between the gate and the other electrodes of
MOSFET’S and this will destroy the IC. So anti-static protection is important.
Never touch the pins.

- 29 -
Gate operating parameters include:

(a) Speed of operation

(b) Fan in
(c) Fan out
(d) Noise margin
(e) Power dissipation

Speed of operation. The time that elapses between the application of a signal to
an input terminal and the resulting change in the logical state at the output
terminals.

Fan-in. The number of inputs coming from similar circuits that can be
connected to the gate without adversely affecting it’s performance.

Fan-out. The maximum number of similar circuits that can be connected to

it’s output terminals without the output falling outside the limits at which
logic levels 1 and 0 are specified.

Noise margin. This is maximum noise voltage (unwanted voltage) that can
appear at it’s input terminals without producing a change in output state.

Power dissipation. As in any circuit, supply voltage multiplied by the current

(Power = V x I) gives the power in the circuit. As power produces heat so this
must be dissipated.

Typical figures for TTL and CMOS are shown below (details need not be
committed to memory).

Speed of Fan Fan Noise Power

Operation in out margin dissipation
Standard TTL 9nS 8 10 0.4v 40mW
CMOS 30nS 8 50 1.5v .001mW

If you look back at the diagrams for the TTL AND gate and the TTL NAND gate
you will see that the NAND gate uses fewer components and is therefore
cheaper to produce.

This also applies to the NOR gate, ie it is cheaper to produce than the OR gate.

NAND gates can be connected together to form any of the other basic gates –
thus reducing production costs by manufacturing one gate only.

The following drawings show how these gates can be formed. Take a moment
to study each gate arrangement and check that it does perform the logic
function
described

- 30 -
 Fig. 21 VARIOUS GATE ARRANGEMENTS

The following drawings show the pin connections of ICs for different gate
configurations. There is no need to remember them but it does give a good idea
of how the chip (with the gates in) is connected externally – although the chip
itself is so small that it looks like a small piece of silver metal 4 or 5 mm
square and about as thick as a piece of paper.

- 31 -
Fig. 22 PIN CONNECTIONS FOR A TTL NOR GATE

Fig. 23 PIN CONNECTIONS FOR A CMOS NOR GATE

Fig. 24 PIN CONNECTIONS FOR A TTL ‘AND’ GATE

- 32 -
 Fig. 25 PIN CONNECTIONS FOR A CMOS ‘AND’ GATE

It is sometimes useful to know other logic gate representations. The drawings

below show some alternative logic gate symbols.

Fig. 26 ‘AND’ GATE

Fig. 27 ‘OR’ GATE

Fig. 28 NAND GATE

Fig. 29 NOR GATE

- 33 -
 Fig. 30 ‘NOT’ OR INVERTING GATE

At first sight it might appear that they are not equivalent by looking at the
Boolean expressions. However using De Morgans rules we can prove they are
the same.

De Morgan’s rules state:

A+B = A.B

A.B = A + B

Taking rule 1. NOT A OR B = NOT A AND NOT B. To apply the rule, split the
bar and change the sign.

A + B split the bar A + B and the change the sign A . B

Taking the first AND gate output A.B. The equivalent circuit output is A + B.

Splitting the bar = A + B and changing the sign = A . B. A double bar over
a letter removes both bars, ie second bar negates the single bar so the output
is A.B, the same as the AND gate. This procedure can be used with all the
equivalent circuits. However, much more importantly, to convert the AND gate
into it’s OR gate equivalent, draw the OR gate, remove bubbles where there are
any and add bubbles where there are none. There are no bubbles on the AND
gate so add bubbles on all three connections of the OR gate.

If you look at the NAND gate you will see that the OR gate has two bubbles on
the input (none on the NAND) and none on the output, (one on the NAND). So
WHERE THERE ARE BUBBLES REMOVE THEM, WHERE THERE ARE NO
BUBBLES PUT SOME IN, this will then give you the equivalent circuit.

ACTIVITY 12 Draw the equivalent circuits of the gates shown below.

- 34 -
 ADDERS

Adders may be in the form of Full Adders or Half Adders. They perform binary
addition and are used in many applications.

The Half Adder

This adds two bits at a time and has a total of four cases to deal with. Figure
31 shows the symbol and table 4 gives the truth table.

Fig. 31 HALF ADDER SYMBOL

Inputs Outputs
A B Sum Carry
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1

TABLE 4 TRUTH TABLE

Note that 1 + 1 = 10 (two), ie 0 carry 1, the carry being used as an input to the
next part of an adder circuit.

There are many ways of building a half-adder from logic gates, one such circuit
is shown in figure 32.

Fig. 32 HALF ADDER CIRCUIT

- 35 -
 A B Sum Carry
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1

TABLE 5 TRUTH TABLE

Follow each addition through. You may well need to look back at the exclusive
OR and AND gate truth tables.

In computers half-adders are combined to make full adders, this adds three
bits at a time and therefore has inputs A, B and C. The basic circuit is shown
in figure 33.

Fig. 33 FULL ADDER - 1

It consists of two half-adders and an OR gate. You will need to go through all
possible combinations, but just as an example we will check the addition of
1 + 1 + 1 (figure 34).

Fig. 34 FULL ADDER - 2

Half adder 1 (H/A 1) has both inputs 1 so gives an output of sum = 0, carry =
1. H/A 2 has inputs of 1 and 0 and this gives an output of sum = 1 carry = 0.
The sum is the output of the full adder, ie 1 and the two inputs to the OR gate
are 1 and 0 so the output (carry of the full adder) is 1. So the answer is 1 carry
1. The truth table for the other three bit combinations is shown in table 6. Try
these for yourself.

- 36 -
 Inputs Outputs
A B C Sum Carry
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
1 0 0 1 0
0 1 1 0 1
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

TABLE 6 TRUTH TABLE

Two multi-bit binary numbers are added by connecting adders in parallel, eg

to add two four-bit numbers, four adders are needed.

COMPARATORS

Within digital systems there are many instances where we need to compare the
values of two binary numbers. The three basic instances are:

A > B A greater than B

A < B A less than B
A = B A equal to B

Fig. 35 COMPARATOR CIRCUIT - 1

The basic logic gate circuit for A > B is shown in figure 35. If A = 1 and B = 0,
the input to the AND gate is 1,1 so the output is high. If A = 0 and B = 1 then
the input to the AND gate is 0,0 and the output is low, so the output is only
high when A > B.

The basic logic gate circuit for A < B is shown in figure 36.

Fig. 36 COMPARATOR CIRCUIT - 2

- 37 -
If B = 1 and A = 0 the inputs to the AND gate is 1,1 so the output again is
high. If B = 1 and A = 1 inputs to the AND gate is 0,0 so the output is low. So
the output is only high when A < B.

The following logic gate circuit combines the two circuits discussed so far but
with their outputs also connected to a NOR gate, the complete combination
giving A > B, A < B and A = B.

A
A C
B A B

E
A=B

A
D
B A B
B

Fig. 37 COMPARATOR CIRCUIT - 3

The truth table below shows output E is only high (logic 1) when A = 1 and B =
1 and also when A = 0 and B = 0.

A B A B C D E
1 0 0 1 1 0 0
1 1 0 0 0 0 1
0 0 1 1 0 0 1
0 1 1 0 0 1 0

TABLE 7 TRUTH TABLE

With further logic gates it is possible to compare two two-bit numbers and two
four-bit numbers.

We now need to look at how these gates are used in aircraft circuits. You
should be able interpret these diagrams and explain how an output is arrived
at. You should also be able to describe the operation of a logic circuit if an
unexpected logic input is present.

Logic gate circuitry is extensively used in aircraft schematic diagrams for all
aircraft systems including airframe systems, engine systems, instrument and
avionic systems.

- 38 -
 LOGIC CIRCUITS – EXAMPLES

Figure 38 shows an aircraft take-off warning circuit to warn the pilot when
he/she is about to take-off if the aircraft is not correctly configured for take-
off. It can be seen that it consists of two OR gates and an AND gate, with logic
states received from 7 parameters.

When either throttle lever is pushed forward, the switch at that position is
made (advance) and there is a logic state 1 to OR gate 1.

Five other parameters are sensed and logic states sent to OR gate 2.

If all the other parameters are in the take-off position, ie

1) Slats fully extended

2) Flaps less than 25°
3) Spoilers in
4) Horizontal stabiliser in the green band (correct angle of incidence
for take-off)

then the inputs to OR gate 2 are all logic 0 and it’s output to the AND gate is
logic state 0.

Aircraft on the ground (weight switch) gives another logic 1 to the AND gate,
which has at this time 2 logic 1’s and a logic 0.

If either of the four inputs go out of the take–off position, eg flaps greater than
25°, then the flap input signal to logic gate 2 is logic 1 which makes the input
to the AND gate logic 1. The AND gate now has three logic 1’s which now gives
an output to the warning circuits (CONFIG light and aural warning in the
flight deck).

blank

- 39 -
Fig. 38 TAKE-OFF WARNING SYSTEM

- 40 -
Figure 39 shows a diagram is of an undercarriage ‘gear disagree’ indication
circuit. Systems 1 and 2 sense any disagreement between the landing gear
position and the landing gear selector lever position. So if a disagreement is
detected then the ‘gear’ light illuminates.

Fig. 39 GEAR LEVER ‘DISAGREE’ CIRCUIT

ACTIVITY 13 Explain the operation of the circuit (figure 39).

To further enhance your ability to interpret logic diagrams,

study the next drawing. It is a take-off warning circuit to warn
the pilot if the aircraft is in the incorrect configuration for take-
off. Draw the logic circuit for the diagram.

blank

- 41 -
 Fig. 40 TAKE-OFF WARNING CIRCUIT

It is important that you look at the logic schematic diagrams for your aircraft
and work out how the gates are used.

SEQUENTIAL/COMBINATIONAL LOGIC

Before we tackle actual devices we need to look at some memory type circuits
which use sequential logic ie, their outputs depend not only on their present
inputs but on past ones as well.

So far we have only been looking at combination logic circuits whose outputs
are always the same for the same combination of inputs.

FLIP-FLOPS

Memory type circuits use ‘flip-flops’ as their main components. There are many
different types but we shall look at three, the SR or RS, D and JK flip-flops.
These are so called because on the application of a suitable pulse at the input
it causes it to ‘flip’ into one of it’s two stable states and stay in that state until
a second input will ‘flop’ it into its previous state.

- 42 -
The SR Flip-flop

The SR flip-flop has two output terminals Q and Q (spoken as Q and NOT Q).
Figure 41 shows the SR flip-flop using NAND gates. Note that the output from
each of the last NAND gates is fed back to the input of the other NAND gate.

Fig. 41 SR FLIP-FLOP

When S = 1 and R = 0, Q = 1 and Q = 0 and the flip-flop is SET.

When S = 0 R = 1 Q = 0 Q = 1 then the flip-flop is RESET

When S = 0 and R = 0 then no change occurs and Q and Q will be what they
were before.

When S = 1 and R = 1 then Q = 1 and Q equals 1. The circuit is stable while S

= R = 1, but if they are changed simultaneously from 1 to 0 then due to
different switching times of the gates we cannot predict whether Q or Q will be
1.

The output state is said to be indeterminate so S = R = 1 should not be allowed

to occur. The truth table is shown below.

S R Q Q
1 0 1 0
0 1 0 1
0 0 Depends on state before inputs applied
1 1 Indeterminate

So basically the flip-flop can exist in two stable states:

Q = 1 (Q = 0) or Q = 0 (Q = 1)

- 43 -
Clocks

In sequential logic circuits where there may be a large number of flip-flops, it

is important they all act at the same time, so no circuit operates out of
sequence.

This is achieved by a CLOCK pulse which is derived from a pulse generator

with a high frequency. The circuits may be triggered when the clock pulse
changes from 1 to 0 or when it changes from 0 to 1 (edge triggered) or when
the level is 1 or 0.

The diagrams below shows a clocked SR flip-flop and it’s truth table.

Fig. 42 CLOCKED SR FLIP FLOP

OUTPUTS OUTPUTS
DURING
BEFORE AFTER
INPUTS CLOCK
CLOCK CLOCK COMMENTS
PULSE
PULSE PULSE
S R A B Q Q Q Q
0 0 1 1 1 0 1 0 NO CHANGE IN
0 0 1 1 0 1 0 1 OUTPUTS

1 0 0 1 1 0 1 0 FLIP-FLOP SETS
WITH
1 0 0 1 0 1 1 0 Q=1 & Q=0
0 1 1 0 1 0 0 1 FLIP-FLOP
RESETS WITH
0 1 1 0 0 1 0 1 Q=0 & Q=1
1 1 0 0 1 0 1 1 THIS INPUT IS
1 1 0 0 0 1 1 1 NOT ALLOWED

TABLE 8 TRUTH TABLE FOR THE CLOCKED SR FLIP-FLOP

- 44 -
The D Type SR Flip-flop

This is a modified SR flip-flop and the D stands for delay. If you look at the
truth table (table 9), when the clock pulse changes (rises), whatever is at D is
transferred to Q, when the clock pulse falls Q stays at that level. No matter
what is applied to D, Q will only change state at the next clock pulse. The truth
table shows that the output equals the input one clock pulse earlier ie, the
data is held back until the clock pulse = 1.

Fig. 43 CLOCKED D TYPE FLIP-FLOP

OUTPUTS
OUTPUTS AFTER
INPUT BEFORE CLOCK
CLOCK PULSE
PULSE

D S R Q Q Q Q
0 0 1 1 0 0 1
0 0 1 0 1 0 1
1 1 0 1 0 1 0
1 1 0 0 1 1 0

TABLE 9 TRUTH TABLE FOR THE CLOCKED D TYPE FLIP-FLOP

The JK Flip-flop

The next drawing (figure 44) shows the layout of a JK flip-flop using NAND
gates and its the truth table is shown in table 10.

- 45 -
 Fig. 44 THE JK FLIP-FLOP

OUTPUTS
DURING CLOCK OUTPUTS AFTER
INPUTS BEFORE CLOCK
PULSE CLOCK PULSE COMMENTS
PULSE
J K Q Q A B Q Q
0 0 1 0 1 1 1 0 NO CHANGE IN
0 0 0 1 1 1 0 1 OUTPUTS

1 0 1 0 1 1 1 0 STAYS AT OR
SETS TO
1 0 0 1 0 1 1 0 Q=1&Q=1
0 1 1 0 1 0 0 1 STAYS AT OR
RESETS TO
0 1 0 1 1 1 0 1 Q=0&Q=1
1 1 1 0 1 0 0 1
TOGGLES
1 1 0 1 0 1 1 0

TABLE 10 TRUTH TABLE FOR THE JK FLIP-FLOP

The two inputs are called J and K, the operation is fully described in the truth
table and J = K = 1 is allowed (unlike S = R = 1 in a SR flip flop which is not
allowed) and toggles (changes state) when this input is applied.

These flip-flops are used in counters and shift registers and a wide variety of
logic circuits.

Counters

There are many types of counters and the flip-flop counter is the one
discussed here. The next diagram shows the basic principles of counting using
flip-flops. It is a 4 bit binary counter using JK flip-flops. The J & K inputs are
at logic 1 so any pulse 1 to 0 will trigger the output to change from it’s
previous state. The output of one flip-flop is the input to the next – they are
said to be connected in ‘cascade’.

- 46 -
 Fig. 45 FOUR BIT BINARY COUNTER

As can be seen from figure 45, every time the input pulse falls from 1 to 0 the
counter increases the 4 bit binary number by 1. This means that QA is the
least significant bit and QD is most significant bit.

After the first pulse QA = 1 QB = 0 QC = 0 QD = 0, so the number is 0001 ie,

decimal 1. After the second pulse QA flips back to 0, QB = 1, QC = 0, QD = 0
which is 0010 (decimal 2).

You should now be able to follow the sequence through yourself. Remember
every time the outputs go from 1 to 0 the next flip-flop triggers. When the
count reaches 1111 (15) all four flip-flops are reset.

Studying the diagram further you will see it takes two input pulses to make
flip-flop A go from 0 to 1 and back to 0, two pulses from QA to force QB from 0
to 1 and back again, and so on down the chain.

- 47 -
In fact, each flip-flop acts as a divide by two circuit and four flip-flops in a
chain like this make a divide by 16 circuit, because the pulse frequency at QD
output is one sixteenth of the frequency of the input.

So this chain of flip-flops can be referred to as either a divide by 16 counter or

modulo 16 counter (modulo means the maximum number a counter can count
to, which is of course the same number it divides by).

QUESTION If there are two flip-flops connected in cascade what would the
division be? (5 mins). If you are not sure of the answer check with
your tutor (Full Students).

Shift Registers

A register is a number of flip-flops arranged in a circuit (typically D or JK) used

for storing data. A shift register is one that is designed to move the data along
the register. The next diagram shows a 4-bit register using JK flip-flops.

Assume the register is cleared and therefore reads 0000 and an externally
generated word 1011 is to be stored in the register. At the end of the first clock
pulse QA = 1 and JB = 1. After the second clock pulse flip-flop B is set QA = 1
QB = 1.

The state of the register when the third clock pulse arrives is JA = 0 KA = 1
JB= JC = 1 KB = KC = 0 and at the trailing edge of the clock pulse flip-flop A
resets and flip-flop C sets. Now QA = JB = 0, QB = QC =JC = JD = 1.

The last bit to be stored is 1 and at the end of the fourth clock pulse flip- flops
A, C and D are set and flip-flop B is reset ie 1011 is stored. The effect of each
clock pulse is to shift the content of the register one place to the right.

Fig. 46 A FOUR BIT SHIFT REGISTER

- 48 -
The shift register shown is SERIAL IN and SERIAL OUT but a register can also
be:

* Serial in – parallel out

* Parallel in – serial out
* Parallel in – parallel out

Fig. 47 REGISTER - SERIAL IN PARALLEL OUT

Fig. 48 REGISTER – PARALLEL IN SERIAL OUT

Fig 49 REGISTER – PARALLEL IN PARALLEL OUT

ENCODERS & DECODERS

Encoders

These are generally at the input end of a system to convert the input signal
into a binary code necessary for the operation of the system. Encoding circuits
may take many forms eg: convert an analogue signal to BCD or 4-bit binary
code; take in a binary signal and convert it into another code to suit the
system eg, OCTAL to BCD etc.

- 49 -
 Fig. 50 DECIMAL TO BCD ENCODER

Figure 50 shows a keyboard layout (decimal input) to give a BCD output. By

pressing any one key or switch (suitably decimal numbered) the appropriate
BCD code is given at the output.

Assume ‘4’ is pressed then diode D5 will conduct through RC making the
output (C) go high, all the other inputs stay low (DBA), so the output is 0100
(decimal 4).

This principle will be employed in INS (Inertial Navigation Systems), IRS

(Inertial Reference Systems) and FMS (Flight Management Systems) as all
these have input keyboards.

Some form of encoding will be needed to convert the input signals into the
correct code for the system.

In Flight Data recording some of the inputs into the system are in analogue
form, such as dc, ac or syncro signals. This means that they have to be
encoded into digital form for use by the Central Processing Unit (CPU). This is
done by an Analogue to Digital Converter.

- 50 -
ANALOGUE TO DIGITAL CONVERTERS

There are several different converters available and different manufacturers

may call the same converter by a different name. The converter changes the
analogue signal to a digital signal, usually for signal transmission purposes,
and after transmission the signal may be changed back to its original analogue
form.

Here we will cover the following:

* The Digital Ramp converter.

* The Successive Approximation converter.
* The Integrating converter.
* The Charge Balancing converter.

The Digital Ramp Converter

Figure 51 shows the basic layout of a digital ramp converter. Study the
drawing and note the analogue input and the clock and start inputs. Note that
the DAC is a digital to analogue converter.

When the start pulse logic 1 is applied, the counter is reset, no pulses are fed
through the AND gate as it is ‘closed’.

The comparator in the drawing compares the voltages of each input to

determine which is greater. The output is logic 1 if A is larger than B and logic
0 if input B is larger than A. On start, B is 0 and A is the larger output. From
the comparator the output is logic state1 and when the start pulse goes low
the AND gate ‘opens’ and the clock pulses go to the counter. Each pulse
causes the counter to advance.

Fig. 51 DIGITAL RAMP CONVERTER

As the counter counts up, its value is converted into its analogue equivalent by
the digital to analogue converter (DAC or D to A or D/A) and applied to the
comparator at B.

- 51 -
The DAC output therefore increases in steps until it reaches just above the
analogue input level, ie B input > A. The comparator output goes low, the AND
gate closes, the count stops, and the digital read-out is then taken from the
counter.

The best approximation that can be obtained depends on how much input B
has to be greater than A, ie the step size. This is known as the Quantization
Error. This type of Analogue to Digital (ADC or A to D or A/D) converter is slow
in operation and unsuitable for high-speed operation, and, of course, the
larger the voltage the longer time it takes (more steps). The comparator would
be an operational amplifier (see LPB EASA module 4 books).

This problem can be partly overcome by using an up/down counter. It counts

up when the comparator is logic 1 and down when the comparator output is
logic 0. As the analogue input varies it simply counts up or down from the
previous count rather than re-setting to zero as did the digital ramp converter.
This type is called the continuous digital-ramp converter and is a considerable
improvement on the previous one.

The Successive Approximation ADC (figure 52).

This is a faster ADC and is similar to the previous circuit but the register is
used instead of a counter and a control logic circuit is included between the
comparator and register, which controls the output of the register.

Initially a reset signal puts all bits in the register to 0. The control logic (first
clock pulse) sets the MSB in the register to 1 and the rest to logic 0. The
output of the DAC is then compared to the analogue input (A). If B < A then
the MSB remains at 1. If B > A it is set to zero.

Fig. 52 SUCCESSIVE APPROXIMATION A TO D CONVERTER

At the next clock pulse the control changes the next bit in the register to logic
1, if B > A it is set to 0, if B < A it remains at 1 and so on until all the bit
values are found. The digital read-out can then be read.

This DAC has a fast conversion time which does not depend on the analogue
voltage level but just on the number of bits in the converter. The converter has
a good resolution and a wide range.

- 52 -
The Integrated (Duel Slope) Converter

This uses an analogue circuit integrator (see module 3). The output voltage of
an integrator varies, not just as a function of the input but also as a function
of time. For example, if the input voltage changes ‘instantly’ (say from 0V to
5V) it takes time ‘t’ for the output voltage to change the same amount. This
can be seen in figure 54 where the input is shown as a positive pulse.

Fig. 53 INTEGRATING A TO D CONVERTER

Fig. 54 INTEGRATOR INPUT & OUTPUT WAVEFORMS

The output of the integrator is a slowly changing voltage, rising to a peak then
decreasing back to zero. Voltages which change like this are often called
‘ramps’ and the voltage ramps-up when it increases and ramps-down when it
decreases.

This converter uses an electronic switch to change the integrators input

voltage between the analogue voltage to be converted (Vin) and a reference
voltage (-Vref).

By integrating the analogue voltage for a fixed time t1 then counting the clock
pulses for the time t2 which the integrator takes for its output to fall back to
zero (ie capacitor fully discharged at a fixed rate) then this time is a measure of
the analogue input.

These converters are slower that the Successive Approximation type but can
be very accurate and have a high immunity to noise. Often used in digital
multimeters where accuracy and not speed is the prime concern.

- 53 -
The Charge Balancing Converter

Where a better than 16 bit resolution is required at high speed, conversion

techniques such as Successive Approximation become less effective. High
speed digital circuits have made possible converters using over-sampling
techniques which work at sampling frequencies much higher than the
theoretical minimum for the bandwidth. This has the benefit of reducing the
noise level. Over-sampling is sometimes known as Delta Sigma conversion and
uses a Charge Balancing converter.

Fig. 55 DELTA SIGMA OVER SAMPLING ADC

With reference to figure 55. The differential amplifier (op-amp) at the input is
continuously comparing the analogue input signal with the output of the
internal 1 bit DAC (Digital to Analogue Converter).

This is typically working at 256 times the required sample frequency of the
final digital output. That is, if the final sampling rate is 44.1kHz the internal
sampling clock would be 11.2896MHz.

The output of the differential amplifier is integrated, then fed to a comparator

whose output is clocked at the over sampling rate. If the integrator output is
greater than 0V the comparator outputs a stream of binary ‘ones’ and if it is
less then 0V a stream of zeros is the result. The comparator is, therefore, a 1
bit ADC and generates a serial bit stream of 1s and 0s according to the value
of the integrated output of the differential amplifier.

The differential amplifier produces the difference between the instantaneous

voltage on the analogue input and the average value of the immediately
preceding analogue samples.

- 54 -
The term Charge Balancing comes about because the whole aim of the DAC –
differential amplifier – comparator loop is to maintain a zero charge on the
integrator capacitor.

The clocked comparator produces just sufficient logic 1 pulses at any one time
to cancel (via the differential amplifier) the charge due to the analogue input
flowing into the integrator. In other words the output of the AND gate carries a
high speed bit stream clocked at typically 11.2896MHz where the density of
the ‘ones’ is proportional to the analogue voltage.

Converting this bit-stream into a 16 bit parallel digital output clocked at

44.1kHz is normally carried out using a low pass filter which removes fast
changes in the digital signal and hence time averages it ready for re-sampling
at any chosen rate.

TERMINOLOGY

Resolution. The number of steps the input range is divided into. This is
usually expressed as bits (n) and the number of steps is 2n – 1 (which equates
to 2n values). A converter with a 12 bit resolution divides the range into 212 or
4096 values.

Range. The input (or gain) range refers to the maximum and minimum voltage
that will be digitised by the ADC.

Sample and Hold Acquisition Time. A sample and hold circuit ‘freezes’ an
otherwise varying analogue voltage at the moment the sample is required. This
voltage is held constant while the signal is digitised by the ADC. The
acquisition time is the time between releasing the hold state and the sample
circuit settling to a new input voltage. Sample and hold circuits are not used
with integrating converters.

Throughput. This the maximum rate at which the converter can acquire and
transfer values, eg if a converter takes 10µs to acquire and convert, it will be
able to generate 100,000 samples per second.

Linearity. Ideally an ADC with n bit resolution will convert the input range into
equal steps. In practice the steps are not exactly equal, which leads to non-
linearity in a plot of A to D output against input signal.

Offset Errors. Offset is where a reading other than zero for a zero condition is
obtained. It means that every reading will be inaccurate by this amount.

- 55 -
DECODERS

A decoder is a device which is usually at the output end of a digital system and
converts the binary code into decimal ie, changes the operational working code
into the code necessary to operate the system. Some examples of this are
where BCD is converted into a code necessary to operate a seven-segment
display. The next diagram shows such a display.

Fig. 56 BCD TO SEVEN SEGMENT DECODER

Another example would be a digital altimeter, or Machmeter/ASI where the

input signal has to be converted from the digital input (from the Digital Air
Data Computer (DADC) to an analogue signal to drive the altimeter pointers
and counters, this would be achieved by a DIGITAL TO ANALOGUE
CONVERTER.

The Digital to Analogue Converter

Figure 57 shows a binary weighted resistor method, so called as the values of

the resistors increase in accordance with the binary system eg, R, 2R, 4R, 8R.
The output from the resistor chain is connected to an operational amplifier as
a summing amplifier with a feedback resistor R f. The output V0 is therefore V0
= Rf ( V1 + V2 + V3 + V4 ) (see EASA study books Module 4).
(R 2R 4R 8R)

Also in the circuit are four switches S, S1, S2, S3, and S4 which are electronic
switches (digitally controlled). Each switch connects the resistor to a fixed
reference Vref when the input bit is logic 1 (+5v) and to ground (0v) when the
input bit is logic 0.
- 56 -
 Fig. 57 DIGITAL TO ANALOGUE CONVERTER

Assuming that Rf = R = 1K then the output formula becomes:

V0 = (V1 + V2 + V3 + V4 )
(1 2 4 8 )

If the input number is 0001 then:

V1 = V2 = V3 = 0

ie each of the electronic switches is connecting the input to ground.

V4 will be connected to Vref, we will assume that Vref is – 8v so the formula

becomes:

V0 = - ( 0 + 0 + 0 - 8 )
8
V0 = + 1V

As you can see the weighting of the LSB is 1V in this case.

Note. With the example shown the output was positive but if Vref was +8V then
the output would be –1V.

With an input of 0100 V1 = V3 = V4 = 0 and V2 = Vref .Assume again Vref = -8V

V0 = - (0+ - 8 + 0 + 0)
(2)

- 57 -
V0 = - (- 8)
(2)

= + 4V

ACTIVITY 14 If the Vref is –5V what would be the weighting of the LSB in this
system where Rf = R = 1K? Use input 0001.

The accuracy of this system depends on the resistors and the precision of the
input supply. Resistors can be made to reasonable accuracy and the electronic
switches can be replaced by precision level amplifiers. These ensure there
outputs are exactly 5V or 0V depending on their outputs.

High input ensures 5V from the amplifier to the input resistor of the op-amp
(operational amplifier) and a low output ensures 0V.

The R–2R Type D to A Converter

Another problem is, the larger the bit word the more the range of resistors is
required ie, for every extra bit the range of the required resistors doubles. So
another method of converting digital to analogue must be found for digital
words with a large number of bits. It is called the R–2R type.

The circuit works on the principle that a pair of 2R resistors at the end of the
ladder can be considered in parallel, forming an overall resistance R.

This system does use twice the number of resistors compared to the binary
weighted network, but the use of only two values of resistors means the
system can handle any number of input bits, simply be extending the resistor
ladder.

Fig. 58 R-2R TYPE OF D TO A CONVERTOR

- 58 -
There is no need to commit the details of the operation to memory but you
should know it exists.

MULTIPLEXERS & DEMULTIPLEXERS

Multiplexers

The idea of multiplexing/de-multiplexing is to send data from several sources

down the one data transmission line – thus saving weight.

A multiplexer is a device which selects data from one of many inputs and
connects this data to a common single output. Some practical examples are in
Flight Data Recording (FDR) where the Digital Flight Data Acquisition Unit
(DFDAU) receives a large number of inputs from the various aircraft
parameters which have to be sampled and fed to the FDR.

Another example is in passenger entertainment systems where the passenger

can select one audio/visual channel from amongst many channels supplied to
the seat. These channels (inputs) are multiplexed in that each input is
sampled and passed in serial fashion along a data line.

When the passenger selects the required service eg the film channel, then only
the information on that line relevant to the film channel is selected by a de-
multiplexer and fed to the passenger.

A multiplexer/de-multiplixer system can be likened to a train service between

two cities (say London and Paris) each having a railway station with several
platforms arranged in parallel. Each platform (say in London) has a train
waiting to go to Paris but there is only one main line between the two cities.
Each train leaves its platform in turn and is caused to go onto the main line by
a set of points (multiplexer). It travels on the main line until it reaches its
destination station where it is caused to go to it’s own platform by another set
of points (de-multiplexer).

Each train is sent down the same main line in this fashion. Data can be
transmitted like this, but at much greater speeds of course.

The multiplexer unit can be likened to a mechanical rotary switch (see drawing
below), with separate units of data waiting in temporary store to be
transmitted down the data output line. In reality it is electronic with no
moving parts and is very fast.

- 59 -
 Fig. 59 SIMPLE REPRESENTATION
OF A MULTIPLEXER

Figure 60 shows the basic principle of a multiplexer showing the data to be

transmitted (A, B, C, and D). When the command signals X and Y = 0 then
NOT gates would be at 1 and gate1 would be open if A is at 1. Working
through the multiplexer action when X = 1 and Y = 0 shows that gate 2 opens
if input B is 1.

Fig. 60 MULTIPLEXER LOGIC CIRCUIT

Now try X = 0 and Y = 1 and you will see the AND gate 3 gives an output of 1
and finally when X = 1 and Y = 1 then AND gate 4 will give an output of 1. So
the OR gate will have passed the input 1111 down to data highway serially.

This data has to be transferred along a data highway usually by Time Division
Multiplexing (TDM). In TDM the data channels each occupy the same
frequency band but divides the channel into time slots into which bits of signal
are transmitted.

Figure 61 shows four data channels operating at 200bits/sec. The buffer store
is a holding store until access to the data highway is signalled.

- 60 -
 Fig. 61 TIME DIVISION MULTIPLEXER

The duration of each bit is 1/200s or 5ms (5 milli seconds) so an 8-bit word
occupies 40ms. The common line is operated at input channel speed times the
number of channels ie, 4 x 200 = 800 bits/sec. So each bit will have a time
slot of 1.25mS.

Data from the systems connected to Channels 1, 2, 3 and 4 are fed into a
Buffer Store, until each store is signalled by the clock pulse to output its data
onto the common line in sequence.

As you can see from the diagram there must be some way of converting these
signals to the appropriate receiving channel, ie channel 1 input signal data to
be picked up by channel 1 receiving channel.

This will be by a de-multiplexer (not shown), a device with a single input but
with multiple outputs.

There obviously has to be synchronisation between the input and output

channels to ensure each data goes to the correct channel. Thus all the system
works on the command of the electronic clock.

De-multipexer

These are similar to a multiplexer but works ‘the other way round’. They take
sequential input data from a common data line and output each piece of data
to its appropriate channel. The drawing below shows the mechanical
equivalent of the electronic device.

- 61 -
 Fig. 62 SIMPLE REPRESENTATION
OF A DE-MULTIPLEXER

Figure 63 shows a 1 line to 8 line de-multiplexer. It has 8 AND gates, three

NOT gates, an input line and 8 output lines.

As the name implies it has 1 input line and 8 output lines, with the single data
input line connected to all 8 gates. Each gate will be enabled by the signals on
the select lines S2 S1 S0. Assuming 000 input on the select lines only GATE 0
will open and the data will appear at its output. The truth table shows the
logic states of the de-multiplexer.

Fig. 63 ONE LINE TO EIGHT LINE MULTIPLEXER

- 62 -
 SELECT CODE OUTPUTS
S2 S1 SO O7 06 05 04 03 02 01 00

0 0 0 0 0 0 0 0 0 0 1
0 0 1 0 0 0 0 0 0 1 0
0 1 0 0 0 0 0 0 1 0 0
0 1 1 0 0 0 0 1 0 0 0
1 0 0 0 0 0 1 0 0 0 0
1 0 1 0 0 1 0 0 0 0 0
1 1 0 0 1 0 0 0 0 0 0
1 1 1 1 0 0 0 0 0 0 0

TABLE 11 TRUTH TABLE FOR THE ONE LINE

TO 8 LINE MULTIPLEXER

Figure 64 shows the basic principles of a passenger entertainment system

using multiplexed channels.

The multiplexer selects all the inputs in turn, (12 channels of recorded music,
passenger address messages and tape signals) digitises them (analogue to
digital converter) into one serial data signal stream. This stream of data is fed
to the seats via sidewall disconnect units. The data is received by the
electronic boxes.

Depending on the selection made by the passenger, the signal is de-

multiplexed and decoded (digital to analogue) to output the required analogue
signal to the passenger’s speakers in the headset.

Fig. 64 A PASSENGER ENTERTAINMENT SYSTEM

- GENERAL ARRANGEMENT

””””””””””
- 63 -
 ASSIGNMENT

Give examples of where the following occur in aircraft systems:

(i) Encoding
(ii) Decoding
(iii) A to D conversion
(iv) D to A conversion
(v) Multiplexing and de-multiplexing

SOLUTIONS TO ACTIVITIES
Activity 1

(a) 1 x 24 + 0 x 23 + 0 x 22 + 1 x 21 + 1 x 20 = 100112

(b) 1 x 24 + 1 x 23 + 1 x 22 + 0 x 21 + 1 x 20 = 111012

(c) 1 x 23 + 1 x 22 + 1 x 21 + 1 x 20 + 0 x 2-1 + 0 x 2-2 + 1 x 2-3 = 1111.0012

(d) 1 x 24 + 0 x 23 + 1 x 22 + 1 x 21 + 0 x 20 + 1 x 2-1 + 1 x 2-2 + 0 x 2-3 + 1 x

2-4 = 10110.00012

Activity 2

(a) 2 846
2 423r0
2 211r1
2 105r1
2 52r1
2 26r0
2 13r0
2 6r1
2 3r0
2 1r1
0r1 = 11010011102

(b) 2 317
2 158r1
2 79r0
2 39r1
2 18r1
2 9r1
2 4r1
2 2r0
2 1r0
0r1 = 1001111012

- 64 -
(c) 2 147
2 73r1
2 36r1
2 18r0
2 9r0
2 4r1
2 2r0
2 1r0
0r1 = 100100112

Activity 3

(a) 32 16 8 4 2 1
1 0 1 1 1 1 2 = 4710

(b) 32 16 8 4 2 1
1 0 0 0 0 0 2 = 3210

(c) 32 16 8 4 2 1
1 0 1 0 1 2 = 2110

Activity 4

(a) 32 16 8 4 2 1
1 1 0 0 1 1 2 = 5110

(b) 64 32 16 8 4 2 1
1 1 1 0 0 1 12 = 11510

(c) 8 4 2 1 .5
1 0 1 1 . 1 2 = 11.510

(d) 8 4 2 1 .5 .25 .125

1 1 0 0 . 0 0 02 = 12.12510

Activity 5

(a) 101010100

101 010 100

5 2 48

(b) 1110100000

001 110 100 000

1 6 4 08

- 65 -
(c) 111010001

111 010 001

7 2 18

(d) 4 2 68

100 010 110

1000101102

(e) 5 6 2 58

101 110 010 110

1011100101102

(f) 6 5 2 1 78

110 101 010 001 111

1101010100011112

Activity 6

(a) 111 .1112

7 . 78

(b) 101 .100

5 . 48

(c) 110 .011100

6 . 3 48

(d) .64

.110 1002

(e) .778

.111 1112

(f) .438

.100 0112

- 66 -
Activity 7

(a) 1110 00102

E 216

(b) 0111 1111

7 F16

(c) 0011 1001

3 916

(d) 2 D
10 16 8 4 2 1
0010 1101 = 1 0 1 1 0 12 = 4510

(e) 1AF
256 128 64 32 16 8 4 2 1
0001 1010 1111 = 1 1 0 1 0 1 1 1 12 = 43110

(f) 21A

512 256 128 64 32 16 8 4 2 1

0010 0001 1010 = 1 0 0 0 0 1 1 0 1 02 = 53810

(g) 163210

1024 512 256 128 64 32 16 8 4 2 1

0 1 1 0 0 1 1 0 0 0 0 02
6 6 0 = 66016

(h) 494
256 128 64 32 16 8 4 2 1
0001 1 1 1 0 1 1 1 02
1 E E16

(i) 5174

4096 2048 1024 512 256 128 64 32 16 8 4 2 1

0001 0 1 0 0 0 0 1 10110
1 4 3 616

- 67 -
(j) 178 to Decimal

256
128
64
32
16
8
4
2
1
0001 0111 1000 = 1 0 1 1 1 1 0 0 02
= 37610
= 101 111 000
= 5708

(k) EF16 = 111011112

= 23910
= 011 101 111
= 3578

Activity 8

(a) 0.6250
= 12-1 + 0 x 2-2 + 1 x 2-3
= .1010
= .916

(b) 0.81250
= 1 x 2-1 + 1 x 2-2 + 1 x 2-3 + 1 x 2-4
= .1101
= .D16

(c) 0.A8 (d) 0.F6

.10101000 0.11110110
= .101012 = .11110112

Activity 9

(a) 9 4

1001 0100

(b) 5 2 9

0101 0010 1001

(c) 2 9 4 7

0010 1001 0100 0111

(d) 0111 0000 1001

7 0 910

(e) 0011 0110 0100

3 6 410

- 68 -
Activity 10

Activity 11 – (a) and (b)

Activity 12

Activity 13 ---

Activity 14 0.625V
”””””””””

- 69 -