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Module #10 - Functions

The document discusses Verilog HDL functions including their declaration syntax, how they are called, that they describe combinational logic, can invoke other functions but not recursively, and must assign the return value to the implicit function name register.

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VLSI Excellence - Gyan Chand Dhaka
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© © All Rights Reserved
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Download as PDF, TXT or read online on Scribd
4 views

Module #10 - Functions

The document discusses Verilog HDL functions including their declaration syntax, how they are called, that they describe combinational logic, can invoke other functions but not recursively, and must assign the return value to the implicit function name register.

Uploaded by

VLSI Excellence - Gyan Chand Dhaka
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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Module #10 : Verilog HDL Functions

10.1: Verilog HDL Function :

- Functions are declared within a module, and can be called from continuous assignments, always
blocks, or other functions.
- In a continuous assignment, they are evaluated when any of its declared inputs change.
- In a procedure, they are evaluated when invoked.
- Functions describe combinational logic, and do not generate latches.
- Functions are a good way to reuse procedural code, since modules cannot be invoked from within a
procedure.

26-11-2022 VLSI Excellence - Gyan Chand Dhaka 1


Module #10 : Verilog HDL Functions
10.2: Function Declaration :
- A function declaration specifies the name of the function, the width of the function return value, the
function input arguments, the variables (reg) used within the function, and the function local parameters
and integers

Syntax: Example 10.1:


function [msb:lsb] function_name; function [7:0] my_func; // function return 8-bit
input [msb:lsb] input_arguments; value
reg [msb:lsb] reg_variable_list; input [7:0] i;
parameter [msb:lsb] parameter_list; reg [4:0] temp;
integer [msb:lsb] integer_list; integer n;
... statements ... temp= i[7:4] | ( i[3:0]);
endfunction my_func = {temp, i[[2:0]};
endfunction

26-11-2022 VLSI Excellence - Gyan Chand Dhaka 2


Module #10 : Verilog HDL Functions
10.3: Function Return Value:
- When we declare a function, a variable is also implicitly declared with the same name as the function
name, and with the width specified for the function name (The default width is 1-bit).
- At least one statement in the function must assign the function return value to this variable.

10.4. Function Call:


- A function call is an operand in an expression. A function call must specify in its terminal list all the
input parameters.

Example 10.2:
wire [7:0] x;
wire [7:0] y;
assign y = my_func[x];

26-11-2022 VLSI Excellence - Gyan Chand Dhaka 3


Module #10 : Verilog HDL Functions
10.5: Function Return Value:
- Functions must contain at least one input argument.
- Functions cannot contain an inout or output declaration.
- Functions cannot contain time controlled statements (#, @, wait).
- Functions can invoke other functions, but not themselves (not recursive).
- Functions cannot invoke tasks.
- Functions must contain a statement that assigns the return value to the implicit function name register.

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Module #10 : Verilog HDL Functions
10.6: Function Example:
- A Function has only one output. If more than one return value is required, the outputs should be
concatenated into one vector before assigning it to the function name.
- The calling module program can then extract (unbundle) the individual outputs from the concatenated
form.

Example 10.3:
module simple_processor (instruction, outp);
input [31:0] instruction;
output [7:0] outp;
reg [7:0] outp;; // so it can be assigned in always block
reg func;
reg [7:0] opr1, opr2;

26-11-2022 VLSI Excellence - Gyan Chand Dhaka 5


Module #10 : Verilog HDL Functions
Continued . . .
function [16:0] decode_add (instr) end
// returns 1 1-bit plus 2 8-bits 8’b10001010: begin // increment operand
input [31:0] instr; add_func = 1;
reg add_func; opr2 = 8’b00000001;
reg [7:0] opcode, opr1, opr2; end
begin default: begin; // decrement operand
opcode = instr[31:24]; add_func = 0;
opr1 = instr[7:0]; opr2 = 8’b00000001;
case (opcode) end
8’b10001000: begin // add two operands endcase
add_func = 1; decode_add = {add_func, opr2, opr1}; // concatenated
opr2 = instr[15:8]; into 17-bits
end end
8’b10001001: begin // subtract two operands endfunction
add_func = 0;
opr2 = instr[15:8];
26-11-2022 VLSI Excellence - Gyan Chand Dhaka 6
Module #10 : Verilog HDL Functions
Continued . . .

always @(instruction) begin


{func, op2, op1} = decode_add (instruction); //
outputs unbundled
if (func == 1)
outp = op1 + op2;
else
outp = op1 - op2;
end
endmodule

26-11-2022 VLSI Excellence - Gyan Chand Dhaka 7

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