ISSN 2278-3083

International Journal of Science and Applied Information Technology (IJSAIT), Vol.5 , No.1, Pages : 14-19 (2016)
Special Issue of ICECT 2016 - Held on February 01, 2016 in Hyderabad Marriot Hotel & Convention Centre, Hyderabad
http://warse.org/IJSAIT/static/pdf/Issue/icect2016sp04.pdf

Design and Verification of Four Port Router for

Network on Chip
Y Mrudula 1, V Harshavardhan2, G Manu3, Bhavana Godavarthi4
1
Farah Institute of Technology, Hyderabad,mrudulamudu@gmail.com
2
Farah Institute of Technology, Hyderabad, harsh.velagapudi@gmail.com
3
Farah Institute of Technology, Hyderabad, manug0808@gmail.com
4
Institute of Aeronautical Engineering, Hyderabad, bhavana.bhanu402@gmail.com

Abstract: This proposed research paper is a (open verification methodology) is one such efficient
Multiprocessor system on chip is emerging as a new methodology and best thing about it is, it is free. This
trend for System on chip design but the wire and power ovm is built on system Verilog and used effectively to
design constraints are forcing adoption of new design achieve maintainability, reusability, speed of
methodologies. Researchers pursued a scalable solution verification etc. This project is aimed at building a
to this problem i.e. Network on Chip (NOC). Network reusable test bench for verifying 8 Port Router Protocol
on chip architecture better supports the integration of Bridge by using system Verilog and OV.
SOC consists of on chip packet switched network. Thus
the idea is borrowed from large scale multiprocessors The use of OVM and system Verilog to verify a
and wide area network domain and envisions on chip design and to develop a reusable test bench is explained
routers based network. Cores access the network by in step by step as defined by verification principles and
means of proper interfaces and have their packets methodology. The test bench contains different
forwarded to destination through multichip routing components and each component is again composed of
path. In order to implement a competitive NOC subcomponents, these components and subcomponents
architecture, the router should be efficiently design as it can be reused for the future projects as long as the
is the central component of NOC architecture. Design interface is same.
and Verify the functionality of the “Design and The report is organized as two major portions; first
Verification Four Port Router for Network on Chip” IP part is brief introduction and history of the functional
core using the latest verification methodologies, verification which tells about different technologies,
Hardware Verification Languages and EDA tools and strategies and methodologies used today for
qualify the IP for Synthesis an implementation. verification. Literature survey will contain an organized
The Four Router Design is done by using of the three collection of data from different sources and significant
blocks .the blocks are 8-Bit Register, Router controller changes that took place in the verification and design.
and output block. the router controller is design by using Ovm methodology basics illustrate some of the
FSM design and the output block consists of three fifo’s methodology concepts necessary for understanding of
combined together the fifo’s are store packet of data and the project which assumes a prior knowledge of the
when u want to data that time the data read from the system Verilog language.
FIFO’s. In this router design has three outputs that is 8- Second part is verification plan specifying the
Bit size and one 8_bit data port it using to drive the data verification requirements and approaches to attack the
into router we are using the global clock and reset signals, problem, architecture of the test bench gives complete
and the err signal and suspended data signals are output’s description about the components and sub components
of the router .the FSM controller gives the err and used to achieve the verification goals and also explains
suspended_data_in signals about improvements made in the design of the usb-i2c
Keywords: Network-on-Chip, Simulation Router, bridge, test plan identifies all the test case required to
FIFO, FSM, Register blocks meet the goals and finally results of the project.
1.1 Router
1. INTRODUCTION

The challenge of the verifying a large design is System on chip is a complex interconnection of various
growing exponentially. There is a need to define new functional elements. It creates communication
methods that makes functional verification easy. bottleneck in the gigabit communication due to its bus
Several strategies in the recent years have been based architecture. Thus there was need of system that
proposed to achieve good functional verification with explicit modularity and parallelism, network on chip
less effort. Recent advancement towards this goal is possess many such attractive properties and solve the
methodologies. The methodology defines a skeleton problem of communication bottleneck. It basically
over which one can add flesh and skin to their works on the idea of interconnection of cores using on
requirements to achieve functional verification. OVM chip network.

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 ISSN 2278-3083

International Journal of Science and Applied Information Technology (IJSAIT), Vol.5 , No.1, Pages : 14-19 (2016)
Special Issue of ICECT 2016 - Held on February 01, 2016 in Hyderabad Marriot Hotel & Convention Centre, Hyderabad
http://warse.org/IJSAIT/static/pdf/Issue/icect2016sp04.pdf

The communication on network on chip is There are many other useful features, but these
carried out by means of router, so for implementing allow you to create test benches at a higher level of
better NOC, the router should be efficiently design. abstraction than you are able to achieve with an HDL or
This router supports four parallel connections at the a programming language such as C.
same time. It uses store and forward type of flow
control and Fsm Controller deterministic routing which 2.2 Svm Verification Component (Svc)
improves the performance of router. The switching
mechanism used here is packet switching which is
generally used on network on chip. The following subsections describe the components of
A router is a device that forwards data packets across an SVC:
computer networks. Routers perform the data "traffic
 Data Item (Transaction)
direction" functions on the Internet. A router is a
microprocessor-controlled device that is connected to  Driver (BFM)
two or more data lines from different networks. When a  Sequencer
data packet comes in on one of the lines. the router  Monitor(Receiver)
reads the address information in the packet to determine  Generator
its ultimate destination. Then, using information in its  Environment
routing table, it directs the packet to the next network The environment is the top-level component of the
on its journey SVC. It contains one or more agents, as well as other
components such as a bus monitor. The env contains
2. FOUR PORT ROUTER configuration properties that enable you to customize
the topology and behaviour and make it reusable. For
The router is a” Four Port Network Router” has a one example, active agents can be changed into passive
input port from which the packet enters. It has three agents when the verification environment is reused in
output ports where the packet is driven out. Packet system verification. Figure 1-2 on page 15 illustrates
contains 3 parts. They are Header, data and frame check the structure of a reusable verification environment.
sequence. Packet width is 8 bits and the length of the Notice that an OVC may contain an environment-level
packet can be between 1 bytes to 64 bytes. Packet monitor. This bus-level monitor performs checking and
header contains three fields DAand length.Destination coverage for activities that are not necessarily related to
address (DA) of the packet is of 8 bits. The switch a single agent. An agent’s monitors can leverage data
drives the packet to respective ports based on this and events collected by the global monitor.
destination address of the packets. Each output port has
8-bit unique port address. If the destination address of The environment class (ovm_env) is architected to
the packet matches the port address, then switch drives provide a flexible, reusable, and extendable verification
the packet to the output port, Length of the data is of 8 component. The main function of the environment class
bits and from 0 to 63. Length is measured in terms of is to model behaviour by generating constrained-
bytes. Data should be in terms of bytes and can take random traffic, monitoring DUT responses, checking
anything. Frame check sequence contains the security the validity of the protocol activity, and collecting
check of the packet. It is calculated over the header and coverage
data.

2.1 System Verilog

The most valuable benefit of SystemVerilog is that it
allows the user to construct reliable, repeatable
verification environments, in a consistent syntax, that
can be used across multiple projects
Some of the typical features of an HVL that distinguish
it from a Hardware Description Language such as
Verilog or VHDL are
 Constrained-random stimulus generation
 Functional Coverage
 Higher-level structures, especially Object
Oriented Programming
 Multi-threading and inter process
communication
 Support for HDL types such as Verilog’s 8- Figure 1. Typical SVC Environments
state values
 Tight integration with event-simulator for
control of the design

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 ISSN 2278-3083

International Journal of Science and Applied Information Technology (IJSAIT), Vol.5 , No.1, Pages : 14-19 (2016)
Special Issue of ICECT 2016 - Held on February 01, 2016 in Hyderabad Marriot Hotel & Convention Centre, Hyderabad
http://warse.org/IJSAIT/static/pdf/Issue/icect2016sp04.pdf

OVM Factory modify the environment object structure without

The factory method is a classic software touching multiple classes.
design pattern that is used to create generic code,
deferring to run time the exact specification of the Test Class
object that will be created. In functional verification, The OVM_test class defines the test scenario for the
introducing class variations is frequently needed. For testbench specified in the test. The test class enables
example, in many tests you might want to derive from configuration of the testbench and environment classes
the generic data item definition and add more as well as utilities for command-line test selection.
constraints or fields to it; or you might want to use the Although IP developers provide default values for
new derived class in the entire environment or only in a topological and run-time configuration properties, if
single interface; or perhaps you must modify the way require configuration customization, use the
data is sent to the DUT by deriving a new driver. The configuration override mechanism provided by the
factory allows you to substitute the verification SystemVerilog OVM Class Library. To provide user-
component without having to provide a derived version defined sequences in a file or package, which is
of the parent component as well. included or imported by the test class. A test provides
data and sequence generation and inline constraints.
The SystemVerilog OVM Class Library provides a Test files are typically associated with a single
built-in central factory that allows: configuration. Tests in OVM are classes that are
derived from an OVM_test class. Using classes allows
 Controlling object allocation in the entire inheritance and reuse of tests.
environment or for specific objects.
The testbench is the container object that defines the
 Modifying stimulus data items as well as testbench topology. The testbench instantiates the
infrastructure components (for example, a reusable verification IP and defines the configuration of
driver). that IP as required by the application. Instantiating the
reusable environment directly inside the tests has
Use of the OVM built-in factory reduces the effort of several drawbacks:
creating an advanced factory or implementing factory
methods in class definitions. It facilitates reuse and  The test writer must know how to
adjustment of predefined verification IP in the end- configure the environment.
user’s environment. One of the biggest advantages of
the factory is that it is transparent to the test writer and  Changes to the topology require updating
reduces the object-oriented expertise required from both multiple test files, which can turn into a
developers and users. big task.

Developing Reusable System Verilog Verification  The tests are not reusable because they
Components (SVCs) This section describes the basic rely on a specific environment structure.
concepts and components that make up a typical
verification environment. It also shows how to combine
these components using a proven hierarchical
architecture to create reusable OVCs. The sections
follow the same order you should follow when
developing an OVC:
I. Modeling Data Items for Generation Data
items
II. Creating the Driver
III. Creating the Monitor
IV. Instantiating Components
V. Creating the Environment
Ovm Configuration Mechanism
An SVC is created on a per-protocol basis for
general purpose protocol related use. It may support Figure 1.1 Complete block diagram of verification
various features or operation modes that are not
required in a particular project. OVM provides a Environment
standard configuration mechanism which allows you to
define the SVC’s configuration to suit the current Router Design Principles
project’s requirements. The SVC can get the
configuration during run time or during the build Router is a packet based protocol. Router drives the
process. Doing this during the build allows you to incoming packet which comes from the input port to

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 ISSN 2278-3083

International Journal of Science and Applied Information Technology (IJSAIT), Vol.5 , No.1, Pages : 14-19 (2016)
Special Issue of ICECT 2016 - Held on February 01, 2016 in Hyderabad Marriot Hotel & Convention Centre, Hyderabad
http://warse.org/IJSAIT/static/pdf/Issue/icect2016sp04.pdf

output ports based on the address contained in the ROUTER INPUT PROTOCOL
packet.The router has a one input port from which the
packet enters. It has three output ports where the packet The characteristics of the DUV input protocol are as
is driven out. The router has an active low synchronous follows:
input reset which resets the router.

Figure 2.2 Router Input Protocol

ROUTER OUTPUT PROTOCOL
Figure 2. Block Diagram of Four Port Router

Data packet moves in to the input channel of one

port of router by which it is forwarded to the output
channel of other port. Each input channel and output
channel has its own decoding logic which increases the
performance of the router. Buffers are present at all
ports to store the data temporarily.The buffering
method used here is store and forward. Control logic is
present to make arbitration decisions. Thus
communication is established between input and output
ports.. According to the destination path of data packet,
control bit lines of FSM are set. The movement of data
from source to destination is called switching
mechanism The packet switching mechanism is used Figure 2.3 Router output Protocol
here, in which the flit size is 8 bits .Thus the packet size
varies from 0 bits to 8 bits. A detailed explanation of Router Architecture
Design is as follow The Four Router Design is done by using of
the three blocks .the blocks are 8-Bit Regiter, Router
Packet Format controller and output block. the router controller is
Packet contains 7 parts. They are Header, payload design by using FSM design and the output block
and parity. consists of three fifo’s combined together the fifo’s are
Packet width is 8 bits and the length of the packet can store packet of data and when u want to data that time
be between 1 bytes to 67 bytes. the data read from the FIFO’s. In this router design has
three outputs that is 8-Bit size and one 8_bit data port it
using to drive the data into router we are using the
global clock and reset signals, and the err signal and
suspended data signals are output’s of the router .the
FSM controller gives the err and suspended_data_in
signals .this functions are discussed clearly in below
FSM description
The router_reg module contains the status,
data and parity registers for the Network
router_1x3.These registers are latched to new status or
input data through the control signals provided by the
fsm_router.There are 3 fifo for each output port, which
stores the data coming from input port based on the
Figure 2.1 Packet format
control signals provided by fsm_router module.The
fsm_router block provides the control signals to the
fifo, and router_reg module.

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 ISSN 2278-3083

International Journal of Science and Applied Information Technology (IJSAIT), Vol.5 , No.1, Pages : 14-19 (2016)
Special Issue of ICECT 2016 - Held on February 01, 2016 in Hyderabad Marriot Hotel & Convention Centre, Hyderabad
http://warse.org/IJSAIT/static/pdf/Issue/icect2016sp04.pdf

ii. Read operation

iii. Read and
iv. Write Operation

Figure 3.3 Four port Router FIFO

Figure 3. Four Port Router Architecture SIMULATION RESULTS

The Router blocks are The below figures shows the simulation results
 Register of test cases applied to the DUT. Figure 4.3 shows the
 Router controller(FSM) response of the device for the control test case at the
 FIFO Output Block usb interface. Figure 4.2 shows the master transmitter
 sending random data to the external slave device.

Figure 3.1 Four Port Router Register

Figure 4. Simulation results of Four Port Router for

Noc

SYNTHESIS REPORT

Figure 3.2 Four port Router Controller State machine

Router Output Block

There are 7 fifos used in the router design.
Each fifo is of 8 bit width and 16 bit depth.
The fifo works on system clock. It has synchronous
input signal reset.If resetn is low then full =0, empty =
1 and data_out = 0
The FIFO has doing 7 deferent operations
i. Write Operation Figure 4.1 Coverage report using one test case

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 ISSN 2278-3083

International Journal of Science and Applied Information Technology (IJSAIT), Vol.5 , No.1, Pages : 14-19 (2016)
Special Issue of ICECT 2016 - Held on February 01, 2016 in Hyderabad Marriot Hotel & Convention Centre, Hyderabad
http://warse.org/IJSAIT/static/pdf/Issue/icect2016sp04.pdf

coverage of Router. In this project used one master and

eight slaves to monitor the Router. Thus the functional
coverage of Router was improved.
The results shows that System Verilog
methodology can be used to make reusable test benches
successfully. Large part of the test bench is made
reusable over multiple projects.even though this
reusablity is limited to the interfaces. A large class of
devices that are build on these inerfaces can be verified
successfully. Once these components are made the
amount of time required to build test benches for other
projects can be reduced a lot.
REFERENCES

[1] Verilog HDL- Digital Design and Synthesis, by

Samir Palnitkar.
Figure 4.2 Synthesis results of Four Port Router for
[2] M. K. Papamichael, J. C. Hoe, and O. Mutlu, “FIST:
Noc.
A Fast, Lightweight, FPGA-Friendly Packet Latency
Estimator for NoC Modeling in Full-System
Simulations”, NOCS, 2011.
[3] Xilinx, “LogiCORE IP Processor Local
Bus(PLB)v4.6”,http://www.xilinx.com/support/docume
ntation/i pdocumentation/plb v46.pdf .
[4] P. Wolkotte, P. Holzenspies, and G. Smit, “Fast,
Accurate and Detailed NoC Simulations”, NOCS, 2007.
[5] System Verilog Manuals by Mentor.
[6] LRM‖, IEEE Standard Hardware Description
Language Based on the Verilog Hardware Description
Language – IEEE STD 1364-1995.
[7] Chris Spears SYSTEMVERILOG FOR
Figure 4.3 Synthesis results of a FIFO VERIFICATION, Publisher: Springer
[8] Cisco Router OSPF: Design& Implementation
CONCLUSION Guide, Publisher: McGraw-Hill

As the functional verification decides the

quality of the silicon, we spend 60% of the design cycle
time only for the verification/simulation. In order to
avoid the delay and meet the TTM, we use the latest
verification methodologies and technologies and
accelerate the verification process. This project helps
one to understand the complete functional verification
process of complex ASICs an SoC’s and it gives
opportunity to try the latest verification methodologies,
programming concepts like Object Oriented
Programming of Hardware Verification Languages and
sophisticated EDA tools, for the high quality
verification.
In this Four Port Router project Design and
verified the functionality of Router with the latest
Verification methodology i.e. System Verilog and
observed the code coverage and functional coverage of
Router by using cover points ,cross and different test
cases like constrained, weighted and directed testcases
.By using these testcases improved the functional

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