Digital Logic Design

University of Gondar
Institute of Technology
Department of Electrical Engineering
Digital Logic Design:
Chapter 4: Combinational Logic Circuit
By:
Habtamu Maru

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Digital Logic Design

Outline

1 Introduction

2 Common Combinational Logic Circuit

Arithmetic and logical Function
Data Transmission
Code Converter

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Digital Logic Design
Introduction

A combinational logic circuit as the name itself indicates that it is

the combination of various kinds of logic gates.
We used Boolean algebra to describe and analyze circuits that
were made up of combinations of logic gates.
The combinational circuit goes with the characteristics of:
I At any instant of time, the output is based only on the levels of cur-
rent input terminals and not on the past state inputs.
I A combinational circuit has no memory or clock characteristic, so its
output depends only on the current value of its inputs.
I A combinational circuit can intake ‘n’ number of inputs and delivers
only one output.

A combinational circuit consists of input variables, logic gates, and

output variables.
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Digital Logic Design
Introduction

It react to the value of the signals at their inputs and produce the
value of the output signal, transforming binary information from
the given input data to a required output data.
A block diagram of a combinational circuit is shown in Fig. below,
The ”n” input binary variables come from an external source; the
”m” output variables are produced by the intend combinational.

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Digital Logic Design
Introduction

For ”n” input variables, there are 2n possible binary input combina-
tions. For each possible input combinations, there is one possible
output value.
Thus a combinational circuit can be specified with a truth table
that lists the output value for each combination of input variables.
A combinational circuit also can be described by ”m” Boolean func-
tion, one for each output variable. Each output function is ex-
pressed in terms of the ”n” input variable.

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Digital Logic Design
Common Combinational Logic Circuit

Classification of Combinational Logic

Common combinational circuits made up from individual logic

gates that carry out a desired application include Multiplexers,
De-multiplexers, Encoders, Decoders, Full and Half Adders etc.

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Digital Logic Design
Common Combinational Logic Circuit
Arithmetic and logical Function

Adders
Adders are important in computers and other types of digital systems in
which numerical data are processed.
Half Adder
Half adder is a combinational logic circuit with two inputs and two out-
puts.
The half adder circuit is designed to add two single bit binary number A
and B and having two outputs carry and sum. It is the basic building block
for addition of two single bit numbers.
The SUM output is the LSB of the result, while the CARRY output is the
MSB of the result, indicating whether there was a carry-over from the
addition of the two inputs.
The half adder can be implemented using basic gates such as XOR and
AND gates.
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Common Combinational Logic Circuit
Arithmetic and logical Function

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Common Combinational Logic Circuit
Arithmetic and logical Function

Full Adder

The full-adder accepts two input bits (A and B) and an input carry (Cin )
and generates a sum output (∑) and an output carry (Cout ).

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Digital Logic Design
Common Combinational Logic Circuit
Arithmetic and logical Function

Parallel Binary Adders

The Full Adder is capable of adding only two single digit binary
number along with a carry input. But in practical we need to add
binary numbers which are much longer than just one bit.
Two or more full adders are connected to form parallel binary
adders.
To add two n-bit binary numbers we need to use the n-bit parallel
adder.
It uses a number of full adders in cascade. The carry output of
the previous full adder is connected to carry input of the next full
adder.
The carry output of each adder is connected to the carry input of
the next higher-order adder.
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Digital Logic Design
Common Combinational Logic Circuit
Arithmetic and logical Function

Figure: Block diagram of a n+1-bit parallel adder circuit using full adders.

A group of 4 bits is called a nibble. A basic 4-bit parallel adder is

implemented with four full adder stages as shown.
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Common Combinational Logic Circuit
Arithmetic and logical Function

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Digital Logic Design
Common Combinational Logic Circuit
Arithmetic and logical Function

Half Subtraction
A half subtractor is a digital logic circuit that performs binary sub-
traction of two single-bit binary numbers.
It has two inputs, A and B, and two outputs, DIFFERENCE and BOR-
ROW. The DIFFERENCE output is the difference of the two input
bits, while the BORROW output indicates whether borrowing was
necessary during the subtraction.

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Digital Logic Design
Common Combinational Logic Circuit
Arithmetic and logical Function

Full Subtraction
The disadvantage of a half subtractor is overcome by full subtrac-
tor.
The full subtractor is a combinational circuit with three inputs A,B
,Bin and two output D and Bout ’. A is the ’minuend’, B is ’subtra-
hend’, Bin is the ’borrow’ produced by the previous stage, D is the
difference output and Bout is the borrow output.

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Digital Logic Design
Common Combinational Logic Circuit
Arithmetic and logical Function

Four bit binary Adder-Subtractor

If K=0 performs A+B (adder); and if K=1 performs A-B (subtractor),

XOR gates act as programeble inverter.

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Digital Logic Design
Common Combinational Logic Circuit
Arithmetic and logical Function

As shown in the figure, the first full adder has a control line directly
as its input(input carry Cin), The input A0 (The LSB of A) is directly
input in the full adder. The third input is the XOR of B0 and K. The
two outputs produced are Sum/Difference (S0) and Carry (C0).
If the value of K (Control line) is 1, the output of B0(XOR)K=B0.
Thus the operation would be A+B0. Now 2’s complement sub-
traction for two numbers A and B is given by A+B0+Cin. This sug-
gests that when K=1, the operation being performed on the four-
bit numbers is subtraction.
Similarly If the Value of K=0, B0 (XOR)K=B0. The operation is A+B
which is simple binary addition. This suggests that When K=0, the
operation is performed on the four-bit numbers in addition.

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Digital Logic Design
Common Combinational Logic Circuit
Arithmetic and logical Function

Comparators
The basic function of comparator is to compare the magnitude of two
binary quantities to determine the relationship of those quantities.
The simplest form a comparator circuit determines whether two num-
bers are equal or not.
The outcome of the comparison is specified by three binary variables that
indicate whether A > B, A = B, or A < B.
Equality
The equality of the two numbers A and B is displayed in a combinational
circuit by an output binary variable that we designate by the symbol (A=B).
This binary variable is equal to ”1” if the input numbers ,A and B, are equal,
otherwise is equal to “0” .
The equality of each pair of bits can expressed logically with an XNOR
function .
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Digital Logic Design
Common Combinational Logic Circuit
Arithmetic and logical Function

To compare binary numbers containing two bits each:

The binary variable (A=B) is equal to ”1” only if all pairs of digit of
the two number are equal.

Inequality
I To determine whether A is greater or less than B, we inspect the
relative magnitudes of pairs of significant digits, starting from the
MSB position.
I If the two digits of a pair are equal, we compare the next lower sig-
nificant pair of digits.
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Digital Logic Design
Common Combinational Logic Circuit
Arithmetic and logical Function

The comparison continues until a pair of unequal digits is reached.

If the corresponding digit of A is “1” and that of B is “0”, we con-
clude that A > B. If the corresponding digit of A is “0” and that of
B is “1”, we have A < B.
To determine an inequality of binary numbers A and B, you first
examine the highest order bit in each number:
I If A3 =1 and B3 =0, then number A is greater than number B.
I If A3 =0 and B3 =1, then number A is less than number B.
I If A3 =B3 , we examine the next lower bit position for an equality.

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Digital Logic Design
Common Combinational Logic Circuit
Data Transmission

Decoders
A decoder is a combinational circuit that converts binary informa-
tion from n input lines to a maximum of 2n unique output lines.
If the m-bit coded information has unused combinations, the de-
coder may have fewer than 2n output.
A decoder detects the presence of a specified combination of bits
(code) on its inputs and indicates the presence of that code by a
specified output level.
In its general form, a decoder has n input lines to handle n bits
and forms one to 2n output lines to indicate the presence of one
or more n-bit combinations.
The decoders presented here are called n-to-m-line decoders, where
m ≤ 2n Their purpose is to generate the 2n (or fewer) minterms of
n input variable.
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Common Combinational Logic Circuit
Data Transmission

2-to-4 decoders

It contains two inputs denoted by A1 and A0 and four outputs D0 , D1 , D2 ,

and D3 . Also note that A1 is the MSB while A0 is the LSB.
For each input combination, one output line is activated, that is, the out-
put line corresponding to the input combination becomes 1, while other
lines remain inactive.

ing from a certain combination of

the inputs, that is.
I D0 =A1 A0 , (m0 ) which corresponds to input 00
Notice that, each output of the de- I D1 =A1 A0 , (m1 ) which corresponds to input 01
I D2 =A1 A0 , ( m2 ) which corresponds to input 10
coder is actually a minterm result- I D3 =A1 A0 , (m3 ) which corresponds to input 11
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Common Combinational Logic Circuit
Data Transmission

Each input combination will invoke the corresponding output, where

each output is minterm corresponding to the input combination.

The 2-to-4 decoder circuit is

implemented with AND
gates.

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Digital Logic Design
Common Combinational Logic Circuit
Data Transmission

Enable Inputs

The n-to-2n decoder, apart from this, there is also a single line
connected to the decoder called enable line.
Some decoders have one or more ENABLE inputs that are used to
control the operation of the decoder.
The enable input are no logical operation, but is only responsible
for making the decoder ACTIVE or INACTIVE.
If the enable ”E” is:
I 0 , then all outputs are zero regardless of the input values.
I 1, then the decoder performs its normal operation.
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Common Combinational Logic Circuit
Data Transmission

Decoder Expansion
It is possible to build larger decoders using two or more smaller ones.
Construct a 3-to-8 decoder using two 2-to-4 decoders with enable inputs.
Two 2-to-4 line are combined to build a 3-to-8 line decoder.
I The two LSBs (i.e. A1 and A0 ) are connected to both decoders
I MSB (A2 ) is connected to the enable input of one decoder.
I The complement of MSB (A2 ) is connected to the enable of the other
decoder.
I When A2 =0, upper decoder is enabled, while the lower is disabled.
Thus, the outputs of the upper decoder correspond to minterms D0
through D3 .
I When A2 = 1, upper decoder is disabled, while the lower is enabled.
Thus, the outputs of the lower decoder correspond to minterms D4
through D7 .
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Common Combinational Logic Circuit
Data Transmission

Decoder design with NAND gates

Some decoders are constructed with NAND rather than AND gates.
In this case, all decoder outputs will be 1’s except the one corre-
sponding to the input code which will be 0.
Decoding functions and truth table with active-LOW outputs.
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Common Combinational Logic Circuit
Data Transmission

Each of the decoding function can be implemented by NAND gates

to provide active LOW output and AND gates to provide active
HIGH output.

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Common Combinational Logic Circuit
Data Transmission

BCD-to-Decimal Decoder
This type of decoder is probably the most widely used in all digital
systems because it changes the inherent binary codes used within
the system to the decimal code used by the human operators.
Four input lines represent the decimal numbers 0 through 9. This
type of decoder is often used in combination with decade coun-
ters and with decimal displays.
The BCD-to-decimal converts each BCD code into one of ten pos-
sible decimal digit indications.

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Common Combinational Logic Circuit
Data Transmission

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Common Combinational Logic Circuit
Data Transmission

The BCD-to-7-segment Decoder

This type of decoder accepts the BCD information and converts it
into seven outputs for connection to a 7-segment display.
These numerical displays can be implemented by light-emitting
diodes (LED), liquid crystal displays (LCD), fluorescent displays.
The BCD-to-7-segment decoder accepts the BCD code on its in-
puts and provides outputs to drive 7-segment display devices to
produce a decimal readout.

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Common Combinational Logic Circuit
Data Transmission

Find the expression for 7

segments a,b,c,d,e,f and g

Design 7 segment decoder

circuit to display 1,5,7 and 8.

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Digital Logic Design
Common Combinational Logic Circuit
Data Transmission

Encoders
An encoder performs the inverse operation of a decoder.
It has 2n inputs, and n output lines.
Only one input can be logic 1 at any given time (active input). All
other inputs must be 0’s.
Output lines generate the binary code corresponding to the active
input.
Encoders can also be devised to encode various symbols and al-
phabetic characters.
The process of converting from familiar symbols or numbers to a
codded format is called encoding.

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Common Combinational Logic Circuit
Data Transmission

Example: Octal-to-binary encoder

We have eight inputs, one for each of the octal digits, and three
outputs that generate the corresponding binary number.
The encoder can be implemented with three OR gates.

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Common Combinational Logic Circuit
Data Transmission

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Common Combinational Logic Circuit
Data Transmission

Priority Encoder
This is a special type of encoder. Priority is given to the input lines.
If two or more input line are 1 at the same time, then the input line
with highest priority will be considered.
For example consider octal to binary encoder, if D3 and D6 are 1
simultaneously, the output of the encoder will be 111 because all
three outputs are equal to 1. The output 111 does not represent
either binary 3 or binary 6.
To resolve this limitation, encoder circuits must establish an input
priority to ensure that only one input is encoded.
If we establish a higher priority for inputs with higher subscript
numbers, and if both D3 and D6 are 1 at the same time, the output
will be 110 because D6 has higher priority than D3 .
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Digital Logic Design
Common Combinational Logic Circuit
Data Transmission

Decimal-to-BCD Encoder
This types of encoder has ten inputs-one for each decimal digit-
and four outputs corresponding to the BCD code. This is a basic
10- to-4 line encoder.
It has 10 inputs and 4 outputs corresponding to the BCD code.

I The output A is 1 when input

8 OR 9 is 1 ∴ A=8+9

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Common Combinational Logic Circuit
Data Transmission

The output B is 1 when input 4 OR 5 OR 6 OR 7 is 1 ∴ B=4+5+6+7

The output C is 1 when input 2 OR 3 OR 6 OR 7 is 1 ∴ C=2+3+6+7
The output D is 1 when input 1 OR 3 OR 5 OR 7 OR 9 is 1 ∴ D=1+3+5+7+9

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Digital Logic Design
Common Combinational Logic Circuit
Data Transmission

Multiplexers (Data selectors)

A digital multiplexer or data selector is a logic circuit that accepts
several digital data inputs and selects one of them at any given
time to pass on to the output
The basic MUX has several data-input lines and a single output
line.
It also has data-select inputs, which permit digital data on any one
of the inputs to be switched to the output line.
The selector lines determine which input is connected to the out-
put, and also to increase the amount of data that can be sent over
a network within certain time.
Normally, there are 2n input lines and n selection lines whose bit
combinations determine which input is selected.
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Common Combinational Logic Circuit
Data Transmission

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Common Combinational Logic Circuit
Data Transmission

A 3 variable truth table has 8 combinations of inputs variables.

when an 4 bit data selector is used, each input is selected twice:
the first time C is 0 and the second time when C is 1.
With this in mind the following rule can be applied (F is the output
and C is the LSB):
I If F=0 both times a given data input is selected by a certain combi-
nation of the input variables AB, connect the data input to 0.
I If F=1 both times a given data input is selected by a certain combi-
nation of the input variables AB, connect the data input to 1.
I If F is different the two times a given data input is selected by a cer-
tain combination of the input variables AB, and if F=C connect the
data input to C.
I If F is different the two times a given data input is selected by a cer-
tain combination of the input variables AB, and if F=C connect the
data input to C .
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Common Combinational Logic Circuit
Data Transmission

Implement the logic function using Multiplexer

Implement the logic function using Multiplexer,F=A BC+AB;

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Common Combinational Logic Circuit
Data Transmission

The data select inputs are

ABC.

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Common Combinational Logic Circuit
Data Transmission

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Common Combinational Logic Circuit
Data Transmission

Demultiplexers (Data Distributors)

A Demultiplexer performs the reverse operation of a multiplexer
function. It takes data from one line and distributes them to a
given number of output lines.
It has only one input, 2n outputs, n select input. At a time only one
output line is selected by the select lines and the input is transmit-
ted to the selected output line.

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Common Combinational Logic Circuit
Data Transmission

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Common Combinational Logic Circuit
Code Converter

BCD to Binary converter

The binary numbers representing the weight of the BCD bits are
summed to produce the total binary number.
In case of BCD number it is similar to binary till decimal value 9,
after 9 each digit of decimal representation takes 4 digit in BCD.

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Digital Logic Design
Common Combinational Logic Circuit
Code Converter

Let us examine an 8 bit BCD code (that represents a 2 digit decimal

number ) to understand the relationship between BCD to binary.
1001 1000
I The left Most 4 bit group represents 90, and the right most 4 bit
group represents 8. That is the left Most group has a weight of 10
and the right Most group has a weight of 1.
I Within each group, the binary weight of each bit is as follow;

The binary equivalent of each BCD bit is a binary number repre-

senting the weight of that bit within the total BCD number. This
representation is given in Table.

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Digital Logic Design
Common Combinational Logic Circuit
Code Converter

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Digital Logic Design
Common Combinational Logic Circuit
Code Converter

Binary to Gray Code Conversion

This conversion method strongly follows the EX-OR gate operation be-
tween binary bits.

Gn =Bn ; Gn−1 =Bn−1 Bn ;...;

L
G3 =B3 ; G2 =B2 B3
L

G1 =B1 B2 ; G0 =B0 B1 G0 =B0 B1

L L L

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Digital Logic Design
Common Combinational Logic Circuit
Code Converter

B3 =G3 ;
B2 =G2 B3 =G2 G3
L L

B1 =G1 B2 = G1 G2 G3 ;
L L L

B0 =G0 B1 = G0 G1 G2 G3
L L L L

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Digital Logic Design

!! !
OU
K Y
A N
T H
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