74ALVC08

Quad 2-input AND gate

Rev. 4 — 30 April 2021 Product data sheet

1. General description
The 74ALVC08 is a quad 2-input AND gate. This device is fully specified for partial power down
applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging
backflow current through the device when it is powered down.
Schmitt-trigger action at all inputs makes the circuit tolerant for slower input rise and fall times.

2. Features and benefits

• Wide supply voltage range from 1.65 V to 3.6 V
• 3.6 V tolerant inputs/outputs
• CMOS low power consumption
• Direct interface with TTL levels (2.7 V to 3.6 V)
• Power-down mode
• Latch-up performance exceeds 250 mA
• Complies with JEDEC standards:
• JESD8-7 (1.65 V to 1.95 V)
• JESD8-5 (2.3 V to 2.7 V)
• JESD8B (2.7 V to 3.6 V)
• ESD protection:
• MM JESD22-A115-A exceeds 200 V
• HBM JESD22-A114E exceeds 2000 V
• Multiple package options
• Specified from -40 °C to +85 °C
Nexperia 74ALVC08
Quad 2-input AND gate

3. Ordering information
Table 1. Ordering information
Type number Package
Temperature range Name Description Version
74ALVC08D -40 °C to +85 °C SO14 plastic small outline package; 14 leads; SOT108-1
body width 3.9 mm
74ALVC08PW -40 °C to +85 °C TSSOP14 plastic thin shrink small outline package; 14 leads; SOT402-1
body width 4.4 mm
74ALVC08BQ -40 °C to +85 °C DHVQFN14 plastic dual in-line compatible thermal enhanced SOT762-1
very thin quad flat package; no leads; 14 terminals;
body 2.5 × 3 × 0.85 mm

4. Functional diagram
1
& 3
2

4
& 6
1 1A
1Y 3 5
2 1B
4 2A
2Y 6 9
5 2B & 8
9 3A 10
3Y 8
10 3B
A
12 4A 12
4Y 11 & 11 Y
13 4B 13
B
mna222 mna223 mna221

Fig. 1. Logic symbol Fig. 2. IEC logic symbol Fig. 3. Logic diagram (one gate)

5. Pinning information

5.1. Pinning
74ALVC08

1A 1 14 VCC
74ALVC08
1B 2 13 4B

1Y 3 12 4A 1A 1 14 VCC
1B 2 13 4B
2A 4 11 4Y
1Y 3 12 4A
2B 5 10 3B 2A 4 11 4Y
2B 5 10 3B
2Y 6 9 3A
2Y 6 9 3A
GND 7 8 3Y GND 7 8 3Y

aaa-27559 aaa-027560

Fig. 4. Pin configuration SOT108-1 (SO14) Fig. 5. Pin configuration SOT402-1 (TSSOP14)

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Product data sheet Rev. 4 — 30 April 2021 2 / 13

Nexperia 74ALVC08
Quad 2-input AND gate

74ALVC08

14 VCC
terminal 1

1A
index area

1
1B 2 13 4B

1Y 3 12 4A

2A 4 11 4Y

2B 5 GND(1) 10 3B

2Y 6 9 3A

8
GND

3Y
aaa-027561

Transparent top view

(1) This is not a ground pin. There is no electrical or mechanical requirement to solder the pad. In case soldered,
the solder land should remain floating or connected to GND
Fig. 6. Pin configuration SOT762-1 (DHVQFN14)

5.2. Pin description

Table 2. Pin description
Symbol Pin Description
1A, 2A, 3A, 4A 1, 4, 9, 12 data input
1B, 2B, 3B, 4B 2, 5, 10, 13 data input
1Y, 2Y, 3Y, 4Y 3, 6, 8, 11 data output
GND 7 ground (0 V)
VCC 14 supply voltage

6. Functional description
Table 3. Function table
H = HIGH voltage level; L = LOW voltage level
Input Output
nA nB nY
L L L
L H L
H L L
H H H

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Product data sheet Rev. 4 — 30 April 2021 3 / 13

Nexperia 74ALVC08
Quad 2-input AND gate

7. Limiting values
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Max Unit
VCC supply voltage -0.5 +4.6 V
VI input voltage [1] -0.5 +4.6 V
VO output voltage none [1] -0.5 VCC + 0.5 V
power-down mode; VCC = 0 V -0.5 +4.6 V
IIK input clamping current VI < 0 V - -50 mA
IOK output clamping current VO > VCC or VO < 0 V - ±50 mA
IO output current VO = 0 V to VCC - ±50 mA
ICC supply current - 100 mA
IGND ground current -100 - mA
Tstg storage temperature -65 +150 °C
Ptot total power dissipation Tamb = -40 °C to +85 °C [2] - 500 mW

[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] For SOT402-1 (TSSOP14) package: Ptot derates linearly with 7.3 mW/K above 81 °C.

8. Recommended operating conditions

Table 5. Recommended operating conditions
Symbol Parameter Conditions Min Max Unit
VCC supply voltage 1.65 3.6 V
VI input voltage 0 3.6 V
VO output voltage VCC = 1.65 to 3.6 V 0 VCC V
power-down mode; VCC = 0 V 0 3.6 V
Tamb ambient temperature -40 +85 °C
Δt/ΔV input transition rise and fall rate VCC = 1.65 V to 2.7 V 0 20 ns/V
VCC = 2.7 V to 3.6 V 0 10 ns/V

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Product data sheet Rev. 4 — 30 April 2021 4 / 13

Nexperia 74ALVC08
Quad 2-input AND gate

9. Static characteristics
Table 6. Static characteristics
At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Tamb = -40 °C to +85 °C Unit
Min Typ [1] Max
VIH HIGH-level VCC = 1.65 V to 1.95 V 0.65 × VCC - - V
input voltage VCC = 2.3 V to 2.7 V 1.7 - - V
VCC = 2.7 V to 3.6 V 2.0 - - V
VIL LOW-level input voltage VCC = 1.65 V to 1.95 V - - 0.35 × VCC V
VCC = 2.3 V to 2.7 V - - 0.7 V
VCC = 2.7 V to 3.6 V - - 0.8 V
VOH HIGH-level VI = VIH or VIL
output voltage IO = -100 μA; VCC = 1.65 V to 3.6 V VCC - 0.2 - - V
IO = -6 mA; VCC = 1.65 V 1.25 1.51 - V
IO = -12 mA; VCC = 2.3 V 1.8 2.10 - V
IO = -18 mA; VCC = 2.3 V 1.7 2.01 - V
IO = -12 mA; VCC = 2.7 V 2.2 2.53 - V
IO = -18 mA; VCC = 3.0 V 2.4 2.76 - V
IO = -24 mA; VCC = 3.0 V 2.2 2.68 - V
VOL LOW-level VI = VIH or VIL
output voltage IO = 100 μA; VCC = 1.65 V to 3.6 V - - 0.2 V
IO = 6 mA; VCC = 1.65 V - 0.11 0.3 V
IO = 12 mA; VCC = 2.3 V - 0.17 0.4 V
IO = 18 mA; VCC = 2.3 V - 0.25 0.6 V
IO = 12 mA; VCC = 2.7 V - 0.16 0.4 V
IO = 18 mA; VCC = 3.0 V - 0.23 0.4 V
IO = 24 mA; VCC = 3.0 V - 0.30 0.55 V
II input leakage current VCC = 3.6 V; VI = 3.6 V or GND - ±0.1 ±5 μA
IOFF power-off VCC = 0 V; VI or VO = 3.6 V - ±0.1 ±10 μA
leakage current
ICC supply current VCC = 3.6 V; VI = VCC or GND; IO = 0 A - 0.2 20 μA
ΔICC additional per input pin; VCC = 3.0 V to 3.6 V; - 5 750 μA
supply current VI = VCC - 0.6 V; IO = 0 A
CI input capacitance - 3.5 - pF

[1] All typical values are measured at VCC = 3.3 V (unless stated otherwise) and Tamb = 25 °C.

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Nexperia 74ALVC08
Quad 2-input AND gate

10. Dynamic characteristics

Table 7. Dynamic characteristics
Voltages are referenced to GND (ground = 0 V). For test circuit, see Fig. 8.
Symbol Parameter Conditions Tamb = -40 °C to +85 °C Unit
Min Typ [1] Max
tpd propagation delay nA, nB to nY; see Fig. 7 [2]
VCC = 1.65 V to 1.95 V 1.2 2.7 5.3 ns
VCC = 2.3 V to 2.7 V 1.0 1.9 3.2 ns
VCC = 2.7 V - 2.2 3.0 ns
VCC = 3.0 V to 3.6 V 1.2 2.0 2.9 ns
CPD power dissipation per gate; VI = GND to VCC; VCC = 3.3 V [3] - 24 - pF
capacitance

[1] Typical values are measured at Tamb = 25 °C and VCC = 1.8 V, 2.5 V, 2.7 V and 3.3 V respectively
[2] tpd is the same as tPHL and tPLH.
[3] CPD is used to determine the dynamic power dissipation (PD in μW).
2 2
PD = CPD × VCC × fi × N + Σ(CL × VCC × fo) where:
fi = input frequency in MHz
fo = output frequency in MHz
CL = output load capacitance in pF
VCC = supply voltage in Volts
N = number of inputs switching
2
Σ(CL × VCC × fo) = sum of the outputs

10.1. Waveforms and test circuit

VI

nA, nB input VM

GND
t PHL t PLH
VOH

nY output VM

VOL
mna224

Measurement points are given in Table 8.

VOL and VOH are typical voltage output levels that occur with the output load.
Fig. 7. Inputs (nA, nB) to output (nY) propagation delays

Table 8. Measurement points

Supply voltage Input
VCC VI VM
1.65 V to 1.95 V VCC 0.5 x VCC
2.3 V to 2.7 V VCC 0.5 x VCC
2.7 V 2.7 V 1.5 V
3.0 V to 3.6 V 2.7 V 1.5 V

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Nexperia 74ALVC08
Quad 2-input AND gate

tW
VI
90 %
negative
pulse VM VM
10 %
0V
tf tr

tr tf
VI
90 %
positive
pulse VM VM
10 %
0V
tW

VEXT
VCC
RL
VI VO
G DUT

RT CL RL

001aae331

Test data is given in Table 9.

Definitions test circuit:
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
CL = Load capacitance including jig and probe capacitance.
RL = Load resistance.
VEXT = Test voltage for switching times.
Fig. 8. Test circuit for measuring switching times

Table 9. Test data

Supply voltage Input Load VEXT
VCC VI tr, tf CL RL tPLH, tPHL tPLZ, tPZL tPHZ, tPZH
1.65 V to 1.95 V VCC ≤ 2.0 ns 30 pF 1 kΩ open 2 × VCC GND
2.3 V to 2.7 V VCC ≤ 2.0 ns 30 pF 500 Ω open 2 × VCC GND
2.7 V 2.7 V ≤ 2.5 ns 50 pF 500 Ω open 6V GND
3.0 V to 3.6 V 2.7 V ≤ 2.5 ns 50 pF 500 Ω open 6V GND

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Product data sheet Rev. 4 — 30 April 2021 7 / 13

Nexperia 74ALVC08
Quad 2-input AND gate

11. Package outline

SO14: plastic small outline package; 14 leads; body width 3.9 mm SOT108-1

D E A
X

y HE v M A

14 8

Q
A2
(A 3) A
A1
pin 1 index
θ
Lp

1 7 L

e w M detail X
bp

0 2.5 5 mm
scale

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

A
UNIT A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) θ
max.
0.25 1.45 0.49 0.25 8.75 4.0 6.2 1.0 0.7 0.7
mm 1.75 0.25 1.27 1.05 0.25 0.25 0.1
0.10 1.25 0.36 0.19 8.55 3.8 5.8 0.4 0.6 0.3 8
o
o
0.010 0.057 0.019 0.0100 0.35 0.16 0.244 0.039 0.028 0.028 0
inches 0.069 0.01 0.05 0.041 0.01 0.01 0.004
0.004 0.049 0.014 0.0075 0.34 0.15 0.228 0.016 0.024 0.012

Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.

OUTLINE REFERENCES EUROPEAN

ISSUE DATE
VERSION IEC JEDEC JEITA PROJECTION

99-12-27
SOT108-1 076E06 MS-012
03-02-19

Fig. 9. Package outline SOT108-1 (SO14)

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Product data sheet Rev. 4 — 30 April 2021 8 / 13

Nexperia 74ALVC08
Quad 2-input AND gate

TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1

D E A
X

y HE v M A

14 8

Q
A2 (A 3 )
A
A1
pin 1 index

θ
Lp
L
1 7
detail X
w M
e bp

0 2.5 5 mm
scale

DIMENSIONS (mm are the original dimensions)

A
UNIT A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ
max.

mm
0.15 0.95 0.30 0.2 5.1 4.5 6.6 0.75 0.4 0.72 8o
1.1 0.25 0.65 1 0.2 0.13 0.1
0.05 0.80 0.19 0.1 4.9 4.3 6.2 0.50 0.3 0.38 0o

Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.

OUTLINE REFERENCES EUROPEAN

ISSUE DATE
VERSION IEC JEDEC JEITA PROJECTION

99-12-27
SOT402-1 MO-153
03-02-18

Fig. 10. Package outline SOT402-1 (TSSOP14)

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Product data sheet Rev. 4 — 30 April 2021 9 / 13

Nexperia 74ALVC08
Quad 2-input AND gate

DHVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;
14 terminals; body 2.5 x 3 x 0.85 mm SOT762-1

D B A

A
A1
E c

terminal 1 detail X
index area

terminal 1 C
e1
index area v C A B
e b y1 C y
w C
2 6
L

1 7
Eh e
14 8
k

13 9
Dh
X
k

0 2 4 mm
scale
Dimensions (mm are the original dimensions)

Unit A(1) A1 b c D(1) Dh E(1) Eh e e1 k L v w y y1

max 1 0.05 0.30 3.1 1.65 2.6 1.15 0.5

mm nom 0.02 0.25 0.2 3.0 1.50 2.5 1.00 0.5 2 0.4 0.1 0.05 0.05 0.1
min 0.00 0.18 2.9 1.35 2.4 0.85 0.2 0.3
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. sot762-1_po

Outline References European

Issue date
version IEC JEDEC JEITA projection
15-04-10
SOT762-1 MO-241 15-05-05

Fig. 11. Package outline SOT762-1 (DHVQFN14)

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Product data sheet Rev. 4 — 30 April 2021 10 / 13

Nexperia 74ALVC08
Quad 2-input AND gate

12. Abbreviations
Table 10. Abbreviations
Acronym Description
CMOS Complementary Metal-Oxide Semiconductor
DUT Device Under Test
ESD ElectroStatic Discharge
HBM Human Body Model
MM Machine Model
TTL Transistor-Transistor Logic

13. Revision history

Table 11. Revision history
Document ID Release date Data sheet status Change notice Supersedes
74ALVC08 v.4 20210430 Product data sheet - 74ALVC08 v.3
Modifications: • Section 1 updated.
• Section 2: Reference to JESD36 removed.
• Section 7: Derating values for Ptot total power dissipation have been updated.
74ALVC08 v.3 20171005 Product data sheet - 74ALVC08 v.2
Modifications: • The format of this data sheet has been redesigned to comply with the identity guidelines of
Nexperia.
• Legal texts have been adapted to the new company name where appropriate.
74ALVC08 v.2 20030516 Product specification - 74ALVC08 v.1
74ALVC08 v.1 20030204 Product specification - -

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Product data sheet Rev. 4 — 30 April 2021 11 / 13

Nexperia 74ALVC08
Quad 2-input AND gate
injury, death or severe property or environmental damage. Nexperia and its

14. Legal information suppliers accept no liability for inclusion and/or use of Nexperia products in
such equipment or applications and therefore such inclusion and/or use is at
the customer’s own risk.
Quick reference data — The Quick reference data is an extract of the
Data sheet status product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
Document status Product Definition Applications — Applications that are described herein for any of these
[1][2] status [3] products are for illustrative purposes only. Nexperia makes no representation
Objective [short] Development This document contains data from or warranty that such applications will be suitable for the specified use
data sheet the objective specification for without further testing or modification.
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and products using Nexperia products, and Nexperia accepts no liability for
Preliminary [short] Qualification This document contains data from
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data sheet the preliminary specification.
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Definitions Limiting values — Stress above one or more limiting values (as defined in
Draft — The document is a draft version only. The content is still under the Absolute Maximum Ratings System of IEC 60134) will cause permanent
internal review and subject to formal approval, which may result in damage to the device. Limiting values are stress ratings only and (proper)
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the quality and reliability of the device.
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full data sheet, which is available on request via the local Nexperia sales published at http://www.nexperia.com/profile/terms, unless otherwise agreed
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Nexperia 74ALVC08
Quad 2-input AND gate

Contents
1. General description...................................................... 1
2. Features and benefits.................................................. 1
3. Ordering information....................................................2
4. Functional diagram.......................................................2
5. Pinning information......................................................2
5.1. Pinning.........................................................................2
5.2. Pin description............................................................. 3
6. Functional description................................................. 3
7. Limiting values............................................................. 4
8. Recommended operating conditions..........................4
9. Static characteristics....................................................5
10. Dynamic characteristics............................................ 6
10.1. Waveforms and test circuit........................................ 6
11. Package outline.......................................................... 8
12. Abbreviations............................................................ 11
13. Revision history........................................................11
14. Legal information......................................................12

© Nexperia B.V. 2021. All rights reserved

For more information, please visit: http://www.nexperia.com
For sales office addresses, please send an email to: salesaddresses@nexperia.com
Date of release: 30 April 2021

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Product data sheet Rev. 4 — 30 April 2021 13 / 13