Design and Implementation of Multilevel Inverter

A Project report submitted in the partial fulfillment of the requirements for the award of

degree of

BACHELOR OF TECHNOLOGY
IN

ELECTRICAL AND ELECTRONICS ENGINEERING

BY
B. SRI CHARAN TEJA 20331A0213
Under the esteemed guidance of

Mr. M. Venu Madhav, M. Tech, (Ph.D)

Associate Professor, Dept. of. EEE

Department of Electrical and Electronics Engineering

Maharaja Vijayaram Gajapathi Raj College of Engineering
(Approved by AICTE, New Delhi, Permanently Affiliated to Jawaharlal Nehru Technological University, GV,

Accredited by NBA and NAAC “B+” grade by UGC)

VIZIANAGARAM

2023-2024
 DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING
MVGR COLLEGE OF ENGINEERING (Autonomous)

CERTIFICATE

This is to certify that the project entitled “DESIGN AND IMPLEMENTATION OF MULTI
LEVEL INVERTER” being submitted by B.SRI CHARAN TEJA (20331A0213) partial
fulfillment for the award of the degree in BACHELOR OF TECHNOLOGY in ELECTRICAL
AND ELECTRONICS ENGINEERING is a record of bonafide work done by them under my
guidance and supervision during the academic year 2023- 2024.

Project guide Head of the department External examiner

Mr. M. Venu Madhav Dr. R. Gowri Sankara Rao
Associate Professor, Professor & H.O.D
Department of EEE, Department of EEE,
MVGRCE (A), MVGRCE (A),
Vizianagaram. Vizianagaram
 ACKNOWLEDGEMENT

It is my privilege to work under the esteemed guidance of Mr. M. VENU MADHAV,

Associate Professor, Department of Electrical and Electronics Engineering, MVGR College of
Engineering, as project supervisor. I would like to express my deep sense of indebtedness and whole
hearted thanks to my beloved project supervisor for his valuable suggestions, support and guidance
in carrying out this project work.

I wish to express my sincere gratitude to Dr. R. GOWRI SANAKARA RAO, Professor &
Head of the Department, Electrical and Electronics Engineering, MVGR College of Engineering,
for his inspiration and above all the moral support and the constant encouragement in carrying out
this project work.

I wish to express my gratitude to Dr. RAMAKRISHNA RAMESH, Principal, MVGR

College of Engineering for providing me with all the facilities to carry out this project work.

Last but not the least, I wish to convey my sincere thanks to all those who have directly and
indirectly contributed for the successful completion of this work.

Project Students:

B. SRI CHARAN TEJA 20331A0213

 ABSTRACT:

Inverter is a power electronic device that converts DC power to AC power at

a desired output voltage and frequency. A multi-level inverter technology has emerged
recently as a very important alternative in the area of power quality applications. The
usual traditional converters are capable to generate an output voltage for switching
limited to 3 levels of voltage. These have the advantage of higher DC link voltages,
low dv/dt to supply lower harmonic content in output voltage and current. On the other
side, having inherent drawbacks like increased no of switches, complexity of the
control circuit and requirement of more sources.

In this project a multilevel inverter is implemented which requires less no of

switches, less gating circuits with reduced voltage stress and cost function. This
inverter topology involves a cascaded H-Bridge enabling the generation of multiple
voltage levels. The design encompasses selection of suitable modulation techniques
and control strategies to achieve precise voltage synthesis. On simulation and
experimental results demonstrate improved harmonic content, reduced switching
losses which can be used as an application for both R and RL loads, renewable energy
systems, electric vehicles etc...
Program Outcomes:

a. Engineering knowledge: Apply the knowledge of mathematics, science, engineering fundamentals,

and an engineering specialization to the solution of complex engineering problems.
b. Problem analysis: Identify, formulate, review research literature, and analyze complex engineering
problems reaching substantiated conclusions using first principles of mathematics, natural sciences,
and engineering sciences.
c. Design/development of solutions: Design solutions for complex engineering problems and design
system components or processes that meet the specified needs with appropriate consideration for the
public health and safety, and the cultural, societal, and environmental considerations.
d. Conduct investigations of complex problems: Use research-based knowledge and research
methods including design of experiments, analysis and interpretation of data, and synthesis of the
information to provide valid conclusions.
e. Modern tool usage: Create, select, and apply appropriate techniques, resources, and modern
engineering and IT tools including prediction and modelling to complex engineering activities with
an understanding of the limitations.
f. The engineer and society: Apply reasoning informed by the contextual knowledge to assess
societal, health, safety, legal and cultural issues and the consequent responsibilities relevant to the
professional engineering practice.
g. Environment and sustainability: Understand the impact of the professional engineering solutions
in societal and environmental contexts, and demonstrate the knowledge of, and need for sustainable
development.
h. Ethics: Apply ethical principles and commit to professional ethics and responsibilities and norms
of the engineering practice.
i. Individual and team work: Function effectively as an individual, and as a member or leader in
diverse teams, and in multidisciplinary settings.
j. Communication: Communicate effectively on complex engineering activities with the engineering
community and with society at large, such as, being able to comprehend and write effective reports
and design documentation, make effective presentations, and give and receive clear instructions.
k. Project management and finance: Demonstrate knowledge and understanding of the engineering
and management principles and apply these to one’s own work, as a member and leader in a team,
to manage projects and in multidisciplinary environments.
l. Life-long learning: Recognize the need for, and have the preparation and ability to engage in
independent and life-long learning in the broadest context of technological change.

Program Specific Outcomes:

1. PSO1: An ability to design & develop models as well as analyze & assess the performance of different types
of generation, transmission, distribution and protection mechanisms in core engineering.

2. PSO2: An ability to devise control strategies and provide optimal solutions for industrial and societal
electrical energy requirements

Outcomes of PROGRAM OUTCOMES

the project a b c d e f g h I J K l PSO1 PSO2

Ability to
understand
concepts of M H H H H M H H H H H M
Electrical and
Electronics
Ability to
design and
implementation
a Multilevel H H H M H L M H M H H H M L
Inverter based
on the
requirement.
Ability to
understand the
knowledge of
simulate the real H H M M M H H H H M M
time application
using
MATLAB.

H - HIGH
M - MEDIUM
L - LOW
 CONTENTS
Acknowledgement ............................................................................................ iii
Abstract .............................................................................................................. iv
Program outcomes ................................................................................................ v

List of figures ....................................................................................................... ix

Chapter 1 ....................................................................................................................................... 12
Introduction .................................................................................................................................. 13
1.1 Introduction ........................................................................................................................ 13
1.2 Classification of Multilevel Inverter .................................................................................. 14
1.3 Diode Clamped Multilevel Inverter ....................................................................................15
1.3.1 Advantages ............................................................................................................................. 16
1.3.2 Disadvantages ........................................................................................................................ 16
1.3.3 Applications............................................................................................................................ 16
1.4 Capacitor Clamped Inverter ................................................................................................ 17
1.4.1 Advantages ............................................................................................................................. 17
1.4.2 Disadvantages ........................................................................................................................ 18
1.4.3 Applications............................................................................................................................ 18
1.5 Cascaded H-Bridge Multilevel Inverter ......................................................................................... 18
1.5.1 Types of Cascaded H-Bridges ............................................................................................... 19
1.5.2 Calculations ............................................................................................................................ 19
1.5.3 Advantages ............................................................................................................................. 19
1.5.4 Disadvantages ........................................................................................................................ 20
1.5.5 Applications............................................................................................................................ 20

Chapter 2 ....................................................................................................................................... 21
Literature Review.......................................................................................................................... 22
Chapter 3 ....................................................................................................................................... 24
Project Description........................................................................................................................ 24
 3.1 Three-Level Inverter............................................................................................................ 25
3.1.1 Circuit Diagram .......................................................................................................... 25
3.1.2 Output waveform ........................................................................................................ 26
3.1.3 FFT Analysis .............................................................................................................. 26
3.2 Five-level Inverter ............................................................................................................... 27
3.2.1 Circuit Diagram .......................................................................................................... 27
3.2.2 Output waveform ........................................................................................................ 28
3.2.3 FFT Analysis .............................................................................................................. 28
3.3 Seven-level Inverter ............................................................................................................ 29
3.3.1 Circuit Diagram .......................................................................................................... 29
3.3.2 Output waveform ........................................................................................................ 30
3.3.3 FFT Analysis .............................................................................................................. 30
3.4 Nine-level Inverter .............................................................................................................. 31
3.4.1 Circuit Diagram .......................................................................................................... 31
3.4.2 Output waveform ........................................................................................................ 32
3.4.3 FFT Analysis .............................................................................................................. 32
3.5 Eleven-level Inverter ........................................................................................................... 33
3.5.1 Circuit Diagram .......................................................................................................... 33
3.5.2 Output waveform ........................................................................................................ 34
3.5.3 FFT Analysis .............................................................................................................. 34
Chapter 4 ....................................................................................................................................... 35
Hardware Model .......................................................................................................................... 36
4.1 Hardware Component Used ................................................................................................ 36
4.2 Gate Driver Unit ................................................................................................................... 40
4.3 Cascaded H-Bridge Circuit ................................................................................................. 42
4.4 Working Model ................................................................................................................... 42
4.5 Generalized Output ............................................................................................................. 43
4.6 Three-Level Model.............................................................................................................. 43
4.6.1 Switching Sequence...................................................................................................... 43
4.6.1.1 Mode 1 ............................................................................................................. 43
4.6.1.2 Mode 2 ............................................................................................................. 43
4.6.2 Arduino Code ............................................................................................................... 44
 4.6.3 Theoretical Calculations ............................................................................................... 45
4.7 Five-Level Model ................................................................................................................ 45
4.7.1 Switching Sequence...................................................................................................... 45
4.7.1.1 Mode 1 ............................................................................................................. 46
4.7.1.2 Mode 2 ............................................................................................................. 46
4.7.1.3 Mode 3 ............................................................................................................. 46
4.7.1.4 Mode 4 ............................................................................................................. 46
4.7.2 Arduino Code ............................................................................................................... 47
4.7.3 Theoretical Calculations ............................................................................................... 48
Chapter 5 ....................................................................................................................................... 49
Result and Conclusion .................................................................................................................. 50
5.1 Simulation Model of 3-Level Inverter ........................................................................... 50
5.2 Hardware Output of 3-Level Inverter............................................................................. 50
5.3 Simulation model of 5-Level Inverter ............................................................................ 51
5.4 Hardware output of 5-Level Inverter………………………………………………… 51

Future Scope ................................................................................................................................. 54

References .................................................................................................................................... 55

List of Figures
Fig 1.1.1 Waveform of 3 level inverter ........................................................................................ 13
Fig 1.1.2 waveform of 31 level inverter ...................................................................................... 13
Fig 1.2: DC-AC power conversion techniques ............................................................................ 13
Fig 1.3: Diode clamped multilevel inverter ................................................................................. 14
Fig 1.4: Capacitor Clamped multilevel inverter .......................................................................... 16
Fig 1.5: Cascaded H-Bridge multilevel inverter ........................................................................... 17
Fig 3.1.1: Simulation Model of Three level Inverter ......................................................................25
Fig 3.1.2: Output Voltage waveform of 3-Level Inverter ............................................................. 26
Fig 3.1.3: FFT Analysis of 3-Level Inverter ................................................................................. 26
Fig 3.2.1: Simulation Model of Five Level Inverter ..................................................................... 27
Fig 3.2.2: Output Voltage waveform of 5-Level Inverter ............................................................. 28
Fig 3.2.3: FFT Analysis of 5-Level Inverter ................................................................................. 28
Fig 3.3.1: Simulation Model of Seven level Inverter ..................................................................... 29
Fig 3.2.2: Output Voltage waveform of 7-Level Inverter ............................................................. 30
Fig 3.3.3: FFT Analysis of 7-Level Inverter ................................................................................. 30
Fig 3.4.1: Simulation Model of Nine level Inverter ........................................................................31
Fig 3.4.2: Output Voltage waveform of 9-Level Inverter ..............................................................32
Fig 3.4.3: FFT Analysis of 9-Level Inverter .................................................................................32
Fig 3.5.1: Simulation Model of Eleven Level Inverter ..................................................................33
Fig 3.5.2: Output Voltage waveform of 11-Level Inverter ........................................................... 34
Fig 3.5.3: FFT Analysis of 11-Level Inverter ............................................................................... 34
Fig 4.1.1: TLP250 Pin Configuration ........................................................................................... 36
Fig 4.1.2: N-Channel MOSFET .................................................................................................. 37
Fig 4.1.3: Arduino ......................................................................................................................... 37
Fig 4.1.4: Bridge Rectifier DB 107 ............................................................................................... 38
Fig 4.1.5: Zener Diode .................................................................................................................. 38
Fig 4.1.6: PN Junction Diode FR 107 ........................................................................................... 39
Fig 4.1.7: Transformers 220v/12v ................................................................................................ 39
Fig 4.1.8: Transistor ...................................................................................................................... 40
Fig 4.2: Block Diagram of Gate Driver unit ................................................................................. 40
Fig 4.2.2: Gate Driver Circuit Unit ............................................................................................... 41
Fig 4.3: H-Bridge unit .................................................................................................................. 42
Fig 4.4: Multi-Level Inverter ........................................................................................................ 42
Fig 4.5: Output Waveform for cascaded Bridge ........................................................................... 43
Fig 4.6.1.1: +ve Logic Sequence .................................................................................................. 43
Fig 4.6.1.2: ve Logic Sequence ..................................................................................................... 43
Fig 4.6.3: Output Waveform of 3 Level Inverter .......................................................................... 45
Fig 4.7.1.1: +ve Vdc Logic Sequence ........................................................................................... 46
Fig 4.7.1.2: +2Vdc Logic Sequence ............................................................................................ 46
Fig 4.7.1.3: -Vdc Logic Sequence ............................................................................................... 46
Fig 4.7.1.4: -2Vdc Logic Sequence ............................................................................................. 46
Fig 4.7.3: Output Waveform of 5-Level Inverter ......................................................................... 48
Fig 5.1 : FFT Analysis of 3-Level Inverter .................................................................................. 49
Fig 5.2: Output Waveform of 3 Level Inverter ............................................................................ 49
Fig 5.3: FFT Analysis of 5-Level Inverter ................................................................................... 50
Fig 5.4 Output Waveform of 5-Level Inverter ............................................................................. 50

List of Tables

Table 4.6.1: Switching sequence of Three level Model................................................................ 43

Table 4.7.1: Switching Sequence of Five level Model ................................................................. 45
Table 5.1: Comparison table for different levels of Inverter ........................................................ 53
CHAPTER - 1
 Chapter 1
Introduction
1.1 Introduction

Inverter is a device which converts DC power into AC. The power in the battery is in DC mode
and the motor that drives the wheels usually uses AC power, therefore there should be a conversion
from DC to AC by a power converter; an inverter is used for this conversion . The two-level is the
simplest topology used for this conversion that consists of four switches. Each switch needs an anti-
parallel diode, so there should also be four anti-parallel diodes. There are many other topologies for
inverters. A multilevel inverter (MLI) is a power electronic system that produces a sinusoidal voltage
output from several DC sources. These DC sources can be fuel cells, solar cells, ultra-capacitors, etc.
The major function of multilevel inverters is to generate a better sinusoidal voltage and current in
the output by using switches in series. Since many switches are put in series the switching angles are
important in the multilevel inverters because all of the switches should be switched in such a way
that the output voltage and current have low harmonic distortion (THD). Comparing two-level
inverter topologies of the same power ratings, MLIs also have the advantage that the harmonic
components of line-to-line voltages fed to the load are reduced owing to its switching frequencies.
The multilevel inverters have become increasingly attractive for researchers andmanufacturers due
to their advantages over conventional three-level pulse widthmodulated (PWM) inverters. The MLI
produces improved output waveforms, low EMI, lower total harmonic distortion (THD) and reduced
filter size. Multilevel inverter topology requires the least components for a given number of levels.
The THD is decreased by increasing the number of levels. Though an output voltage with low THD
is desirable, increasing the number of levels leads to more hardware, also the control will be more
complicated.

Fig1.1.1: waveform of 3 level inverter Fig1.1.2: waveform of 31 level inverter

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From the above figures 1.1&1.2, it is clear that as the number of voltage levels is increasing the
output waveform is becoming similar to the sinusoidal waveform. So researchers are focusing more
on multilevel inverters with more voltage levels and less harmonic distortion rather than conventional
2 level inverters.

1.2 Classification of Multilevel Inverter:

Fig1.2: DC-AC power conversion techniques

Fig:1.2 shows the classification of DC-AC power conversion techniques. Multilevel inverters can be
classified into different types based on the type of source used. The most frequently used MLIs are
Diode clamped multilevel inverters , flying capacitor multilevel inverters and cascaded H- bridge
multilevel inverters . Among these multilevel topologies the diode clamped inverters (DCMLI),
particularly, the three-level structure has a wide popularity in motor drive applications besides other
multilevel inverter topologies. But, it has limitations such as complexity and number of clamping
diodes for the DCMLIs, as the level exceeds. The Flying Capacitor Inverters (FCMLI) are based on
balancing capacitors on phase buses and generate multilevel output voltage waveform clamped by
capacitors instead of diodes. Even these flying capacitors also have limitations due to the presence
of capacitors, as they induce ripples into the output waveform. The Cascaded H- bridge multilevel
inverter will produce an output waveform which is quite similar to the sinusoidal wave even though
filters are not used. As they do not need capacitors or diodes for clamping, they are extensively used
in industries.

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 1.3 Diode Clamped Multilevel Inverter:

Fig1.3: Diode clamped multilevel inverter

Diode clamped multilevel inverters(Fig1.3) use clamping diodes in order to limit the voltage stress
of power devices in a particular power circuit. It was first proposed in the year of 1981 and it is also
called a neutral point converter.

● A k level diode clamped inverter needs (2k – 2) switching devices, (k –1)input voltage
source and (k – 1) (k – 2) diodes in order to operate.
● The notable drawbacks are Clamping diodes are increased with the increase ofeach level and
DC level will discharge when control and monitoring are not very precise.
● When compared with other types of inverters the advantages are that back inverters can be
used, capacitors used here are pre charged and at fundamentalfrequency the efficiency is high.
● This inverter is mostly applied in high voltage power drives and in power compensators.

1.3.1 Advantages:

• All of the phases share a common DC bus, which minimizes the capacitancerequirements of
the converter.
• The capacitors can be pre-charged as a group.
• Efficiency is high for fundamental frequency switching.

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1.3.2 Disadvantages:

• Real power flow is difficult for a single inverter because the intermediate DClevels will tend
to overcharge or discharge without precise monitoring and control.

• Capacitor Voltage Balance problem.

1.3.3 Applications:

• Static var compensation.

• Variable speed motor drive.
• High voltage system interconnection.
• High voltage DC and AC transmission lines.

1.4 Capacitor Clamped Inverter:

Fig1.4: Capacitor Clamped multilevel inverter

Capacitor Clamped (CC), or Flying Capacitor topology(Fig1.4) is similar to theNeutral Point

Clamped MLI topology. Instead of using clamping diodes it uses capacitors to hold the voltages to
the desired values. As for the NPCMLI, m-1 number of capacitors on a shared DC- bus, where m is
the level number of the inverter, and 2(m-1) switch-diode valve pairs are used.
However, for the CC MLI, instead of clamping diodes, one or more (depending on position
and level of the inverter) capacitors are used to create the output voltages. They are connected to the
midpoints of two valve pairs on the same position on each side of the midpoint between the valves.

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The voltage synthesis in a seven-level capacitor-clamped converter has more flexibility than a diode-
clamped converter.

1.4.1 Advantages:

• Phase redundancies are available for balancing the voltage levels of thecapacitors.
• Real and reactive power flow can be controlled.
• The large number of capacitors enables the inverter to ride through shortduration
outages and deep voltage sags.

1.4.2 Disadvantages:

• Pre charging all of the capacitors to the same voltage level and startupcomplex.
• Switching utilization and efficiency are poor for real power transmission.
• Complicated control, leading to high switching frequency and losses, when
transferring real power.

1.4.3 Applications:

• Sinusoidal current rectifiers.

• Converters with harmonic distortion capability.
• Both DC-AC and AC-DC conversion applications.(paper no.18)
• Induction motor control.
• Static var generation

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1.5 Cascaded H-Bridge:

Fig1.5:Cascaded H-Bridge multilevel inverter

• Each H-Bridge Cell consists of four switches and four diodes as shown in theFig1.5

• Like every H-Bridge, different combinations of switch positions determinedifferent

voltages such as V+, V- and 0.
• Two switching combinations are present for 0 volts.
• S1 and S2 are connected to positive voltage and S3 and S4 are connected tonegative
voltage.
1.5.1 Types of Cascaded H-Bridge:
• Symmetric:
In this symmetric multi-level inverter configuration, the magnitude of input dc sources is
equal, due to which a number of output levels are less in addition to utilizing more number
of switches with increased total harmonic distortion (THD).
• Asymmetric:
Asymmetric Multi level inverter configuration input dc sources are unequal due to which
different voltage levels can be generated. by combining such voltage levels more levels
can be generated with a lesser number of switches with a consequent reduction in total
harmonic distortion(THD).

1.5.2 Calculations:
The design calculations for single-phase m-level CMLI is explained below.
Number of main switching devices = 2(m-1)

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 Number of main diodes = 2(m-1)
Number of bridges = (m-1)/2
Number of sources = Number of bridges = Number of DC bus capacitors
Where m = number of levels

1.5.3 Advantages:

• This does not need any capacitors or diodes for clamping.

• The wave is quite sinusoidal in nature even if you don’t filter it.
• Output voltages levels are doubled the number of sources
• Easy and quick Manufacturing.
• Packaging and Layout is modularized.
• We can control it Easily with a transformer.
• Inexpensive.
Due to their advantages they are often used now-a-days.

1.5.4 Disadvantages:
• Every H Bridge needs a separate dc source.
• Due to a large number of sources, Applications are Limited.

1.5.5 Applications:

• Motor Drivers

• Active Filters

• Electric vehicle drives

• DC power source utilization.

• Power factor compensators.

• Back to back frequency link systems.

• Interfacing with renewable energy sources.

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 CHAPTER- 2

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 Chapter 2
Literature Review
[1] J. Rodriguez, Jih-Sheng Lai and Fang Zheng Peng, "Multilevel inverters: a survey of
topologies, controls, and applications," in IEEE Transactions on Industrial Electronics,
vol. 49, no. 4, pp. 724-738, Aug. 2002, doi: 10.1109/TIE.2002.801052.

The paper discusses the advantages of cascaded H-bridge inverters over conventional diode-
clamped or capacitor-clamped inverters, emphasizing their suitability for various applications due
to fewer components required. It highlights the utilization of single-phase inverters connected in
series to generate high voltages from renewable energy sources such as solar PV cells, biofuel
cells, or wind turbines. However, a limitation arises from the necessity of a separate DC source for
each H-bridge module. To modulate the power switches effectively, the paper employs sinusoidal
pulse-width modulation (SPWM) wherein a reference sinusoidal wave of fundamental frequency
is compared to a high-frequency carrier wave. The PWM technique varies the level, frequency, or
amplitude of multiple carrier signals to achieve desired output characteristics

[2] C. C, V. N and M. N. Vishwanath, "Asymmetric Multi-Level Inverter," 2022 2nd

International Conference on Intelligent Technologies (CONIT), Hubli, India, 2022, pp. 1-
7, doi: 10.1109/CONIT55038.2022.9848116.

The paper explores the utilization of stacked basic DC source units in series to achieve
higher voltage levels and introduces different pulse-width modulation (PWM) techniques such as
PD, POD, and APOD, which are differentiated based on carrier wave signals. These techniques
are implemented and compared through Matlab simulation in the context of a 15-level multi-
inverter system. Evaluation metrics include Total Harmonic Distortion (THD) levels, the number
of switches required, and the selection between MOSFETs and IGBTs. Additionally, the paper
investigates the number of quadrants each switch operates in, providing insights into the system's
operational characteristics and efficiency.

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[3] R .Nair, Mahalakshmi R and Sindhu Thampatty K.C., "Performance of three phase 11-
level inverter with reduced number of switches using different PWM techniques," 2015
International Conference on Technological Advancements in Power and Energy (TAP
Energy), Kollam, India, 2015, pp. 375-380, Doi: 10.1109/TAPENERGY.2015.7229648.
The paper introduces a novel topology employing 8 switches, aiming to achieve lower Total
Harmonic Distortion (THD) levels, validated through Fast Fourier Transform (FFT) analysis. It
outlines the calculation of modulation index for amplitude and frequency modulation.
Furthermore, the paper describes the design of separate LC filters for both single-phase and
polyphase circuits. Various pulse-width modulation (PWM) techniques are implemented, and
corresponding voltages and THD levels are calculated to evaluate the performance of each
technique. Through these analyses, the paper offers insights into achieving improved THD levels
while considering different PWM strategies and voltage variations.

[4] Sathyam and H. R. Ramesh, "Design of New Cascaded Multilevel Inverter Topology,"
2019 IEEE 5th International Conference for Convergence in Technology (I2CT),
Bombay, India, 2019, pp. 1-6, doi: 10.1109/I2CT45611.2019.9033719.
The paper conducts a comparative analysis between a 19-level symmetrical multi-level
inverter (MLI) and a proposed asymmetrical MLI topology, which utilizes unequal DC voltage
sources. The study focuses on cascaded H-bridges interconnected in series to achieve the desired
output voltage levels. The modulation technique employed is the equal phase method, and the
paper calculates the number of H-bridges necessary for the proposed configuration.

[5] S. Vadhiraj, K. N. Swamy and B. P. Divakar, "Generic SPWM technique for multilevel
inverter," 2013 IEEE PES Asia-Pacific Power and Energy Engineering Conference
(APPEEC), Hong Kong, China, 2013, pp. 1-5, doi: 10.1109/APPEEC.2013.6837117
In this paper, the proposed control method stands out due to its simplicity and efficiency, as
it utilizes only one sine wave and one carrier wave, unlike other control methods that may require
multiple waves. The simulation methodology involves using a separate repeating sequence block
for the carrier wave and a sine pulse block for the sine wave. Additionally, relational and logical
operators are employed to trigger the MOSFETs, enabling precise control over the switching
signals. The outputs of the simulation are visually represented using scope blocks.

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[6] V. Thiyagarajan and P. Somasundaram, "Simulation of New Symmetric and Asymmetric
Multilevel Inverter Topology with Reduced Number of Switches," 2018 4th International
Conference on Electrical Energy Systems (ICEES), Chennai, India, 2018, pp. 315-319, doi:
10.1109/ICEES.2018.8443283.
In this paper, the proposed topology demonstrates its capability to produce both 9-level and
17-level waveforms during symmetric and asymmetric operations, respectively. The calculation
of switching angles is crucial for the proper functioning of the system, and the paper outlines the
formulae used for this purpose. These angles are then triggered according to the predetermined
switching sequence, ensuring precise control over the output waveform. The comparison between
different levels, ranging from 3 to 11, allows for a comprehensive evaluation of the system's
performance in terms of voltage levels and Total Harmonic Distortion (THD).

[7] R.Mathew and S. Agarwal, “Modified reduced switch symmetrical multilevel inverter,” 2017
International Confernce on circuit, power and computing Technologies (ICCPCT), Kollam,
India,2017,pp.1-8,doi:10.1109/ICCPCT.2017.8074253
In this paper, a novel 7-level topology is introduced, designed with only 6 switches,
representing a reduction in component count compared to conventional designs. The Total
Harmonic Distortion (THD) of the proposed topology is calculated manually using Fourier series
formulas for both odd and even functions. These calculated THD values are then compared with
simulated results to validate the accuracy . Additionally, practical measurements of harmonics are
conducted using a harmonic analyzer to further validate the performance of the proposed topology.
The comparative analysis is carried out between the 7-level topology utilizing 7 switches and the
proposed topology with 6 switches.

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 CHAPTER- 3

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 Chapter 3
Project Description

This chapter deals with the brief description of operation of proposed MULTI-LEVEL
topology.

3.1 THREE-LEVEL INVERTER:

3.1.1 Circuit Diagram:

In the Three level Inverter model, the following scheme has been implemented:
1) Switching Scheme- Sinusoidal PWM
2) Power Supply 12V DC each
3) Switches - MOSFET
4) Load - R load

Fig 3.1.1:Simulation Model of Three level Inverter

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3.1.2 Output Waveform:

Fig 3.1.2:Output Voltage waveform of 3-Level Inverter

3.1.3 FFT Analysis:

Fig 3.1.3: FFT Analysis of 3-Level Inverter

• THD % = 41.30%

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3.2 FIVE-LEVEL INVERTER

3.2.1 Circuit Diagram:

In the Five level Inverter model, the following scheme has been implemented:
1) Switching Scheme- Sinusoidal PWM
2) Power Supply 12V DC each
3) Switches - MOSFET
4) Load - R load

Fig 3.2.1 : Simulation Model of Five level Inverter

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3.2.2 Output Waveform:

Fig 3.2.2: Output Voltage waveform of 5-Level Inverter

3.2.3 FFT Analysis:

Fig 3.2.3: FFT Analysis of 5-Level Inverter

• THD % = 15.14%

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3.3 SEVEN-LEVEL INVERTER

3.3.1 Circuit Diagram:

In the Seven level Inverter model, the following scheme has been implemented:
1) Switching Scheme- Sinusoidal PWM
2) Power Supply 12V DC each
3) Switches - MOSFET
4) Load - R load

Fig 3.3.1: Simulation Model of Seven level Inverter

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3.3.2 Output Waveform:

Fig 3.3.2 Output Voltage waveform of 7-Level Inverter

3.3.3 FFT Analysis:

Fig 3.3.3 FFT Analysis of 7-Level Inverter

• THD % = 13.90 %

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3.4 NINE-LEVEL INVERTER

3.4.1 Circuit Diagram:

In the Five level Inverter model, the following scheme has been implemented:
1) Switching Scheme- Sinusoidal PWM
2) Power Supply 12V DC each
3) Switches - MOSFET
4) Load - R load

Fig 3.4.1: Simulation Model of Nine -level Inverter

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 3.4.2 Output Waveform:

Fig 3.4.2 Output Voltage waveform of 9-Level Inverter

3.4.3 FFT Analysis:

Fig 3.4.3 FFT Analysis of 9-Level Inverter

• THD % = 11.55%

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3.5 ELEVEN-LEVEL INVERTER

3.5.1 Circuit Diagram:

In the Five level Inverter model, the following scheme has been implemented:
1) Switching Scheme- Sinusoidal PWM
2) Power Supply 12V DC each
3) Switches - MOSFET
4) Load - R load

Fig 3.5.1: Simulation Model of Eleven level Inverter

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 3.5.2 Output Waveform:

Fig 3.5.2 Output Voltage waveform of 11-Level Inverter

3.5.3 FFT Analysis:

Fig 3.5.3 FFT Analysis of 11-Level Inverter

• THD % = 9.35%

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 CHAPTER 4

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 Chapter 4
Hardware Model
This chapter deals with the brief description of operation of hardware implemented
MULTI-LEVEL topology.
4.1 Hardware Components Used:

1. TLP 250 octo coupler IC -8

2. N-Channel MOSFET IRF 840 - 8
3. Bridge Rectifier DB-107
4. Arduino UNO
5. Zener Diode 18 volts
6. PN Junction Diode FR 107
7. Transformers 220v/12v
8. Transistors SK100, 2n222n
9. Capacitor 0.1 micro Farad
10. Resistors, LED,s
11. Connecting wires

1. TLP 250 octo coupler IC:

1. N.C.
2. Anode
3. Cathode
4. N.C.
5. GND
6. Vo (output)
7. Vo
8. Vcc

Fig 4.1.1: TLP250 Pin Configuration

The TLP250, like any driver, has an input stage, an output stage and a power supply
connection. The TLP250 is an optically isolated driver, meaning that the input and output are
"optically isolated". The isolation is optical - the input stage is an LED and the receiving output

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 stage is light sensitive (think "photodetector").

2. N-Channel MOSFET IRF 840:

Features:
• Dynamic dV/dt rating
• Repetitive avalanche rated
• Fast Switching
• Ease of paralleling
• Simple drive requirements

Fig 4.1.2 : N-Channel MOSFET

The IRF840 is an N-channel power MOSFET from International Rectifier that can switch
loads up to 500V and 8A. It has fast switching, low on-state resistance, and high transconductance.
It's also cost-effective, has superior reverse energy, and can withstand extreme dv/dt rate and
higher avalanche energy. The IRF840 is designed for applications such as switching power
supplies, motor controls, inverters, choppers, and audio amplifiers.

3. Arduino UNO:

Fig 4.1.3 : Arduino

Arduino UNO is a microcontroller board based on the ATmega328P. It has 14
digital input/output pins (of which 6 can be used as PWM outputs), 6 analog inputs, a 16
MHz ceramic resonator, a USB connection, a power jack, an ICSP header and a reset
button. It contains everything needed to support the microcontroller; simply connect it to a

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 computer with a USB cable or power it with a AC-to-DC adapter or battery to get started.

4. Bridge Rectifier :

Fig 4.1.4 : Bridge Rectifier DB 107

The bridge rectifier is a type of full-wave rectifier that uses four or more diodes in a bridge
circuit configuration to convert alternating (AC) current to a direct (DC) current.

5. Zener Diode:

Fig 4.1.5 : Zener Diode

Zener diodes are semiconductor devices that allow current to flow in both directions but
specialize in current flowing in reverse. Also known as breakdown diodes, Zener diodes are the
most common electronic components used as stable voltage references for electronic circuits.

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6. PN Junction Diode FR 107:

Fig4.1.6 : PN Junction Diode FR 107

A PN Junction Diode is one of the simplest semiconductor devices around, and which has
the electrical characteristic of passing current through itself in one direction only. However, unlike
a resistor, a diode does not behave linearly with respect to the applied voltage.

7. Transformers:

Fig 4.1.7 : Transformers 220v/12v

A transformer is a device that moves electric energy from one alternating current (AC)
circuit to another, while increasing or decreasing the voltage. Transformers are used in power
transmission and work on the principles of electromagnetic induction and mutual induction.

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8. Transistor:

Fig 4.1.8 : Transistor

A transistor is a semiconductor device used to amplify or switch electrical signals and

power. It is one of the basic building blocks of modern electronics. It is composed of
semiconductor material, usually with at least three terminals for connection to an electronic circuit.

4.2 Gate Driver Unit:

Fig 4.2.1 : Block Diagram of Gate Driver unit

A gate driver circuit is the most important tool for connecting the power semiconductor
switches with the microcontroller. Therefore, a proper selection of the gate driver circuit is required
which provides adequate quality and quantity of output control power and consistency of the
inverter. Deviation from the above may lead to the occurrence of a fault in the driver circuit. We
need a harmless and less cost-efficient gate driver solution for power electronics applications. Gate
driver circuits are one of the important links. These gate drive power semiconductor switches
(MOSFETs and IGBTs) and produce high output voltage and less current abilities with gate driver
voltages which are generally, up to 12V. There are various types of gate driver circuits used for
MOSFETs and IGBTs. The gate driver circuits are differentiated based on its configuration, the

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 gate driver reactance, the type of power semiconductor switches package, and the input DC power
supply which collectively determines the peak value of output voltage rating and current. Gate
driver circuit is frequently used as a bootstrap circuit between MOSFET and IGBT. But it is not
quite safe as in fault condition, the controller is not separated. This is the major disadvantage of
high voltage circuits as giving proper isolation while controlling the voltage of the gate driver is
quite challenging. In this paper, a new six-channel gate driver circuit is presented with the
following specifications: -
• For turning ON of IGBTs, the positive output voltage is provided and similarly negative
voltage is provided for turning OFF. This helps in reducing the result of the voltage induced by the
source inductance.
• Complete isolation is provided between the microcontroller and the power circuit.
• Any type of power semiconductor switches can be used with this circuit.
• It decreases the capacitance value to a very low value which indeed helps to reduce the
ground currents that are being injected through the capacitor to the microcontroller thereby
disturbing the signals of the same.

Fig 4.2.2 : Gate Driver Circuit Unit

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4.3 Cascaded H-Bridge Circuit:

Fig 4.3 : H-Bridge unit

4.4 Working Model:

Fig 4.4 : Multi-Level Inverter

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4.5 Generalized Output:

Fig 4.5 : Output Waveform for cascaded Bridge

4.6 Three-Level Model:

4.6.1 Switching Sequence:

S1 S2 S3 S4
+Vdc 1 0 0 1
0Volts 0 0 0 0
-Vdc 0 1 1 0
Table 4.6.1: Switching sequence of Three level Model

4.6.1.1 Mode 1: 4.6.1.2 Mode 2:

Fig 4.6.1.1 : +ve Logic Sequence Fig 4.6.1.2 : -ve Logic Sequence

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 4.6.2 Arduino code:
float f=50;
float t=(1/f)*1000000;
float a1=45;
float a=(a1*t)/360;
float d=5;
int pin1=2;
int pin2=4;
int pin3=5;
int pin4=7;

void setup() {
// put your setup code here, to run once:
pinMode(pin1,OUTPUT);
pinMode(pin2,OUTPUT);
pinMode(pin3,OUTPUT);
pinMode(pin4,OUTPUT);
}

void loop() {
// put your main code here, to run repeatedly:
digitalWrite(pin3,HIGH);
digitalWrite(pin4,HIGH);
delayMicroseconds(a);
digitalWrite(pin3,LOW);
delayMicroseconds(d);
digitalWrite(pin1,HIGH);
delayMicroseconds((t/2)-(2*a)-d);
digitalWrite(pin4,LOW);
delayMicroseconds(d);
digitalWrite(pin2,HIGH);
delayMicroseconds((2*a)-d);
digitalWrite(pin1,LOW);
delayMicroseconds(d);
digitalWrite(pin3,HIGH);
delayMicroseconds((t/2)-(2*a)-d);
digitalWrite(pin2,LOW);
delayMicroseconds(d);
digitalWrite(pin4,HIGH);
delayMicroseconds(a-d);
}

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 4.6.3 Theoritical Calculations:

Harmonics Tnk*Fa α1 Vdc Van V1 THD%

3,5,7,9,11 3 30 12 4.5225 13.23 34.18%

𝟐
1. Tnk*Fa : 𝒌 +𝟑𝒌+𝟐
𝟐
; (k= 0,1,2,3,4,………...)
2. Van: 𝟒𝑽𝒅𝒄
𝒏𝝅
(𝒄𝒐𝒔(𝒏𝜶𝟏 )
3. V1: 𝟒𝑽𝒅𝒄
𝝅
𝒄𝒐𝒔(𝜶𝟏 )
𝟐
√∑∞
𝒏=𝟑,𝟓,𝟕,… [
𝟒𝑽𝒅𝒄
𝒄𝒐𝒔(𝒏𝜶𝟏 )]
𝒏𝝅
4. THD%: 𝟒𝑽𝒅𝒄
𝒄𝒐𝒔(𝜶𝟏 )
𝝅

4.7 Five-Level Model:

4.7.1 Switching Sequence:

S1 S2 S3 S4 S5 S6 S7 S8

0 Volts 0 0 0 0 0 0 0 0

Vdc 1 0 0 1 0 0 1 1

2Vdc 1 0 0 1 1 0 0 1

-Vdc 0 0 1 1 0 1 1 0

-2Vdc 0 1 1 0 0 1 1 0

Table 4.7.1: Switching sequence of Five level Model

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 4.7.1.1 Mode 1: 4.7.1.2 Mode 2:

Fig 4.7.1.1: +ve Vdc Logic Sequence Fig4.7.1.2: +2Vdc Logic Sequence

4.7.1.3 Mode 3: 4.7.1.4 Mode 4:

Fig 4.7.1.3 : -Vdc Logic Sequence Fig 4.7.1.4: -2Vdc Logic Sequence

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 4.7.2 Arduino Code:

float f=50;
float t=(1/f) *1000000;
float al=10;
float a2=40;
float alpl=(al*t)/360;
float alp2=(a2*t)/360;
float d=5;
int pinl=9;
int pin2=1;
int pin3=12;
int pin4=4;
int pin5=5;
int pin6=11;
int pin7=7;
int pin8=10;
void setup() {
pinMode (pinl, OUTPUT);
pinMode (pin2, OUTPUT);
pinMode (pin3, OUTPUT);
pinMode (pin4, OUTPUT);
pinMode (pin5, OUTPUT);
pinMode (pin6, OUTPUT);
pinMode (pin7, OUTPUT);
pinMode (pin8, OUTPUT);
}
void loop(){
digitalWrite(pinl, HIGH); digitalWrite(pin2, HIGH); digitalWrite(pin5, HIGH);
digitalWrite(pin6, HIGH); delayMicroseconds (alpl-d);
digitalWrite(pin2, LOW); delayMicroseconds (d); digitalWrite(pin4, HIGH);
delayMicroseconds (alp2-alpl-d);
digitalWrite(pin6, LOW); delayMicroseconds (d); digitalWrite(pin8, HIGH);
delayMicroseconds (t/2-(2*alp2)-d);
digitalWrite(pin5, LOW); delayMicroseconds (d); digitalWrite(pin7, HIGH);
delayMicroseconds (alp2-alpl-d);
digitalWrite(pinl, LOW); delayMicroseconds (d); digitalWrite(pin3, HIGH);
delayMicroseconds((2*alpl)-d);
digitalWrite (pin4, LOW);
digitalWrite(pin4, LOW); delayMicroseconds (d); digitalWrite(pin2, HIGH);
delayMicroseconds (alp2-alpl-d);
digitalWrite(pin8, LOW); delayMicroseconds (d); digitalWrite(pin6, HIGH);
delayMicroseconds (t/2-(2*alp2)-d);
digitalWrite (pin7, LOW); delayMicroseconds (d); digitalWrite(pin5, HIGH);
delayMicroseconds (alp2-alpl-d);

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digitalWrite (pin3, LOW); delayMicroseconds (d); digitalWrite(pinl, HIGH);
delayMicroseconds (alpl); }

4.7.3 Theoretical Calculations:

Harmonics Tnk*Fa α1 α2 Vdc Van V1 THD%

5,7,9,11 1,3 15 45 36 15.75 76.64 20.55%

𝟐
1. Tnk*Fa : 𝒌 +𝟑𝒌+𝟐
𝟐
; (k= 0,1,2,3,4,………...)
2. Van: 𝟒𝑽𝒅𝒄
𝒏𝝅
((𝒄𝒐𝒔(𝒏𝜶𝟏 ) + (𝒄𝒐𝒔(𝒏𝜶𝟐 ) )

𝟒𝑽𝒅𝒄
3. V1: 𝝅
(𝒄𝒐𝒔(𝜶𝟏 )+ 𝒄𝒐𝒔(𝜶𝟐 ))

𝟐
√∑∞
𝟒𝑽𝒅𝒄
𝒏=𝟑,𝟓,𝟕,… [ ( ) ( )]
((𝒄𝒐𝒔 𝒏𝜶𝟏 +(𝒄𝒐𝒔 𝒏𝜶𝟐 )
𝒏𝝅
4. THD%: 𝟒𝑽𝒅𝒄
( ) ( )
((𝒄𝒐𝒔 𝜶𝟏 +(𝒄𝒐𝒔 𝜶𝟐 )
𝝅

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 CHAPTER 5

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 Chapter 5
Result and Conclusion
5.1 Simulation model of 3-Level Inverter:

Fig 5.1 : FFT Analysis of 3-Level Inverter

5.2 Hardware Output of 3-Level Inverter:

Fig 5.2: Output Waveform of 3 Level Inverter

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 5.3 Simulation Model of 5-Level Inverter:

Fig 5.2 : FFT Analysis of 5-Level Inverter

5.4 Hardware output of 5-Level Inverter:

Fig 5.4 : Output Waveform of 5-Level Inverter

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 The Symmetrical Multi-level inverter using H-Bridge Cascaded topology of Three, Five,
Seven, Nine and Eleven were implemented in Simulation. Three and Five Level Multilevel inverter
was implemented on hardware and Total Harmonic Distortion (THD) were also been measured.
• It is observed that 3-Level model contains 3rd , 5th ,7th, 9th,11th harmonics and 5-
Level contains 5th ,7th, 9th,11th harmonics.
• The THD% of 3-Level simulation model is observed as 41.30%, and the hardware
model is 34.18%.
• The THD% of 5-level simulation model is observed as 15.14% and the hardware
model is 20.55%.
• The number of switches used for 3-Level inverter was Four, and for 5-Level
inverter was Eight.
• As the level of inverter increases from 3-Level to 5-Level the amount of THD%
reduces to 15.14% in simulation model.
• It is also Observed that in the practical implementation of 5 level the THD% reduces
to 20.55%.
• It is also Observed that in the practical implementation the presence of non-linear
devices such as transistors and diodes are the main causes for the distortions in
practical model.

The design parameters are considered to make the calculations with Symmetrical Cascaded
H-Bridge because it works efficiently. Hence the results of both Simulation and Hardware were
compared and detailed.

The design calculations are done with different Number of Levels, Input Voltage of each
level, Number of Switches, THD. Here, the characteristics need to be satisfied while selecting the
Inverter design.

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 Number of Input Voltage of Number of Number of Peak THD%
levels each Bridge bridges Switches Voltage
3 12V 1 4 12V 41.30%
5 12V 2 8 24V 15.14%
7 12V 3 12 36V 13.90%
9 12V 4 16 48V 11.55%
11 12V 5 20 60V 9.35%
Table 5.1: Comparison table for different levels of Inverter

 From the above results as the number of levels increases, the number of bridges are also
increases.
 As the number of bridges increases, the switches count to the respective bridges are also
increases whereas each bridge contain four switches.
 The THD % keeps on decreasing with the increase in number of level.
 Input Voltage to the each bridge is 12 VOLTS.
 Peak Voltages will also increases with increase in levels of multilevel inverter.

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 Future Scope

Multi-level inverters (MLIs) have been experiencing significant growth and innovation due
to their ability to produce high-quality voltage waveforms with lower harmonic distortion and
reduced electromagnetic interference. This makes them highly sought after in various applications,
from renewable energy systems to electric vehicle (EV) drivetrains and industrial drives. Looking
ahead, we can expect several advancements and opportunities in the field of MLIs:
1. Integration with Renewable Energy Systems: As the world shifts towards
renewable energy sources like solar panels and wind turbines, MLIs will play a crucial role in
efficiently converting and managing power. Their capacity to handle high power levels with
minimal losses makes them ideal for these applications.
2. Advancements in Electric Vehicle (EV) Technology: MLIs are set to become more
prevalent in EVs, especially in managing power flow between batteries and motors. Their high
efficiency and ability to operate at different voltage levels can contribute to improved performance
and longer battery life, essential for the widespread adoption of EVs.
3. Energy Storage Systems: With the growing demand for energy storage solutions,
MLIs can enhance the efficiency and reliability of battery storage systems. They can facilitate
better integration of storage systems with the grid and renewable energy sources, thereby
improving the stability and flexibility of the power system.
4. Smart Grids and Microgrids: MLIs will be vital in the development of smart grids
and microgrids, offering superior control over power distribution and quality. Their capability to
minimize harmonics and manage power flows efficiently makes them well-suited for the complex
energy systems of the future.

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 REFERENCES:
[1] J. Rodriguez, Jih-Sheng Lai and Fang Zheng Peng, "Multilevel inverters: a survey of
topologies, controls, and applications," in IEEE Transactions on Industrial Electronics, vol.
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[2] C. C, V. N and M. N. Vishwanath, "Asymmetric Multi-Level Inverter," 2022 2nd

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[3] R .Nair, Mahalakshmi R and Sindhu Thampatty K.C., "Performance of three phase 11 level
inverter with reduced number of switches using different PWM techniques," 2015
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[4] Sathyam and H. R. Ramesh, "Design of New Cascaded Multilevel Inverter Topology,"
2019 IEEE 5th International Conference for Convergence in Technology (I2CT), Bombay,
India, 2019, pp. 1-6, doi: 10.1109/I2CT45611.2019.9033719.

[5] S. Vadhiraj, K. N. Swamy and B. P. Divakar, "Generic SPWM technique for multilevel pu
rainverter," 2013 IEEE PES Asia-Pacific Power and Energy Engineering Conference
(APPEEC), Hong Kong, China, 2013, pp. 1-5, doi: 10.1109/APPEEC.2013.6837117.

[6] V. Thiyagarajan and P. Somasundaram, "Simulation of New Symmetric and Asymmetric

Multilevel Inverter Topology with Reduced Number of Switches," 2018 4th International
Conference on Electrical Energy Systems (ICEES), Chennai, India, 2018, pp. 315-319,
doi: 10.1109/ICEES.2018.8443283.

[7] R. Mathew and S. Agarwal, "Modified reduced switch symmetrical multilevel inverter,"
2017 International Conference on Circuit, Power and Computing Technologies
(ICCPCT), Kollam, India, 2017, pp. 1-8, doi: 10.1109/ICCPCT.2017.8074253.

[8] J. Rodriguez, Jih-Sheng Lai and Fang Zheng Peng, "Multilevel inverters: a survey of
topologies, controls, and applications," in IEEE Transactions on Industrial Electronics, vol.
49, no. 4, pp. 724-738, Aug. 2002, doi: 10.1109/TIE.2002.801052.

[9] Sarika D Patil and Akshay D Kadu, “Analysis for Selective Harmonic Elimination in a
Multilevel Inverter”, International Journal for Modern Trends in Science and Technology,
Vol. 06, Issue 04, April 2020, pp.:293-298.

Department of Electrical and Electronics Engineering Page 55

 [10] A. Kumar, R. K. Mandal, R. raushan and P. gauri. “Design and Analysis of the gate
Driver circuit for Power Semiconductor Switches,” 2020 International Conference on
Emerging Frontiers in Electrical and Electronics Technologies (ICEFEET), Patna, India,
2020, pp-1-6, doi: 10.1109/ICEFEET49149.2020.9186960.
[11] C. Chidananda, N. Venugopal and M. N. Vishwanath, "Asymmetric Multi-Level
Inverter," 2022 3rd International Conference for Emerging Technology (INCET),
Belgaum, India, 2022, pp. 1-7, doi: 10.1109/INCET54531.2022.9824659. keywords:
{Matched filters;Software packages;Voltage;Transforms;Pulse width
modulation;Multilevel inverters;Topology;multi-level inverter;components;phase
opposition disposition AMLI;PWM;THD}.
[12] M. Shahrukh, A. A. Usmani, P. Shrivastava, M. R. Khan and S. Kidwai, "NEW single
phase 11 level inverter topology using multilevel PWM switching with lesser components
count," 2018 IEEE Texas Power and Energy Conference (TPEC), College Station, TX,
USA, 2018, pp. 1-6, doi: 10.1109/TPEC.2018.8312102
[13] Ibrahim Haruna Shanono, Nor Rul Hasma Abdullah, Aisha Muhammad, “A Survey of
Multilevel Voltage Source Inverter Topologies, Controls, and Applications”, International
Journal of Power Electronics and Drive Systems (IJPEDS).
[14] Sarika D Patil, Akshay D Kadu, “Analysis for Selective Harmonic Elimination in a Multilevel
Inverter”, International Journal for Modern Trends in Science and Technology ISSN: 2455-3778
:: Volume: 06, Issue No: 04, April 2020.
[15] Shalini Tahunguriya, A. Rakesh Kumar and T. Deepa, “Multilevel Inverter with Reduced
Number of Switches and Reduction of Harmonics”, Middle-East Journal of Scientific Research
24 (S1): 184-191, 2016.
[16] Alla Eddine TOUBAL MAAMAR, M’hamed HELAIMI, Rachid TALEB, Hadj
MOULOUDJ,Oumaymah ELAMRI, Abdelatif GADOUM, “Mathematical Analysis of N-R
Algorithm for Experimental Implementation of SHEPWM Control on Single-phase Inverter”,
International Journal of Engineering Trends and Technology(IJETT) – Volume68 Issue 2- Feb
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[17] Vijaya Anand N, Hema Latha J,G Devadasu, Kumar C, “Generation of Optimal Switching
Angle for Nin”, Turkish Journal of Computer and Mathematics Education, Vol.12 No.6 (2021),
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Published online: 5 April 2021.
[18] Mohammed Rasheed, Rosli Omar, Marizan Sulaiman, Ahmed Aljanad, Azhar Ahmad,
“Performance Studies of Three-Phase Cascaded H Bridge and Diode-Clamped Multilevel
inverters”, IEEE Conference on Clean Energy and Technology (CEAT), 2013.

Department of Electrical and Electronics Engineering Page 56