Table Instructions

FUN100 D P FUN100 D P
REGISTER TO TABLE MOVE
R→T R→T

Ladder symbol Rs : Source data , can be constant or register

100DP.R T Td : Source register for destination table
Move control EN RS : END Move to end L : Length of destination table
Td :
Pointer increment INC L : ERR Pointer error Pr : Pointer register
Pr : Rs, Td can associate with V, Z, P0~P9 index
Pointer clear CLR register as indirect addressing

Range WX WY WM WS TMR CTR HR IR OR SR ROR DR K XR

WX0 WY0 WM0 WS0 T0 C0 R0 R3840 R3904 R3968 R5000 D0 16/32bit V、Z
Ope- ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ +/-
rand WX240 WY240 WM1896 WS984 T255 C255 R3839 R3903 R3967 R4167 R8071 D4095 number P0~P9
Rs ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
Td ○ ○ ○ ○ ○ ○ ○ ○* ○* ○ ○
L ○ ○* ○ 2~2048
Pr ○ ○ ○ ○ ○ ○ ○ ○* ○* ○

● When move control "EN" = 1 or transition from 0 to 1( P instruction), the contents of the source register Rs
will be written onto the register Tdpr indicated by the pointer Pr within the destination table Td (length is L).
Before executing, this instruction will first check the pointer clear "CLR" input signal. If "CLR" is 1, it will first
clear the pointer Pr, and then carry out the move operation. After the move has been completed, it will then
check the Pr value. If the Pr value has already reached L-1 (point to the last register in the table) then it will
only set the move-to-end flag "END" to 1, and finish execution of this instruction. If the Pr value is less than
L-1, then it must again check the pointer increment "INC" input signal. If "INC" is 1, then Pr value will be also
increased. Besides, pointer clear "CLR" is able to operate independently, without being influenced by other
input.

● The effective range of the pointer is 0 to L-1. Beyond this range, the pointer error "ERR" will be set to 1, and
this instruction will not be performed.

100P.R T z The example at left at the very beginning pointer Pr = 4,

X1
EN RS : R 0 END the entire content of table Td is 0, and the Rs value is
Td : R 10 8888. The diagram below shows the operation results
INC L : 8 ERR
when X1 have the transition of 0→1 twice.
Pr : R 50
CLR z Because INC is 1, Pr will increase by 1 each time the
instruction is executed.

Pr Pr Pr
4 R50 5 R50 6 R50
Td Td Td
0000 R10(T0) 0000 R10 0000 R10
0000 R11(T1) 0000 R11 0000 R11
Rs 0000 R12(T2)
X0＝ 0000 R12
X0＝ 0000 R12
R0 8888 0000 R13(T3) (First) 0000 R13 (Second) 0000 R13
0000
0000
R14(T4)
R15(T5)
Ö 8888
0000
R14
R15
Ö 8888
8888
R14
R15
0000 R16(T6) 0000 R16 0000 R16
0000 R17(T7) 0000 R17 0000 R17

Before First time result Second time result

7-100
Table Instructions

FUN101 D P FUN101 D P
TABLE TO REGISTER MOVE
T→R T→R

Ladder symbol Ts : Source table starting register

101DP.T R L : Length of source table
Move control EN TS : END Move to end Pr : Pointer register
L : Rd : Destination register
Pointer increment INC Pr : ERR Pointer error Ts, Rd may combine with V, Z, P0~P9 to
Rd : serve indirect address application
Pointer clear CLR

Range WX WY WM WS TMR CTR HR IR OR SR ROR DR K XR

WX0 WY0 WM0 WS0 T0 C0 R0 R3840 R3904 R3968 R5000 D0 16/32bit V、Z
Ope- ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ +/-
rand WX240 WY240 WM1896 WS984 T255 C255 R3839 R3903 R3967 R4167 R8071 D4095 number P0~P9
Ts ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
L ○ ○* ○
Pr ○ ○ ○ ○ ○ ○ ○ ○* ○* ○ 2~2048
Rd ○ ○ ○ ○ ○ ○ ○ ○* ○* ○ ○

z When move control "EN" = 1 or transition from 0 to 1 ( P instruction), the value of the register Tspr specified by
pointer Pr within source table Ts (length is L) will be written into the destination register Rd. Before executing,
this instruction will first check the input signal of pointer clear "CLR". If "CLR" is 1, it will first clear Pr and then
carry out the move operation. After completing the move operation, it will then check the value of Pr. If the Pr
value has already reached L-1 (point to the last register in the table), then it sets the move-to-end flag to 1, and
finishes executing of this instruction. If Pr is less than L-1, it check the status of "INC". If "INC" is 1, then it will
increase Pr and finish the execution of this instruction. Besides, pointer clear "CLR" can execute independently
and is not influenced by other inputs.

z The effective range of the pointer is 0 to L-1. Beyond this range the pointer error "ERR" will be set to 1 and this
instruction will not be carried out.

X0
101P.T R z In the example at left, at the very beginning Pr = 7 and Ts
EN TS : R 0 END and Rd are as shown at left in the diagram below. When X0
L : 9
have a transition from 0→1 twice, the results are shown at
INC Pr : R 19 ERR
right in the diagram below.
Rd : R 20
CLR z At the second time execution, the pointer has already
reached to the end so there will be no increment.

Ts Pr Pr Pr
R0(T0) 1111 7 R19 8 R19 8 R19
R1(T1) 2222
R2(T2) 3333 X0＝ X0＝
R3(T3) 4444 Rd (first) Rd (second) Rd
R4(T4)
R5(T5)
5555
6666
0 0 0 0 R20
Ö 8 8 8 8 R20
Ö 9 9 9 9 R20

R6(T6) 7777 END END END

R7(T7) 8888 0 0 1
R8(T8) 9999

Before execution First time execution Second time execution

7-101
 Table Instructions

FUN102 D P FUN102 D P
TABLE TO TABLE MOVE
T→T T→T

Ladder symbol Ts : Starting number of source table register

102DP.T T Td : Starting number of destination table
TS : register
Move control EN END Move to end
L : Table (Ts and Td) length
Td :
Pr : Pointer register
Pointer increment INC L : ERR Pointer error
Ts, Td may combine with V, Z, P0~P9 to
Pr : serve indirect address application
Pointer clear CLR

Range WX WY WM WS TMR CTR HR IR OR SR ROR DR K XR

WX0 WY0 WM0 WS0 T0 C0 R0 R3840 R3904 R3968 R5000 D0 2 V、Z
Ope- ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣
rand WX240 WY240 WM1896 WS984 T255 C255 R3839 R3903 R3967 R4167 R8071 D4095 2048 P0~P9
Ts ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
Td ○ ○ ○ ○ ○ ○ ○ ○* ○* ○ ○
L ○ ○* ○ ○
Pr ○ ○ ○ ○ ○ ○ ○ ○* ○* ○

z When move control "EN" = 1 or have a transition from 0 to 1( P instruction), the register Tspr pointed by pointer
Pr within the source table will be moved to a register Tdpr, which also pointed by the pointer Pr in the
destination table. Before execution, it will first check the input signal of pointer clear "CLR". If "CLR" is 1, it will
first clear Pr to 0 and then do the move (in this case Ts0→Td0). After the move action has been completed it
will then check the value of pointer Pr. If the Pr value has already reached L-1 (point to the last register on the
table), then it will set the move-to-end flag "END" to 1 and finish executing of this instruction. If the Pr value is
less than L-1, it will check the status of "INC". If "INC" is 1, then the Pr value will be increased by 1 before
execution. Besides, pointer clear "CLR" can execute independently, and will not be influenced by other input.

z The effective range of the pointer is 0 to L-1. Beyond this range, the pointer error flag "ERR" will be set to 1,
and this instruction will not be carried out.

102P.T T
z The diagram at left below is the status before execution.
X0
EN TS : R 0 END
When X0 from 0→1, the content of R5 in Ts table will copy to
Td : R 10 R15 and pointer R20 will be increased by 1.
INC L : 10 ERR
Pr : R 20
CLR

Pr Pr
R20 5 R20 6
Ts Td Td
R0 1111 R10 0000 R10 0000
R1 1111 R11 0000 R11 0000
R2 1111 R12 0000 R12 0000
R3 1111 R13 0000 X0＝ R13 0000
R4 1111 R14 8888 Ö R14 8888
R5 1111 R15 0000 R15 1111
R6 1111 R16 0000 R16 0000
R7 1111 R17 0000 R17 0000
R8 1111 R18 0000 R18 0000
R9 1111 R19 0000 R19 0000
Before execution result

7-102
Table Instructions

FUN103 D P FUN103 D P
BLOCK TABLE MOVE
BT_M BT_M

Ts :Starting register for source table

Td : Starting register for destination table

L: Lengths of source and destination tables

Ts, Td may combine with V, Z, P0~P9 to serve indirect

Range WX WY WM WS TMR CTR HR IR OR SR ROR DR K XR

WX0 WY0 WM0 WS0 T0 C0 R0 R3840 R3904 R3968 R5000 D0 2 V、Z
Ope- ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣
rand WX240 WY240 WM1896 WS984 T255 C255 R3839 R3903 R3967 R4167 R8071 D4095 256 P0~P9
Ts ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
Td ○ ○ ○ ○ ○ ○ ○ ○* ○* ○ ○
L ○ ○* ○ ○

z In this instruction the source table and destination table are the same length. When this instruction was
executed all the data in the Ts table is completely copied to Td. No pointer is involved in this instruction.

z When move control "EN" = 1 or have a transition from 0 to 1 ( P instruction), all the data from source table Ts
(length L) is copied to the destination table Td, which is the same length.

z One table is completely copied every time this instruction is executed, so if the table length is long, it will be
very time consuming. In practice, P modifier should be used to avoid time waste caused by each scan
repeating the same movement action.

z The diagram at left below is the status before execution. When

103P.BT_M
X0 X0 from 0→1, the content of R0~R9 in Ts table will copy to
EN TS : R 0
R10~R19.
Td : R 10
L : 10

Ts Td Td
R0 0000 ──→ R10 0000 R10 0000
R1 1111 ──→ R11 0000 R11 1111
R2 2222 ──→ R12 0000 R12 2222
R3 3333 ──→ R13 0000 X0＝ R13 3333
R4 4444 ──→ R14 0000 Ö R14 4444
R5 5555 ──→ R15 0000 R15 5555
R6 6666 ──→ R16 0000 R16 6666
R7 7777 ──→ R17 0000 R17 7777
R8 8888 ──→ R18 0000 R18 8888
R9 9999 ──→ R19 0000 R19 9999

Execute
Before executed result

7-103
 Table Instructions

FUN104 D P FUN104 D P
BLOCK TABLE SWAP
T_SWP T_SWP

Ta : Starting register of Table a

Tb : Starting register of Table b
L : Lengths of Table a and b
Ts, Td may combine with V, Z, P0~P9 to serve
indirect address application

Range WY WM WS TMR CTR HR OR SR ROR DR K XR

WY0 WM0 WS0 T0 C0 R0 R3904 R3968 R5000 D0 2 V、Z
Ope- ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣
rand WY240 WM1896 WS984 T255 C255 R3839 R3967 R4167 R8071 D4095 256 P0~P9
Ta ○ ○ ○ ○ ○ ○ ○ ○* ○* ○ ○
Tb ○ ○ ○ ○ ○ ○ ○ ○* ○* ○ ○
L ○ ○* ○ ○

z This instruction swaps the contents of Tables a and b, so the table must be the same length, and the registers
in the table must of write able. Since a complete swap is done with each time the instruction is executed, no
pointer is needed.

z When move control "EN" = 1 or have a transition from 0 to 1 ( P instruction), the contents of Table a and Table
b will be completely swapped.

z This instruction will swap all the registers specified in L each time the instruction is executed, so if the table
length is big, it will be very time consuming, therefore P instruction should be used.

z The diagram at left below is the status before execution.

104P.T_SWP When X0 from 0→1, the contents of R0~R9 in Ts table will
X0
EN Ta : R 0 swap with R10~R19.
Tb : R 10
L : 10

Ta Tb Ta Tb
R0 0000 R10 1111 R0 1111 R10 0000
R1 0000 R11 1111 R1 1111 R11 0000
R2 0000 R12 1111 R2 1111 R12 0000
R3 0000 R13 1111 X0＝ R3 1111 R13 0000
R4 0000 R14 1111 Ö R4 1111 R14 0000
R5 0000 R15 1111 R5 1111 R15 0000
R6 0000 R16 1111 R6 1111 R16 0000
R7 0000 R17 1111 R7 1111 R17 0000
R8 0000 R18 1111 R8 1111 R18 0000
R9 0000 R19 1111 R9 1111 R19 0000

Before executed After executed

7-104
Table Instructions

FUN105 D P FUN105 D P
REGISTER TO TABLE SEARCH
R-T_S R-T_S

Rs : Data to search, It can be a constant

or a register
Ts : Starting register of table being
searched
L : Label length
Pr : Pointer of table
Rs, Ts may combine with V, Z, P0~P9 to
serve indirect address application

Range WX WY WM WS TMR CTR HR IR OR SR ROR DR K XR

WX0 WY0 WM0 WS0 T0 C0 R0 R3840 R3904 R3968 R5000 D0 V、Z
16/32-bit
Ope- ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣
+/- number
rand WX240 WY240 WM1896 WS984 T255 C255 R3839 R3903 R3967 R4167 R8071 D4095 P0~P9
Rs ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
Ts ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
L ○ ○* ○ 2~256
Pr ○ ○ ○ ○ ○ ○ ○ ○* ○* ○

z When search control "EN" = 1 or has a transition from 0 to 1 ( P instruction), will search from the first register of
Table Ts (when "FHD" = 1 or Pr value has reached L-1), or from the next register (Tspr + 1) pointed by the
pointer within the table ("FHD" = 0, while Pr value is less than L-1) to find the first data different with Rs(when
D/S = 1) or find the first data the same with Rs (when D/S = 0). If it find a data match the condition it will
immediately stop the search action, and the pointer Pr will point to that data and found objective flag "FND" will
set to 1. When the searching has searched to the last register of the table, the execution of the instruction will
stop, whether it was found or not. In that case the search-to-end flag "END" will be set to 1 and the Pr value will
stop at L-1. When this instruction next time is executed, Pr will automatically return to the head of the table (Pr
= 0) before the search begin.

z The effective range of Pr is 0 to L-1. If the value exceeds this range then the pointer error flag "ERR" will
change to 1, and this instruction will not be carried out.

105P.R-T_S
X0 z The instruction at left is searching the table for a register with the
EN RS : 5555 FND value 5555 (because D/S = 0, it is searching for same value).
TS : R 0 Before execution, the pointer point to R2, but the starting point of
FHD L : 10 END the search is Pr + 1 (i.e. it starts from R3). After X0 has transition
Pr : R 20 from 0→1 3 times, the results of each search may be obtained
D/S ERR as shown in the diagram below.

Pr Ts Pr FN EN
R20 2 R0 5555 cX0＝ R20 6 1 0
R1 0000 (First)
R2 5555
Start
Rs R3 2222← Pr FN EN
point
5555 R4 3333 dX0＝ R20 9 0 1
R5 4444 (Second)
R6 5555
R7 6666 Pr FN EN
R8 7777 eX0＝ R20 0 1 0
R9 8888 (Third)

Before execution After execution

7-105
 Table Instructions

FUN106 D P FUN106 D P
TABLE TO TABLE COMPARE
T-T_C T-T_C

Ta : Starting register of Table a

Tb : Starting register of Table b
L : Lengths of Table
Pr : Pointer
Ta, Tb may combine with V, Z, P0~P9 to
serve indirect address application

Range WX WY WM WS TMR CTR HR IR OR SR ROR DR K XR

WX0 WY0 WM0 WS0 T0 C0 R0 R3840 R3904 R3968 R5000 D0 2 V、Z
Ope- ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣
rand WX240 WY240 WM1896 WS984 T255 C255 R3839 R3903 R3967 R4167 R8071 D4095 256 P0~P9
Ta ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
Tb ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
L ○ ○* ○ ○
Pr ○ ○ ○ ○ ○ ○ ○ ○* ○* ○

z When comparison control "EN" = 1 or has a transition from 0 to 1( P instruction), then starting from the first
register in the tables Ta and Tb (when "FHD" = 1 or Pr value has reached L-1) or starting from the next pair of
registers (Tapr+1 and Tbpr+1) pointed by Pr ("FHD" = 0, while Pr is less than L-1), this instruction will search
for pairs of registers with different values (when "D/S" = 1) or the same value (when "D/S" = 0). When search
found (either different or the same), it will immediately stop the search and the pointer Pr will point to the
register pairs met the search criteria. The found flag "FND" will be set to 1. When it has searched to the last
register of the table, the instruction will stop executing. whether it found or not. The compare-to-end flag "END"
will be set to 1, and the pointer value will stop at L-1. When this instruction is executed next time, Pr will
automatically return to the head of the table to begin the search. The effective range of Pr is 0 to L-1. The Pr
value should not changed by other programs during the operation. As this will affect the result of the search. If
the Pr value not in the effective range, the pointer error flag "ERR" will be set to 1, and this instruction will not
be carried out.

z The instruction at left starts from the register next to the register
106P.T-T_C pointed by the pointer (because "FHD" is 0) to search for register
X0
EN Ta : R 0 FND pairs with different data (because "D/S" is 1) within the 2 tables.
Tb : R 11 At the very beginning, Pr points to Ta1 and Tb1. There are 3
FHD L : 10 END different pairs of data at the position 1,3,6 of the table.
However, it does not compare from the beginning, and this
Pr : R 10
instruction will start searching from position 3 downwards. After
D/S ERR
X0 has changed 3 times from 0 to 1, the results are shown in the
diagram below.
Pr
R10 1
Ta Tb Pr FN EN

R0 0000 R11 0000 cX0＝ R10 3 1 0

R1 1111 R12 0000
(First)
R2 2222 R13 2222←
Start
R3 3333 R14 1234 Pr FN EN
point
R4 4444 R15 4444 dX0＝ R10 6 1 0
R5 5555 R16 5555 (Second)
R6 6666 R17 0000
R7 7777 R18 7777 Pr FN EN
R8 8888 R19 8888 eX0＝ R10 9 0 1
R9 9999 R20 9999 (Third)

Before execution After execution

7-106
Table Instructions

FUN107 D P FUN107 D P
TABLE FILL
T_FIL T_FIL

Rs : Source data to fill, can be a constant or a register

Td : Starting register of destination table

L :Table length

Rs, Td may combine with V, Z, P0~P9 to serve indirect

address application

Range WX WY WM WS TMR CTR HR IR OR SR ROR DR K XR

WX0 WY0 WM0 WS0 T0 C0 R0 R3840 R3904 R3968 R5000 D0 16/32-bit V、Z
Ope- ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ +/-
rand WX240 WY240 WM1896 WS984 T255 C255 R3839 R3903 R3967 R4167 R8071 D4095 number P0~P9
Ts ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
Td ○ ○ ○ ○ ○ ○ ○ ○* ○* ○ ○
L ○ ○* ○ 2~256

z When fill control "EN" = 1 or has a transition from 0 to 1 ( P instruction), the Rs data will be filled into all the
registers of the table Td.

z This instruction is mainly used for clearing the table (fill 0) or unifying the table (filling in the same values). It
should be used with the P instruction.

107P.T_FIL
X0 z The instruction at left will fill 5555 into the whole table
EN RS : 5555 Td. The results are as shown in the diagram below.
Td : R 0
L : 10

Td Td
R0 1547 R0 5555
R1 2314 R1 5555
R2 7725 R2 5555
Rs R3 0013 X0＝ R3 5555
5555 R4 5247 Ö R4 5555
R5 1925 R5 5555
R6 6744 R6 5555
R7 5319 R7 5555
R8 9788 R8 5555
R9 2796 R9 5555

Before execution After execution

7-107
 Table Instructions

FUN108 D P FUN108 D P
TABLE SHIFT
T_SHF T_SHF

IW : Data to fill the room after shift operation, can be a

constant or a register
Ts : Source table
Td : Destination table storing shift results
L : Lengths of tables Ts and Td
OW : Register to accept the shifted out data
Ts, Td may combine with V, Z, P0~P9 to serve indirect
address application
Range WX WY WM WS TMR CTR HR IR OR SR ROR DR K XR
WX0 WY0 WM0 WS0 T0 C0 R0 R3840 R3904 R3968 R5000 D0 16/32-bit V、Z
Ope- ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ +/-
rand WX240 WY240 WM1896 WS984 T255 C255 R3839 R3903 R3967 R4167 R8071 D4095 number P0~P0
IW ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
Ts ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
Td ○ ○ ○ ○ ○ ○ ○ ○* ○* ○ ○
L ○ ○* ○ 2~256
OW ○ ○ ○ ○ ○ ○ ○ ○* ○* ○

z When shift control "EN" = 1 or has a transition from 0 to 1( P instruction), all the data from table Ts will be taken
out and shifted one position to the left (when "L/R" = 1) or to the right (when "L/R" = 0). The room created by
the shift operation will be filled by IW and the results will be written into table Td. The data shifted out will be
written into OW.

z In the program at left, Ts and Td is the same table.

108P.T_SHF
X0 Therefore, the table shifts itself and then writes back to
EN IW : R 10 itself (the table must be writ able). It first perform a shift left
X1 TS : R 0 operation (let X1 = 1, and X0 go from 0→1) then perform a
L/R Td : R 0 shift to right operation (let X1 = 0, and makes X0 go from 0
L : 10 →1). The result are shown at right in the diagram below.
OW : R 11

Ts(Td) (Shift left) (Shift right)

Td(Ts) Td(Ts)
R0 0000 R0 1234 R0 0000
(Shift left) R1 1111 R1 0000 R1 1111
R2 2222 R2 1111 R2 2222
R3 3333 OW R3 2222 R3 3333
R10 1 2 3 4 R4 4444 R11 ×××× R4 3333 R4 4444
R5 5555 R5 4444 R5 5555
R6 6666 R6 5555 R6 6666
R7 7777 R7 6666 R7 7777
R8 8888 R8 7777 R8 8888
R9 9999 (Shift left) R9 8888 R9 1234
OW OW
Dotted line is the path for shift right R11 9999 R11 1234

Before execution cFirst time dSecond time

7-108
Table Instructions

FUN109 D P FUN109 D P
TABLE ROTATE
T_ROT T_ROT

Ts : Source table for rotate

Td : Destination table storing results of rotation
L : Lengths of table
Ts, Td may combine with V, Z, P0~P9 to serve indirect
address application

Range WX WY WM WS TMR CTR HR IR OR SR ROR DR K XR

WX0 WY0 WM0 WS0 T0 C0 R0 R3840 R3904 R3968 R5000 D0 2 V、Z
Ope- ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣
rand WX240 WY240 WM1896 WS984 T255 C255 R3839 R3903 R3967 R4167 R8071 D4095 256 P0~P9
Ts ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
Td ○ ○ ○ ○ ○ ○ ○ ○* ○* ○ ○
L ○ ○* ○ ○

z When rotation control "EN" = 1 or has a transition from 0 to 1( P instruction), the data from the table of Ts will
be rotated 1 position to the left (when "L/R" = 1)or 1 position to the right (when "L/R" = 0). The results of the
rotation will then be written onto table Td.

109P.T_ROT z In the program at left, Ts and Td is the same table. The

X0
EN TS : R 0 table after rotation will write back to itself. It first perform
Td : R
one left rotation (let X1 = 1, and X0 go from 0→1), and
X1 0
L : 10
then performs one right rotation (let X1 = 0, and X0 go
L/R
from 0→1). The results are shown at right in the diagram
below.

Rotate left Rotate right (Rotate left) (Rotate right)

Ts(Td)
Td(Ts) Td(Ts)
R0 0 0 0 0 (right) R0 9999 R0 0000
R1 1111 R1 0000 R1 1111
R2 2222 R2 1111 R2 2222
R3 3333 R3 2222 R3 3333
R4 4444 R4 3333 R4 4444
R5 5555 R5 4444 R5 5555
R6 6666 R6 5555 R6 6666
R7 7777 R7 6666 R7 7777
R8 8888 R8 7777 R8 8888
R9 9 9 9 9 (left) R9 8888 R9 9999

Before execution cFirst time dSecond time

7-109
 Table Instructions

FUN110 D P FUN110 D P
QUEUE
QUEUE QUEUE

IW : Data pushed into queue, can be a constant

or a register
QU : Starting register of queue
L : Size of queue
Pr : Pointer register
OW : Register accepting data popped out
from queue
QU may combine with V, Z, P0~P9 to serve
indirect address application
Range WX WY WM WS TMR CTR HR IR OR SR ROR DR K XR
WX0 WY0 WM0 WS0 T0 C0 R0 R3840 R3904 R3968 R5000 D0 16/32-bit V、Z
Ope- ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ +/- number
rand WX240 WY240 WM1896 WS984 T255 C255 R3839 R3903 R3967 R4167 R8071 D4095 P0~P9
IW ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
QU ○ ○ ○ ○ ○ ○ ○ ○ ○* ○ ○
L ○ ○* ○ 2~256
Pr ○ ○ ○ ○ ○ ○ ○ ○* ○* ○
OW ○ ○ ○ ○ ○ ○ ○ ○* ○* ○

z Queue is also a kind of table. It is different from ordinary table in that its queue register numbers go from 1 to L
and not from 0 to L-1. In other words QU1~QUL respectively correspond to pointers Pr = 1 to L, and Pr = 0 is
used to show that the queue is empty.

z Queue is a first in first out (FIFO) device, i.e. - the data that first pushed into the queue will be the first to pop
out from the queue. A queue is comprised of L consecutive 16 or 32 bit registers ( D instruction) starting from
the QU register, as in the diagram below:

Pr
4

IW QU
g5555 QU1 f4444
QU2 e3333 Push
push(I/O=1) QU3 d2222 down
QU4 c1111 OW
1.IW always push into QU5 ××××
QU1
……

2.Pr＋1→Pr Pop out(I/O=0)

c ～ gis the sequence number of 2. QUpr →OW

operation QUL 3. Pr－1→Pr

z When execution control "EN" = 1 or has a transition from 0 to 1 ( P instruction), the status of in/out control "I/O"
determines whether the IW data will be pushed into the queue (when "I/O" = 1) or be popped out and
transferred to OW (when "I/O" = 0). As shown in the diagram above, the IW data will always be pushed into the
first (QU1) register of the queue. After it has been pushed in, Pr will immediately be increased by 1, so that the
pointer can always point to the first data that was pushed into the queue. When it is popped out, the data
pointed by Pr will be transferred directly to OW. Pr will be reduced by 1, so that it still point to the first data
remained in the queue.

7-110
Table Instructions

FUN110 D P FUN110 D P
QUEUE
QUEUE QUEUE

z If no data has yet been pushed into the queue or the pushed in data has already been popped out (Pr = 0),
then the queue empty flag will be set to 1. In this case, even if there is further popping out action, this
instruction will not be executed. If data is only pushed in and not popped out, or pushed in is more than that
popped out, then the queue finally becomes full (pointer Pr indicates the QUL position), and the queue full flag
is changed to 1. In this case, if there is more pushing in action, this instruction will not execute. The pointer for
this instruction is used during access of the queue, to indicate the data that was pushed in the earliest. Other
programs should not be allowed to change it, or else an operation error will be created. If there is a specific
application, which requires the setting of a Pr value, then its permissible range is 0 to L (0 means empty, and 1
to L respectively correspond to QU1 to QUL). Beyond this range, the pointer error flag "ERR" will be set as 1,
and this instruction will not be carried out.

z The program at left assumes the queue content is the

110P.QUEUE
X0 same with the queue at preceding page. It will first
EN IW : R 0 EPT perform queue push operation, and then perform pop
X1 QU : R 2 out action. The results are shown below. Under any
I/O L : 10 FUL circumstance, Pr always point to the first (oldest) data
Pr : R 1 that was remained in queue.
OW : R 20 ERR

Pr Pr
5 4

QU QU
QU1 5555 R2 QU1 5555 R2
QU2 4444 R3 QU2 4444 R3
QU3 3333 R4 QU3 3333 R4
QU4 2222 R5 OW QU4 2222 R5 OW
QU5 1111 R6 ×××× R20 QU5 R6 1 1 1 1 R20
QU6 R7 ↑ QU6 R7
QU7 R8 OW unchanged QU7 R8
QU8 R9 QU8 R9
QU9 R10 QU9 R10
QU10 R11 QU10 R11

After push in (X1=1，X0 from 0→1) After pop off (X1=0，X0 from 0→1)

7-111
 Table Instructions

FUN111 D P FUN111 D P
STACK
STACK STACK

IW : Data pushed into stack, can be a constant

or a register
ST : Starting register of stack
L : Size of stack
Pr : Pointer register
OW : Register accepting data popped out from
stack
ST may combine with V, Z, P0~P9 to serve
indirect address application

Range WX WY WM WS TMR CTR HR IR OR SR ROR DR K XR

WX0 WY0 WM0 WS0 T0 C0 R0 R3840 R3904 R3968 R5000 D0 16/32-bit V、Z
Ope- ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ +/-
rand WX240 WY240 WM1896 WS984 T255 C255 R3839 R3903 R3967 R4167 R8071 D4095 number P0~P9
IW ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
ST ○ ○ ○ ○ ○ ○ ○ ○* ○* ○ ○
L ○ ○* ○ 2~256
Pr ○ ○ ○ ○ ○ ○ ○ ○* ○* ○
OW ○ ○ ○ ○ ○ ○ ○ ○* ○* ○

z Like queue, stack is also a kind of table. The nature of its pointer is exactly the same as with queue, i.e. Pr = 1
to L, which corresponds to ST1 to STL, and when Pr = 0 the stack is empty.

z Stack is the opposite of queue, being a last in first out (LIFO) device. This means that the data that was most
recently pushed into the stack will be the first to be popped out of the stack. The stack is comprised of L
consecutive 16 or 32-bit ( D instruction) registers starting from ST, as shown in the following diagram:

Pr
4
c～g is the sequence
number of operation ST
ST1 c1111 ← Bottom of stack
ST2 d2222
ST3 e3333
IW ST4 f4444 OW
g5555 ST5 ××××

push(I/O=1) push pop(I/O=0)

1.Pr＋1→Pr 1.STpr→OW
2.IW→STpr STL 2.Pr－1→Pr

z When execution control "EN" = 1 or has a transition from 0 to 1( P instruction), the status of in/out control "I/O"
determines whether the IW data will be pushed into the stack (when "I/O" = 1), or the data pointed by Pr within
the stack (the data most recently pushed into the stack) will be moved out and transferred to OW (when "I/O"
= 0). Note that the data pushed in is stacking, so before pushed in, Pr will increased by 1 to point to the top of
the stack then the data will be pushed in. When it is popped out, the data pointed by pointer Pr (the most
recently pushed in data) will be transferred to OW. After then Pr will decreased by 1. Under any circumstances,
the pointer Pr will always point to the data that was pushed into the stack most recently.

7-112
Table Instructions

FUN111 D P FUN111 D P
STACK
STACK STACK

z When no data has yet been pushed into the stack or the pushed in data has already been popped out (Pr = 0),
the stack empty flag "EPT" will set to 1. In this case any further pop up actions, will be ignored. If more data is
pushed than popped out, sooner or latter the stack will be full (pointer Pr points to STL position), and the stack
full flag "FUL" will set to 1. In this case any further push actions, will be ignored. As with queue, the stack
pointer in normal case should not be changed by other instructions. If there is a special application which
requires to set the Pr value, then its effective range is 0 to L (0 means empty, 1 to L respectively correspond to
ST1 to STL). Beyond this range, the pointer error flag "ERR" will set to 1, and the instruction will not be carried
out.

X0
111P.STACK z The program at left assumes that the initial content of the
EN IW : R 0 EPT stack is just as in the diagram of a stack on the
ST : R 2 preceding page. The operation illustrated in this example
X1
I/O L : 10 FUL is to push a data and than pop it from stack. The results
Pr : R 1 are shown below. Under any circumstances, Pr always
point to the data that was most recently pushed into the
OW : R 20 ERR
stack.

Pr Pr
5 R1 4

ST QU
ST1 1111 R2 ST1 1111 R2
ST2 2222 R3 ST2 2222 R3
ST3 3333 R4 ST3 3333 R4
ST4 4444 R5 OW ST4 4444 R5 OW
ST5 5555 R6 ×××× R20 ST5 R6 5 5 5 5 R20
ST6 R7 ↑ ST6 R7
ST7 R8 OW unchanged ST7 R8
ST8 R9 ST8 R9
ST9 R10 ST9 R10
ST10 R11 ST10 R11

After push(X1=1，X0 from 0→1) After pop up(X1=0，X0 from 0→1)

7-113
 Table Instructions

FUN112 D P FUN112 D P
BLOCK COMPARE（DRUM）
BKCMP BKCMP

Rs : Data for compare, can be a constant or a

register
Ts : Starting register block storing upper and
lower limit
L : Number of pairs of upper and lower limits
D : Starting relay storing results of
comparison

Range Y M S WX WY WM WS TMR CTR HR IR OR SR ROR DR K

Y0 M0 S0 WX0 WY0 WM0 WS0 T0 C0 R0 R3840 R3904 R3968 R5000 D0 16/32-bit
Ope- ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ +/-
rand Y255 M999 S999 WX240 WY240 WM1896 WS984 T255 C255 R3839 R3903 R3967 R4167 R8071 D4095 number
Rs ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
Ts ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
L ○ ○* ○ 1~256
D ○ ○ ○

z When comparison control "EN" = 1 or has a transition from 0 to 1( P instruction), comparisons will be perform
one by one between the contents of Rs and the upper and lower limits form by L pairs of 16 or 32-bit ( D
modifier) registers starting from the Ts register (starting from T0 each adjoining 2 register units form a pair of
upper and lower limits). If the value of Rs falls within the range of the pair, then the bit within the comparison
results relay D which corresponds to that pair will be set to 1. Otherwise it will be set as 0 until comparison of
all the L pairs of upper and lower limits is completed.

z When M1975=0, if there is any pair where the upper limit value is less than the lower limit value, then the limit
error flag "ERR" will be set to 1, and the comparison output for that pair will be 0.

z When M1975=1, there is no restriction on the relation of upper limit and lower limit, this can apply for 360°rotary
electronic drum switch application.

Upper limit Lower limit Compare Compared Result

value
0 TS1 TS0 D0
1 TS3 TS2 D1
    Rs  
L−1 TS2L−1 TS2L−2 DL−1

z Actually this instruction is a drum switch, which can be used in interrupt program and when incorporate with
immediate I/O instruction (IMDIO) can achieve an accurate electronic drum.

X0 112.BKCMP
z In this program, C0 represents the rotation angle (Rs) of
EN RS : C 0 ERR
a drum shaft. The block compare instruction performs a
Ts : R 10
comparison between Rs and the 4 pairs (L = 4) of upper
L : 4
and lower limits, R10,R11, R12,R13, R14,R15 and
D : Y 5 R16,R17. The comparison results can be obtained from
X1 the four drum output points Y5 to Y8.
PSU C 0 z The input point X1 is a rotation angle detector mounted
C0 PV : 360 on the drum shaft. With each one degree rotation of the
CLR drum shaft angle, X1 produces a pulse. When the drum
shaft rotates a full cycle, X1 produces 360 pulses.

7-114
Table Instructions

FUN112 D P FUN112 D P
BLOCK COMPARE（DRUM）
BKCMP BKCMP

z The program in the diagram above coordinates a rotary encoder or other rotating angle detection device
(directly connect to a rotating mechanism), which can form a mechanical device equivalent to the mechanical
structure of an actual drum (see mechanism shown within dotted line in diagram below). While the upper and
lower limits are being adjusted, you can change at will the range of the activated angle of the drum. This
cannot be done with the traditional drum mechanism.

Equivalent mechanical drum emulated by above program

Rotary encoder
Rotary encoder 200
200
180
180 180
180
Rotating
Rotating
140
140
220
220 ． mechanism
mechanism
80
80
90
90 80
80

60
60

320
320 40
40 0
00

Limit
Limit swsw

X1
X1
Y7 Y8
Y5 Y6
Y6

40 140
Y5
80 180
Y6
60
Y7
80 200
Y8

C0
0° 40° 80° 120° 160° 200° 240° 280° 320° 360°

7-115
 Table Instructions

FUN113 D P FUN113 D P
DATA SORTING
SORT SORT

S : Starting register of source registers to sort

D : Starting register of destination registers to store the
data after sorted
L : Total register for sorting

Range TMR CTR HR IR OR SR ROR DR K

T0 C0 R0 R3840 R3904 R3968 R5000 D0 2
Ope- ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣
rand T255 C255 R3839 R3903 R3967 R4167 R8071 D4095 127
S ○ ○ ○ ○ ○ ○ ○ ○
D ○ ○* ○
L ○ ○ ○ ○

● When sort control "EN" = 1 or has a transition from 0 to 1( P instruction), will sort the registers with ascending
order (if A/D = 1) or descending order (if A/D = 0) and put the sorted result to the registers starting by D
register.

● The valid data length of sort operation is between 2 and 127, other length will set the “ERR” to 1 and the sort
operation will not perform.

113P.SORT
X0
EN S : R 0 ERR ․The example at left sorts the table comprised of R0~R9
D : R 10 and stores the sorted data to the table locate at
A/D L : 10 R10~R19.

S D
R0 1547 R10 0013
R1 2314 R11 1547
R2 7725 R12 1925
R3 0013 R13 2314
R4 5247
X0＝ R14 2796
R5 1925 Ö R15 5247
R6 6744 R16 5319
R7 5319 R17 6744
R8 9788 R18 7725
R9 2796 R19 9788

Before After

7-116
Table Instructions

FUN114 D P FUN114 D P
ZONE WRITE
Z-WR Z-WR

D : Starting address of being set or reset

N : Quantity of being set oe reset, 1~511

D 、 N operand can combine V 、 Z 、 P0~P9 for index

addressing while word operation

Y M S WY WM WS TMR CTR HR IR OR SR ROR DR K XR

Range
Y0 M0 S0 WY0 WM0 WS0 T0 C0 R0 R3840 R3904 R3968 R5000 D0 V、Z
∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣
Operand
Y255 M1911 S99 WY240 WM1896 WS984 T255 C255 R3839 R3903 R3967 R4167 R8071 D4095 P0～P9
D ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
N ○ ○ ○ 1-511 ○

● When operation control "EN"=1 or changes from 0→1（ P instruction）, it will perform the write operation
according to the input status of write selection, the specified area of registers or bits will all be reset to 0
("1/0"=0) or set to 1("1/0"=1).

114.Z-WR
X0
EN D : R0 ERR
N : 10
I/O

․Above example, registers R0~R9 will be reset to 0 while X0=1.

114.Z-WR
X0
EN D : M5 ERR

N : 7
I/O

․Above example, bits M5~M11 will be reset to 0 while X0=1.

7-117
 Matrix Instructions

Matrix Instructions

Fun No. Mnemonic Functionality Fun No. Mnemonic Functionality

120 MAND Matrix AND 126 MBRD Matrix Bit Read
121 MOR Matrix OR 127 MBWR Matrix Bit Write
122 MXOR Matrix XOR 128 MBSHF Matrix Bit Shift
123 MXNR Matrix XNOR 129 MBROT Matrix Bit Rotate
124 MINV Matrix Inverse 130 MBCNT Matrix Bit Count
125 MCMP Matrix Compare

● A matrix is comprised of 2 or more consecutive 16-bit registers. The number of registers comprising the
matrix is called the matrix length (L). One matrix altogether has L×16 bits (points), and the basic unit of the
object for each operation is bit.
● The matrix instructions treats the 16×L matrix bits as a set of series points( denoted by M0 to M16L-1).
Whether the matrix is formed by register or not, the operation object is the bit not numerical value.

● Matrix instructions are used mostly for discrete status processing such as moving, copying, comparing,
searching, etc, of single point to multipoint (matrix), or multipoint-to-multipoint. These instructions are
convenient, important for application.

● Among the matrix instructions, most instruction need to use a 16-bit register as a pointer to points a specific
point within the matrix. This register is known as the matrix pointer (Pr). Its effective range is 0 to 16L-1,
which corresponds respectively to the bits M0 to M16L-1 within the matrix.

● Among the matrix operations, there are shift left/right, rotate left/right operations. We define the movement
toward higher bit is left direction, while the movement toward lower bit is right direction, as shown in the
diagram below.

←─ Width is 16 bit ─→
Pr
40 M15 M M0 (right)
M40
↓ ↓
R0
R1 ↑
R2 1
R3
│
R4 │
Pr=40, point y
y
to M40, y
y length
y
y L
y
y
y y │
y y
y y │
y y
↓
RL−1

↑
M16L−1(left)

7 - 11 8
Matrix Instructions

FUN120 P FUN120 P
MATRIX AND
MAND MAND

Ma : Starting register of source matrix a

Mb : Starting register of source matrix b
Md : Starting register of destination matrix
L : Length of matrix (Ma, Mb and Md)
Ma, Mb, Md may combine with V, Z, P0~P9 to serve
indirect address application

Range WX WY WM WS TMR CTR HR IR OR SR ROR DR K XR

WX0 WY0 WM0 WS0 T0 C0 R0 R3840 R3904 R3968 R5000 D0 2 V、Z
Ope- ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣
rand WX240 WY240 WM1896 WS984 T255 C255 R3839 R3903 R3967 R4167 R8071 D4095 256 P0~P9
Ma ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
Mb ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
Md ○ ○ ○ ○ ○ ○ ○ ○* ○* ○ ○
L ○ ○* ○ ○

z When operation control "EN" = 1 or has a transition from 0 to 1( P Ma Mb Md

instruction), this instruction will perform a logic AND (only if 2 bits
are 1 will the result be 1, otherwise it will be 0)operation between
two source matrixes with a length of L, Ma and Mb. The result will
then be stored in the destination matrix Md, which is also the same L
length (the AND operation is done by bits with the same bit
numbers). For example, if Ma0 = 0, Mb0 = 1, then Md0 = 0; if Ma1 =
1, Mb1 = 1, then Md1 = 1; etc, right up until AND reaches Ma16L-1
and Mb16L-1.
AND

z In the program at left, when X0 goes from 0→1, then

120P.MAND matrix Ma, comprised by R0 to R4, and matrix Mb,
X0
EN Ma : R 0 comprised by R10 to R14, will do an AND operation. The
Mb : R 10 results will be stored back in matrix Md, comprised by
Md : R 20
R20 to R24. The result is shown at right in the diagram
L : 5
below.

Ma15 Ma0 Mb15 Mb0 Md15 Md0

↓ Ma ↓ ↓ Mb ↓ ↓ Md ↓
R0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R10 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R20 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 R11 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 R21 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R2 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 R12 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 R22 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
R3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R13 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R23 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R14 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R24 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
↑ ↑ ↑ ↑ ↑ ↑
Ma79 Ma64 Mb79 Mb64 Md79 Md64

Before execution After execution

7 - 11 9
 Matrix Instructions

FUN121 P FUN121 P
MATRIX OR
MOR MOR

Ladder symbol
121P.MOR Ma : Starting register of source matrix a

Operation control EN Ma : Mb : Starting register of source matrix b

Mb : Md : Starting register of destination matrix

Md : L : Length of matrix (Ma, Mb and Md)

Ma, Mb, Md may combine with V, Z, P0~P9 to serve
L :
indirect address application

Range WX WY WM WS TMR CTR HR IR OR SR ROR DR K XR

WX0 WY0 WM0 WS0 T0 C0 R0 R3840 R3904 R3968 R5000 D0 2 V、Z
Ope- ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣
rand WX240 WY240 WM1896 WS984 T255 C255 R3839 R3903 R3967 R4167 R8071 D4095 256 P0~P9
Ma ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
Mb ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
Md ○ ○ ○ ○ ○ ○ ○ ○* ○* ○ ○
L ○ ○* ○ ○

Ma Mb Md
z When operation control "EN" = 1 or has a transition from 0 to 1 ( P
instruction), this instruction will perform a logic OR(If any 2 of the
bits are 1, then the result will be 1, and only if both are 0 will the
result be 0) operation between 2 source matrixes with a length of
L, Ma and Mb. The result will then be stored in the destination L
matrix Md, which is also the same length (the OR operation is
done by bits with the same bit numbers). For example, if Ma0 = 0,
Mb0 = 1, then Md0 = 1; if Ma1 = 0, Mb1 = 0, then Md1 = 0; etc, right
up until OR reaches Ma16L-1 and Mb16L-1.
OR

121P.MOR z In the program at left, when X0 goes from 0→1, then matrix
X0
EN Ma : R 0 Ma, comprised by R0 to R4, and matrix Mb, comprised by
Mb : R 10 R10 to R14, will do an OR operation. The results will then
be stored into the destination matrix Md, comprised by R10
Md : R 10
to R14. In this example, Mb and Md is the same matrix, so
L : 5
after operation the source matrix Mb will replaced by the
new value. The result is shown at right in the diagram
below.

Ma15 Ma0 Mb15 Mb0 Md15 Md0

↓ Ma ↓ ↓ Mb ↓ ↓ Md ↓
R0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R10 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R20 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
R1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 R11 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 R21 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
R2 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 R12 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 R22 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
R3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R13 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R23 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R14 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R24 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
↑ ↑ ↑ ↑ ↑ ↑
Ma79 Ma64 Mb79 Mb64 Md79 Md64

Before execution After execution

7-120
Matrix Instructions

FUN122 P FUN122 P
MATRIX EXCLUSIVE OR（XOR）
MXOR MXOR

Ma: Starting register of source matrix a

Mb: Starting register of source matrix b
Md: Starting register of destination matrix
L : Length of matrix (Ma, Mb and Md)

Ma, Mb, Md may combine with V, Z, P0~P9 to serve

indirect address application

Range WX WY WM WS TMR CTR HR IR OR SR ROR DR K XR

WX0 WY0 WM0 WS0 T0 C0 R0 R3840 R3904 R3968 R5000 D0 2 V、Z
Ope- ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣
rand WX240 WY240 WM1896 WS984 T255 C255 R3839 R3903 R3967 R4167 R8071 D4095 256 P0~P9
Ma ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
Mb ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
Md ○ ○ ○ ○ ○ ○ ○ ○* ○* ○ ○
L ○ ○* ○ ○

Ma Mb Md

z When operation control "EN" = 1 or has a transition from 0 to 1 ( P

instruction), this instruction will performs a logic XOR (if the 2 bits
are different, then the result will be 1, otherwise it will be
0)between 2 source matrixes with a length of L, Ma and Mb. The L
result will then be stored back into the destination matrix Md, which
also has a length of L. For example the XOR operation is done by
bits with the same bit numbers - for example, if Ma0 = 0, Mb0 = 1,
then Md0 = 1; if Ma1 = 1, Mb1 = 1, then Md1 = 0; etc, right up until
XOR reaches Ma16L-1 and Mb16L-1.
XOR

122P.MXOR z In the program at left, when X0 goes from 0→1, will

X0
EN Ma : R 0 perform a XOR operation between matrix Ma, comprised
Mb : R 10 by R0 to R4, and matrix Mb, comprised by R10 to R14.
The results will then be stored in destination matrix Md,
Md : R 20
comprised by R20 to R24. The results are shown at right
L : 5
in the diagram below.

Ma15 Ma0 Mb15 Mb0 Md15 Md0

↓ Ma ↓ ↓ Mb ↓ ↓ Md ↓
R0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R10 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R20 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
R1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 R11 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 R21 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
R2 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 R12 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 R22 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R13 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R23 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R14 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R24 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
↑ ↑ ↑ ↑ ↑ ↑
Ma79 Ma64 Mb79 Mb64 Md79 Md64

Before execution After execution

7-121
 Matrix Instructions

FUN123 P FUN123 P
MATRIX EXCLUSIVE NOR（XNR）
MXNR MXNR

Ma : Starting register of source matrix a

Mb : Starting register of source matrix b
Md : Starting register of destination matrix
L : Length of matrix (Ma, Mb and Md)
Ma, Mb, Md may combine with V, Z,P0~P9 to serve
indirect address application

Range WX WY WM WS TMR CTR HR IR OR SR ROR DR K XR

WX0 WY0 WM0 WS0 T0 C0 R0 R3840 R3904 R3968 R5000 D0 2 V、Z
Ope- ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣
rand WX240 WY240 WM1896 WS984 T255 C255 R3839 R3903 R3967 R4167 R8071 D4095 256 P0~P9
Ma ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
Mb ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
Md ○ ○ ○ ○ ○ ○ ○ ○* ○* ○ ○
L ○ ○* ○ ○

Ma Mb Md
z When operation control "EN" = 1 or has a transition from 0 to 1 ( P
instruction), will perform a logic XNR operation (if the 2 bits are the
same, then the result will be 1, otherwise it will be 0)between 2
source matrixes with a length of L, Ma and Mb. The results will
then be stored into the destination matrix Md, which also has the L
same length (the XNR operation is done by bits with the same bit
numbers). For example, if Ma0 = 0, Mb0 = 1, then Md0 = 0; Ma1 = 0,
Mb1 = 0, then Md1 = 1; etc, right up until XNR reaches Ma16L-1 and
Mb16L-1.
XNR

X0
123P.MXNR z When operation control "EN" = 1 or goes from 0 to 1 ( P
EN Ma : R 0 instruction), will perform a XNR operation between Ma
Mb : R 10 matrix comprised by R0~R9 and Mb matrix comprised by
Md : R 10 R10~R19. The results will then be stored into the
L : 5 destination matrix Md comprised by R10~R19. The results
are shown at right in the diagram below.

Ma15 Ma 0 Mb15 Mb0 Md15 Md0

↓ Ma ↓ ↓ Mb ↓ ↓ Md ↓
R0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R10 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R20 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 R11 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 R21 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R2 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 R12 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 R22 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
R3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R13 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R23 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
R4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R14 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R24 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
↑ ↑ ↑ ↑ ↑ ↑
Ma79 Ma64 Mb79 Mb64 Md79 Md64

Before execution After execution

7-122
Matrix Instructions

FUN124 P FUN124 P
MATRIX INVERSE
MINV MINV

Ladder symbol Ms : Starting register of source matrix

124P.MINV Md : Starting register of destination
Operation control EN Ms : L : Length of matrix (Ms and Md)
Md : Ma, Md may combine with V, Z, P0~P9 to serve indirect
L : address application

Range WX WY WM WS TMR CTR HR IR OR SR ROR DR K XR

WX0 WY0 WM0 WS0 T0 C0 R0 R3840 R3904 R3968 R5000 D0 2 V、Z
Ope- ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣
rand WX240 WY240 WM1896 WS984 T255 C255 R3839 R3903 R3967 R4167 R8071 D4095 256 P0~P9
Ms ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
Md ○ ○ ○ ○ ○ ○ ○ ○* ○* ○ ○
L ○ ○* ○ ○

z When operation control "EN" = 1 or has a transition from 0 to 1 ( P Ms Md

instruction), source register Ms, which has a length of L, will be
completely inverted (all the bits with a value of 1 will change to 0,
and all those with a value of 0 will change to 1). The results will
then be stored into destination matrix Md.
L

Inverse
Ms

z In the program at left, when X0 goes from 0→1, the

124P.MINV
X0 matrix comprised by R0 to R4 will be inverted, and then
EN Ms : R 0 store back into itself (because in this example Ms and
Md : R 0 Md are the same matrix). The results obtained are
L : 5 shown at right in the diagram below.

Ms15 Ms0 Md15 Md0

↓ Ms ↓ ↓ Md ↓
R0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
R1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 R1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
R2 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 R2 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0
R3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R3 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
R4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
↑ ↑ ↑ ↑
Ms79 Ms64 Md79 Md64

Before execution After execution

7-123
 Matrix Instructions

FUN125 P FUN125 P
MATRIX COMPARE
MCMP MCMP

Ladder symbol
125P.MCMP Md : Starting register of matrix a
Comparison control EN Ma : FND Found objective Mb : Starting register of matrix b
Mb : L : Length of matrix (Ma, Mb)
Compare from head FHD L : END Compare to end Pr : Pointer register
Ma, Mb may combine with V, Z, P0~P9 to
Pr :
serve indirect address application
Different/Same option D/S ERR Pointer error

Range WX WY WM WS TMR CTR HR IR OR SR ROR DR K XR

WX0 WY0 WM0 WS0 T0 C0 R0 R3840 R3904 R3968 R5000 D0 2 V、Z
Ope- ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣
rand WX240 WY240 WM1896 WS984 T255 C255 R3839 R3903 R3967 R4167 R8071 D4095 256 P0~P9
Ma ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
Mb ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
L ○ ○* ○ ○
Pr ○ ○ ○ ○ ○ ○ ○ ○* ○* ○

z When comparison control "EN" = 1 or has a transition from 0 to 1 ( P

instruction), then beginning from the top pair of bits (Ma0 and Mb0) Pr
within the 2 matrixes Ma and Mb (when "FHD" = 1 or Pr value is
equal to 16L-1), or beginning from the next pair of bits (Mapr + 1 and Ma Mb
Mbpr + 1) pointed by pointer Pr (when "FHD" = 0 and Pr value is less
than L-1), this instruction will compare and search for pairs of bits
with different value (when D/S = 1) or the same value (when D/S = 0).
Once match found, pointer Pr will point to the bit number in the matrix
met the search condition. The found objective flag "FND" will be set
L Mapr : Mbpr
to 1. When it has searched to the final pair of bits in the matrix
(Ma16L-1, Mb16L-1), this execution of the instruction will finish, no matter
it has found or not. If this happen then The compare-to-end flag
"END" will be set as 1, and the Pr value will set to 16L-1 and the next
time that this instruction is executed, Pr will automatically return to
the starting point of the matrix (Pr = 0) to begin the comparison
search.
z The range for the pointer value is 0 to 16L-1. The Pr value should not be changed by other instructions, as this will
affect the result of search. If the Pr value exceeds its range, then the pointer error flag "ERR" will be set to 1, and
this instruction will not be carried out.
125P.MCMP
X0 z In the program at left, the "FHD" input is 0, so starting from a
EN Ma : R 0 FND
position 1 greater than the pointer value at that time (marked
Mb : R 10
by *), the instruction will do a search for bits with different
FHD L : 5 END status (because D/S = 1). When X0 has a transition from 0→
Pr : R 20 1 three times, the results are shown at right in the diagram
D/S ERR below.

Pr Pr FND END
4 R20
c R20 39 1 0
Ma15 Ma0 Mb15 Mb0
↓ Ma * ↓ ↓ Mb * ↓
R0 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 R10 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 Pr FND END
R1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R11 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 d R20 79 0 1
R2 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 R12 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
R3 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R13 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Pr FND END
R4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R14 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
↑ ↑ ↑ ↑ e R20 2 1 0
Ma79 Ma64 Mb79 Mb64

Before execution Execution result

7-124
Matrix Instructions

FUN126 P FUN126 P
MATRIX BIT READ
MBRD MBRD

Ms : Starting register of matrix

L : Matrix length
Pr : Pointer register
Ms may combine with V, Z, P0~P9 to serve
indirect address application

Range WX WY WM WS TMR CTR HR IR OR SR ROR DR K XR

WX0 WY0 WM0 WS0 T0 C0 R0 R3840 R3904 R3968 R5000 D0 2 V、Z
Ope- ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣
rand WX240 WY240 WM1896 WS984 T255 C199 R3839 R3903 R3967 R4167 R8071 D4095 256 P0~P9
Ms ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
L ○ ○* ○ ○
Pr ○ ○ ○ ○ ○ ○ ○ ○* ○* ○

Pr
z When readout control "EN" = 1 or has a transition from 0 to 1
( P instruction), the status of the bit Mspr pointed by pointer Pr Ms
within matrix Ms will be read out and appear at the output bit
"OTB". Before the readout, this instruction will first check the Mspr
input -pointer clear "CLR". If "CLR" is 1, then the Pr value will be
OTB
cleared to 0 first before the readout action is carried out. After
the readout is completed, If the Pr value has already reached
16L-1 (the final bit), then the read-to-end flag "END" will be set
L
to 1. If Pr is less than 16L-1, then the status of pointer increment
"INC" will be checked. If "INC" is 1, then Pr will be increased by
1. Besides this, pointer clear "CLR" can execute independently,
and is not affected by other input.

z The effective range of the pointer is 0 to 16L-1. Beyond this range the pointer error flag "ERR" will be set to 1,
and this instruction will not be carried out.

126P.MBRD z In the program at left, INC = 1, so every time there is

X0
EN Ms : R 0 OTB one readout the pointer will be increased by 1. With this
L : 5
way each bit in Ms may be read out successively, as
shown at left in the diagram below. When X0 goes 3
INC Pr : R 20 END
times from 0→1, the results are shown at right in the
diagram below .
CLR ERR

Pr Pr OTB END
Ms15 Ms0
↓ Ms ↓ R20 77 c R20 78 1 0
R0 0 0 0 0 0 1 1 1 1 1 0 0 0 0 0 1
R1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 OTB Pr OTB END
R2 0 0 0 1 1 1 0 0 0 1 1 1 0 0 0 1 0
R3 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 d R20 79 0 0
R4 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
↑ ↑ ↑ Pr OTB END
Ms79 Ms77 Ms64
e R20 79 1 1

Before execution Execution result

7-125
 Matrix Instructions

FUN127 P FUN127 P
MATRIX BIT WRITE
MBWR MBWR

Md : Starting register of matrix

L : Matrix length

Pr : Pointer register

Md may combine with V, Z, P0~P9 to serve

indirect address application

Range WY WM WS TMR CTR HR OR SR ROR DR K XR

WY0 WM0 WS0 T0 C0 R0 R3904 R3968 R5000 D0 2 V、Z
Ope- ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣
rand WY240 WM1896 WS984 T255 C255 R3839 R3967 R4167 R8071 D4095 256 P0~P9
Md ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
L ○ ○* ○ ○
Pr ○ ○ ○ ○ ○ ○ ○ ○* ○* ○

Pr
z When write control "EN" = 1 or has a transition from 0 to 1 ( P
instruction), the status of the write-in bit "INB" will be written into Ms
the bit Mdpr pointed by pointer Pr within matrix Md. Before the Mspr
write-in takes place, the status of pointer clear "CLR" will be
checked. If "CLR" is 1, then Pr will be cleared to 0 before the OTB
write-in action. After the write-in action has been completed, the
Pr value will be checked again. If the Pr value has already L
reached 16L-1 (last bit), then the write-to-end flag will be set to
1. If the Pr value is less than 16L-1 and "INC" is 1, then the
pointer will increased by 1. Besides this, pointer clear "CLR" can
execute independently, and is not affected by other input.

z The effective range of Pr is 0 to 16L-1. Beyond this range, the pointer error flag "ERR" will be set to 1, and
this instruction will not be carried out.

127P.MBWR z In the program at left, pointer will be increased each time

X0
EN Md : R 0 END execution (because "INC" is 1). As shown in the diagram
X1 L : 5
below, when X0 has a transition from 0→1, the status of
INB ERR INB (X1) will be written into the Mdpr (Md78) position, and
Pr : R 20
pointer Pr will increased by 1 (changing to 79). In this
INC case, although Pr is pointing to the end, it has not yet
been written into Md79, so "END" flag is still 0. Only the
CLR
next attempt to write to Md79 will set “END” to 1.

X1 Pr Pr END
1 R20 78 R20 79 0
Md15 Md0 Md15 Md0
↓ Md ↓ ↓ Md ↓
R0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 X0= R0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R1
R2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0 Ö R1
R2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R4 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0
↑ ↑ ↑ ↑
Md79 Md64 Md79 Md64

Before execution After execution

7-126
Matrix Instructions

FUN128 P FUN128 P
MATRIX BIT SHIFT
MBSHF MBSHF

Ms : Starting register of source matrix

Md : Starting register of destination
matrix
L : Length of matrix (Ms and Md)
Ms, Md may combine with V, Z, P0~P9
to serve indirect address application

Range WX WY WM WS TMR CTR HR IR OR SR ROR DR K XR

WX0 WY0 WM0 WS0 T0 C0 R0 R3840 R3904 R3968 R5000 D0 2 V、Z
Ope- ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣
rand WX240 WY240 WM1896 WS984 T255 C255 R3839 R3903 R3967 R4167 R8071 D4095 256 P0~P9
Ms ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
Md ○ ○ ○ ○ ○ ○ ○ ○* ○* ○ ○
L ○* ○ ○

INB
z When shift control "EN" = 1 or has a transition from 0 to 1 Ms Md
( P instruction), source matrix Ms will be retrieved and
completely shifted one position to the left (when L/R = 1) or
one position to the right (when L/R = 0). The space caused
by the shift (with a left shift it will be M0, and with a right
shift it will be M16L-1), is replaced by the status of fill-in bit L
"INB". The status of the bits popped out (with a left shift it
will be M16L-1, and with a right shift it will be M0) will appear Shift
at the output bit "OTB". Then the results of this shifted left
OTB 1 bit
matrix will be filled into the destination matrix Md.

z The program at left is an example where Ms and Md are

the same matrix. When X0 goes from 0→1, Ms will be OTB
Ms Md
completely retrieved and moved to the left (because L/R =
1) by 1 bit. It will then be stored back to Md, and the results
are shown at right in the diagram below.

128P.MBSHF
X0
EN Ms : R 0 OTB L
X0 Md : R 0
INB
Shift
L : 5
right
INB 1 bit
L/R

Ms15 Ms0 Md15 Md0

↓ Ms ↓ ↓ Md ↓
R0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
R1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 X0= R1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0

Ö
R2 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 R2 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1
R3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
R4 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0
↑ ↑ ↑ ↑
Ms79 Ms64 Md79 Md64

Before execution After execution

7-127
 Matrix Instructions

FUN129 P FUN129 P
MATRIX BIT ROTATE
MBROT MBROT

Ms : Starting register of source matrix

Md : Starting register of destination matrix
L : Length of matrix (Ms and Md)
Ms, Md may combine with V, Z, P0~P9 to
serve indirect address application

Range WX WY WM WS TMR CTR HR IR OR SR ROR DR K XR

WX0 WY0 WM0 WS0 T0 C0 R0 R3840 R3904 R3968 R5000 D0 2 V、Z
Ope- ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣
rand WX240 WY240 WM1896 WS984 T255 C255 R3839 R3903 R3967 R4167 R8071 D4095 256 P0~P9
Ms ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
Md ○ ○ ○ ○ ○ ○ ○ ○* ○* ○ ○
L ○* ○ ○

L/R=1
z When rotate control "EN" = 1 or has a transition from 0 Ms Md
to 1 (P instruction), matrix Ms will be completely
retrieved and rotated by one bit towards the left (when
L/R = 1) or to the right (when L/R = 0). The space
created by the rotation (with a left rotation it will be M0,
and with a right rotation it will be M16L-1) will be L
replaced by the status of the rotated-out bit (with a left
Rotate
rotation it will be M16L-1, and with a right rotation it will left
be M0). The rotated-out bit will not only be used to fill OTB 1 bit
the above-mentioned space, it will also be transferred
to rotated-out bit "OTB".

129P.MBROT L/R=0 OTB

X0 Ms Md
EN Ms : R 0 OTB
Md : R 0
L/R L : 5

L
z In the program at left, Ms and Md are the same Shift
matrix. When X0 goes from 0→1, then the whole of Ms right
is retrieved and rotated right (because L/R = 0) by 1 1 bit
bit. It is then stored back into Ms itself (because in this
example Ms and Md are the same matrix). The results
are shown at right in the diagram below.

Ms15 Ms0 Md15 Md0

↓ Ms ↓ ↓ Md ↓
R0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 X0= R1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
OTB
Ö
R2 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 R2 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0
R3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R3 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R4 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
↑ ↑ ↑ ↑
Ms79 Ms64 Md79 Md64

Before execution After execution

7-128
Matrix Instructions

FUN130 P FUN130 P
MATRIX BIT STATUS COUNT
MBCNT MBCNT

Ms : Starting register of matrix

L : Matrix length
D : Register storing count results
Ms may combine with V, Z, P0~P9 to serve
indirect address application

Range WX WY WM WS TMR CTR HR IR OR SR ROR DR K XR

WX0 WY0 WM0 WS0 T0 C0 R0 R3840 R3904 R3968 R5000 D0 2 V、Z
Ope- ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣
rand WX240 WY240 WM1896 WS984 T255 C255 R3839 R3903 R3967 R4167 R8071 D4095 256 P0~P9
Ms ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
L ○ ○* ○ ○
D ○ ○ ○ ○ ○ ○ ○ ○* ○* ○

z When count control "EN" = 1 or has a transition from 0 to 1( P instruction), then among the 16L bits of the
Ms matrix, this instruction will count the total amount of bits with a status of 1 (when input "1/0" = 1) or the
total amount of bits with a status of 0 (when input "1/0" = 0). The results of the counting will be stored into
the register specified by D. If the value of these amounts is 0, then the Result-is-0 flag "D = 0" will be set to
1.

130P.MBCNT z The program at left sets X1 first as 0 (to count bits with
X0
EN Ms : R 0 D=0 status of 0) and then as 1 (to count bits with status of 1)
L : 5 and let the signal X0 has a transition from 0→1 for both
X1
1/0 D : R 0 case, the execution results are shown at right in the
diagram below .

Ms15
Ms
Ms0
D
d D
↓ ↓
R0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0
R1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 X0= R20 64 R20 16
R2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 c
R3
R4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Ö X1=0 X1=1
↑ ↑
Ms79 Ms64

Source matrix Count of ‘0’ bit Count of ‘1’ bit

7-129
 I/O Instructions II

FUN 139 FUN 139

HIGH SPEED PULSE WIDTH MODULATION OUTPUT
H S PWM H S PWM

PW : PWM output ( 0 = Y0、1 = Y2、2 = Y4、3 = Y6 )

Op : Output polarity ; 0 = Normal

1 = Inverse of output
RS : Resolution ; 0 = 1/100 (1%)
1 = 1/1000 (0.1%)
Pn : Setting of output frequency( 0~255 )
OR : Setting register of output pulse width ( 0~100 or
0~1000)
WR : Working register

Y WX WY WM WS TMR CTR HR IR OR SR ROR DR K

Range
Yn of WX0 WY0 WM0 WS0 T0 C0 R0 R3840 R3904 R3968 R5000 D0
main ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣
Operand
unit WX240 WY240 WM1896 WS984 T255 C255 R3839 R3903 R3967 R4167 R8071 D4095
Pw ○ 0～3
Op 0～1
Rs 0～1
Pn ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ 0～255
OR ○ ○ ○ 0～1000
WR ○ ○ ○ ○ ○ ○ ○ ○ ○ ○

Description

z The setting of resolution(RS) must be same between output0(Y0) and output1(Y2) also the setting of output
frequency(Pn). It means both output0 and output1 have the same output frequency and the same output
resolution, only the pulse width can be different. Same principle for output2(Y4) and output3(Y6).

z When operation control “EN” = 1, the specified digital output will perform the PWM output, the expression for
output frequency as shown bellow:

184320
1. f pwm = while Rs(Resolution)=1/100
(Pn + 1)

18432
2. fpwm = while Rs(Resolution)=1/1000
(Pn + 1)

Example 1 : If Pn ( Setting of output frequency ) = 50, Rs = 0( 1/100 ), then

184320
f pwm = =3614.117‧‧‧≒3.6KHz
( 50 + 1)

1
T(Period)= ≒277uS
fpwm

For Rs = 1/100, if OR( Setting of output pulse width ) = 1, then T0 ≒ 2.7uS; if OR( Setting of output pulse width )
= 50, then To ≒ 140uS.

.Output waveform :

(1).Pn ( Output frequency ) = 50, Rs = 0 ( 1/100 ), OR ( Output pulse width ) = 1 :

7-130
I/O Instructions II

FUN 139 FUN 139

HIGH SPEED PULSE WIDTH MODULATION OUTPUT
H S PWM H S PWM

To ≒ 2.7usec

Tp ≒ 277usec

(2).Pn ( Output frequency ) = 50, Rs = 0 ( 1/100 ), OR ( Output pulse width ) = 50 :

Example 2 : If Pn ( Setting of output frequency ) = 200, Rs = 1( 1/1000 ), then

18432
f pwm = ≒91.7Hz
( 200 + 1)

1
T(Period)= ≒10.9mS
fpwm

For Rs = 1/1000, if OR( Setting of output pulse width ) = 10, then T0 ≒ 109uS; if OR( Setting of output pulse
width ) = 800, then To ≒ 8.72mS
.Output waveform :

(1).Pn ( Output frequency ) = 200, Rs = 1 ( 1/1000 ), OR ( Output pulse width ) = 10 :

(2).Pn ( Output frequency ) = 200, Rs = 1 ( 1/1000 ), OR ( Output pulse width ) = 800 :

7-131
 NC Positioning Instructions I

FUN140 HIGH SPEED PULSE OUTPUT INSTRUCTION FUN140

HSPSO (Brief description on function) HSPSO

Ps : The Pulse Output (0～3) selection

0:Y0 & Y1
1:Y2 & Y3
2:Y4 & Y5
3:Y6 & Y7
SR : Positioning program starting register.
WR : Starting working register of instruction operation,
total 7 registers, can not used in any other part of
program.

Range HR DR ROR K
R0 D0 R5000 2
Ope- ∣ ∣ ∣ ∣
rand R3839 D4095 R8071 256
Ps 0～3
SR ○ ○ ○
WR ○ ○ ○*

Command descriptions
z The NC positioning program of HSPSO (FUN140) instruction is a program written and edited with text. The
executing unit of program is divided by step (which includes output frequency, traveling distance, and
transferring conditions). For one FUN140 instruction, can program 250 steps of positioning points at the most.
Each step of positioning program requires 9 registers. For detailed application, please refer to chapter 13 “the
NC positioning control of FBs-PLC”.
z The benefits of storing the positioning program in the register is that, while in application which use the MMI
(man machine interface) as the operation console can save the positioning programs to MMI. Whenever the
change of the positioning programs is requested, the download of positioning program can be simply done by
a series of write register commands.
z The NC positioning of this instruction doesn’t provide the linear interpolation function.
z When execution control “EN”=1, if Ps0～3 is not controlled by other FUN140 instruction (the status of
Ps0=M1992, Ps1=M1993, Ps2=M1994, and Ps3=M1995 is ON respectively), it will start to execute from the
next step of positioning point (when goes to the last step, it will be restarted from the first step); if Ps0～3 is
controlled by other FUN140 instruction (the status of Ps0=M1992, Ps1=M1993, Ps2=M1994, and
Ps3=M1995 are OFF), this instruction will wait and acquires the control right of output point immediately right
after other FUN140 release the output.
z When execution control input “EN” =0, it stops the pulse output immediately.
z When output pause “PAU” =1 and execution control was 1, it will pause the pulse output. When output
pause “PAU” =0 and execution control is still 1, it will continue the unfinished pulse output.
z When output abort “ABT”=1, it will halt and stop pulse output immediately. (When the execution control
input “EN” becomes 1 next time, it will restart from the first step of positioning point to execute.)
z While send the output pulse, the output indication “ACT” is ON.
z When there is an execution error, the output indication “ERR” will be ON. (The error code is stored in the
error code register.)
z When the execution of each step of positioning program is completed, the output indication “DN” will be ON.
*** The working mode of Pulse Output must be configured (without setting, Y0～Y7 will be treated as normal
output) to any one of following modes, before the HSPSO instruction can be worked.

U/D Mode: Y0 (Y2, Y4, Y6), as up pulse.

Y1 (Y3, Y5, Y7), as down pulse.
K/R Mode: Y0 (Y2, Y4, Y6), as the pulse out..
Y1 (Y3, Y5, Y7), as the direction.
A/B Mode: Y0 (Y2, Y4, Y6), as A phase pulse.
Y1 (Y3, Y5, Y7), as B phase pulse.
hThe output polarity for Pulse Output can select to be Normally ON or Normally OFF.
hThe working mode of Pulse Output can be configured by WINPROLADDER in “Output Setup” setting page.

7-132
NC Positioning Instructions I

FUN141 NC POSITIONING PARAMETER VALUE SETTING FUN141

MPARA (Brief description on function) MPARA

Ps : The pulse output (0～3) selection

SR : Starting register for parameter table; it has 18

parameters totally, and occupy 24 registers.

Range HR DR ROR K
R0 D0 R5000 2
Ope- ∣ ∣ ∣ ∣
rand R3839 D4095 R8071 256
Ps 0～3
SR ○ ○ ○

Operation descriptions

hIt is not necessary to use this instruction. if the system default for parameter values is matching what user
demanded, then this instruction is not needed. However, if it needs to change the parameter value
dynamically, this instruction is required.

hThis instruction incorporates with FUN140 or FUN147 for positioning control purpose.

hWhether the execution control input “EN” = 0 or 1, this instruction will be performed.

hWhen there are any errors in parameter value, the output indication “ERR” will be ON. (The error code is
stored in the error code register.)

hFor detailed functional description and usage, please refer to Chapter 11 “The NC positioning control of
FBs-PLC” for explanation.

7-133
 NC Positioning Instructions I

FUN142 P STOP THE HSPSO PULSE OUTPUT FUN142 P

PSOFF (Brief description on function) PSOFF

Ps : 0～3
Enforce the Pulse Output PSOn (n= Ps) to stop.

Command descriptions

z When execution control “EN” =1 or changes from 0→1( P instruction), this instruction will enforce the
assigned number set of HSPSO (High Speed Pulse Output) to stop pulse output.

z While in the application for mechanical original point reset, as soon as reach the original point can use this
instruction to stop the pulse output immediately, so as to make the original point stop at the same position
every time when performing mechanical original point resetting.

z For detailed functional description and usage, please refer to Chapter 11 “The NC positioning control of
FBs-PLC” for explanation.

7-134
NC Positioning Instructions I

FUN143 P CONVERT THE CURRENT PULSE VALUE TO DISPLAY VALUE FUN143 P

PSCNV (mm, Deg, Inch, PS) (Brief description on function) PSCNV

Ps : 0～3; it converts the number of the pulse position to be

the mm (Deg, Inch, PS) that has same unit as the set
value, so as to make current position displayed.

D : Register that stores the current position after

conversion. It uses 2 registers, e.g. if D = D10, which
means D10 is Low Word and D11 is High Word.

Range HR DR ROR K
R0 D0 R5000 2
Ope- ∣ ∣ ∣ ∣
rand R3839 D4095 R8071 256
Ps 0 ～3
D ○ ○ ○

Command descriptions

z When execution control “En” =1 or changes from 0→1( P instruction), this instruction will convert the
assigned current pulse position (PS) to be the mm (or Deg, Inch, or PS) that has same unit as the set value,
so as to make current position displaying.

z Only when the FUN140 instruction is executed, then it can get the correct conversion value by executing
this instruction.

z For detailed functional description and usage, please refer to Chapter 11 “The NC positioning control of
FBs-PLC” for explanation.

7-135
 Enable/Disable Instructions

FUN145 P FUN145 P
ENABLE CONTROL OF THE INTERRUPT AND PERIPHERAL
EN EN

LBL : External input or peripheral label name that to be

enabled.

z When enable control “EN” =1 or changes from 0→1 ( P instruction), it allows the external input or peripheral
interrupt action which is assigned by LBL.
z The enabled interrupt label name is as follows:(Please refer the section 9.3 for details)

LBL name Description LBL name Description LBL name Description

HSTA High speed X4 positive edge X10 positive edge
HSTAI X4+I X10+I
counter interrupt interrupt interrupt
HSC0 High speed X5 negative edge X10 negative edge
HSC0I X4−I X10−I
counter interrupt interrupt interrupt
HSC1 High speed X5 positive edge X11 positive edge
HSC1I X5+I X11+I
counter interrupt interrupt interrupt
HSC2 High speed X5 negative edge X11 negative edge
HSC2I X5−I X11−I
counter interrupt interrupt interrupt
HSC3 High speed X6 positive edge X12 positive edge
HSC3I X6+I X12+I
counter interrupt interrupt interrupt
X0 positive edge X6 negative edge X12 negative edge
X0+I X6−I X12−I
interrupt interrupt interrupt
X0 negative edge X7 positive edge X13 positive edge
X0−I X7+I X13+I
interrupt interrupt interrupt
X1 positive edge X7 negative edge X13 negative edge
X1+I X7−I X13−I
interrupt interrupt interrupt
X1 negative edge X8 positive edge X14 positive edge
X1−I X8+I X14+I
interrupt interrupt interrupt
X2 positive edge X8 negative edge X14 negative edge
X2+I X8−I X14−I
interrupt interrupt interrupt
X2 negative edge X9 positive edge X15 positive edge
X2−I X9+I X15+I
interrupt interrupt interrupt
X3 positive edge X9 negative edge X15 negative edge
X3+I X9−I X15−I
interrupt interrupt interrupt
X3 negative edge
X3−I
interrupt

z In practical application, some interrupt signals should not be allowed to work at sometimes, however, it should
be allowed to work at some other times. Employing FUN146 (DIS) and FUN145 (EN) instructions could
attain the above mentioned demand.

Program example

M0 145P. z When M0 changes from 0→1, it allows X0 to send

EN EN X0+I interrupt when X0 changes from 0→1. CPU can rapidly
process the interrupt service program of X0+I.

7-136
Enable/Disable Instructions

FUN146 P FUN146 P
DISABLE CONTROL OF THE INTERRUPT AND PERIPHERAL
DIS DIS

LBL : Interrupt label intended to disable or peripheral name to

be disabled.

z When prohibit control “EN” =1 or changes from 0→1 ( P instruction), it disable the interrupt or peripheral
operation designated by LBL.

z The interrupt label name is as follows:

LBL name Description LBL name Description LBL name Description

HSTA High speed X4 positive edge X10 positive edge
HSTAI X4+I X10+I
counter interrupt interrupt interrupt
HSC0 High speed X5 negative edge X10 negative edge
HSC0I X4−I X10−I
counter interrupt interrupt interrupt
HSC1 High speed X5 positive edge X11 positive edge
HSC1I X5+I X11+I
counter interrupt interrupt interrupt
HSC2 High speed X5 negative edge X11 negative edge
HSC2I X5−I X11−I
counter interrupt interrupt interrupt
HSC3 High speed X6 positive edge X12 positive edge
HSC3I X6+I X12+I
counter interrupt interrupt interrupt
X0 positive edge X6 negative edge X12 negative edge
X0+I X6−I X12−I
interrupt interrupt interrupt
X0 negative edge X7 positive edge X13 positive edge
X0−I X7+I X13+I
interrupt interrupt interrupt
X1 positive edge X7 negative edge X13 negative edge
X1+I X7−I X13−I
interrupt interrupt interrupt
X1 negative edge X8 positive edge X14 positive edge
X1−I X8+I X14+I
interrupt interrupt interrupt
X2 positive edge X8 negative edge X14 negative edge
X2+I X8−I X14−I
interrupt interrupt interrupt
X2 negative edge X9 positive edge X15 positive edge
X2−I X9+I X15+I
interrupt interrupt interrupt
X3 positive edge X9 negative edge X15 negative edge
X3+I X9−I X15−I
interrupt interrupt interrupt
X3 negative edge
X3−I
interrupt

z In practical application, some interrupt signals should not be allowed to work at certain situation. To achieve
this, this instruction may be used to disable the interrupt signal.

Program example

M0 146P. z When M0 changes from 0→1, it prohibits X2 from

EN DIS X2+I
sending interrupt when X2 changes from 0→1.

7-137
 NC Positioning Instructions II

FUN 147 FUN 147

Multi-Axis High Speed Pulse Output
MHSPO MHSPO

Gp : Group number (0～1)

SR : Starting register for positioning program

(example explanation)

WR : Starting register for instruction operation (example

explanation). It controls 9 registers, which the other
program cannot repeat in using.

Range HR DR ROR K
R0 D0 R5000
Ope- ∣ ∣ ∣
rand R3839 D3999 R8071
Gp 0～1
SR ○ ○ ○
WR ○ ○ ○*

Instruction Explanation

1. The FUN147 (MHSPO) instruction is used to support the linear interpolation for multi-axis motion control, it
consists of the motion program written and edited with text programming. We named every position point as
a step (which includes output frequency, traveling distance, and transfer conditions). Every step of positioning
point owns 15 registers for coding.

2. The FUN147 (MHSPO) instruction can support up to 4 axes for simultaneous linear interpolation; or 2 sets of 2-axis
linear interpolation (i.e. Gp0 = Axes Ps0 & Ps1 ; Gp1 = Axes Ps2 & Ps3)

3. The best benefit to store the positioning program into the registers is that in the case of association with MMI
(Man Machine Interface) to operate settings, it may save and reload the positioning program via MMI when
replacing the molds.

4. When execution control “EN”=1, if the other FUN147/FUN140 instructions to control Ps0～3 are not active
(corresponding status of Ps0=M1992, Ps1=M1993, Ps2=M1994, and Ps3=M1995 will be ON), it will start to
execute from the next step of positioning point (when goes to the last step, it will be restarted from the first
step to perform); if Ps0～3 is controlled by other FUN147/FUN140 instruction (corresponding status of
Ps0=M1992, Ps1=M1993, Ps2=M1994, and Ps3=M1995 would be OFF), this instruction will acquire the pulse
output right of positioning control once the controlling FUN147/FUN140 has released the control right.

5. When execution control input “EN” =0, it stops the pulse output immediately.

6. When output pause “PAU” =1 and execution control “EN” was 1 beforehand, it will pause the pulse output.
When output pause “PAU” =0 and execution control is still 1, it will continue the unfinished pulse output.

7. When output abort “ABT”=1, it stops pulse output immediately. (When the execution control input “EN”
becomes 1 next time, it will restart from the first step of positioning point to execute.)

8. While the pulse is in output transmitting, the output indication “ACT” is ON.

9. When there is execution error, the output indication “ERR” will be ON.
(The error code is stored in the error code register.)

10. When each step of positioning point is complete, the output indication “DN” will be ON.

11. Please refer to Chapter 11 “The NC Positioning Control of FBs-PLC” for further details.

7-138
NC Positioning Instructions II

FUN148 FUN148
MANUAL PULSE GENERATOR FOR POSITIONING
MPG MPG

148. MPG
：Source of high speed counter; 0~7
Sc
Execution EN Sc : ACT ：Axis of pulse output; 0~3
Ps
Ps : ：Setting of output speed (2 registers)
Fo
：Setting of multiplier (2 registers)
Mr
Fo :
Mr+0：Multiplicand (Fa)
Mr : Mr+1：Dividend (Fb)
WR：Starting address of working registers, it needs
WR :
4 registers
＊This instruction can be supported in PLC OS
firmware V4.60 or late

HR ROR DR K
Range

R0 R5000 D0
Operand

∣ ∣ ∣ 16 bit
R3839 R8071 D3999
Sc ○ ○ ○ 0~7
Ps ○ ○ ○ 0~3
Fo ○ ○ ○
Mr ○ ○ ○
WR ○ ○* ○

● Let this instruction be executed in 50mS fixed time interrupt service routine (50MSI)、or by using
the 0.1mS high speed timer to generate 50mS fixed time interrupt service to have accurate repeat
time to sample the pulse input from manual pulse generator. If it comes the input pulses, it will
calculate the number of pulses needing to output according to the setting of multiplier (Mr+0 and
Mr+1), and then outputs the pulse stream in the speed of setting (Fo) during this time interval.
The setting of output speed (Fo) must be fast enough, and the acceleration / deceleration rate
( Parameter 4 and parameter 8 of FUN141 instruction) must be sharp to guarantee it can complete
the sending of pulse stream during the time interval if it is under high multiplier (100 or 200 times)
situation.
● When execution 〝EN〞=1, this instruction will sample the pulse input from manual pulse generator
by reading the current value of assigned high speed counter every time interval; it doesn’t have
any output if it doesn’t have any input pulse; but If it senses the input pulses, it will calculate the
number of pulses needing to output according to the setting of multiplier (Mr+0 and Mr+1), and
then outputs the pulse stream in the speed of setting (Fo) during this time interval.
Number of output pulses = (Number of input pulses × Fa) / Fb
● This instruction also under the control of hardware resource management; it wouldn’t be executed
if the hardware is occupied.
● The output indicator ACT=1 if it outputs the pulses; otherwise ACT=0.
● Please refer to Chapter 11 “The NC Positioning Control of FBs-PLC” for further details.

50mS 50mS

． Sample pulse input … ． Sample pulse input

． Output pulse stream ． Output pulse stream
in the speed of Fo in the speed of Fo

7-139
 Communication Instructions

FUN150 MODBUS MASTER INSTRUCTION FUN150

M-BUS （WHICH MAKES PLC AS THE MODBUS MASTER THROUGH PORT 1~4） M-BUS

Pt ：1~4, specify the communication port being acted

as the Modbus master

SR：Starting register of communication program

WR :Starting register for instruction operation. It controls 8

registers, the other programs can not repeat in using.

Range HR ROR DR K
R0 R5000 D0
Ope- ∣ ∣ ∣
rand R3839 R8071 D4095
Pt 1～4
SR ○ ○ ○
WR ○ ○* ○

Description

1. FUN150 (M-BUS) instruction makes PLC act as Modbus master through Port 1～4, thus it is very easy to
communicate with the intelligent peripheral with Modbus RTU/ASCII protocol.
2. The master PLC may connect with 247 slave stations through the RS-485 interface.
3. Only the master PLC needs to use Modbus RTU/ASCII instruction.
4. It employs the program coding method or table filling method to plan for the data flow controls; i.e. from which
one of the slave station to get which type of data and save them to the master PLC, or from the master PLC
to write which type of data to the assigned slave station. It needs only seven registries to make definition;
every seven registers define one packet of data transaction.
5. When execution control 〝EN〞changes from 0→1 and both inputs Pause “PAU” and Abort “ABT” are 0, and if
Port 1/2/3/4 hasn’t been controlled by other communication instructions [i.e. M1960 (Port1) / M1962 (Port2) /
M1936 (Port3) / M1938 (Port4) = 1], this instruction will control the Port 1/2/3/4 immediately and set the
M1960/M1962/M1936/M1938 to be 0 (which means it is being occupied), then going on a packet of data
transaction immediately. If Port 1/2/3/4 has been controlled (M1960/M1962/M1936/M1938 = 0), then this
instruction will enter into the standby status until the controlling communication instruction completes its
transaction or pause/abort its operation to release the control right (M1960/M1962/M1936/M1938 =1), and
then this instruction will become enactive, set M1960/M1962/M1936/M1938 to be 0, and going on the data
transaction immediately.
6. While in transaction processing, if operation control “ABT” becomes 1, this instruction will abort this
transaction immediately and release the control right (M1960/M1962/M1936/M1938 = 1). Next time, when this
instruction takes over the transmission right again, it will restart from the first packet of data transaction.
7. While〝A/R〞=0，Modbus RTU protocol；〝A/R〞=1，Modbus ASCII protocol。
8. While it is in the data transaction, the output indication “ACT” will be ON.
9. If there is error occurred when it finishes a packet of data transaction, the output indication “DN” & “ERR” will
be ON.
10. If there is no error occurred when it finishes a packet of data transaction, the output indication “DN” will be
ON.

7-140
Communication Instructions

COMMUNICATION LINK INSTRUCTION

FUN 151 FUN 151
(WHICH MAKES PLC ACT AS THE MASTER STATION IN CPU LINK NETWORK
CLINK CLINK
THROUGH PORT 1~4)

Pt : Assign the port, 1～4

MD : Communication mode, MD0~MD3
SR : Starting register of communication table
(see example for its explanation)
WR : Starting register for instruction operation (see
example for its explanation). It controls 8 registers,
the other programs can not repeat in using.

Range HR ROR DR K
R0 R5000 D0
Ope- ∣ ∣ ∣
rand R3839 R8071 D4095
Pt 1～4
MD 0～3
SR ○ ○ ○
WR ○ ○* ○

Description

● This instruction provides 4 instruction modes MD0～MD3. Of which, three instruction modes MD0～MD2, are
“regular link network”, and the MD3 is the “high speed link network”. The following are the function description of
respective modes.
hMD0 : Master station mode for FATEK CPU LINK.
For any PLC, whose ladder program contains the FUN151:MD0 instruction, will become master
station of FATEK CPU LINK network. The master station PLC will base on the communication
program stored in data registers in which the target station, data type, data length, etc, were
specified to read or write slave station via “FATEK FB-PLC Communication Protocol” command.
With this approach up to 254 PLC stations can share the data each other
hMD1 : Active ASCII data transmission mode.
With this mode, the FUN151 instruction will parse the communication program stored in data
registers and base on the parsing result send the data from port2 to ASCII peripherals (such as
computer, other brand PLC, inverter, moving sign, etc, this kind of device can command by ASCII
message). The operation can set to be (1) transmit only, which ignores the response from
peripherals, (2) transmit and then to receive the response from peripherals. When operate with
mode (2) then the user must base on the communication protocol of peripheral to parsing and
prepare the response message by writing the ladder instructions.
hMD2 : Passive ASCII data receiving mode.
With this mode, the FUN151 will first wait to receive ASCII messages sent by external ASCII
peripherals (such as computer, other brand PLC, card reader, bar code reader, electronic weight,
etc. this kind of device can send ASCII message). Upon receiving the message, the user can base
on the communication protocol of peripheral to parsing and react accordingly. The operation can
set to (1) receive only without responding, or (2) receive then responding. For operation mode (2)
the user can use the table driver method to write a communication program and after received a
message this instruction can base on this communication program automatically reply the
message to peripheral.
hMD3 : Master station mode of FATEK high speed CPU LINK.
The most distinguished difference between this mode and MD0 is that the communication
response of MD3 is much faster than MD0. With The introduction of MD3 mode CPU LINK, The
FATEK PLC can easily to implement the application of distributed control and real time data
monitoring.

7-141
 Data Movement Instructions II

FUN160 D P FUN160 D P
READ/WRITE FILE REGISTER
RWFR RWFR

Ladder symbol Sa: Starting address of data register

160DP.RWFR
Sb: Starting address of file register
Operation control EN Sa : ERR Range Error

Sb : Pr : Record pointer register

Read/Write R/W Pr : L : Quantity of register to form a record, 1~511
L : Sa operand can combine V、Z、P0~P9 for index
Increment INC addressing.

Range WX WY WM WS TMR CTR HR IR OR SR ROR DR K XR FR

WX0 WY0 WM0 WS0 T0 C0 R0 R3840 R3904 R3968 R5000 D0 V、Z F0
Ope- ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣
rand WX240 WY240 WM1896 WS984 T255 C255 R3839 R3903 R3967 R4167 R8071 D4095 P0～P9 F8191
Sa ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
Sb ○
Pr ○ ○ ○ ○ ○ ○ ○ ○* ○* ○
L ○ ○* ○ 1~511

Description

● When operation control "EN"=1 or changes from 0→1( P instruction), it will perform the read ("R/W"=1) or
write ("R/W"=0) file register operation. While reading, the content of data registers starting from Sa will be
overwritten by the content of file registers addressed by the base file register Sb and record pointer Pr; while
writing, the content of file registers addressed by the base file register Sb and record pointer Pr will be
overwritten by the content of data registers starting from Sa; L is the operation quantity or record size. The
access of file register adopts the concept of RECORD data structure to implement. For example, Sa=R0,
Sb=F0, L=10, the read/write details shown as below

Sb
F0 ~ F9
(L=10) Pr = 0
F10 ~ F19
Sa (L=10) Pr = 1
R0 ~ R9 F20 ~ F29
(L=10) (L=10)
Pr = 2
F30 ~ F39
(L=10) Pr = 3

7-142
Data Movement Instructions II

FUN160 D P FUN160 D P
READ/WRITE FILE REGISTER
RW F R RW F R

● For ladder program application, only this instruction can access the file registers.

● The record pointer will be increased by 1 after execution while pointer control input "INC"=1.

● This instruction will not be executed and error indicator ”ERR" will be 1 while incorrect record size (L=0 or >
511) or the operation out of the file register's range (F0～F8191).

160P.RWFR M10 When M0 changes from 0Æ1, if D0 =2, the contents

M0
EN Sa : R0 ERR of file registers F200~F249 will be overwritten by the
Sb : F100 content of data registers R0~R49. the record length is
R/W Pr : D0 50.
L : 50 .Pointer will be increased by 1 after operation.
INC

160P.RWFR M10 .When M0 changes from 0Æ1, if D0 = 1, the content

M0
EN Sa : R0 ERR of data registers R0~R49 will be overwritten by the file
Sb : F100 registers F150~F199.
R/W Pr : D0 .The record pointer will be increased by 1 after
L : 50 operation.
INC

7-143
 Data Movement Instructions II

FUN161P Write Data Record into the MEMORY_PACK FUN161P

WR-MP （Write memory pack） WR-MP

S ：Starting address of the source data

BK：Block number of the MEMORY_PACK，0～1
Os：Offset of the block
Pr：Address of the pointer
L：Quantity of writing，1～128
WR：Starting address of working registers, it takes 2
registers
S may combine with V、Z、P0～P9 for indirect addressing
application

HR ROR DR K XR
Range

R0 R5000 D0
Operand

V、Z
∣ ∣ ∣
P0～P9
R3839 R8071 D4095
S ○ ○ ○ ○
BK 0～1
Os ○ ○ ○ 0～32510
Pr ○ ○* ○
L ○ ○* ○ 1～128
WR ○ ○* ○

● The main purpose of the MEMORY_PACK of FBs series's is used for long term storing of the user's ladder
program, except this, through the FUN161/FUN162 instructions, the MEMORY_PACK can be worked as the
portable MEMORY_PACK for machine working parameters's saving and loading.
When execution control〝EN〞changes from 0→1, it will perform the data writing, where S is the starting
address of the source data, BK is the block number of the MEMORY_PACK to store this writing, Os is the
offset of specified block, Pr is the pointer to point to corresponding data area, L is the quantity of this writing.
The access of MEMORY_PACK manipulation adopts the concept of RECORD data structure to implement
with. The working diagram as shown below :
MEMORY_PACK

● When input "INC" = 1, the content of the pointer will be increased by one after the execution of writing, it
points to next record.

7-144
Data Movement Instructions II

FUN161P Write Data Record into the MEMORY_PACK FUN161P

WR-MP （Write memory pack） WR-MP

● If the value of L is equal to 0 or greater than 128, or the pointed data area over the range, the output "ERR"
will be 1, it will not perform the writing operation.

● It needs couple of PLC solving scans for data writing and verification; during the execution, the output "ACT"
will be 1; when completing the execution and verification without the error, the output "DN" will be 1; when
completing the execution and verification with the error, the output "ERR" will be 1.
The MEMORY_PACK can be configured to store the user's ladder program or machine's working
parameters, or both. The ladder program can be stored into the block 0 only, but the machine's working
parameters can be stored into block 0 or 1; the memory capacity of each block has 32K Word in total.

Example program : Writing the record into block 1 of MEMORY_PACK with the different length

161P.WR_MP
M1 M100
EN S : R0 ACT
Bk : 1 M101
M2
INC Os : 0 ERR
Pr : D1 M102
DN
L : 20
WR: R2900

161P.WR_MP
M3 M103
EN S : R100 ACT
Bk : 1 M104
M4
INC Os : 10000 ERR
Pr : D2 M105
DN
L : 50
WR: R2910

MEMORY_PACK

Block 1

Head of Block 1
The RECORD starts from R0, Write Os = 0 The length is 20 Pr = 0
the length is 20(R0~R19) of RECORD 0
The length is 20
Pr = 1
of RECORD 1
•
•
•
•
•
The length is 20
Pr = 499
Os = 9999 of RECORD 499
The RECORD starts from R100, Write Os = 10000
The length is 50
the length is 50(R100~R149). Pr = 0
of RECORD 0

•
•
•
•
The length is 50 Pr = 449
Os = 32510 of RECORD 449

7-145
 Data Movement Instructions II

FUN162 P Read Data Record from the MEMORY_PACK FUN162 P

RD-MP （Read memory pack） RD-MP

BK：Block number of the MEMORY_PACK，0～1

Os：Offset of the block
Pr：Address of the pointer
L：Quantity of reading，1～128
D：Starting address to store the reading record

Range HR ROR DR K
R0 R5000 D0
Operand

∣ ∣ ∣
R3839 R8071 D3999
BK 0～1
Os ○ ○ ○ 0～32510
Pr ○ ○* ○
L ○ ○* ○ 1～128
D ○ ○* ○

● If the MEMORY_PACK of the FBs series's has stored the data record written by the FUN161 instruction,
they can be read out for machine's working through this instruction, it will reduce the tuning time for machine
operation.

● When execution control "EN" = 1 or from 0→1( P instruction), it will perform the data reading, where BK is
the block number of the MEMORY_PACK storing the record, Os is the offset of specified block, Pr is the
pointer to point to corresponding data area, L is the quantity of this record, and D is the starting address to
stor this reading of record. The access of MEMORY_PACK manipulation adopts the concept of RECORD
data structure to implement with.
The working diagram as shown below:
MEMORY_PACK

Block 0 Block 1

Head of Block 0 Head of Block 1

Os = 0 The length is L The length is L Pr = 0
of RECORD 0 of RECORD 0
The length is L The length is L
Pr = 1
The RECORD strats from D, of RECORD 1 of RECORD 1
Read
the length is L. The length is L The length is L
Pr = 2
of RECORD 2 of RECORD 2
• •
• •
• •
• •
Os = 32510 • • Pr = N

● When input "INC"=1, the content of the pointer will be increased by one after the execution of reading, it
points to next record.

7-146
Data Movement Instructions II

FUN162 P Read Data Record from the MEMORY_PACK FUN162 P

RD-MP （Read memory pack） RD-MP

● If the value of L is equal to 0 or greater than 128, or the pointed data area over the range, the output "ERR"
will be 1, it will not perform the reading operation.

● Output will be “ERR” if MEMORY_PACK is empty or data format not correct, and user used FUN162 to read
data from MEMORY_PACK.

Example program : Reading the record from block 1 of MEMORY_PACK with the different length

※ It is necessary that correct data in MEMORY_PACK or this example can’t execute correctly.

162P.RD_MP
M10 M110
EN Bk : 1 ERR

M11 Os : 0
INC Pr : D10
L : 20
D : R0

162P.RD_MP
M12 M111
EN Bk : 1 ERR

M13 Os : 10000
INC Pr : D11
L : 50
D : R100

7-147
 In Line Comparison Instructions

FUN170 D EQUAL TO COMPARE FUN170 D

= （Compare whether Sa is equal to Sb） =

170D. Sa Sa：Operand A or the starting address of Sa

Execution EN = Sb Sb：Operand B or the starting address of Sb
Sa、Sb may combine with V、Z、P0～P9 for indirect
addressing application
＊This instruction can be supported in PLC
OS firmware V4.60 or later

WX WY WM WS TMR CTR HR SR ROR DR K XR

Range

WX0 WY0 WM0 WS0 T0 C0 R0 R3804 R5000 D0

Operand

16/ 32 bit V、Z

∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣
+/- number P0~P9
WX240 WY240 WM1896 WS984 T255 C255 R3839 R4167 R8071 D3999
Sa ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
Sb ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○

● When execution input 〝EN〞=1, this instruction will be executed in signed number to compare Sa
with Sb. If Sa=Sb, the output is 1; otherwise the output is 0.

Example 1：

Description: When R0=R2、R4=R6 and M0=1, the output status of Y0 is 1; otherwise it is 0

R0=R2、R8=R10 and M1=1, the output status of Y1 is 1; otherwise it is 0

Example 2：

Description: When DR600=DR602 or DR604>DR606, after them DR608<DR610 and DR616≧DR618,

or DR612≠DR614 and DR620≦DR622, or M200=1and M201=1, and then M100=1, the
output status of Y10 is 1; otherwise it is 0.

7-148
In Line Comparison Instructions

FUN171 D GREATER THAN COMPARE FUN171 D

> （Compare whether Sa is greater than Sb） >

171D. Sa Sa：Operand A or the starting address of Sa

Execution EN > Sb Sb：Operand B or the starting address of Sb
Sa、Sb may combine with V、Z、P0～P9 for indirect
addressing application
＊This instruction can be supported in PLC
OS firmware V4.60 or later

WX WY WM WS TMR CTR HR SR ROR DR K XR

Range

WX0 WY0 WM0 WS0 T0 C0 R0 R3804 R5000 D0

Operand

16/ 32 bit V、Z

∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣
+/- number P0~P9
WX240 WY240 WM1896 WS984 T255 C255 R3839 R4167 R8071 D3999
Sa ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
Sb ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○

● When execution input 〝EN〞=1, this instruction will be executed in signed number to compare Sa
with Sb. If Sa>Sb, the output is 1; otherwise the output is 0.

Example 1：

Description: When M10=1、R20 > R22 or M11=1, the output status of Y2 is 1; otherwise it is 0.

Example 2：

Description: When DR600=DR602 or DR604>DR606, after them DR608<DR610 and DR616≧DR618,

or DR612≠DR614 and DR620≦DR622, or M200=1and M201=1, and then M100=1, the
output status of Y10 is 1; otherwise it is 0.

7-149
 In Line Comparison Instructions

FUN172 D LESS THAN COMPARE FUN172 D

< （Compare whether Sa is less than Sb） <

172D. Sa Sa：Operand A or the starting address of Sa

Execution EN < Sb Sb：Operand B or the starting address of Sb
Sa、Sb may combine with V、Z、P0～P9 for indirect
addressing application
＊This instruction can be supported in PLC
OS firmware V4.60 or later

WX WY WM WS TMR CTR HR SR ROR DR K XR

Range

WX0 WY0 WM0 WS0 T0 C0 R0 R3804 R5000 D0

Operand

16/ 32 bit V、Z

∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣
+/- number P0~P9
WX240 WY240 WM1896 WS984 T255 C255 R3839 R4167 R8071 D3999
Sa ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
Sb ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○

● When execution input 〝EN〞=1, this instruction will be executed in signed number to compare Sa
with Sb. If Sa<Sb, the output is 1; otherwise the output is 0.

Example 1：

Description: When M10=1、R20 < R22 or M11=1, the output status of Y2 is 1; otherwise it is 0.

Example 2：

Description: When DR600=DR602 or DR604>DR606, after them DR608<DR610 and DR616≧DR618, or DR612
≠DR614 and DR620≦DR622, or M200=1and M201=1, and then M100=1, the output status of Y10
is 1; otherwise it is 0.

7-150
In Line Comparison Instructions

FUN173 D NOT EQUAL TO COMPARE FUN173 D

<> （Compare whether Sa is not equal to Sb） <>

173D. Sa Sa：Operand A or the starting address of Sa

Execution EN <> Sb Sb：Operand B or the starting address of Sb
Sa、Sb may combine with V、Z、P0～P9 for indirect
addressing application
＊This instruction can be supported in PLC
OS firmware V4.60 or later

WX WY WM WS TMR CTR HR SR ROR DR K XR

Range

WX0 WY0 WM0 WS0 T0 C0 R0 R3804 R5000 D0

Operand

16/ 32 bit V、Z

∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣
+/- number P0~P9
WX240 WY240 WM1896 WS984 T255 C255 R3839 R4167 R8071 D3999
Sa ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
Sb ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○

● When execution input 〝EN〞=1, this instruction will be executed in signed number to compare Sa
with Sb. If Sa≠Sb, the output is 1; otherwise the output is 0.

Example 1：

Description: When M10=1、R20≠R22 or M11=1, the output status of Y2 is 1; otherwise it is 0.

Example 2：

Description: When DR600=DR602 or DR604>DR606, after them DR608<DR610 and DR616≧DR618,

or DR612≠DR614 and DR620≦DR622, or M200=1and M201=1, and then M100=1, the
output status of Y10 is 1; otherwise it is 0.

7-151
 In Line Comparison Instructions

FUN174 D GREATER THAN OR EQUAL TO COMPARE FUN174 D

>= （Compare whether Sa is greater than or equal to Sb） >=

174D. Sa Sa：Operand A or the starting address of Sa

Execution EN >= Sb Sb：Operand B or the starting address of Sb
Sa、Sb may combine with V、Z、P0～P9 for indirect
addressing application
＊This instruction can be supported in PLC
OS firmware V4.60 or later

WX WY WM WS TMR CTR HR SR ROR DR K XR

Range

WX0 WY0 WM0 WS0 T0 C0 R0 R3804 R5000 D0

Operand

16/ 32 bit V、Z

∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣
+/- number P0~P9
WX240 WY240 WM1896 WS984 T255 C255 R3839 R4167 R8071 D3999
Sa ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
Sb ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○

● When execution input 〝EN〞=1, this instruction will be executed in signed number to compare Sa
with Sb. If Sa≧Sb, the output is 1; otherwise the output is 0.

Example 1：

Description: When M10=1、R20≧R22 or M11=1, the output status of Y2 is 1; otherwise it is 0.

Example 2：

Description: When DR600=DR602 or DR604>DR606, after them DR608<DR610 and DR616≧DR618, or DR612
≠DR614 and DR620≦DR622, or M200=1and M201=1, and then M100=1, the output status of Y10
is 1; otherwise it is 0.

7-152
In Line Comparison Instructions

FUN175 D LESS THAN OR EQUAL TO COMPARE FUN175 D

=< （Compare whether Sa is less than or equal to Sb） =<

175D. Sa Sa：Operand A or the starting address of Sa

Execution EN =< Sb Sb：Operand B or the starting address of Sb
Sa、Sb may combine with V、Z、P0～P9 for indirect
addressing application
＊This instruction can be supported in PLC
OS firmware V4.60 or later

WX WY WM WS TMR CTR HR SR ROR DR K XR

Range

WX0 WY0 WM0 WS0 T0 C0 R0 R3804 R5000 D0

Operand

16/ 32 bit V、Z

∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣
+/- number P0~P9
WX240 WY240 WM1896 WS984 T255 C255 R3839 R4167 R8071 D3999
Sa ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
Sb ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○

● When execution input 〝EN〞=1, this instruction will be executed in signed number to compare Sa
with Sb. If Sa≦Sb, the output is 1; otherwise the output is 0.

Example 1：

Description: When M10=1、R20≦R22 or M11=1, the output status of Y2 is 1; otherwise it is 0.

Example 2：

Description: When DR600=DR602 or DR604>DR606, after them DR608<DR610 and DR616≧DR618, or DR612
≠DR614 and DR620≦DR622, or M200=1and M201=1, and then M100=1, the output status of Y10
is 1; otherwise it is 0.

7-153
 Other Instructions

FUN 190 FUN 190

R E A D S Y S T E M S TAT U S
STAT STAT

1 9 0 . S TAT
Gp : Specified status group
Execution EN Gp : 0 : Get information of I/O expansion
1~3 : Reserved
D :
D : Starting address of register to store the system status
D+0 : Quantity of status
D+1 : Status 1
…
K
D+N: Status N
HR ROR DR
Range

R0 R5000 D0 ＊ This instruction can be supported in PLC OS

Operand

∣ ∣ ∣
firmware V4.62 or later
R3839 R8071 D3999
Gp 0~3
D ○ ○* ○

● When execution 〝EN〞=1, this instruction being executed, and if Gp=0, it means to get the
information of I/O expansion modules; total quantity of I/O expansion modules will be stored in D
register, code of I/O expansion module will be stored in D+1~D+N registers in order. Gp=1~3,
reserved for future.

Code of I/O Name of I/O Code of I/O Name of I/O

Expansion Expansion Module Expansion Expansion Module
Module Module
1 FBs-8XYR 21 FBs-6TC
2 FBs-8X 22 FBs-6RTD
3 FBs-8YR 23 FBs-16TC
4 FBs-16XYR 24 FBs-16RTD
5 FBs-20X 25 FBs-2TC
6 FBs-16YR 26 FBs-2A4TC
7 FBs-24X 27 FBs-2A4RTD
8 FBs-24Y 28 FBs-6NTC
9 FBs-24XYR 29 FBs-16NTC (Reserved)
10 FBs-40XYR 30 FBs-32DGI
11 FBs-60XYR 31 FBs-VOM
12 FBs-7SG1S (Decode) 32 FBs-1LC

13 FBs-7SG1H
(Non-decode)
14 FBs-7SG2S (Decode)
15 FBs-7SG2H (Non-decode)
16 FBs-6AD
17 FBs-2DA
18 FBs-4DA
19 FBs-4PT
20 FBs-4A2D

7-154
Other Instructions

FUN 190 FUN 190

R E A D S Y S T E M S TAT U S
STAT STAT

Example：There are two I/O expansion modules FBs-2DA + FBs-6AD installed in one system

Description: When M500=1, this instruction being executed, register D200 is used to store the total
quantity of I/O expansion modules, register D201 is used to store the code (17=FBs-2DA)
of first I/O expansion module, register D202 is used to store the code (16=FBs-6AD) of
second I/O expansion module.

7-155
 Floating Point Instructions

FUN200 D P FUN200 D P
CONVERSION OF INTEGER TO FLOATING POINT NUMBER
IÆF IÆF

S : Starting register of Integer to be converted

D : Starting register to store the result of conversion

Range HR ROR DR K XR
R0 R5000 D0 16/32 V、Z
∣ ∣ ∣ bit
Operand R3839 R8071 D4095 Integer P0～P9
S ○ ○ ○ ○ ○
D ○ ○* ○ ○

Description

z The format of floating point number of Fatek-PLC follows the IEEE-754 standard. For detail explanation of
the format please refer to 5.3 (Numbering System)…page 5 - 9 .

z When conversion control "EN" = 1 or has a transition from 0 to 1 ( P instruction), will convert the integer data
from S register into D~D+1 32-bits register( floating point number data)

200P.I F
X0
EN S : R0 ※ R0 = 200 ( 0000000011001000)
D : D0

Integer To Floating

DD0 = 43480000H

0 0 0 0 0 0 0 0 1 1 0 0 1 0 0 0
R0 :
b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0

I F
0 1 0 0 0 0 1 1 0 1 0 0 1 0 0 0 0 00…0 0
DD0 : b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 b15 b14 ~ b1 b0

s e e e e e e e e m m m m m m m m mm…m m

7-156
Floating Poing Instructions

FUN201 D P FUN201 D P
CONVERSION OF FLOATING POINT NUMBER TO INTEGER
FÆ I FÆ I

S : Starting register of Integer to be converted

D : Starting register to store the result of conversion

Range HR ROR DR XR
R0 R5000 D0 V、Z
∣ ∣ ∣
Operand R3839 R8071 D4095 P0～P9
S ○ ○ ○ ○
D ○ ○* ○ ○

Description

z The format of floating point number of Fatek-PLC follows the IEEE-754 standard. For detail explanation of
the format please refer to 5.3 (Numbering System)…page 5 - 9 .

z When conversion control "EN" = 1 or has a transition from 0 to 1 ( P instruction), will convert the floating
point data from S~S+1 32bits register into D register( integer data ).

z If the value exceeds the valid range of destination, then do not carry out this instruction, and set the
range-error flag “ERR” as 1 and the D register will be intact.

※ DR20 = 123.45 Normalize 42F6E666H

201P.F I
X2 Floating To Integer
EN S : R20 ERR
D : D10
D10 = 007BH

7-157
 Floating Point Instructions

FUN202 P FUN202 P
FLOATING POINT NUMBER ADDITION
FADD FADD

Sa: Augend
Sb: Addend
D : Destination register to store the results
of the addition
Sa, Sb, D may combine with V, Z, P0~P9 to
serve indirect addressing

Range HR ROR DR K XR
R0 R5000 D0 Floating V、Z
∣ ∣ ∣ point
Operand R3839 R8071 D4095 number P0～P9
Sa ○ ○ ○ ○ ○
Sb ○ ○ ○ ○ ○
D ○ ○* ○ ○

Description

z The format of floating point number of Fatek-PLC follows the IEEE-754 standard. For detail explanation of
the format please refer to 5.3 (Numbering System)…page 5 - 9 .

z Performs the addition of the data specified at Sa and Sb and writes the results to a specified register D when
the add control input "EN" =1 or from 0 to 1 ( P instruction). If the result exceed the range that the floating
38
point number can be expressed(± 3 . 4 * 1 0 ) then the error flag FO0 will be set to 1 and the D register will
be intact.

202P.FADD
X0
Sa : R0 ERR
Sb : R10
D : R20

7-158
Floating Poing Instructions

FUN 203 P FUN 203 P

FLOATING POINT NUMBER SUBTRACTION
FSUB FSUB

Ladder symbol
203P.FSUB Sa: Minuend
Subtraction control EN Sa : ERR Ranger Error (FO0)
Sb: Subtrahend
Sb : D : Destination register to store the results
D : of the subtraction
Sa, Sb, D may combine with V, Z, P0~P9 to
serve indirect addressing

Range HR ROR DR K XR
R0 R5000 D0 Floating V、Z
∣ ∣ ∣ point
Operand R3839 R8071 D4095 number P0～P9
Sa ○ ○ ○ ○ ○
Sb ○ ○ ○ ○ ○
D ○ ○* ○ ○

Description

z The format of floating point number of Fatek-PLC follows the IEEE-754 standard. For detail explanation of
the format please refer to 5.3 (Numbering System)…page 5 - 9 .

z Performs the subtraction of the data specified at Sa and Sb and writes the results to a specified register D
when the subtract control input "EN" =1 or from 0 to 1 ( P instruction). If the result exceed the range that the
38
floating point number can be expressed(± 3 . 4 * 1 0 ) then the error flag FO0 will be set to 1 and the D
register will be intact.

203P.FSUB
X0
EN Sa : R0 ERR
Sb : R4
D : R10

DR0 200 Floating Point Number : DR0 43480000H

DR4 500 Floating Point Number : DR4 43FA0000H

DR10 C3960000H

7-159
 Floating Point Instructions

FUN 204 P FUN 204 P

FLOATING POINT NUMBER MULTIPLICATION
FMUL FMUL

Ladder symbol
204P.FMUL Sa: Multiplicand
Multiplication control EN Sa : ERR Ranger Error (FO0)
Sb: Multiplier
Sb : D : Destination register to store the results
D : of the multiplication
Sa, Sb, D may combine with V, Z, P0~P9 to
serve indirect addressing

Range HR ROR DR K XR
R0 R5000 D0 Floating V、Z
∣ ∣ ∣ point
Operand R3839 R8071 D4095 number P0～P9
Sa ○ ○ ○ ○ ○
Sb ○ ○ ○ ○ ○
D ○ ○* ○ ○

Description

z The format of floating point number of Fatek-PLC follows the IEEE-754 standard. For detail explanation of
the format please refer to 5.3 (Numbering System)…page 5 - 9 .

z Performs the multiplication of the data specified at Sa and Sb and writes the results to a specified register D
when the multiplication control input "EN" =1 or from 0 to 1 ( P instruction). If the result exceed the range
38
that the floating point number can be expressed(± 3 . 4 * 1 0 ) then the error flag FO0 will be set to 1 and
the D register will be intact.

204P.FMUL
M10
EN Sa : R10 ERR
Sb : R12
D : R14

DR10 1 2 3 . 4 5 Floating Point Number : DR10 42F6E666H

DR12 6 7 8 . 5 4 Floating Point Number : DR12 4429A28FH

DR14 47A39AE2H

7-160
Floating Poing Instructions

FUN 205 P FUN 205 P

FLOATING POINT NUMBER DIVISION
FDIV FDIV

Sa: Dividend
Sb: Divisor
D : Destination register to store the results
of the division
Sa, Sb, D may combine with V, Z, P0~P9 to
serve indirect addressing

Range HR ROR DR K XR
R0 R5000 D0 Floating V、Z
∣ ∣ ∣ point
Operand R3839 R8071 D4095 number P0～P9
Sa ○ ○ ○ ○ ○
Sb ○ ○ ○ ○ ○
D ○ ○* ○ ○

Description

z The format of floating point number of Fatek-PLC follows the IEEE-754 standard. For detail explanation of
the format please refer to 5.3 (Numbering System) page 5 - 9 .

z Performs the division of the data specified at Sa and Sb and writes the result to the registers specified by
register D when the division control input "EN" =1 or from 0 to 1 ( P instruction). If the result exceed the
38
range that the floating point number can be expressed(± 3 . 4 * 1 0 ) then the error flag FO0 will be set to 1
and the D register will be intact.

205P.FDIV
X5
EN Sa : R0 ERR
Sb : R2
D : R4

7-161
 Floating Point Instructions

FUN 206 P FUN 206 P

FLOATING POINT NUMBER COMPARE
FCMP FCMP

Sa: The register to be compared

Sb: The register to be compared

Sa, Sb may combine with V, Z, P0~P9 to serve

indirect addressing.

Range HR ROR DR K XR
R0 R5000 D0 Floating V、Z
∣ ∣ ∣ point
Operand R3839 R8071 D4095 number P0～P9
Sa ○ ○ ○ ○ ○
Sb ○ ○ ○ ○ ○

Description

z The format of floating point number of Fatek-PLC follows the IEEE-754 standard. For detail explanation of
the format please refer to 5.3 (Numbering System) page 5 - 9 .

z Compares the data of Sa and Sb when the compare control input "EN" =1 or from 0 to 1 ( P instruction). If
the data of Sa is equal to Sb, then set FO0 to 1. If the data of Sa>Sb, then set FO1 to 1. If the data of Sa<Sb,
then set FO2 to 1. If the data of Sa < Sb, then set the FO2 to 1.

X0 206P.FCMP
EN Sa : R0 a=b
Sb : R2 a>b
Y0
a<b

DR0 200.1 Floating Point Number : DR0 4348199AH

DR2 200.2 Floating Point Number : DR2 43483333H

z From the above example, we first assume the data of DR0 is 200.1 and DR2 is 200.2, and then compare the
data by executing the CMP instruction. The FO0 and FO1 are set to 0 and FO2 (a<b) is set to 1 since a<b.

z If you want to have the compound results, such as≧、≦、< > etc., please send =、< and > results to relay first
and then combine the result from the relays.

7-162
Floating Point Instructions

FUN 207 P FUN 207 P

FLOATING POINT NUMBER ZONE COMPARE
FZCP FZCP

S : Register for zone comparison

SU : The upper limit value

SL: The lower limit value

S, SU, SL may combine with V, Z, P0~P9 to

serve indirect address application

Range HR ROR DR K XR
R0 R5000 D0 Floating V、Z
∣ ∣ ∣ point
Operand R3839 R8071 D4095 number P0～P9
S ○ ○ ○ ○ ○
Su ○ ○ ○ ○ ○
SL ○ ○ ○ ○ ○

Description

z The format of floating point number of Fatek-PLC follows the IEEE-754 standard. For detail explanation of
the format please refer to 5.3 (Numbering System) page 5 - 9 .

z When compare control "EN" = 1 or changes from 0 to 1 ( P instruction), compares S with upper limit SU and
lower limit SL. If S is between the upper limit and the lower limit (SL≦S≦SU), then set the inside zone flag
"INZ" to 1. If the value of S is greater than the upper limit SU, then set the higher than upper limit flag "S>U"
to 1. If the value of S is smaller then the lower limit SL, then set the lower than lower limit flag "S<L" as 1.

z The upper limit SU should be greater than the lower limit SL. If SU<SL, then the limit value error flag "ERR"
will set to 1, and this instruction will not carry out.

z The instruction at left compares the value of

DR10 with the upper and lower limit zones
X0 207P.FZCP Y0
formed by DR12 and DR14. If the values of
EN S : R10 INZ
DR10~DR14 are as shown in the diagram at
Su : R12 S>U bottom left, then the result can then be
SL : R14 S<L obtained as at the right of this diagram.
ERR
z If want to get the status of out side the zone,
then OUT NOT Y0 may be used, or an OR
operation between the two outputs S>U and
S<L may be carried out, and move the result
to Y0.

7-163
 Floating Point Instructions

FUN 207 P FUN 207 P

FLOATING POINT NUMBER ZONE COMPARE
FZCP FZCP

S DR10 2 0 0 0 . 2 Floating Point Number : DR10 44FA0666H

Su DR12 3 0 0 0 . 3 Floating Point Number : DR12 453B84CDH ( Upper limit value )

SL DR14 1 0 0 0 . 1 Floating Point Number : DR14 447A0666H ( Lower limit value )

Before-execution

X0＝ Æ FLOATING ZONE COMPARE Æ Y0 = 1

Results of execution

7-164
Advance Function Instruction

FUN 208 P FUN 208 P

FLOATING POINT NUMBER SQUARE ROOT
FSQR FSQR

S : Source register to be taken square root

D : Register for storing result

(square root value)

S, D may combine with V, Z, P0~P9 to serve

indirect address application

Range HR ROR DR K XR
R0 R5000 D0 Floating V、Z
Ope- ∣ ∣ ∣ point
rand R3839 R8071 D4095 number P0～P9
S ○ ○ ○ ○ ○
D ○ ○* ○ ○

Description

z The format of floating point number of Fatek-PLC follows the IEEE-754 standard. For detail explanation of
the format please refer to 5.3 (Numbering System) page 5 - 9 .

z When operation control "EN" = 1 or from 0 to 1( P instruction), take the square root of the data specified by
the S value or S~S+1 register, and store the result into the register specified by D~D+1.

z If the value of S is negative, then the error flag "ERR" will be set to 1, and do not execute the operation.

208P.FSQR
X0
EN S : 2520.04 ERR
D : D0

7-165
 Floating Point Instructions

FUN 209 P FUN 209 P

SIN TRIGONOMETRIC INSTRUCTION
FSIN FSIN

S : Source register to be taken SIN

Ladder symbol
209P.FSIN D : Register for storing result
Operation control EN S : ERR S range error (SIN value)

D : S, D may combine with V, Z, P0~P9 to serve

indirect address application.

Range HR ROR DR K XR
R0 R5000 D0 Integer V、Z
Ope- ∣ ∣ ∣ 16 Bit
rand R3839 R8071 D4095 number P0～P9
S ○ ○ ○ ○ ○
D ○ ○* ○ ○

Description

z The format of floating point number of Fatek-PLC follows the IEEE-754 standard. For detail explanation of the
format please refer to 5.3 (Numbering System) page 5 - 9 .

z When operation control "EN" = 1 or from 0 to 1 ( P instruction), take the SIN value of the angle data specified
by the S register and store the result into the register D~D+1 in floating point number format. The valid range
of the angle is from –18000 to +18000, unit in 0.01 degree.

z If the S value is not within the valid range, then the S value error flag "ERR" will be set to 1, and do not
execute the operation.

209P.FSIN
X0
EN S : 3000 ERR z At left, the example program gets the SIN value of 30,

D : R100 and stores the results the register DR100.

7-166
Floating Point Instructions

FUN 210 P FUN 210 P

COS TRIGONOMETRIC INSTRUCTION
FCOS FCOS

S : Source register to be taken COS

Ladder symbol
210P.FCOS D : Register for storing result
Operation control EN S : ERR S range error (COS value)

D : S, D may combine with V, Z, P0~P9 to serve

indirect address application

Range HR ROR DR K XR
R0 R5000 D0 Integer V、Z
Ope- ∣ ∣ ∣ 16 Bit
rand R3839 R8071 D4095 number P0～P9
S ○ ○ ○ ○ ○
D ○ ○* ○ ○

Description

z The format of floating point number of Fatek-PLC follows the IEEE-754 standard. For detail explanation of the
format please refer to 5.3 (Numbering System) page 5-9.

z When operation control "EN" = 1 or from 0 to 1 ( P instruction), take the COS value of the angle data specified
by the S register and store the result into the register D~D+1 in floating point number format. The valid range
of the angle is from –18000 to +18000, unit in 0.01 degree.

z If the S value is not within the valid range, then the S value error flag "ERR" will be set to 1, and do not
execute the operation.

210P.FCOS
X0 z At left, the example program gets the COS value of 60,
EN S : R0 ERR and stores the results the register DR200.
D : R200

7-167
 Floating Point Instructions

FUN 211 P FUN 211 P

TAN TRIGONOMETRIC INSTRUCTION
FTAN FTAN

S : Source register to be taken TAN

Ladder symbol
211P.FTAN D : Register for storing result
Operation control EN S : ERR S range error (TAN value)

D : S, D may combine with V, Z, P0~P9 to serve

indirect address application

Range HR ROR DR K XR
R0 R5000 D0 Integer V、Z
Ope- ∣ ∣ ∣ 16 Bit
rand R3839 R8071 D4095 number P0～P9
S ○ ○ ○ ○ ○
D ○ ○* ○ ○

Description

z The format of floating point number of Fatek-PLC follows the IEEE-754 standard. For detail explanation of the
format please refer to 5.3 (Numbering System) page 5-9.

z When operation control "EN" = 1 or from 0 to 1 ( P instruction), take the COS value of the angle data specified
by the S register and store the result into the register D~D+1 in floating point number format. The valid range
of the angle is from –18000 to +18000, unit in 0.01 degree.

z If the S value is not within the valid range, then the S value error flag "ERR" will be set to 1, and do not
execute the operation.

211P.FTAN
M0 z At left, the example program gets the TAN value of 45,
EN S : R0 ERR and stores the results the register DD50.
D : D50

7-168
Floating Point Instructions

FUN 212 P FUN 212 P

CHANGE SIGN OF THE FLOATING POINT NUMBER
FNEG FNEG

D : Register to be changed sign

D may combine with V, Z, P0~P9 to serve indirect
address application

Range HR ROR DR XR
R0 R5000 D0 V、Z
Ope- ∣ ∣ ∣
rand R3839 R8071 D4095 P0～P9
D ○ ○* ○ ○

Description

z The format of floating point number of Fatek-PLC follows the IEEE-754 standard. For detail explanation of the
format please refer to 5.3 (Numbering System) page 5 - 9 .

z When operation control "EN" = 1 or from 0 to 1 ( P instruction), the sign of the floating point number register
specified by D will be toogled.

Programming Example

X0 212P. z The instruction at left negates the value of the

EN FNEG R0
DR0 register, and stores it back to DR0.

7-169
 Floating Point Instructions

FUN 213 P FUN 213 P

FLOATING POINT NUMBER ABSOLUTE VALUE
FABS FABS

D : Register to be taken absolute value

D may combine with V, Z, P0~P9 to serve indirect
address application

Range HR ROR DR XR
R0 R5000 D0 V、Z
Ope- ∣ ∣ ∣
rand R3839 R8071 D4095 P0～P9
D ○ ○* ○ ○

Description

z The format of floating point number of Fatek-PLC follows the IEEE-754 standard. For detail explanation of the
format please refer to 5.3 (Numbering System) page 5 - 9 .

z When operation control "EN" = 1 or from 0 to 1 ( P instruction), calculate the absolute value of the floating
point number register specified by D, and write it back into the original D register.

Programming Example

X0 213P.
z The instruction at left calculates the absolute
EN FABS R0
value of the DR0 register, and stores it back in
DR0.

7-170
Floating Point Instructions

FUN 214 P FUN 214 P

FLOATING POINT NAPIERIAN LOGARITHM, logex or ln(x)
FLN FLN

S : Source data or register to be calculated Napierian

logarithm value
F 2 1 4 P. F L N
Operation
Control EN S : ERR D : Register for storing the result
D :
S, D may combine with V, Z, P0~P9 to serve indirect
address application

Range HR ROR DR K XR
R0 R5000 D0 V、Z
Floating
Ope- ∣ ∣ ∣
rand R3839 R8071 D3999 number P0～P9

S ○ ○ ○ ○ ○
D ○ ○* ○ ○

Description

z The format of floating point number of Fatek-PLC follows the IEEE-754 standard of 32-bit.

z When operation control "EN" = 1 or from 0 to 1 ( P instruction), take the Napierian logarithm of the data
specified by the S value or S~S+1 register, and store the result into the register specified by D~D+1.

z If the value of S is negative or equal to 0、 invalid indirect addressing、 or over range of the result , the error
flag "ERR" will be set to 1, and not update the value of D~D+1.

z All floating point instructions can’t be executed in interrupt service routine.

E x a mp le

․ When M214=1, calculate the Napierian logarithm value, it is DD246 = ln (DD46)

7-171
 Floating Point instructions

FUN 215 P FUN 215 P

FLOATING POINT NATURE POWER FUNCTION, ex
FEXP FEXP

F 2 1 5 P. F E X P
S : Source data or register to be calculated power
Operation function of nature number
Control EN S : ERR
D : D : Register for storing the result

S, D may combine with V, Z, P0~P9 to serve indirect

address application

Range HR ROR DR K XR
R0 R5000 D0 V、Z
Floating
Ope- ∣ ∣ ∣
rand R3839 R8071 D3999 number P0～P9

S ○ ○ ○ ○ ○
D ○ ○* ○ ○

Description

z The format of floating point number of Fatek-PLC follows the IEEE-754 standard of 32-bit.

z When operation control "EN" = 1 or from 0 to 1 ( P instruction), calaulate the nature power function of the data
specified by the S value or S~S+1 register, and store the result into the register specified by D~D+1.

z If the value of S is out of range、 invalid indirect addressing、 or over range of the result , the error flag "ERR"
will be set to 1, and not update the value of D~D+1.

z All floating point instructions can’t be executed in interrupt service routine.

E x a mp le

․ W h e n M 2 1 5 = 1 , c a l c u l a t e t h e n a t u r e p o we r f u n c t i o n , i t i s D D 2 4 8 = e D D 4 8

7-172
Floating Point Instructions

FUN 216 P FUN 216 P

FLOATING POINT LOGARITHM, log10x or log(x)
FLOG FLOG

F 2 1 6 P. F L O G
S : Source data or register to be calculated logarithm
Operation value
Control EN S : ERR
D : D : Register for storing the result

S, D may combine with V, Z, P0~P9 to serve indirect

address application

HR ROR DR K XR
Range
R0 R5000 D0 V、Z
Floating
∣ ∣ ∣
Ope- number P0～P9
R3839 R8071 D3999
rand
S ○ ○ ○ ○ ○
D ○ ○* ○ ○

Description

z The format of floating point number of Fatek-PLC follows the IEEE-754 standard of 32-bit.

z When operation control "EN" = 1 or from 0 to 1 ( P instruction), calculate the logarithm value of the data
specified by the S value or S~S+1 register, and store the result into the register specified by D~D+1.

z If the value of S is negative or equal to 0、 invalid indirect addressing、 or over range of the result , the error
flag "ERR" will be set to 1, and not update the value of D~D+1.

z All floating point instructions can’t be executed in interrupt service routine.

E x a mp le

․ When M216=1, calculate the logarithm value, it is DD250 = log (DD50)

7-173
 Floating Point instructions

FUN 217 P FUN 217 P

FLOATING POINT POWER FUNCTION, xy
FPOW FPOW

Sy: Source data or register of exponential

Operation F 2 1 7 P. F P O W
SX: Source data or register of base。
Control EN ERR
Sy :
D : Register for storing the result
Sx :
D : S y, S x , D may combine with V, Z, P0~P9 to serve
indirect address application

Range HR ROR DR K XR
R0 R5000 D0 V、Z
Floating
Ope- ∣ ∣ ∣
rand R3839 R8071 D3999 number P0～P9

Sy ○ ○ ○ ○ ○
Sx ○ ○* ○ ○ ○
D ○ ○ ○ ○

Description

z The format of floating point number of Fatek-PLC follows the IEEE-754 standard of 32-bit.

z When operation control "EN" = 1 or from 0 to 1 ( P instruction), calculate the power function of the exponential
data specified by the Sy、base data specified by the Sx, and store the result into the register specified by
D~D+1.

z If it exists invalid indirect addressing、or over range of the result , the error flag "ERR" will be set to 1, and not
update the value of D~D+1.

z All floating point instructions can’t be executed in interrupt service routine.

E x a mp le

․ W h e n M 2 1 7 = 1 , c a l c u l a t e t h e p o we r f u n c t i o n , i t i s D D 2 5 2 = D D 5 4 D D 5 2

7-174
Floating Point Instructions

FUN 218 P FUN 218 P

FLOATING POINT ARC SINE FUNCTION, sin-1
FASIN FASIN

F 2 1 8 P. FA S I N
S : Source data or register to be calculated the arc sine
Operation value
Control EN S : ERR
D : D : Register for storing the result

S, D may combine with V, Z, P0~P9 to serve indirect

address application

Range HR ROR DR K XR
R0 R5000 D0 V、Z
Floating
Ope- ∣ ∣ ∣
rand R3839 R8071 D3999 number P0～P9
S ○ ○ ○ ○ ○
D ○ ○* ○ ○

Description

z The format of floating point number of Fatek-PLC follows the IEEE-754 standard of 32-bit.
z When operation control "EN" = 1 or from 0 to 1 ( P instruction), calculate the arc sine value of the data
specified by the S value or S~S+1 register, and store the result into the register specified by D~D+1.
z Range of S data : -1~ +1 ; range of D value : -π/2 ~ π/2 (Unit in radian)
z If the value of S is out of range、or invalid indirect addressing, the error flag "ERR" will be set to 1, and not
update the value of D~D+1.
z All floating point instructions can’t be executed in interrupt service routine.

E x a mp le

․ W h e n M 2 1 8 = 1 , c a l c u l a t e t h e a r c s i n e v a l u e , i t i s D D 2 5 6 = s in - 1 D D 5 6 ;
DD256(Unit in radian) × 57.295788(180/π ) to acquire the degree value

7-175
 Floating Point instructions

FUN 219 P FUN 219 P

FLOATING POINT ARC COSINE FUNCTION, cos-1
FACOS FACOS

F 2 1 9 P. FA C O S
S : Source data or register to be calculated the arc
Operation cosine value
Control EN S : ERR
D : D : Register for storing the result

S, D may combine with V, Z, P0~P9 to serve indirect

address application

Range HR ROR DR K XR
R0 R5000 D0 V、Z
Floating
Ope- ∣ ∣ ∣
rand R3839 R8071 D3999 number P0～P9

S ○ ○ ○ ○ ○
D ○ ○* ○ ○

Description

z The format of floating point number of Fatek-PLC follows the IEEE-754 standard of 32-bit.
z When operation control "EN" = 1 or from 0 to 1( P instruction), calculate the arc cosine value of the data
specified by the S value or S~S+1 register, and store the result into the register specified by D~D+1.
z Range of S data : -1~ +1 ; range of D value : 0 ~ π(Unit in radian)
z If the value of S is out of range、or invalid indirect addressing, the error flag "ERR" will be set to 1, and not
update the value of D~D+1.
z All floating point instructions can’t be executed in interrupt service routine.

E x a mp le

․ W h e n M 2 1 9 = 1 , c a l c u l a t e t h e a r c c o s i n e v a l u e , i t i s D D 2 5 8 = cos - 1 D D 5 8 ;
DD258(Unit in radian) × 57.295788(180/π ) to acquire the degree value

7-176
Floating Point Instructions

FUN 220 P FUN 220 P

FLOATING POINT ARC TANGENT FUNCTION, tan-1
FATAN FATAN

F 2 2 0 P. FATA N
S : Source data or register to be calculated the arc
Operation tangent value
Control EN S : ERR
D : D : Register for storing the result

S, D may combine with V, Z, P0~P9 to serve indirect

address application

Range HR ROR DR K XR
R0 R5000 D0 V、Z
Floating
Ope- ∣ ∣ ∣
rand R3839 R8071 D3999 number P0～P9
S ○ ○ ○ ○ ○
D ○ ○* ○ ○

Description

z The format of floating point number of Fatek-PLC follows the IEEE-754 standard of 32-bit.
z When operation control "EN" = 1 or from 0 to 1 ( P instruction), calculate the arc tangent value of the data
specified by the S value or S~S+1 register, and store the result into the register specified by D~D+1.
z S data is any number ; range of D value : -π/2 ~ π/2 (Unit in radian)
z If it exists invalid indirect addressing, the error flag "ERR" will be set to 1, and not update the value of D~D+1.
z All floating point instructions can’t be executed in interrupt service routine.

E x a mp le

․ W h e n M 2 2 0 = 1 , c a l c u l a t e t h e a r c ta n g e n t v a l u e , i t i s D D 2 6 0 = tan - 1 D D 6 0 ;
DD260(Unit in radian) × 57.295788(180/π ) to acquire the degree value

7-177