AD9914

Data Sheet
AD9914
3.5 GSPS Direct Digital Synthesizer with 12-Bit DAC
FEATURES FUNCTIONAL BLOCK DIAGRAM

► 3.5 GSPS internal clock speed
► Integrated 12-bit DAC
► Frequency tuning resolution to 190 pHz
► 16-bit phase tuning resolution
► 12-bit amplitude scaling
► Programmable modulus
► Automatic linear and nonlinear frequency sweeping capability
► 32-bit parallel datapath interface
► 8 frequency/phase offset profiles
► Phase noise: −128 dBc/Hz (1 kHz offset at 1396 MHz)
► Wideband SFDR < −50 dBc
► Serial or parallel input/output control
► 1.8 V/3.3 V power supplies
► Software and hardware controlled power-down
► 88-lead LFCSP package Figure 1.
► PLL REF CLK multiplier
► Phase modulation capability
► Amplitude modulation capability
APPLICATIONS
► Agile LO frequency synthesis
► Programmable clock generator
► FM chirp source for radar and scanning systems
► Test and measurement equipment
► Acousto-optic device drivers
► Polar modulator
► Fast frequency hopping
Rev. G
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Data Sheet AD9914
TABLE OF CONTENTS
Features................................................................ 1 12-Bit DAC Output............................................21

Applications........................................................... 1 DAC Calibration Output....................................21
Functional Block Diagram......................................1 Reconstruction Filter........................................ 21
General Description...............................................4 Clock Input (REF_CLK/REF_CLK)...................22
Specifications........................................................ 5 Output Shift Keying (OSK)............................... 23
DC Specifications............................................... 5 Digital Ramp Generator (DRG)........................ 24
AC Specifications............................................... 6 Power-Down Control........................................ 29
Absolute Maximum Ratings...................................9 Programming and Function Pins......................... 31
Thermal Performance.........................................9 Serial Programming.............................................34
ESD Caution.......................................................9 Control Interface—Serial Input/Output............. 34
Pin Configuration and Function Descriptions...... 10 General Serial Input/Output Operation.............34
Typical Performance Characteristics................... 12 Instruction Byte.................................................34
Equivalent Circuits...............................................16 Serial Input/Output Port Pin Descriptions.........34
Theory of Operation.............................................17 Serial Input/Output Timing Diagrams............... 35
Single Tone Mode.............................................17 MSB/LSB Transfers..........................................35
Profile Modulation Mode...................................17 Parallel Programming (8-/16-Bit)......................... 36
Digital Ramp Modulation Mode........................ 17 Register Map and Bit Descriptions...................... 37
Parallel Data Port Modulation Mode.................17 Register Bit Descriptions.................................. 41
Programmable Modulus Mode......................... 18 Outline Dimensions............................................. 48
Mode Priority.................................................... 18 Ordering Guide.................................................48
Functional Block Detail........................................ 20 Evaluation Boards............................................ 48
DDS Core......................................................... 20
REVISION HISTORY
6/2022—Rev. F to Rev. G
Changes to Base DDS Power, PLL Disabled Parameter and Base DDS Power, PLL Enabled
Parameter, Table 1.........................................................................................................................................5
Changes to SYNC_CLK Output Driver, Duty Cycle Parameter, Data Latency (Pipeline Delay)
Parameter, and SCLK Clock Rate (1/tCLK ) Parameter, Table 2.....................................................................6
Changes to Table 5........................................................................................................................................ 10
Changes to Figure 12 Caption....................................................................................................................... 13
Changes to Figure 14 Caption....................................................................................................................... 13
Added Figure 22; Renumbered Sequentially................................................................................................. 15
Change to Figure 23...................................................................................................................................... 15
Changes to Theory of Operation Section ......................................................................................................17
Changes to Profile Modulation Mode Section................................................................................................17
Changes to Digital Ramp Modulation Mode Section..................................................................................... 17
Changes to Parallel Data Clock (SYNC_CLK) Section..................................................................................17
Changes to Programmable Modulus Mode Section...................................................................................... 18
Changes to Reconstruction Filter Section......................................................................................................21
Changes to REF_CLK/REF_CLK Overview Section and Figure 33.............................................................. 22
Changes to Direct Driven REF_CLK/REF_CLK Section............................................................................... 22
Changes to Phase-Locked Loop (PLL) Multiplier Section............................................................................. 22
Changes to PLL Lock Indication Section....................................................................................................... 23
Changes to DRG Overview Section and Table 9........................................................................................... 24
Added Table 10; Renumbered Sequentially...................................................................................................24
Changes to DRG Slope Control Section........................................................................................................25
Changes to DRG Limit Control Section......................................................................................................... 26
analog.com Rev. G | 2 of 48
Data Sheet AD9914
TABLE OF CONTENTS
Changes to Figure 39.................................................................................................................................... 26

Changes to No-Dwell Ramp Generation Section and Figure 40................................................................... 27
Changes to DROVER Pin Section................................................................................................................. 29
Changes to Frequency Jumping Capability in DRG Mode Section and Figure 41........................................ 29
Changes to Power-Down Control Section..................................................................................................... 29
Changes to Programming and Function Pins Section................................................................................... 31
Changes to Table 15...................................................................................................................................... 37
Changes to Table 16...................................................................................................................................... 42
Changes to Table 17...................................................................................................................................... 43
Changes to Table 18...................................................................................................................................... 44
Changes to Lower Frequency Jump Register—Address 0x09 Section and Table 25................................... 45
Changes to Upper Frequency Jump Register—Address 0x0A Section and Table 26................................... 46
Changes to Table 28...................................................................................................................................... 46
Data Sheet AD9914
GENERAL DESCRIPTION
The AD9914 is a direct digital synthesizer (DDS) featuring a 12‑bit The AD9914 also supports a user defined linear sweep mode
DAC. The AD9914 uses advanced DDS technology, coupled with of operation for generating linear swept waveforms of frequency,
an internal high speed, high performance DAC to form a digitally phase, or amplitude. A high speed, 32-bit parallel data input port
programmable, complete high frequency synthesizer capable of is included, enabling high data rates for polar modulation schemes
generating a frequency-agile analog output sinusoidal waveform and fast reprogramming of the phase, frequency, and amplitude
at up to 1.4 GHz. The AD9914 enables fast frequency hopping tuning words.
and fine tuning resolution (64‑bit capable using programmable
modulus mode). The AD9914 also offers fast phase and amplitude The AD9914 is specified to operate over the extended industrial
hopping capability. The frequency tuning and control words are temperature range (see the Absolute Maximum Ratings section).
loaded into the AD9914 via a serial or parallel input/output port.
Figure 2. Detailed Block Diagram
Data Sheet AD9914
SPECIFICATIONS
DC SPECIFICATIONS
AVDD (1.8 V) and DVDD (1.8 V) = 1.8 V ± 5%, AVDD (3.3 V) and DVDD_I/O (3.3 V) = 3.3 V ± 5%, TA = 25°C, RSET = 3.3 kΩ, IOUT = 20 mA,
external reference clock frequency = 3.5 GHz with reference clock (REF CLK) multiplier bypassed, unless otherwise noted.
Table 1.
Parameter Min Typ Max Unit Test Conditions/Comments
SUPPLY VOLTAGE
DVDD_I/O 3.135 3.30 3.465 V Pin 16, Pin 83
DVDD 1.71 1.80 1.89 V Pin 6, Pin 23, Pin 73
AVDD (3.3 V) 3.135 3.30 3.465 V Pin 34, Pin 36, Pin 39, Pin 40, Pin 43, Pin 47, Pin 50, Pin 52, Pin 53, Pin
60
AVDD (1.8 V) 1.71 1.80 1.89 V Pin 32, Pin 56, Pin 57
SUPPLY CURRENT See also the total power dissipation specifications
IDVDD_I/O 20 mA Pin 16, Pin 83
IDVDD 433 mA Pin 6, Pin 23, Pin 73
IAVDD(3.3V) 640 mA Pin 34, Pin 36, Pin 39, Pin 40, Pin 43, Pin 47, Pin 50, Pin 52, Pin 53, Pin
60
IAVDD(1.8V) 178 mA Pin 32, Pin 56, Pin 57
TOTAL POWER DISSIPATION
Base DDS Power, PLL Disabled 2392 3091 mW 3.5 GHz, single-tone mode, programmable modulus disabled, linear
sweep disabled, amplitude scaler disabled
Base DDS Power, PLL Enabled 2237 2627 mW 2.5 GHz, single-tone mode, programmable modulus disabled, linear
sweep disabled, amplitude scaler disabled
Linear Sweep Additional Power 28 mW
Modulus Additional Power 20 mW
Amplitude Scaler Additional Power 138 mW Manual or automatic
Full Power-Down Mode 400 616 mW Using either the power-down and enable register or the
EXT_PWR_DWN pin
CMOS LOGIC INPUTS
Input High Voltage (VIH) 2.0 DVDD_I/O V
Input Low Voltage (VIL) 0.8 V
Input Current (IINH, IINL) ±60 ±200 µA At VIN = 0 V and VIN = DVDD_I/O
Maximum Input Capacitance (CIN) 3 pF
CMOS LOGIC OUTPUTS
Output High Voltage (VOH) 2.7 DVDD_I/O V IOH = 1 mA
Output Low Voltage (VOL) 0.4 V IOL = 1 mA
REF CLK INPUT CHARACTERISTICS REF CLK inputs must always be ac-coupled (both single‑ended and
differential)
REF CLK Multiplier Bypassed
Input Capacitance 1 pF Single-ended, each pin
Input Resistance 1.4 kΩ Differential
Internally Generated DC Bias Voltage 2 V
Differential Input Voltage 0.8 1.5 V p-p
REF CLK Multiplier Enabled
Input Capacitance 1 pF Single-ended, each pin
Input Resistance 1.4 kΩ Differential
Internally Generated DC Bias Voltage 2 V
Differential Input Voltage 0.8 1.5 V p-p
Data Sheet AD9914
SPECIFICATIONS
AC SPECIFICATIONS
AVDD (1.8V) and DVDD (1.8V) = 1.8 V ± 5%, AVDD3 (3.3V) and DVDD_I/O (3.3V) = 3.3 V ± 5%, TA = 25°C, RSET = 3.3 kΩ, IOUT = 20 mA,
external reference clock frequency = 3.5 GHz with reference clock (REF CLK) multiplier bypassed, unless otherwise noted.
Table 2.
REF CLK INPUT Input frequency range
REF CLK Multiplier Bypassed
Input Frequency Range 500 3500 MHz Maximum fOUT is 0.4 × fSYSCLK
Duty Cycle 45 55 %
Minimum Differential Input Level 632 mV p-p Equivalent to 316 mV swing on each leg
System Clock (SYSCLK) PLL Enabled
VCO Frequency Range 2400 2500 MHz
VCO Gain (KV) 60 MHz/V
Maximum PFD Rate 125 MHz
CLOCK DRIVERS
SYNC_CLK Output Driver
Frequency Range 146 MHz
Duty Cycle 33 % See Figure 22 vs. frequency in the Typical Performance
Characteristics section
Rise Time/Fall Time (20% to 80%) 650 ps
SYNC_OUT Output Driver 10 pF load
Frequency Range 9.1 MHz
Duty Cycle 33 66 % CFR2 register, Bit 9 = 1
Rise Time (20% to 80%) 1350 ps 10 pF load
Fall Time (20% to 80%) 1670 ps 10 pF load
DAC OUTPUT CHARACTERISTICS
Output Frequency Range (1st Nyquist Zone) 0 1750 MHz
Output Resistance 50 Ω Single-ended (each pin internally terminated to AVDD (3.3
V))
Output Capacitance 1 pF
Full-Scale Output Current 20.48 mA Range depends on DAC RSET resistor
Gain Error −10 +10 % FS
Output Offset 0.6 μA
Voltage Compliance Range AVDD − 0.50 AVDD + 0.50 V
Wideband SFDR See the Typical Performance Characteristics section
101.1 MHz Output −66 dBc 0 MHz to 1750 MHz
Narrow-Band SFDR See the Typical Performance Characteristics section
100.5 MHz Output −95 dBc ±500 kHz
DIGITAL TIMING SPECIFICATIONS
Time Required to Enter Power-Down 45 ns Power-down mode loses DAC/PLL calibration settings
Time Required to Leave Power-Down 250 ns Must recalibrate DAC/PLL
Minimum Master Reset time 24 SYSCLK cycles
Maximum DAC Calibration Time (tCAL) 135 µs See the DAC Calibration Output section for formula
Data Sheet AD9914
SPECIFICATIONS
Table 2.
Maximum PLL Calibration Time (tREF_CLK) 16 ms PFD rate = 25 MHz
8 ms PFD rate = 50 MHz
Maximum Profile Toggle Rate 2 SYNC_CLK period
PARALLEL PORT TIMING
Write Timing
Address Setup Time to WR Active 1 ns
Address Hold Time to Inactive 0 ns
Data Setup Time to WR Inactive 3.8 ns
Data Hold Time to WR Inactive 0 ns
WR Minimum Low Time 2.1 ns
WR Minimum High Time 3.8 ns
Minimum WR Time 10.5 ns
Read Timing
Address to Data Valid 92 ns
Address Hold to RD Inactive 0 ns
RD Active to Data Valid 69 ns
RD Inactive to Data Tristate 50 ns
RD Minimum Low Time 69 ns
RD Minimum High Time 50 ns
SERIAL PORT TIMING
SCLK Clock Rate (1/tCLK) 80 MHz SCLK duty cycle = 50%; maximum SCLK rate applies only
to write cycles; read cycles are constrained to <3 MHz
SCLK Pulse Width High, tHIGH 1.5 ns
SCLK Pulse Width Low, tLOW 5.1 ns
SDIO to SCLK Setup Time, tDS 4.9 ns
SDIO to SCLK Hold Time, tDH 0 ns
SCLK Falling Edge to Valid Data on SDIO/ 78 ns
SDO, tDV
CS to SCLK Setup Time, tS 4 ns
CS to SCLK Hold Time, tH 0 ns
CS Minimum Pulse Width High, tPWH 4 ns
DATA PORT TIMING
D[31:0] Setup Time to SYNC_CLK 2 ns
D[31:0] Hold Time to SYNC_CLK 0 ns
F[3:0] Setup Time to SYNC_CLK 2 ns
F[3:0] Hold Time to SYNC_CLK 0 ns
IO_UPDATE Pin Setup Time to SYNC_CLK 2 ns
IO_UPDATE Pin Hold Time to SYNC_CLK 0 ns
Profile Pin Setup Time to SYNC_CLK 2 ns
Profile Pin Hold Time to SYNC_CLK 0 ns
DR_CTL/DR_HOLD Setup Time to SYNC_CLK 2 ns
DR_CTL/DR_HOLD Hold Time to SYNC_CLK 0 ns
DATA LATENCY (PIPELINE DELAY) 1 SYSCLK cycle = 1 period of the system clock (1/fS)
Single Tone Mode or Profile Mode (Matched
Latency Disabled)
Frequency 318 SYSCLK cycles OSK disabled
342 SYSCLK cycles OSK enabled
Phase 294 SYSCLK cycles OSK disabled
Data Sheet AD9914
SPECIFICATIONS
Table 2.
Amplitude 102 SYSCLK cycles OSK enabled
Single Tone Mode or Profile Mode (Matched
Latency Enabled)
Modulation Mode with 32-Bit Parallel Port
(Matched Latency Disabled)
Modulation Mode with 32-Bit Parallel Port
(Matched Latency Enabled)
Sweep Mode (Match Latency Disabled)
Sweep Mode (Match Latency Enabled)
Data Sheet AD9914
ABSOLUTE MAXIMUM RATINGS
Table 3. THERMAL PERFORMANCE

Parameter Rating
Table 4.
AVDD (1.8 V), DVDD (1.8 V) Supplies 2V
Symbol Description Value1 Unit
AVDD (3.3 V), DVDD_I/O (3.3 V) Supplies 4V
θJA Junction-to-ambient thermal resistance (still 24.1 °C/W
Digital Input Voltage −0.7 V to +4 V
air) per JEDEC JESD51-2
Digital Output Current 5 mA
θJMA Junction-to-ambient thermal resistance (1.0 21.3 °C/W
Storage Temperature Range −65°C to +150°C m/sec airflow) per JEDEC JESD51-6
Operating Temperature Range −40°C to +85°C θJMA Junction-to-ambient thermal resistance (2.0 20.0 °C/W
Maximum Junction Temperature 150°C m/sec air flow) per JEDEC JESD51-6
Lead Temperature (10 sec Soldering) 300°C θJB Junction-to-board thermal resistance (still 13.3 °C/W
air) per JEDEC JESD51-8
Stresses at or above those listed under Absolute Maximum Ratings ΨJB Junction-to-board characterization 12.8 °C/W
may cause permanent damage to the product. This is a stress parameter (still air) per JEDEC JESD51-6
rating only; functional operation of the product at these or any other θJC Junction-to-case thermal resistance 2.21 °C/W
conditions above those indicated in the operational section of this ΨJT Junction-to-top-of-package characterization 0.23 °C/W
specification is not implied. Operation beyond the maximum operat- parameter (still air) per JEDEC JESD51-2
ing conditions for extended periods may affect product reliability.
1 Results are from simulations. Printed circuit board (PCB) is JEDEC multilayer.
Thermal performance for actual applications requires careful inspection of the
conditions in the application to determine if they are similar to those assumed
in these calculations.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Charged devi-
ces and circuit boards can discharge without detection. Although
this product features patented or proprietary protection circuitry,
damage may occur on devices subjected to high energy ESD.
Therefore, proper ESD precautions should be taken to avoid
performance degradation or loss of functionality.
Data Sheet AD9914
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Figure 3. Pin Configuration
Table 5. Pin Function Descriptions

Pin No. Mnemonic I/O1 Description
1, 2, 13 to 15, 68 to D5 to D7, D16 to D31, I/O Parallel Port Pins. The 32-bit parallel port offers the option for serial or parallel programming of the internal registers.
72, 75 to 81, 87, 88 D27 to D31 In addition, the parallel port can be configured to provide direct FSK, PSK, or ASK (or combinations thereof)
modulation data. The 32-bit parallel port configuration is set by the state of the four function pins (F0 to F3).
3 D15/A7 I/O Parallel Port Pin/Address Line. The state of the F0 to F3 function pins determines if this pin acts as a line for direct
FSK, PSK, or ASK data or as an address line for programming the internal registers.
10 D10/A2 I/O Parallel Port Pin/Address Line. Multipurpose pin depending on the state of the function pins (F0 to F3). The state of
the F0 to F3 function pins determines if this pin acts as a line for direct FSK, PSK, or ASK data or as an address line
for programming the internal registers.
11 D9/A1 I/O Parallel Port Pin/Address Line. Multipurpose pin depending on the state of the function pins (F0 to F3). The state of
the F0 to F3 function pins determines if this pin acts as a line for direct FSK, PSK, or ASK data or as an address line
for programming the internal registers.
18 D4/SYNCIO I Parallel Port Pin/Serial Port Synchronization Pin. This pin is D4 for direct FSK, PSK, or ASK data. If serial mode is
invoked via F0 to F3, this pin resets the serial port.
19 D3/SDO I/O Parallel Port Pin/Serial Data Output. This pin is D3 for direct FSK, PSK, or ASK data. If serial mode is invoked via F0
to F3, this pin is used for readback mode for serial operation.
20 D2/SDIO/WR I/O Parallel Port Pin/Serial Data Input and Output/Write Input. This pin is D2 for direct FSK, PSK, or ASK data. If serial
mode is invoked via F0 to F3, this pin is used for the SDIO for serial operation. If parallel mode is enabled, this pin
invokes a write operation for updating the values of the internal registers.
21 D1/SCLK/RD I Parallel Port Pin/Serial Clock/Read Input. This pin is D1 for direct FSK, PSK, or ASK data. If serial mode is invoked
via F0 to F3, this pin is used for SCLK for serial operation. If parallel mode is enabled, this pin invokes a read
operation for reading back the value of the internal registers.
Data Sheet AD9914
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Table 5. Pin Function Descriptions

Pin No. Mnemonic I/O1 Description
22 D0/CS/PWD I Parallel Port Pin/Chip Select/Parallel Width. This pin is D0 for direct FSK, PSK, or ASK data. If serial mode is
invoked via F0 to F3, this pin is used for the chip select for serial operation. If parallel mode is enabled, this pin sets
either 8-bit data or 16-bit data.
6, 23, 73 DVDD (1.8V) I Digital Core Supplies (1.8 V).
7, 17, 24, 74, 84 DGND I Digital Ground.
16, 83 DVDD_I/O (3.3V) I Digital Input/Output Supplies (3.3 V).
32, 56, 57 AVDD (1.8V) I Analog Core Supplies (1.8 V).
33, 35, 37, 38, 44, 46, AGND I Analog Ground.
49, 51
34, 36, 39, 40, 43, 47, AVDD (3.3V) I Analog DAC Supplies (3.3 V).
50, 52, 53, 60
25, 26, 27 PS0 to PS2 I Profile Select Pins. Digital inputs (active high). Use these pins to select one of eight phase/frequency profiles for
the DDS. Changing the state of one of these pins transfers the current contents of all input/output buffers to the
corresponding registers. State changes must be set up on the SYNC_CLK pin (Pin 82).
28, 29, 30, 31 F0 to F3 I Function Pins. Digital inputs. The state of these pins determines if a serial or parallel interface is used. In addition,
the function pins determine how the 32-bit parallel data-word is partitioned for FSK, PSK, or ASK modulation mode.
41 AOUT O DAC Complementary Output Source. Analog output (voltage mode). Internally connected through a 50 Ω resistor to
AVDD (3.3 V).
42 AOUT O DAC Output Source. Analog output (voltage mode). Internally connected through a 50 Ω resistor to AVDD (3.3 V).
45 DAC_BP I DAC Bypass Pin. Provides access to the common control node of the DAC current sources. Connecting a capacitor
between this pin and ground can improve noise performance at the DAC output.
48 DAC_RSET O Analog Reference. This pin programs the DAC output full-scale reference current. Connect a 3.3 kΩ resistor to
AGND.
54 REF_CLK I Complementary Reference Clock Input. Analog input.
55 REF_CLK I Reference Clock Input. Analog input.
58 LOOP_FILTER O External PLL Loop Filter Node.
59 REF O Local PLL Reference Supply. Typically at 2.05 V.
61 SYNC_OUT O Digital Synchronization Output. Clock source (output) for synchronizing multiple chips.
62 SYNC_IN I Digital Synchronization Input. Clock receiver (input) for synchronizing multiple chips.
63 DRCTL I Ramp Control. Digital input (active high). This pin controls the sweep direction (up/down).
64 DRHOLD I Ramp Hold. Digital input (active high). Pauses the sweep when active.
65 DROVER O Ramp Over. Digital output (active high). This pin switches to Logic 1 when the digital ramp generator reaches the
programmed upper or lower limit.
66 OSK I Output Shift Keying. Digital input (active high). When the OSK features are placed in either manual or automatic
mode, this pin controls the OSK function. In manual mode, it toggles the multiplier between 0 (low) and the
programmed amplitude scale factor (high). In automatic mode, a low sweeps the amplitude down to zero and a high
sweeps the amplitude up to the amplitude scale factor. This pin is only functional when enabled via a register bit.
67 EXT_PWR_DWN I External Power-Down. Digital input (active high). A high level on this pin initiates the currently programmed
power-down mode.
82 SYNC_CLK O Clock Output. Digital output. Many of the digital inputs on the chip, such as I/O_UPDATE, PS[2:0], and the parallel
data port (D0 to D31), must be set up on the rising edge of this signal.
85 MASTER_RESET I Master Reset. Digital input (active high). Clears all memory elements and sets registers to default values.
86 I/O_UPDATE I Input/Output Update. Digital input (active high). A high on this pin transfers the contents of the input/output buffers to
the corresponding internal registers.
EPAD Exposed Pad. The EPAD must be soldered to ground.
1 I = input, O = output.
Data Sheet AD9914
TYPICAL PERFORMANCE CHARACTERISTICS
Nominal supply voltage; DAC RSET = 3.3 kΩ, TA = 25°C, unless otherwise noted.
Figure 4. Wideband SFDR at 171.5 MHz, SYSCLK = 3.5 GHz (SYSCLK PLL Figure 7. Narrow-Band SFDR at 171.5 MHz, SYSCLK = 3.5 GHz (SYSCLK PLL
Bypassed) Bypassed)
Bypassed) Bypassed)
Bypassed) Bypassed)
Data Sheet AD9914
Figure 10. Wideband SFDR at 1396.5 MHz, SYSCLK = 3.5 GHz (SYSCLK PLL Figure 13. Narrow-Band SFDR at 1396.5 MHz, SYSCLK = 3.5 GHz (SYSCLK
Bypassed) PLL Bypassed)
Figure 11. Wideband SFDR vs. Normalized fOUT, SYSCLK = 3.5 GHz Figure 14. Absolute Phase Noise of REF CLK Source (Rohde & Schwarz
SMA100 Signal Generator at 3.5 GHz Buffered by Series ADCLK925) Driving
AD9914
Figure 12. Wideband SFDR vs. Normalized fOUT, SYSCLK = 1.5 GHz to 3.5
GHz
Figure 15. Absolute Phase Noise Curves of DDS Output at 3.5 GHz Operation
Data Sheet AD9914
Figure 16. Absolute Phase Noise Curves of Normalized REF CLK Source to Figure 19. Absolute Phase Noise Curves of DDS Output Using Internal PLL at
DDS Output at 1396 MHz (SYSCLK = 3.5 GHz) 2.5 GHz Operation
Figure 17. Residual Phase Noise Curves Figure 20. Residual PN vs. Absolute PN Measurement Curves at 1396 MHz
Figure 18. Power Supply Current vs. SYSCLK Figure 21. Residual Phase Noise vs. Normalized Absolute REF CLK Source
Phase Noise at 1396 MHz
Data Sheet AD9914
Figure 22. SYNC_CLK Amplitude at Various Frequencies (fSYSCLK/24), Figure 25. Measured Rising Linear Frequency Sweep
Measured at the SYNC_CLK Pin Using an Active Probe (1 GHz Bandwidth, 1
MΩ, 1 pF) with the SYNC_CLK Pin Loaded by a 1-inch PCB Trace Connected
to an Open SMA Connector
Figure 26. Measured Falling Linear Frequency Sweep
Figure 23. SYNC_OUT (fSYSCLK/384)
Figure 24. DAC Calibration Time vs. SYSCLK Rate. See the DAC Calibration
Output Section for Formula.
Data Sheet AD9914
EQUIVALENT CIRCUITS
Figure 29. CMOS Input
Figure 27. DAC Output
Figure 30. CMOS Output
Figure 28. REF CLK input
Data Sheet AD9914
THEORY OF OPERATION
The AD9914 has five modes of operation. DIGITAL RAMP MODULATION MODE
► Single tone In digital ramp modulation mode, the DRG directly modulates one
► Profile modulation of the DDS signal control parameters (frequency, phase, or ampli-
► Digital ramp modulation (linear sweep) tude) via a dedicated 32-bit sweep accumulator (the sweep accu-
► Parallel data port modulation mulator is completely independent of the 32-bit phase accumulator
in the DDS core). The user controls the characteristics of a ramp
► Programmable modulus mode (for example, sweep range, step size, and step rate) by program-
The modes define the data source that supplies the DDS with ming the appropriate registers via the serial or parallel input/output
the signal control parameters: frequency, phase, or amplitude. The port. The registers provide the user with the ability to control the
partitioning of the data into different combinations of frequency, rising and falling characteristics of a ramp independently.
phase, and amplitude is established based on the mode and/or The ramp is digitally generated via the 32-bit sweep accumulator
specific control bits and function pins. within the DRG. The user can program the digital ramp generator
Although the various modes are described independently, they can (DRG) to direct the 32-bit output of the sweep accumulator to
be enabled simultaneously. This provides an unprecedented level affect the frequency, phase, or amplitude parameter of the DDS.
of flexibility for generating complex modulation schemes. However, When programmed for a frequency sweep, all 32 bits of the sweep
to avoid multiple data sources from driving the same DDS signal accumulator are delivered to the DDS for frequency control. When
control parameter, the device has a built-in priority protocol. programmed for a phase sweep, the 16 LSBs of the sweep accu-
mulator are delivered to the DDS for phase control. Therefore, for
In single tone mode, the DDS signal control parameters come a phase sweep, the 16 MSBs of the 32-bit registers normally used
directly from the profile programming registers. In digital ramp mod- for frequency sweeping must be programmed with zeros. When
ulation mode, the DDS signal control parameters are delivered by programmed for an amplitude sweep, the 12 LSBs of the sweep
a digital ramp generator. In parallel data port modulation mode, the accumulator are delivered to the DDS for amplitude control. There-
DDS signal control parameters are driven directly into the parallel fore, for an amplitude sweep, the 20 MSBs of the 32-bit registers
port. normally used for frequency sweeping must be programmed with
The various modulation modes generally operate on only one of zeros.
the DDS signal control parameters (two in the case of the polar The ramp direction (rising or falling) is externally controlled by
modulation format via the parallel data port). The unmodulated DDS the DRCTL pin. The user can also suspend the operation of the
signal control parameters are stored in programming registers and ramp generator by asserting the DRHOLD pin. Note that the DRG
automatically routed to the DDS based on the selected mode. requires the amplitude control of the DDS to be enabled via the
A separate output shift keying (OSK) function is also available. This OSK enable bit in Register CFR1.
function affects only the amplitude parameter of the DDS. The OSK PARALLEL DATA PORT MODULATION MODE
function has priority over the other data sources that can drive the
DDS amplitude parameter. As such, no other data source can drive In parallel data port modulation mode, the modulated DDS signal
the DDS amplitude when the OSK function is enabled. control parameter(s) are supplied directly from the 32-bit parallel
data port. The function pins define how the 32-bit data-word is
SINGLE TONE MODE applied to the DDS signal control parameters. Formatting of the
In single tone mode, the DDS signal control parameters are sup- 32-bit data-word is unsigned binary, regardless of the destination.
plied directly from the profile programming registers. A profile is an
independent register that contains the DDS signal control parame- Parallel Data Clock (SYNC_CLK)
ters. Eight profile registers are available. Note that the profile pins The AD9914 has an internal clock signal (SYNC_CLK) that runs at
must select the desired register. 1/24 of the DAC sample rate. SYNC_CLK is the primary internal
PROFILE MODULATION MODE timing signal of the AD9914. For example, the PS[2:0] pins, DRCTL
pin, and DRHOLD pin are all gated internally by SYNC_CLK.
Each profile is independently accessible. For FSK, PSK, or ASK
modulation, use the three external profile pins (PS[2:0]) to select In parallel data port modulation mode (CFR2[22] = 1), the AD9914
the desired profile. A change in the state of the profile pins with uses the rising edge of SYNC_CLK to capture the logic level
the next rising edge on SYNC_CLK updates the DDS with the applied to the D[31:0] pins and the F[3:0] pins. Thus, the parallel
parameters specified by the selected profile. Therefore, the profile data port essentially operates at the SYNC_CLK rate in parallel
change must meet the setup and hold times to the SYNC_CLK data port modulation mode.
rising edge. Note that amplitude control must also be enabled via Because the AD9914 uses the internal SYNC_CLK signal to cap-
the OSK enable bit in the CFR1 register (0x00[8]). ture the state of the D[31:0] and F[3:0] pins in parallel data port
Data Sheet AD9914
THEORY OF OPERATION
modulation mode, an external replica of the SYNC_CLK signal is behavior changes the modulus of the phase accumulator to B × 232
useful for controlling external circuitry used to drive the D[31:0] and (instead of 232), allowing it to synthesize the desired f0.
F[3:0] pins (an FPGA, for example). As such, the AD9914 provides
an option that makes the internal SYNC_CLK signal externally To determine the programmable modulus mode register values for
available at the SYNC_CLK pin. Program CFR2[11] = 1 (default) FTW, A, and B, the user must first define f0/fS as a ratio of relatively
to make the internal SYNC_CLK signal appear at the SYNC_CLK prime integers, M/N. That is, having converted f0 and fS to integers,
pin. The user also has the option to invert the external SYNC_CLK M and N, reduce the fraction, M/N, to the lowest terms. Then, divide
signal via CFR2[10]. M × 232 by N. The integer part of this division operation is the value
of FTW (Register 0x04[31:0]). The remainder, Y, of this division
Enabling the SYNC_CLK pin driver to provide an external replica of operation is
the SYNC_CLK signal results in transient current spikes associated
with the edges of the SYNC_CLK signal. As such, the SYNC_CLK Y = (232 × M) – (FTW × N)
driver is, by design, a weak CMOS driver. The use of a weak The value of Y facilitates the determination of A and B by taking
driver limits the magnitude of the current spikes and mitigates their the fraction, Y/N, and reducing it to the lowest terms. Then, the
coupling onto sensitive analog nodes within the AD9914. numerator of the reduced fraction is A (Register 0x06[31:0]) and the
Note the SYNC_CLK signal of the AD9914 has a nominal duty denominator is B (Register 0x05[31:0]).
cycle of 1/3 (~33%). The low duty cycle of the SYNC_CLK signal For example, synthesizing precisely 300 MHz with a 1 GHz system
combined with the limited drive capability of the SYNC_CLK pin clock is not possible with a standard DDS. It is possible, however,
driver means that any interface circuitry must exhibit a high input using programmable modulus as follows.
impedance. The recommendation is to use the shortest possible
trace length with minimal parasitic capacitive loading when connect- First, express f0/fS as a ratio of integers:
ing to a receiving circuit. 300,000,000/1,000,000,000
PROGRAMMABLE MODULUS MODE Reducing this fraction to lowest terms yields 3/10; therefore, M = 3
In programmable modulus mode, the DRG is used as an auxiliary and N = 10. FTW is the integer part of (M × 232)/N, or (3 × 232)/10,
accumulator to alter the frequency equation of the DDS core, which is 1,288,490,188 (0x4CCCCCCC in 32-bit hexadecimal nota-
making it possible to implement fractions that are not restricted to tion). The remainder, Y, of (3 × 232)/10, is (232 × 3) − (1,288,490,188
a power of 2 in the denominator. A standard DDS is restricted to × 10), which is 8. Therefore, Y/N is 8/10, which reduces to 4/5.
fractions with a power of 2 in the denominator because the phase Therefore, A = 4 and B = 5 (0x00000004 and 0x00000005 in 32-bit
accumulator is a set of bits as wide as the frequency tuning word hexadecimal notation, respectively). Programming the AD9914 with
(FTW). these values of FTW, A, and B results in an output frequency that is
exactly 3/10 of the system clock frequency.
When in programmable modulus mode, however, the frequency
equation is: MODE PRIORITY
f0 = (fS)(FTW + A/B)/232 The ability to activate each mode independently makes it possible
to have multiple data sources attempting to drive the same DDS
where f0/fS < ½, 0 ≤ FTW < 231, 2 ≤ B ≤ 232 – 1, and A < B. signal control parameter (frequency, phase, and amplitude). To
This equation implies a modulus of B × 232 (rather than 232, in the avoid contention, the AD9914 has a built-in priority system. Table
case of a standard DDS). Furthermore, because B is programma- 6 summarizes the priority for each of the DDS modes. The data
ble, the result is a DDS with a programmable modulus. source column in Table 6 lists data sources for a particular DDS
signal control parameter in descending order of precedence. For
When in programmable modulus mode, the 32-bit auxiliary accumu- example, if the profile mode enable bit and the parallel data port
lator operates in a way that allows it to roll over at a value other enable bit (0x01[23:22]) are set to Logic 1 and both are program-
than the full capacity of 232. That is, it operates with a modified med to source the frequency tuning word to DDS output, the profile
modulus based on the programmable value of B. With each roll modulation mode has priority over the parallel data port modulation
over of the auxiliary accumulator, a value of 1 LSB adds to the mode.
current accumulated value of the 32-bit phase accumulator. This
Table 6. Data Source Priority
DDS Signal Control Parameters
Priority Data Source Conditions
Highest Priority Programmable modulus If programmable modulus mode is used to output frequency only, no other data source can control the output
frequency in this mode. Note that the DRG is used in conjunction with programmable modulus mode; therefore,
the DRG cannot be used to sweep phase or amplitude in programmable modulus mode.
Data Sheet AD9914
THEORY OF OPERATION
Table 6. Data Source Priority

DDS Signal Control Parameters
Priority Data Source Conditions
If output phase offset control is desired, enable profile mode and use the profile registers and profile pins
accordingly to control output phase adjustment.
If output amplitude control is desired, enable profile mode and use the profile registers and profile pins
accordingly to control output amplitude adjustment. Note that the OSK enable bit must be set to control the
output amplitude.
DRG The digital ramp modulation mode is the next highest priority mode. If the DRG is enabled to sweep output
frequency, phase, or amplitude, the two parameters not being swept can be controlled independently via the
profile mode.
Profiles The profile modulation mode is the next highest priority mode. Profile mode can control all three parameters
independently, if desired.
Lowest Priority Parallel port Parallel data port modulation has the lowest priority but the most flexibility as far as changing any parameter at
the high rate. See the Programming and Function Pins section.
Data Sheet AD9914
FUNCTIONAL BLOCK DETAIL
DDS CORE applied prior to the angle to amplitude conversion block internal to
the DDS core. The relative phase offset (Δθ) is given by
The direct digital synthesizer (DDS) block generates a reference
signal (sine or cosine based on Register 0x00, Bit 16, the enable 2π POW
sine output bit). The parameters of the reference signal (frequency, 216
Δθ =
phase, and amplitude) are applied to the DDS at the frequency, POW
phase offset, and amplitude control inputs, as shown in Figure 31. 360
216
The output frequency (fOUT) of the AD9914 is controlled by the where the upper quantity is for the phase offset expressed as
frequency tuning word (FTW) at the frequency control input to the radian units and the lower quantity as degrees.
DDS. The relationship among fOUT, FTW, and fSYSCLK is given by
To find the POW value necessary to develop an arbitrary Δθ, solve
fOUT = FTW
fSYSCLK (1) the preceding equation for POW and round the result (in a manner
232 similar to that described previously for finding an arbitrary FTW).
where FTW is a 32-bit integer ranging in value from 0 to The relative amplitude of the DDS signal can be digitally scaled
2,147,483,647 (231 − 1), which represents the lower half of the full (relative to full scale) by means of a 12-bit amplitude scale factor
32-bit range. This range constitutes frequencies from dc to Nyquist (ASF). The amplitude scale value is applied at the output of the
(that is, ½ fSYSCLK). angle to amplitude conversion block internal to the DDS core. The
The FTW required to generate a desired value of fOUT is found by amplitude scale is given by
solving Equation 1 for FTW, as given in Equation 2. ASF
212
fOUT
FTW = round 232 (2) Amplitude Scale = (3)
fSYSCLK ASF
20log
212
where the round(x) function rounds the argument (the value of
x) to the nearest integer. This is required because the FTW is where the upper quantity is amplitude expressed as a fraction of full
constrained to be an integer value. For example, for fOUT = 41 MHz scale and the lower quantity is expressed in decibels relative to full
and fSYSCLK = 122.88 MHz, FTW = 1,433,053,867 (0x556AAAAB). scale.
Programming an FTW greater than 231 produces an aliased image To find the ASF value necessary for a particular scale factor, solve
that appears at a frequency given by Equation 3 for ASF and round the result (in a manner similar to that
described previously for finding an arbitrary FTW).
FTW
fOUT = 1 − fSYSCLK
232 When the AD9914 is programmed to modulate any of the DDS
signal control parameters, the maximum modulation sample rate is
for FTW ≥ 231. 1/24 fSYSCLK. This means that the modulation signal exhibits images
The relative phase of the DDS signal can be digitally controlled by at multiples of 1/24 fSYSCLK. The impact of these images must be
means of a 16-bit phase offset word (POW). The phase offset is considered when using the device as a modulator.
Figure 31. DDS Block Diagram
Data Sheet AD9914
12-BIT DAC OUTPUT is typically passed through an external reconstruction filter that
serves to remove the artifacts of the sampling process and other
The AD9914 incorporates an integrated 12-bit, current output DAC. spurs outside the filter bandwidth.
The output current is delivered as a balanced signal using two
outputs. The use of balanced outputs reduces the potential amount Because the DAC constitutes a sampled system, the output must
of common-mode noise present at the DAC output, offering the be filtered so that the analog waveform accurately represents the
advantage of an increased signal-to-noise ratio. An external resistor digital samples supplied to the DAC input. The unfiltered DAC
(RSET) connected between the DAC_RSET pin and AGND estab- output contains the desired baseband signal, which extends from
lishes the reference current. The recommended value of RSET is 3.3 dc to the Nyquist frequency (fS/2). It also contains images of the
kΩ. baseband signal that theoretically extend to infinity. Notice that the
odd numbered images (shown in Figure 32) are mirror images of
Attention must be paid to the load termination to keep the output the baseband signal. Furthermore, the entire DAC output spectrum
voltage within the specified compliance range; voltages developed is affected by a sin(x)/x response, which is caused by the sample-
beyond this range cause excessive distortion and can damage the and-hold nature of the DAC output signal.
DAC output circuitry.
For applications using the fundamental frequency of the DAC out-
DAC CALIBRATION OUTPUT put, the response of the reconstruction filter must preserve the
The DAC CAL enable bit in the CFR4 control register (0x03[24]) baseband signal (Image 0), while completely rejecting all other
must be manually set and then cleared after each power-up and images. However, a practical filter implementation typically exhibits
every time the REF CLK or internal system clock is changed. This a relatively flat pass band that covers the desired output frequency
initiates an internal calibration routine to optimize the setup and followed by a transition band where the response rolls off as steeply
hold times for internal DAC timing. Failure to calibrate may degrade as possible, and then a stop band that maintains significant (though
performance and even result in loss of functionality. The length of not complete) rejection of the remaining images. Depending on how
time to calibrate the DAC clock is calculated from the following close unwanted spurs are to the desired signal, a third-, fifth-, or
equation: seventh-order elliptic low-pass filter is common.
469, 632 Some applications operate from an image above the Nyquist fre-
tCAL = fS quency, and those applications use a band-pass filter instead of
a low-pass filter. The design of the reconstruction filter has a
RECONSTRUCTION FILTER significant impact on the overall signal performance. Therefore,
The DAC output signal appears as a sinusoid sampled at fS. The good filter design and implementation techniques are important for
frequency of the sinusoid is determined by the frequency tuning obtaining the best possible jitter results.
word (FTW) that appears at the input to the DDS. The DAC output
Figure 32. DAC Spectrum vs. Reconstruction Filter Response
Data Sheet AD9914
CLOCK INPUT (REF_CLK/REF_CLK)
REF_CLK/REF_CLK Overview
The AD9914 supports a number of options for producing the
internal SYSCLK signal (that is, the DAC sample clock) via the
REF_CLK/REF_CLK input pins. The REF_CLK input can be driv-
en directly from a differential or single-ended source. There is
also an internal phase-locked loop (PLL) multiplier that can be
independently enabled. However, the PLL limits the SYSCLK signal
between 2.4 GHz and 2.5 GHz operation. A differential signal is
recommended when the PLL is bypassed. A block diagram of the
REF_CLK functionality is shown in Figure 33. Figure 33 also shows
how the CFR3 control bits are associated with specific functional
blocks. Figure 34. Direct Connection Diagram
Phase-Locked Loop (PLL) Multiplier

An internal PLL provides the option to use a reference clock fre-
quency that is significantly lower than the system clock frequency.
The PLL supports a wide range of programmable even frequency
multiplication factors (20× to 510×; that is, two times the program-
med value of N (CFR3[15:8])) as well as a programmable charge
pump current and external loop filter components (connected via
the PLL LOOP_FILTER pin). These features add an extra layer of
flexibility to the PLL, allowing optimization of phase noise perform-
Figure 33. REF_CLK Block Diagram ance and flexibility in frequency plan development. The PLL is also
equipped with a lock detector, enabled via CFR3[2] = 1. When
The PLL enable bit (0x02[18]) chooses between the PLL path and enabled, lock detect status is available via 0x1B[24].
the direct input path. The direct input path is the default condition.
The PLL output frequency range (fSYSCLK) is constrained to the
When the direct input path is selected, the REF_CLK/REF_CLK
range of 2.4 GHz ≤ fSYSCLK ≤ 2.5 GHz by the internal VCO.
pins must be driven by an external signal source (single-ended or
differential). Input frequencies up to 3.5 GHz are supported. As shown in Figure 33, to use the PLL, the user must program
CFR3[18] = 1, which enables the PLL circuitry and selects the VCO
Direct Driven REF_CLK/REF_CLK output of the PLL as the internal system clock (SYSCLK) source.
There are three ways to route the REF_CLK input signal to the
With a differential signal source, the REF_CLK/REF_CLK pins input of the PLL, as follows:
are driven with complementary signals and ac-coupled with 0.1
µF capacitors. With a single-ended signal source, either a single- ► Feedthrough (PLL input frequency = REF_CLK input frequency)
ended-to-differential conversion can be employed or the REF_CLK ► Divided (PLL input frequency = REF_CLK input frequency divid-
input can be driven single-ended directly. In either case, 0.1 µF ed by 2, 4, or 8)
capacitors ac couples both REF_CLK/ REF_CLK pins to avoid ► Multiplied (PLL input frequency = twice the REF_CLK input
disturbing the 2 V dc internal bias voltage. See Figure 34 for more frequency)
details.
Regardless of the routing option chosen, the user must ensure the
The REF_CLK/REF_CLK input resistance is ~2.5 kΩ differential frequency at the input to the PLL does not exceed 125 MHz.
(~1.2 kΩ single-ended). Most signal sources have relatively low
output impedances. The REF_CLK/REF_CLK input resistance is The feedthrough path is the default PLL input option (in effect
relatively high; therefore, the effect on the termination impedance is when CFR3[17] = 0 and CFR3[19] = 0). Because the feedthrough
negligible and can usually be chosen to be the same as the output path delivers the REF_CLK input signal to the PLL input without
impedance of the signal source. The bottom two examples in Figure frequency division or multiplication, the PLL can be made to align
34 assume a signal source with a 50 Ω output impedance. with either the rising or falling edge of the REF_CLK input signal
via CFR3[16]. Logic 0 selects the rising edge of the REF_CLK input
signal, whereas Logic 1 selects the falling edge. Normally, there
is no particular advantage over choosing one edge over the other.
However, some clock sources exhibit more jitter on one edge than
Data Sheet AD9914
the other. Thus, the ability to choose the edge with less jitter yields Table 8. N Divider vs. Charge Pump Current
less noise. Recommended Charge Pump Current, ICP
N Divider Range (μA)
The divided path is in effect when CFR3[17] = 1 (the state of
CFR3[16] and CFR3[19] is immaterial). The user has four options 16 to 23 250
via CFR3[21:20]: disable the divider or divide by 2, 4 or 8. Note that 24 to 35 375
the divided path uses the inverted version of the REF_CLK input 36 to 43 500
signal exclusively. 44 to 55 625
56 to 63 750
The multiplied path is in effect when CFR3[19] = 1 and CFR3[17] 64 to 79 875
= 0, which doubles the frequency of the REF_CLK input before
80 to 100 1000
delivering it to the input of the PLL.
VCO Calibration PLL Loop Filter Components
When using the PLL to generate the system clock, VCO calibration The loop filter is mostly internal to the device, as shown in Figure
is required to tune the VCO appropriately and achieve good per- 35. The recommended external capacitor value is 560 pF. Because
formance. When the reference input signal is stable, the VCO cal CP and RPZ are integrated, it is not recommended to adjust the
enable bit in the CFR1 register, 0x00[24], must be asserted. Sub- loop bandwidth via the external capacitor value. The better option
sequent VCO calibrations require that the VCO calibration bit be is to adjust the charge pump current even though it is a coarse
cleared prior to initiating another VCO calibration. VCO calibration adjustment.
must occur before DAC calibration to ensure optimal performance For example, suppose the PLL is manually programmed such that
and functionality. ICP = 375 μA, KV = 60 MHz/V, and N = 25. This produces a loop
bandwidth of approximately 250 kHz.
PLL Charge Pump/Total Feedback Divider
The charge pump current (ICP) value is automatically chosen via
the VCO calibration process and N value (N = 10 to 255) stored in
Feedback Divider N[7:0] in the CFR3 register (0x02[15:8]). N values
below 10 must be avoided.
Note that the total PLL multiplication value for the PLL is always 2N
due to the fixed divide by 2 element in the feedback path. This is
shown in Figure 35. This fixed divide by 2 element forces only even
PLL multiplication. Figure 35. REF CLK PLL External Loop Filter
To manually override the charge pump current value, the manual
ICP selection bit in CFR3 (0x02[6]) must be set to Logic 1. This PLL Lock Indication
provides the user with additional flexibility to optimize the PLL When the PLL is in use and CFR3[2] = 1, the PLL lock bit
performance. Table 7 lists the bit settings vs. the nominal charge (0x1B[24]) provides an active high indication that the PLL has
pump current. locked to the REF CLK input signal.
Table 7. PLL Charge Pump Current
OUTPUT SHIFT KEYING (OSK)
ICP Bits (CFR3[5:3]) Charge Pump Current, ICP (μA)
000 125 The OSK function (see Figure 36) allows the user to control the
001 250 output signal amplitude of the DDS. The amplitude data generated
010 375 by the OSK block has priority over any other functional block that
011 500 (default)
is programmed to deliver amplitude data to the DDS. Therefore, the
OSK data source, when enabled, overrides all other amplitude data
100 625
sources.
101 750
110 875 The operation of the OSK function is governed by two CFR1 regis-
111 1000 ter bits, OSK enable (0x00[8]) and external OSK enable (0x00[9]),
the external OSK pin, the profile pins, and the 12 bits of amplitude
Table 8. N Divider vs. Charge Pump Current
scale factor found in one of eight profile registers. The profile pins
Recommended Charge Pump Current, ICP select the profile register containing the desired amplitude scale
N Divider Range (μA)
factor.
10 to 15 125
Data Sheet AD9914
The primary control for the OSK block is the OSK enable bit The primary control for the DRG is the digital ramp enable bit
(0x00[8]). When the OSK function is disabled, the OSK input (0x01[19]). When disabled, the other DRG input controls are ignor-
controls and OSK pin are ignored. ed and the internal clocks are shut down to conserve power.
The OSK pin functionality depends on the state of the external OSK The output of the DRG is a 32-bit unsigned data bus that can
enable bit and the OSK enable bit. When both bits are set to Logic be routed to any one of the three DDS signal control parameters,
1 and the OSK pin is Logic 0, the output amplitude is forced to 0; as controlled by the two digital ramp destination bits in Control
otherwise, if the OSK pin is Logic 1, the output amplitude is set Function Register 2 according to Table 9. The 32-bit output bus is
by the amplitude scale factor value in one of eight profile registers LSB-aligned with the 32-bit frequency parameter, the 16‑bit phase
depending on the profile pin selection. parameter, or the 12-bit amplitude parameter, as defined by the
destination bits. When the destination is phase or amplitude, the
unused MSBs are ignored.
Table 9. Digital Ramp Destination
Allocation of the DDS
Digital Ramp Destination DDS Signal Control Parameter Bits in the
Bits (CFR2[21:20]) Parameter 32-Bit DRG Output Bus
00 Frequency 31:0
01 Phase 15:0
1x1 Amplitude 11:0
Figure 36. OSK Block Diagram 1 x = don’t care.
DIGITAL RAMP GENERATOR (DRG)
The ramp characteristics of the DRG are fully programmable. This
includes the upper and lower ramp limits, and independent control
DRG Overview
of the step size and step rate for both the positive and negative
To sweep phase, frequency, or amplitude from a defined start point slope characteristics of the ramp. A detailed block diagram of the
to a defined endpoint, a completely digital ramp generator is includ- DRG is shown in Figure 38.
ed in the AD9914. The DRG makes use of eight control register The direction of the ramping function is controlled by the DRCTL
bits, three external pins, and five 32-bit registers (see Figure 37). pin. The DRG responds differently to the DRCTL pin depending on
the state of the two no-dwell bits (CFR2[18:17]) per Table 10.
The DRG also supports a hold feature controlled via the DRHOLD
pin. When this pin is set to Logic 1, the DRG is stalled at the
last state; otherwise, the DRG operates normally. The DDS signal
control parameters that are not the destination of the DRG are
taken from the active profile.
Figure 37. Digital Ramp Block Diagram

Table 10. DRCTL Pin Functionality
CFR2[18] CFR2[17] Dwell Type DRCTL Pin Behavior
0 0 Hold upper (lower) frequency Level sensitive. Logic 0 on the DRCTL pin causes the DRG to initiate a falling ramp,
limit at end of rising (falling) whereas Logic 1 causes the DRG to initiate a rising ramp.
ramp
Data Sheet AD9914
Table 10. DRCTL Pin Functionality

CFR2[18] CFR2[17] Dwell Type DRCTL Pin Behavior
0 1 Return to upper frequency limit Edge sensitive. A Logic 1 to Logic 0 transition on the DRCTL pin causes the DRG to initiate
at end of falling ramp a negative slope ramp, which continues uninterrupted (regardless of any further activity on
the DRCTL pin) until the lower limit is reached.
1 0 Return to lower frequency limit Edge sensitive. A Logic 0 to Logic 1 transition on the DRCTL pin causes the DRG to initiate
at end of rising ramp a positive slope ramp, which continues uninterrupted (regardless of any further activity on
the DRCTL pin) until the upper limit is reached.
1 1 Continuous rising and falling Edge sensitive. During a positive slope ramp, a Logic 1 to Logic 0 transition on the DRCTL
ramp pin causes the DRG to immediately change the ramp direction to a negative slope using the
negative slope parameters. During a negative slope ramp, a Logic 0 to Logic 1 transition
on the DRCTL pin causes the DRG to immediately change the ramp direction to a positive
slope using the positive slope parameters.
Figure 38. Digital Ramp Generator Detail
DRG Slope Control step size by substituting STEPN or STEPP for M in the following
equations as required:
The core of the DRG is a 32-bit accumulator clocked by a program-
mable timer. The time base for the timer is the DDS clock, which Frequency Step = M
fSYSCLK
operates at 1/24 fSYSCLK. The timer establishes the interval between 232
successive updates of the accumulator. The positive (+Δt) and πM
negative (−Δt) slope step intervals are independently programmable Pℎase Step = (radians)
215
as given by
45M
Pℎase Step = (degrees)
+Δt = 24P 213
fSYSCLK
M
24N Amplitude Step = IFS
−Δt = fSYSCLK 212
where P and N are the two 16-bit values stored in the 32-bit digital Note that the frequency units are the same as those that represent
ramp rate register and control the step interval. N defines the step fSYSCLK (MHz, for example). The amplitude units are the same as
interval of the negative slope portion of the ramp. P defines the step those that represent IFS, the full-scale output current of the DAC
interval of the positive slope portion of the ramp. (mA, for example).
The step size of the positive (STEPP) and negative (STEPN) slope Although the sweep accumulator has 32 bits of resolution, phase
portions of the ramp are 32-bit values programmed into the 32-bit and amplitude sweeps make use of the 16 LSBs or 12 LSBs of the
rising and falling digital ramp step size registers (0x06 and 0x07). sweep accumulator, respectively. Thus, the phase step equations
Program each of the step sizes as an unsigned integer (the hard- and the amplitude step equation reflect 16-bit or 12-bit resolution,
ware automatically interprets STEPN as a negative value). The accordingly. As such, when programming the associated step size
relationship between the 32-bit step size values and actual units registers for phase or amplitude sweeps, the user must ensure the
of frequency, phase, or amplitude depend on the digital ramp 16 MSBs or 20 MSBs, respectively, are programmed with zeros.
destination bits. Calculate the actual frequency, phase, or amplitude
Data Sheet AD9914
As described previously, the step interval is controlled by a 16-bit For a phase sweep, program the 16 LSBs of the 32-bit upper limit
programmable timer. There are three events that can cause this and lower limit registers with the desired phase value and program
timer to be reloaded prior to the expiration, as follows: the 16 MSBs of the upper limit and lower limit registers with zeros.
For an amplitude sweep, program the 12 LSBs of the 32-bit upper
► A transition of the digital ramp enable bit from cleared to set, limit and lower limit registers with the desired amplitude value and
followed by assertion of the IO_UPDATE pin the 20 MSBs of the upper limit and lower limit registers with zeros.
► A change of state of the DRCTL pin
► Anytime the IO_UPDATE pin is asserted while the load LRR at DRG Accumulator Clear
input/output update bit is set (0x00[15] = 1)
The ramp accumulator can be cleared (that is, reset to 0) under
DRG Limit Control program control. When the ramp accumulator is cleared, it forces
the DRG output to the lower limit programmed into the digital ramp
The ramp accumulator is followed by limit control logic that enforces limit register.
an upper and lower boundary on the output of the ramp generator.
Under no circumstances does the output of the DRG exceed the With the limit control block embedded in the feedback path of the
programmed limit values while the DRG is enabled. The limits are accumulator, resetting the accumulator is equivalent to presetting it
set through the 64-bit digital ramp limit register, comprising a 32-bit to the lower limit value.
upper limit value and a 32-bit lower limit value. Note that the upper
limit value must be greater than the lower limit value to ensure
normal operation.
Figure 39. Normal Ramp Generation
Data Sheet AD9914
Normal Ramp Generation Event 9—An input/output update registers that the clear digital
ramp accumulator bit is set, resetting the ramp accumulator and
Normal ramp generation implies that both no-dwell bits are cleared forcing the DRG output to the programmed lower limit. The DRG
(see the No-Dwell Ramp Generation section for details). In Figure output remains at the lower limit until the clear condition is re-
39, a sample ramp waveform is depicted with the required control moved.
signals. The top trace is the DRG output. The next trace down
is the status of the DROVER output pin (assuming that the DRG Event 10—The clear digital ramp accumulator bit is cleared, which
over output enable bit is set). The remaining traces are control bits has no effect on the DRG output because the bit is not effective
and control pins. The pertinent ramp parameters are also identified until an input/output update is issued.
(upper and lower limits plus step size and Δt for the positive Event 11—An input/output update registers that the clear digital
and negative slopes). Along the bottom, circled numbers identify ramp accumulator bit is cleared, releasing the ramp accumulator;
specific events. These events are referred to by number (Event 1 and the previous positive slope profile restarts.
and so on) in the following paragraphs.
Event 12—The autoclear digital ramp accumulator bit is set, which
In this example, the positive and negative slopes of the ramp are has no effect on the DRG output because the bit is not effective
different to demonstrate the flexibility of the DRG. The parameters until an input/output update is issued.
of both slopes can be programmed to make the positive and
negative slopes the same. Event 13—An input/output update registers that the autoclear digital
ramp accumulator bit is set, resetting the ramp accumulator. How-
Event 1—The digital ramp enable bit is set, which has no effect on ever, with an automatic clear, the ramp accumulator is held in reset
the DRG output because the bit is not effective until an input/output for only a single DDS clock cycle. This forces the DRG output to the
update occurs. lower limit, but the ramp accumulator is immediately made available
Event 2—An input/output update registers the digital ramp enable for normal operation. In this example, the DRCTL pin remains Logic
bit. If DRCTL = 1 is in effect (the gray portion of the DRCTL 1; therefore, the DRG output restarts the previous positive ramp
trace), the DRG output immediately begins a positive slope (the profile.
gray portion of the DRG output trace). Otherwise, if DRCTL = 0, the
DRG output is initialized to the lower limit. No-Dwell Ramp Generation
Event 3—DRCTL transitions to Logic 1 to initiate a positive slope The no-dwell high and no-dwell low bits (0x01[18:17]) add to the
at the DRG output. In this example, the DRCTL pin is held long flexibility of the DRG capabilities. During normal (default) ramp
enough to cause the DRG to reach the programmed upper limit. generation, when the DRG output reaches the programmed upper
The DRG remains at the upper limit until the ramp accumulator or lower limit, it simply remains at the limit until the operating pa-
is cleared (DRCTL = 0) or the upper limit is reprogrammed to a rameters dictate otherwise. However, during no-dwell operation, the
higher value. In the latter case, the DRG immediately resumes the DRG output does not necessarily remain at the limit. For example,
previous positive slope profile. during no-dwell high operation (0x01[18:17] = 10 (binary)), when
the DRG reaches its upper limit, the DRG immediately snaps to
Event 4—DRCTL transitions to Logic 0 to initiate a negative slope the lower limit and halts. Likewise, during no-dwell low operation
at the DRG output. In this example, the DRCTL pin is held long (0x01[18:17] = 01 (binary)), when the DRG reaches its lower limit,
enough to cause the DRG to reach the programmed lower limit. the DRG immediately snaps to the upper limit and halts. Alterna-
The DRG remains at the lower limit until DRCTL = 1, or until the tively, a continuous ramping mode is in effect when 0x01[18:17] =
lower limit is reprogrammed to a lower value. In the latter case, the 11 (binary), in which case the DRG output automatically oscillates
DRG immediately resumes the previous negative slope profile. between the upper and lower limits using the programmed slope
Event 5—DRCTL transitions to Logic 1 for the second time, initiat- parameters.
ing a second positive slope. Note that in continuous ramping mode, the DROVER signal oper-
Event 6—The positive slope profile is interrupted by DRHOLD tran- ates differently than in dwell operation. In dwell operation, the
sitioning to Logic 1. This stalls the ramp accumulator and freezes DROVER signal assumes a static Logic 1 state indicating the end
the DRG output at the last value. of the sweep. In continuous ramping mode, however, the DROVER
signal is a positive pulse (with a period of two cycles of the DDS
Event 7—DRHOLD transitions to Logic 0, releasing the ramp accu- clock) that occurs each time the DRG output reaches either of the
mulator and reinstating the previous positive slope profile. programmed limits (assuming that the DRG over output enable bit
Event 8—The clear digital ramp accumulator bit is set, which has (0x01[13]) is set).
no effect on the DRG because the bit is not effective until an A no-dwell high DRG output waveform is shown in Figure 40. The
input/output update is issued. waveform diagram assumes that the digital ramp no-dwell high bit
is set and has been registered by an input/output update. The
Data Sheet AD9914
status of the DROVER pin is also shown with the assumption that Event 5—DRCTL transitions from Logic 0 to Logic 1, which restarts
the DRG over output enable bit has been set. a positive slope ramp.
The circled numbers in Figure 40 indicate specific events, which are Event 6 and Event 7—DRCTL transitions are ignored until the DRG
explained as follows: output reaches the programmed upper limit.
Event 1—Indicates the instant that an input/output update registers Event 8—Because the digital ramp no-dwell high bit is set, the
that the digital ramp enable bit is set. moment that the DRG output reaches the upper limit, it immediately
switches to the lower limit, where it remains until the next Logic 0 to
Event 2—DRCTL transitions to Logic 1, initiating a positive slope at Logic 1 transition of DRCTL.
the DRG output.
Operation with the digital ramp no-dwell low bit set (instead of the
Event 3—DRCTL transitions to Logic 0, which has no effect on the digital ramp no-dwell high bit) is similar, except that the DRG output
DRG output. ramps in the negative direction on a Logic 1 to Logic 0 transition of
Event 4—Because the digital ramp no-dwell high bit is set, the DRCTL and jumps to the upper limit upon reaching the lower limit.
moment that the DRG output reaches the upper limit, it immediately
switches to the lower limit, where it remains until the next Logic 0 to
Logic 1 transition of DRCTL.
Figure 40. No-Dwell High Ramp Generation
Data Sheet AD9914
DROVER Pin ► Setting both no-dwell bits (0x01[18:17]) to Logic 1 disables the
frequency jump feature.
The DROVER pin provides an external signal to indicate the sweep
status of the DRG (assuming the DRG is enabled via CFR2[19] = 1
and the DROVER pin is enabled via CFR2[13] = 1). The behavior
of the DROVER pin depends on the state of the no-dwell bits
(CFR2[17:18]).
With neither no-dwell bit set (dwell operation), the DROVER pin is
Logic 1 whenever the DRG output is at the upper or lower limit Figure 41. Frequency vs. Time
(per the prevailing sweep direction). Upon initiation of a new sweep,
the DROVER pin switches to Logic 0 until the DRG output again
reaches the appropriate limit. POWER-DOWN CONTROL
With either (but not both) no-dwell bit set (no-dwell operation), the The AD9914 offers the ability to independently power down three
DROVER pin behavior is the same as for dwell operation. However, specific sections of the device. Power-down functionality applies to
the DROVER pin remains Logic 1 even after the DRG returns to the the following:
starting point as prescribed by no-dwell operation. Upon initiation of ► Digital core
a new sweep, the DROVER pin switches to Logic 0 until the DRG
► DAC
output again reaches the appropriate limit.
► Input REF CLK clock circuitry
With both no-dwell bits set (bidirectional sweep operation), instead
of providing a static indication, the DROVER pin generates a A power-down of the digital core disables the ability to update the
positive pulse for two SYNC_CLK clock cycles on the final step the serial/parallel input/output port. However, the digital power-down
DRG makes to reach either of the programmed limits. That is, a bit (0x00[7]) can still be cleared to prevent the possibility of a
positive pulse is generated each time the DRG output reaches the nonrecoverable state.
upper limit and a positive pulse each time the DRG output reaches Software power-down is controlled via three independent pow-
the lower limit. er-down bits in CFR1. Software control requires that the
EXT_PWR_DWN pin be forced to a Logic 0 state. In this case,
Frequency Jumping Capability in DRG Mode setting the desired power-down bits (0x00[7:5]) via the serial
Another feature of the AD9914 allows the user to skip a predefined input/output port powers down the associated functional block,
range of frequencies during a normal sweep. The frequency jump whereas clearing the bits restores the function.
enable bit in CFR2 (0x01[14]) enables this functionality. When this Alternatively, all three functions can be simultaneously powered
bit is set, the sweeping logic monitors the instantaneous frequency. down via external hardware control through the EXT_PWR_DWN
For example, during an up sweep, when the sweeping logic detects pin. When this pin is forced to Logic 1, all four circuit blocks are
that the next output of the DRG sweep accumulator is equal or powered down regardless of the state of the power-down bits;
exceed the frequency point defined in the lower frequency jump that is, the independent power-down bits in CFR1 are ignored and
register (0x09), instead of accumulating a delta tuning word (as in overridden when EXT_PWR_DWN is Logic 1.
normal sweeping), the output of the DRG sweep accumulator skips
directly to the frequency value set in the upper frequency jump The type of power-down activated by asserting the
register (0x0A), and vice versa for a down sweep. Figure 41 is a EXT_PWR_DWN pin depends on the state of CFR1[3]. When
frequency vs. time profile depicting an example of the behavior of CFR1[3] = 1 (default), assertion of the EXT_PWR_DWN pin
the frequency jump feature. activates full power-down mode. As such, deasserting the
EXT_PWR_DWN pin necessitates DAC calibration and, if the
A second frequency jump can also be allowed if the frequency jump PLL is enabled, VCO calibration, as well. Alternatively, when
registers are reprogrammed before the sweeping is complete. CFR1[3] = 0, assertion of the EXT_PWR_DWN pin activates
The following rules apply when this feature is enabled: fast recovery power-down mode. Fast recovery power-down mode
maintains power to the DAC bias circuitry, the PLL, VCO, and
► The frequency jump feature requires that P and N (see the DRG input clock circuitry. Because the DAC, input clock circuitry, and
Slope Control section) be greater than 2. PLL remain active in fast recovery power-down mode, it is not
► The frequency jump values must lie between the lower limit and necessary to perform DAC or VCO calibration after deasserting the
upper limit of the frequency sweep range. EXT_PWR_DWN pin when CFR1[3] = 0. Although fast recovery
► The value stored in the lower frequency jump register must be power-down mode offers only incremental power savings compared
less than the value stored in the upper frequency jump register. to full power-down mode, fast recovery power-down mode allows
the device to awaken from the power-down state very quickly.
Data Sheet AD9914
Fast recovery power-down is especially beneficial when using the

PLL, because the PLL remains locked to the input reference signal
even while the EXT_PWR_DWN pin is asserted. Note that while
the EXT_PWR_DWN pin is asserted in fast recovery power-down
mode, the DAC is not fully asleep and may exhibit unspecified
signal or noise at the output. Therefore, applications that require
a quiet DAC output during fast recovery power-down must include
external circuitry to mute the DAC output during power-down.
Data Sheet AD9914
PROGRAMMING AND FUNCTION PINS
The AD9914 is equipped with a 32-bit parallel port. The 32-bit port Note that the OSK enable bit, CFR1[8], must be set to enable
is for programming the internal registers of the device in either seri- amplitude control, as shown in Table 11.
al mode or parallel mode as well as allowing for direct modulation
control of frequency (FTW), phase (POW), and amplitude (AMP).
The state of the external function pins (F0 to F3) determines how
the 32-bit parallel port is configured. Pin 28 to Pin 31 are the
function pins. Refer to Table 11 for possible configurations.
Table 11. Parallel Port Configurations
Function Pins, 32-Bit Parallel Port Pin Assignment
F[3:0]1 Mode Description Bits[31:24]2 Bits[23:16]3 Bits[15:8]4 Bits[7:0]5
0000 Parallel programming mode Data[15:8] Data[7:0] Address[7:0] Controls writes, reads, and 8-bit or 16-bit
(optional) data-word. See the Parallel Programming
(8-/16-Bit) section for details.
0001 Serial programming mode Not used Not used Not used Controls SCLK, SDIO, SDO, CS,
and SYNCIO. See the Serial Programming
section for details.
0010 Full 32 bits of direct frequency tuning word FTW[31:24] FTW[23:16] FTW[15:8] FTW[7:0]
control. MSB and LSB aligned to parallel
port pins
0011 Full 32 bits of direct frequency tuning FTW[15:8] FTW[7:0] FTW[31:24] FTW[23:16]
word control with different parallel port pin
assignments
0100 Full 16 bits of direct phase offset control POW[15:8] POW[7:0] AMP[11:8] AMP[7:0]
and full 12 bits of direct amplitude control
0101 Full 12 bits of direct amplitude control and AMP[11:8] AMP[7:0] POW[15:8] POW[7:0]
full 16 bits of direct phase offset control
0110 24 bits of partial FTW control and 8 bits of FTW[31:24] FTW[23:16] FTW[15:8] AMP[15:8]
partial amplitude control
0111 24 bits of partial FTW control and 8 bits of FTW[31:24] FTW[23:16] FTW[15:8] POW[15:8]
partial phase offset control
1110 Not used Not used Not used Not used
1111 Not used Not used Not used Not used
1 Pin 31 to Pin 28.
2 Pin 68 to Pin 72, Pin 75 to Pin 77.
3 Pin 78 to Pin 81, Pin 87, Pin 88, Pin 1, Pin 2.
Data Sheet AD9914
Figure 42. Parallel Port Block Diagram
The 32-pin parallel port of the AD9914 works in conjunction with an parallel port are functional (Bits[4:0]). These pins provide chip
independent set of four function pins that control the functionality of select (CS), serial clock (SCLK), and input/output synchronization
the parallel port. The 32 pins of the parallel port constitute a 32-bit (SYNCIO) functionality for the serial interface, as well as two serial
word designated by Bits[31:0] (31 indicating the most significant data lines (SDO and SDIO). The serial mode supports data rates of
bit (MSB) and 0 indicating the least significant bit (LSB)), with the up to 80 Mbps for write operations (read operations are constrained
four function pins designated as F[3:0]. The relationship between to <3 Mbps).
the function pins, the 32-pin parallel port, the internal programming
registers, and the DDS control parameters (frequency, phase, and When the logic levels applied to the function pins are F[3:0] =
amplitude) is illustrated in Figure 42. Note that the parallel port 0010 to 1101 (note that 1110 and 1111 are unused), the parallel
operates in three different modes as defined by the function pins. port functions as a high speed interface with direct access to the
32-bit frequency, 16-bit phase, and 12-bit amplitude parameters
The parallel mode is in effect when the logic levels applied to the of the DDS core. The table in Figure 42 shows the segmentation
function pins are F[3:0] = 0000. This allows the parallel port to of the 32-pin parallel port by identifying Bits[31:0] with the frequen-
function as a parallel interface providing access to all of the device cy (FTW[31:0]), phase (POW[15:0]), and amplitude (AMP[15:0])
programming registers. In parallel mode, the 32-pin port (Bits[31:0]) parameters of the DDS. Note, however, that although AMP[15:0]
is subdivided into three groups with Bits[31:16] constituting 16 data indicate 16-bit resolution, the actual amplitude resolution is 12
bits, Bits[15:8] constituting eight address bits, and Bits[2:0] consti- bits. Therefore, only AMP[11:0] provide amplitude control (that is,
tuting three control bits. The address bits target a specific device AMP[15:12] are not used).
register, whereas the data bits constitute the register content. The
control bits establish read or write functionality as well as set the Furthermore, to make use of amplitude control, the user must be
width of the data bus. That is, the user can select whether the sure to program the OSK enable bit in the CFR1 register (0x00[8])
data bus spans 16 bits (Bits[31:16]) or eight bits (Bits[23:16]). The to Logic 1.
parallel mode allows the user to write to the device registers at The combination of the F[3:0] pins and Bits[31:0] provides the
rates of up to 200 MBps using 16-bit data (or 100 MBps using 8-bit AD9914 with unprecedented modulation capability by allowing the
data). user direct control of the DDS parameters (frequency, phase, ampli-
The serial mode is in effect when the logic levels applied to the tude, or various combinations thereof). Furthermore, the parallel
function pins are F[3:0] = 0001. This allows the parallel port to port operates at a sample rate equal to 1/24 of the system sample
function as a serial interface providing access to all of the device clock. This allows for updates of the DDS parameters at rates of
programming registers. In this mode, only five pins of the 32‑pin up to 145 MSPS (assuming a 3.5 GHz system clock) allowing the
Data Sheet AD9914
AD9914 to accommodate applications with wideband modulation mode of operation reduces the overall modulation rate by a factor
requirements. of three because it requires two direct mode cycles (a minimum
of two SYNC_CLK periods) followed by an IO_UPDATE assertion.
Be aware that the frequency, phase, and amplitude changes ap- However, this mode still allows modulation sample rates as high as
plied at the parallel port travel to the DDS core over different ~49 MSPS.
paths, experiencing different propagation times (latency). Therefore,
modulating more than one DDS parameter necessitates setting
the matched latency enable bit in the CFR2 register (0x01[15]) of
the device, which equalizes the latency of each DDS parameter
as it propagates from the parallel port to the DDS core. Note
that high speed modulation requires a DAC reconstruction filter
with sufficient bandwidth to accommodate the instantaneous time
domain transitions.
Because direct access to the DDS parameters occurs via the FTW,
POW, and AMP registers, the IO_UPDATE pin (see Figure 42)
adds another layer of flexibility. That is, by default, 0x00[17] = 0.
Therefore, writing data to the FTW, POW, or AMP registers does
not make the data immediately available to the DDS core. Instead,
the user must assert the IO_UPDATE pin to transfer the data from
the FTW, POW, and AMP registers to the DDS core. Asserting the
IO_UPDATE pin gives the user a level of control over the timing
of when an FTW, POW, or AMP register change is applied to the
DDS core. Note that assertion of IO_UPDATE or changing the state
of the profile select pins (PS2 to PS0) is functionally equivalent.
Furthermore, either action is gated by the rising edge of the internal
SYNC_CLK signal.
However, when the logic levels applied to the function pins (F[3:0])
= 0010 to 1101 (that is, the high speed parallel data port is active),
programming 0x00[17] = 1 activates streaming mode. In streaming
mode, data at the D[31:0] pins is transferred to the FTW, POW,
or AMP register and directly to the DDS core on each rising edge
of the internal SYNC_CLK signal. Thus, streaming mode provides
for wide band modulation by eliminating the need to assert IO_UP-
DATE.
As as example to demonstrate the flexibility of the parallel data port,
suppose an application requires frequency and amplitude modula-
tion with full 32-bit frequency resolution and full 12-bit amplitude
resolution. Note that none of the F[3:0] pin combinations supports
such modulation capability directly. To circumvent this problem, pro-
gram 0x00[17]) = 0 (that is, disable streaming mode). This setting
allows the use of two direct mode cycles of the 32-pin parallel
port, each with a different function pin setting, without affecting the
DDS core until assertion of the IO_UPDATE pin. That is, the first
direct mode cycle constitutes setting the function pins to F[3:0] =
0010, which routes all 32 bits to the FTW register (frequency).
The second direct mode cycle constitutes setting the function pins
to F[3:0] = 0100, which provides full 12-bit access to the AMP
register (amplitude). Be aware, however, that F[3:0] = 0100 also
includes the POW register (phase). Therefore, be sure keep the
phase bits unchanged from their previous value. Next, toggle the
IO_UPDATE pin, which synchronously (on the rising edge of the
internal SYNC_CLK signal) transfers the new frequency and phase
values from the FTW and POW registers to the DDS core. This
Data Sheet AD9914
SERIAL PROGRAMMING
To enable SPI operations, set Pin 28 (F0) to logic high and Pin 29 After a write cycle, the programmed data resides in the serial port
to Pin 31 (F1 to F3) to logic low. To program the AD9914 with a buffer and is inactive. I/O_UPDATE transfers data from the serial
parallel interface, see the Parallel Programming (8-/16-Bit) section. port buffer to active registers. The input/output update can be sent
either after each communication cycle or when all serial operations
CONTROL INTERFACE—SERIAL INPUT/ are complete. In addition, a change in profile pins can initiate an
OUTPUT input/output update.
The AD9914 serial port is a flexible, synchronous serial commu- For a read cycle, Phase 2 is the same as the write cycle with the
nications port allowing easy interface to many industry-standard following differences: data is read from the active registers, not the
microcontrollers and microprocessors. The serial input/output is serial port buffer, and data is driven out on the falling edge of SCLK.
compatible with most synchronous transfer formats.
Note that, to read back any profile register (0x0B to 0x1A), the
The interface allows read/write access to all registers that configure three external profile pins must be used. For example, if the profile
the AD9914. MSB-first or LSB-first transfer formats are supported. register is Profile 5 (0x15), the PS[0:2] pins must equal 101.This is
In addition, the serial interface port can be configured as a single not required to write to the profile registers.
pin input/output (SDIO) allowing a 2-wire interface, or it can be
configured as two unidirectional pins for input/output (SDIO and INSTRUCTION BYTE
SDO), enabling a 3-wire interface. Two optional pins (I/O_SYNC The instruction byte contains the following information as shown in
and CS) enable greater flexibility for designing systems with the the instruction byte information bit map.
AD9914.
Table 12. Serial Input/Output Pin Description Instruction Byte Information Bit Map
Pin No. Mnemonic Serial Input/Output Description
MSB LSB
18 D4/SYNCIO SYNCIO
I7 I6 I5 I4 I3 I2 I1 I0
19 D3/SDO SDO
R/W X A5 A4 A3 A2 A1 A0
20 D2/SDIO/WR SDIO
21 D1/SCLK/RD SCLK R/W—Bit 7 of the instruction byte determines whether a read or
22 D0/CS/PWD CS—chip select write data transfer occurs after the instruction byte write. Logic 1
GENERAL SERIAL INPUT/OUTPUT indicates a read operation. Logic 0 indicates a write operation.
OPERATION X—Bit 6 of the instruction byte is don’t care.
There are two phases to a serial communications cycle. The first is A5, A4, A3, A2, A1, A0—Bit 5, Bit 4, Bit 3, Bit 2, Bit 1, and Bit 0 of
the instruction phase to write the instruction byte into the AD9914. the instruction byte determine which register is accessed during the
The instruction byte contains the address of the register to be data transfer portion of the communications cycle.
accessed and defines whether the upcoming data transfer is a write
or read operation. SERIAL INPUT/OUTPUT PORT PIN
DESCRIPTIONS
For a write cycle, Phase 2 represents the data transfer between the
serial port controller to the serial port buffer. The number of bytes SCLK—Serial Clock
transferred is a function of the register being accessed. For exam-
ple, when accessing Control Function Register 2 (Address 0x01), The serial clock pin synchronizes data to and from the AD9914 and
Phase 2 requires that four bytes be transferred. Each bit of data is to run the internal state machines.
registered on each corresponding rising edge of SCLK. The serial
port controller expects that all bytes of the register be accessed; CS—Chip Select Bar
otherwise, the serial port controller is put out of sequence for the
CS is an active low input that allows more than one device on
next communication cycle. However, one way to write fewer bytes
the same serial communications line. The SDO and SDIO pins go
than required is to use the SYNCIO pin feature. The SYNCIO pin
to a high impedance state when this input is high. If driven high
function can abort an input/output operation and reset the pointer
during any communications cycle, that cycle is suspended until CS
of the serial port controller. After a SYNCIO, the next byte is the
is reactivated low. Chip select (CS) can be tied low in systems that
instruction byte. Note that every completed byte written prior to a
maintain control of SCLK.
SYNCIO is preserved in the serial port buffer. Partial bytes written
are not preserved. At the completion of any communication cycle,
SDIO—Serial Data Input/Output
the AD9914 serial port controller expects the next eight rising SCLK
edges to be the instruction byte for the next communication cycle. Data is always written into the AD9914 on this pin. However, this
pin can be used as a bidirectional data line. Bit 1 of CFR1 (0x00)
Data Sheet AD9914
SERIAL PROGRAMMING
controls the configuration of this pin. The default is Logic 0, which SERIAL INPUT/OUTPUT TIMING DIAGRAMS
configures the SDIO pin as bidirectional.
Figure 43 through Figure 46 provide basic examples of the tim-
SDO—Serial Data Out ing relationships between the various control signals of the serial
input/output port. Most of the bits in the register map are not trans-
Data is read from this pin for protocols that use separate lines ferred to the internal destinations until assertion of an input/output
for transmitting and receiving data. When the AD9914 operates in update, which is not included in the timing diagrams that follow.
single bidirectional input/output mode, this pin does not output data
and is set to a high impedance state. Note that the SCLK stall condition between the instruction byte
cycle and data transfer cycle in Figure 43 to Figure 46 is not
required.
SYNCIO—Input/Output Reset
MSB/LSB TRANSFERS
SYNCIO synchronizes the input/output port state machines without
affecting the contents of the addressable registers. An active high The AD9914 serial port can support both most significant bit (MSB)
input on the SYNCIO pin causes the current communication cycle first or least significant bit (LSB) first data formats. This functionality
to abort. After SYNCIO returns low (Logic 0), another communica- is controlled by Bit 0 in CFR1 (0x00). The default format is MSB
tion cycle can begin, starting with the instruction byte write. first. If LSB first is active, all data, including the instruction byte,
must follow LSB-first convention. Note that the highest number
I/O_UPDATE—Input/Output Update found in the bit range column for each register is the MSB, and the
lowest number is the LSB for that register.
The input/output update initiates the transfer of written data from
the serial or parallel input/output port buffer to active registers.
I/O_UPDATE is active on the rising edge, and the pulse width must
be greater than one SYNC_CLK period.
Figure 43. Serial Port Write Timing, Clock Stall Low
Figure 44. 3-Wire Serial Port Read Timing, Clock Stall Low
Figure 45. Serial Port Write Timing, Clock Stall High
Figure 46. 2-Wire Serial Port Read Timing, Clock Stall High
Data Sheet AD9914
PARALLEL PROGRAMMING (8-/16-BIT)
The state of the external function pins (F0 to F3) determine the type Table 13. Parallel Port Read Timing (See Figure 47)
of interface used by the AD9914. Pin 28 to Pin 31 are dedicated Parameter Value Unit Test Conditions/Comments
function pins. To enable the parallel mode interface set Pin 28 to tAHD 0 ns min Address hold time to RD signal
Pin 31 to logic low. inactive
Parallel programming consists of eight address lines and either tRDLOV 69 ns max RD low to output valid
eight or 16 bidirectional data lines for read/write operations. The tRDHOZ 50 ns max RD high to data three-state
logic state on Pin 22 determines the width of the data bus used. tRDLOW 69 ns max RD signal minimum low time
A logic low on Pin 22 sets the data width to eight bits, and logic tRDHIGH 50 ns max RD signal minimum high time
high sets the data width to 16 bits. In addition, parallel mode has Table 14. Parallel Port Write Timing (See Figure 48)
dedicated write/read control inputs. If 16-bit mode is used, the
Parameter Value Unit Test Conditions/Comments
upper byte, Bits[15:8], goes to the addressed register and the lower
byte, Bits[7:0], goes to the adjacent lower address. tASU 1 ns Address setup time to WR signal active
tDSU 3.8 ns Data setup time to WR signal active
Parallel input/output operation allows write access to each byte of tAHD 0 ns Address hold time to WR signal inactive
any register in a single input/output operation. Readback capability tDHD 0 ns Data hold time to WR signal inactive
for each register is included to ease designing with the AD9914. tWRLOW 2.1 ns WR signal minimum low time
Table 13. Parallel Port Read Timing (See Figure 47) tWRHIGH 3.8 ns WR signal minimum high time
Parameter Value Unit Test Conditions/Comments tWR 10.5 ns Minimum write time
tADV 92 ns max Address to data valid time
Figure 47. Parallel Port Read Timing Diagram
Figure 48. Parallel Port Write Timing Diagram
Data Sheet AD9914
REGISTER MAP AND BIT DESCRIPTIONS
Table 15. Register Map

Bit Range Default
Register Name (Parallel Bit 7 Value
(Serial Address) Address) (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) (Hex)1
CFR1—Control [7:0](0x00) Digital DAC power- REF CLK Open External power- Open SDIO input LSB first 0x08
Function Register power- down input power- down control only mode
1 (0x00) down down
[15:8] Load LRR Autoclear Autoclear Clear digital Clear phase Open External OSK OSK enable 0x00
(0x01) on input/ digital ramp phase ramp accumulator enable
output accumulator accumulator accumulator
update
[23:16] Open Parallel port Enable sine 0x01
(0x02) streaming output
enable
[31:24] Open VCO cal 0x00
(0x03) enable
CFR2—Control [7:0](0x04) Open 0x00
Function Register [15:8] Matched Frequency DRG over Open SYNC_CLK SYNC_CLK Reserved Open 0x09
2 (0x01) (0x05) latency jump enable output enable enable invert
enable
[23:16] Profile Parallel data Digital ramp destination Digital ramp Digital ramp Digital ramp Programmable 0x00
(0x06) mode port enable enable no-dwell high no-dwell low modulus
enable enable
[31:24] Open 0x00
(0x07)
CFR3—Control [7:0](0x08) Open Manual ICP ICP[2:0] Lock detect Minimum LDW[1:0] 0x1C
Function Register selection enable
3 (0x02) [15:8] Feedback Divider N[7:0] 0x19
(0x09)
[23:16] Open PLL input PLL input divide value[1:0] PLL input PLL enable PLL input PLL edge 0x00
(0x0A) divider reset doubler select divider select select
[31:24] Open 0x00
(0x0B)
CFR4—Control [7:0](0x0C) Requires register default value settings (0x20) 0x20
Function Register [15:8] Requires register default value settings (0x21) 0x21
4 (0x03) (0x0D)
[23:16] Requires register default value settings (0x05) 0x05
(0x0E)
[31:24] Open Auxiliary DAC CAL DAC CAL 0x00
(0x0F) divider clock power- enable2
power-down down
Digital Ramp [7:0] (0x10) Digital ramp lower limit[7:0] 0x00
Lower Limit [15:8] (0x11) Digital ramp lower limit[15:8] 0x00
Register (0x04)
[23:16] Digital ramp lower limit[23:16] 0x00
(0x12)
[31:24] Digital ramp lower limit[31:24] 0x00
(0x13)
Digital Ramp [7:0] (0x14) Digital ramp upper limit[7:0] 0x00
Upper Limit [15:8] Digital ramp upper limit[15:8] 0x00
Register (0x05) (0x15)
[23:16] Digital ramp upper limit[23:16] 0x00
(0x16)
[31:24] Digital ramp upper limit[31:24] 0x00
(0x17)
Data Sheet AD9914

Bit Range Default
Rising Digital [7:0] (0x18) Rising digital ramp increment step size[7:0] N/A
Ramp Step Size [15:8] Rising digital ramp increment step size[15:8] N/A
[23:16] Rising digital ramp increment step size[23:16] N/A
(0x1A)
[31:24] Rising digital ramp increment step size[31:24] N/A
(0x1B)
Falling Digital [7:0] (0x1C) Falling digital ramp decrement step size[7:0] N/A
Ramp Step Size [15:8] Falling digital ramp decrement step size[15:8] N/A
Register (0x07) (0x1D)
[23:16] Falling digital ramp decrement step size[23:16] N/A
(0x1E)
[31:24] Falling digital ramp decrement step size[31:24] N/A
(0x1F)
Digital Ramp [7:0] (0x20) Digital ramp positive slope rate[7:0] N/A
Rate Register [15:8] Digital ramp positive slope rate[15:8] N/A
(0x08) (0x21)
[23:16] Digital ramp negative slope rate[7:0] N/A
(0x22)
[31:24] Digital ramp negative slope rate[15:8] N/A
(0x23)
Lower Frequency [7:0] (0x24) Lower frequency jump point[7:0] 0x00
Jump Register [15:8] Lower frequency jump point[15:8] 0x00
(0x09) (0x25)
[23:16] Lower frequency jump point[23:16] 0x00
(0x26)
[31:24] Lower frequency jump point[31:24] 0x00
(0x27)
Upper Frequency [7:0] (0x28) Upper frequency jump point[7:0] 0x00
Jump Register [15:8] Upper frequency jump point[15:8] 0x00
(0x0A) (0x29)
[23:16] Upper frequency jump point[23:16] 0x00
(0x2A)
[31:24] Upper frequency jump point[31:24] 0x00
(0x2B)
Profile 0 (P0) [7:0] (0x2C) Frequency Tuning Word 0[7:0] 0x00
Frequency Tuning [15:8] Frequency Tuning Word 0[15:8] 0x00
Word 0 Register (0x2D)
(0x0B)
[23:16] Frequency Tuning Word 0[23:16] 0x00
(0x2E)
[31:24] Frequency Tuning Word 0[31:24] 0x00
(0x2F)
Profile 0 (P0) [7:0] (0x30) Phase Offset Word 0[7:0] 0x00
Phase/Amplitude [15:8] Phase Offset Word 0[15:8] 0x00
Register (0x0C) (0x31)
[23:16] Amplitude Scale Factor 0[7:0] 0x00
(0x32)
[31:24] Open Amplitude Scale Factor 0[11:8] 0x00
(0x33)
Data Sheet AD9914

Bit Range Default
Profile 1 (P1) [7:0] (0x34) Frequency Tuning Word 1[7:0] N/A
Frequency Tuning [15:8] Frequency Tuning Word 1[15:8] N/A
Word 1 Register (0x35)
(0x0D)
[23:16] Frequency Tuning Word 1[23:16] N/A
(0x36)
(0x37)
Profile 1 (P1) [7:0] (0x38) Phase Offset Word 1[7:0] N/A
Phase/Amplitude [15:8] Phase Offset Word 1[15:8] N/A
Register (0x0E) (0x39)
[23:16] Amplitude Scale Factor 1[7:0] N/A
(0x3A)
[31:24] Open Amplitude Scale Factor 1[11:8] N/A
(0x3B)
Profile 2 (P2) [7:0] (0x3C) Frequency Tuning Word 2[7:0] N/A
(0x0F)
(0x3E)
(0x3F)
(0x42)
(0x43)
(0x11)
(0x46)
(0x47)
(0x4A)
(0x4B)
(0x13)
(0x4E)
(0x4F)
Data Sheet AD9914

Bit Range Default
(0x52)
(0x53)
(0x15)
(0x56)
(0x57)
(0x5A)
(0x5B)
(0x17)
(0x5E)
(0x5F)
(0x62)
[31:24] Open Amplitude Scale Factor 6[11:8] n/a
(0x63)
(0x19)
(0x66)
(0x67)
Register (0x1A) (0x69)
(0x6A)
(0x6B)
Data Sheet AD9914

Bit Range Default
USR0 (0x1B) [7:0] (0x6C) Requires register default value settings (0x00) 0x00
(0x6D)
(0x6E)
[31:24] Open PLL lock Read only
(0x6F)
1 A master reset is required after power up. The master reset returns the internal registers to the default values.
2 The DAC CAL enable bit must be manually set and then cleared after each power-up and every time REF CLK or the internal system clock is changed. This initiates an
internal calibration routine to optimize the setup and hold times for internal DAC timing. Failure to calibrate degrades ac performance or makes the device nonfunctional.
REGISTER BIT DESCRIPTIONS

The serial input/output port registers span an address range of 0 to
27 (0x00 to 0x1B in hexadecimal notation). This represents a total
of 28 individual serial registers. If programming in parallel mode,
the number of parallel registers increases to 112 individual parallel
registers. Additionally, the registers are assigned names according
to the functionality. In some cases, a register is given a mnemonic
descriptor. For example, the register at Serial Address 0x00 is
named Control Function Register 1 and is assigned the mnemonic
CFR1.
This section provides a detailed description of each bit in the
AD9914 register map. For cases in which a group of bits serves a
specific function, the entire group is considered a binary word and
is described in aggregate.
This section is organized in sequential order of the serial addresses
of the registers. Each subheading includes the register name and
optional register mnemonic (in parentheses). Also given is the serial
address in hexadecimal format and the number of bytes assigned
to the register.
Following each subheading is a table containing the individual bit
descriptions for that particular register. The location of the bit(s) in
the register is indicated by a single number or a pair of numbers
separated by a colon; that is, a pair of numbers (A:B) indicates a
range of bits from the most significant (A) to the least significant (B).
For example, [5:2] implies Bit Position 5 to Bit Position 2, inclusive,
with Bit 0 identifying the LSB of the register.
Unless otherwise stated, programmed bits are not transferred to the
internal destinations until the assertion of the I/O_UPDATE pin or a
profile pin change.
Data Sheet AD9914
Control Function Register 1 (CFR1)—Address 0x00

Table 16. Bit Description for CFR1
Bits Mnemonic Description
[31:25] Open
24 VCO cal enable 1 = initializes the auto internal PLL calibration. The calibration is required if the PLL is to provide the internal system
clock. Must first be reset to Logic 0 before another calibration can be issued.
[23:18] Open Open.
17 Parallel port streaming enable 0 = the 32 bit parallel port needs an input/output update to activate or register any FTW, POW, or AMP data
presented to the 32-bit parallel port.
1 = the parallel port continuously samples data on the 32 input pins using SYNC_CLK and multiplexes the value of
FTW/POW/AMP accordingly, per the configuration of the F0 to F3 pins, without the need of an input/output update.
Data must meet the setup and hold times of the SYNC_CLK rising edge. If the function pins are used dynamically to
alter data between parameters, they must also meet the timing of the SYNC_CLK edge.
16 Enable sine output 0 = cosine output of the DDS is selected.
1 = sine output of the DDS is selected (default).
15 Load LRR on input/output update Ineffective unless CFR2[19] = 1.
0 = normal operation of the digital ramp timer (default).
1 = interrupts the digital ramp timer operation to load a new linear ramp rate (LRR) value any time I/O_UPDATE is
asserted or a PS[2:0] change occurs.
14 Autoclear digital ramp accumulator 0 = normal operation of the DRG accumulator (default).
1 = the digital ramp accumulator is reset for one cycle of the DDS clock (SYNC_CLK), after which the accumulator
automatically resumes normal operation. As long as this bit remains set, the ramp accumulator is momentarily reset
each time an input/output update is asserted or a PS[2:0] change occurs. This bit is synchronized with either an
input/output update or a PS[2:0] change and the next rising edge of SYNC_CLK.
13 Autoclear phase accumulator 0 = normal operation of the DDS phase accumulator (default).
1 = synchronously resets the DDS phase accumulator anytime I/O_UPDATE is asserted or a profile change occurs.
12 Clear digital ramp accumulator 0 = normal operation of the digital ramp generator (default).
1 = asynchronous, static reset of the DRG accumulator. The ramp accumulator remains reset as long as this bit
remains set. This bit is synchronized with either an input/output update or a PS[2:0] change and the next rising edge
of SYNC_CLK.
11 Clear phase accumulator 0 = normal operation of the DDS phase accumulator (default).
1 = asynchronous, static reset of the DDS phase accumulator as long as this bit is set. This bit is synchronized with
either an input/output update or a PS[2:0] change and the next rising edge of SYNC_CLK.
10 Open Open.
9 External OSK enable 0 = manual OSK enabled (default).
1 = automatic OSK enabled.
Ineffective unless CFR1[8] = 1.
8 OSK enable 0 = OSK disabled (default).
1 = OSK enabled. This bit must be set to affect any digital amplitude change using the DRG, a profile, direct mode
via the 32-bit parallel port, or OSK pin.
7 Digital power-down This bit is effective without the need for an input/output update.
0 = clock signals to the digital core are active (default).
1 = clock signals to the digital core are disabled.
6 DAC power-down 0 = DAC clock signals and bias circuits are active (default).
1 = DAC clock signals and bias circuits are disabled.
5 REFCLK input power-down This bit is effective without the need for an input/output update.
0 = REFCLK input circuits and PLL are active (default).
1 = REFCLK input circuits and PLL are disabled.
4 Open Open.
3 External power-down control 0 = assertion of the EXT_PWR_DWN pin affects fast recovery power-down.
Data Sheet AD9914
Table 16. Bit Description for CFR1

Bits Mnemonic Description
1 = assertion of the EXT_PWR_DWN pin affects power-down.
2 Open Open.
1 SDIO input only 0 = configures the SDIO pin for bidirectional operation; 2-wire serial programming
mode (default).
1 = configures the serial data input/output pin (SDIO) as an input only pin; 3-wire serial
programming mode.
0 LSB first mode 0 = configures the serial input/output port for MSB-first format (default).
1 = configures the serial input/output port for LSB-first format.

Table 17. Bit Descriptions for CFR2
Bit(s) Mnemonic Description
[31:24] Open Open.
23 Profile mode enable 0 = disables profile mode functionality (default).
1 = enables profile mode functionality. Profile pins select the desired profile.
22 Parallel data port enable See the Parallel Data Port Modulation Mode section for more details.
0 = disables parallel data port modulation functionality (default).
1 = enables parallel data port modulation functionality.
[21:20] Digital ramp destination See Table 9 for details. Default is 00. See the Digital Ramp Generator (DRG) section for more details.
19 Digital ramp enable 0 = disables digital ramp generator functionality (default).
1 = enables digital ramp generator functionality.
18 Digital ramp no-dwell high See the Digital Ramp Generator (DRG) section for details.
0 = disables no-dwell high functionality (default).
1 = enables no-dwell high functionality.
17 Digital ramp no-dwell low See the Digital Ramp Generator (DRG) section for details.
0 = disables no-dwell low functionality (default).
1 = enables no-dwell low functionality.
16 Programmable modulus enable 0 = disables programmable modulus.
1 = enables programmable modulus.
15 Matched latency enable 0 = simultaneous application of amplitude, phase, and frequency changes to the DDS arrive at the output at different
times based on their individual path latency listed in Table 2 under data latency (pipe line delay)(default).
1 = simultaneous application of amplitude, phase, and frequency changes to the DDS arrive at the output
simultaneously.
14 Frequency jump enable 0 = disables frequency jump mode (default).
1 = enables frequency jump mode. Must have the digital generator DRG enabled for this feature.
13 DRG over output enable 0 = disables the DROVER output.
1 = enables the DROVER output.
12 Open Open.
11 SYNC_CLK enable 0 = the SYNC_CLK pin is disabled and forced to a static Logic 0 state; the internal clock signal continues to operate
and provide timing.
1 = the internal SYNC_CLK signal appears at the SYNC_CLK pin (default).
10 SYNC_CLK invert 0 = normal SYNC_CLK pin polarity (default).
1 = inverted SYNC_CLK pin polarity.
9 Reserved Keep logic 0.
[8:0] Open Open.
Data Sheet AD9914

Table 18. Bit Descriptions for CFR3
[31:23] Open Open.
22 PLL input divider reset 0 = disables the PLL input divider reset function.
1 = resets the PLL input divider.
[21:20] PLL input divide value Divides the input REF CLK signal to the PLL by one of three values (2, 4, 8). Bit 17 must be set to Logic 1 to use the
PLL input divider.
00 = disable divider.
01 = divide by 2.
10 = divide by 4.
11 = divide by 8.
19 PLL input doubler select 0 = selects the feedthrough path.
1 = selects the 2× path.
This bit is only meaningful when CFR3[18] = 1 and CFR3[17] = 0.
18 PLL enable 0 = disables the internal PLL.
1 = enables the internal PLL for generating the system clock (the PLL must be calibrated via CFR1[24]).
17 PLL input divider select 0 = Selects the feed through and 2× multiplier paths.
1 = selects the PLL input divider path.
This bit is only meaningful when CFR3[18] = 1.
16 PLL edge select 0 = select rising edge.
1 = select falling edge.
This bit is only meaningful when CFR3[18] = 1, CFR3[17] = 0 and CFR3[19] = 0. The PLL locks to the selected edge of
REF_CLK.
[15:8] Feedback divider N The N divider value in Bits[15:8] is one part of the total PLL multiplication available. The second part is the fixed divide
by two element in the feedback path. Therefore, the total PLL multiplication value is 2N. The valid N divider range is
10× to 255×. The default N value for Bits[15:8] = 25, which sets the total default PLL multiplication to 50× or 2N.
7 Open Open.
6 Manual ICP selection 0 = the internal charge pump current is chosen automatically during the VCO calibration routine (default).
1 = the internal charge pump is set manually per Table 7.
[5:3] ICP Manual charge pump current selection. See Table 7.
2 Lock detect enable 0 = disables PLL lock detection.
1 = enables PLL lock detection.
[1:0] Minimum LDW Selects the number of REF CLK cycles that the phase error (at the PFD inputs) must remain within before a PLL lock
condition can be read back via Bit 24 in Register 0x00.
00 = 128 REF CLK cycles.

Table 19. Bit Descriptions for DAC
[31:27] Open Open.
26 Auxiliary divider power‑down 0 = enables the SYNC OUT circuitry.1 = disables the SYNC OUT circuitry.
25 DAC CAL clock power‑down 0 = enables the DAC CAL clock if Bit 26 in Register 0x03 is Logic 0.1 = disables the DAC CAL clock.
24 DAC CAL enable 1 = initiates an auto DAC calibration. The DAC CAL calibration is required at power-up and any time the internal
system clock is changed.
[23:0] (See description) These bits must always be programmed with the default values listed in the default column in Table 15.
Data Sheet AD9914
Digital Ramp Lower Limit Register—Address 0x04

This register is effective only if the digital ramp enable bit in the CFR2 register (0x01[19]) = 1. See the Digital Ramp Generator (DRG) section
for details.
Table 20. Bit Descriptions for Digital Ramp Lower Limit Register
[31:0] Digital ramp lower limit 32-bit digital ramp lower limit value.
Digital Ramp Upper Limit Register—Address 0x05

for details.
Table 21. Bit Descriptions for Digital Ramp Limit Register

[31:0] Digital ramp upper limit 32-bit digital ramp upper limit value.
Rising Digital Ramp Step Size Register—Address 0x06

for details.
Table 22. Bit Descriptions for Rising Digital Ramp Step Size Register
[31:0] Rising digital ramp increment step 32-bit digital ramp increment step size value.
size
Falling Digital Ramp Step Size Register—Address 0x07

for details.
Table 23. Bit Descriptions for Falling Digital Ramp Step Size Register
[31:0] Falling digital ramp decrement step 32-bit digital ramp decrement step size value.
size
Digital Ramp Rate Register—Address 0x08

for details.
Table 24. Bit Descriptions for Digital Ramp Rate Register

[31:16] Digital ramp negative slope rate 16-bit digital ramp negative slope value that defines the time interval between decrement values.
[15:0] Digital ramp positive slope rate 16-bit digital ramp positive slope value that defines the time interval between increment values.
Lower Frequency Jump Register—Address 0x09

This register is effective only if the digital ramp enable bit (0x01[19]) = 1, the frequency jump enable bit (0x01[14]) = 1 in the CFR2 register, and
at least one of the no-dwell bits (CFR2[18:17]) is Logic 0. See the Digital Ramp Generator (DRG) section for details.
Data Sheet AD9914
Table 25. Bit Descriptions for Lower Frequency Jump Register

[31:0] Lower frequency jump point 32-bit digital lower frequency jump value. During a rising frequency sweep, when the lower frequency jump value is
reached, the output frequency jumps to the upper frequency jump value instantaneously and continues frequency
sweeping in a phase-continuous manner. During a falling frequency sweep, when the upper frequency jump value
is reached, the output frequency jumps to the lower frequency jump value instantaneously and continues frequency
sweeping in a phase-continuous manner.
Upper Frequency Jump Register—Address 0x0A

This register is effective only if the digital ramp enable bit (0x01[19]) = 1, the frequency jump enable bit (0x01[14]) = 1 in the CFR2 register, and
at least one of the no-dwell bits (CFR2[18:17]) is Logic 0. See the Digital Ramp Generator (DRG) section for details.
Table 26. Bit Descriptions for Upper Frequency Jump Register

[31:0] Upper frequency jump point 32-bit digital upper frequency jump value. During a rising frequency sweep, when the lower frequency jump
value is reached, the output frequency jumps to the upper frequency jump value instantaneously and continues
frequency sweeping in a phase-continuous manner. During a falling frequency sweep, when the upper frequency
jump value is reached, the output frequency jumps to the lower frequency jump value instantaneously and
continues frequency sweeping in a phase-continuous manner.
Profile Registers
There are 16 serial input/output addresses (Address 0x0B to Address 0x01A) dedicated to device profiles. Eight of the 16 profiles house up
to eight single tone frequencies. The remaining eight profiles contain the corresponding phase offset and amplitude parameters relative to the
profile pin setting.
To enable profile mode, set the profile mode enable bit in CFR2 (0x01[23]) = 1. The active profile register is selected using the external PS[2:0]
pins.
Profile 0 to Profile 7, Single Tone Registers—0x0B, 0x0D, 0x0F, 0x11, 0x13, 0x15, 0x17, 0x19
Four bytes are assigned to each register.
Table 27. Bit Descriptions for Profile 0 to Profile 7 Single Tone Registers
[31:0] Frequency tuning word This 32-bit number controls the DDS frequency.
Profile 0 to Profile 7, Phase Offset and Amplitude Registers—0x0C, 0x0E, 0x10, 0x12, 0x14, 0x16,
0x18, 0x1A
Four bytes are assigned to each register.
Table 28. Bit Descriptions for Profile 0 to Profile 7 Phase Offset and Amplitude Registers
[31:28] Open Open.
[27:16] Amplitude scale factor This 12-bit word controls the DDS amplitude. Note that the OSK enable bit (0x00[8]) must be set to logic high to make amplitude
adjustments.
[15:0] Phase offset word This 16-bit word controls the DDS phase offset.
Data Sheet AD9914
USR0 Register—Address 0x1B

Table 29. Bit Descriptions for USR0 Register
[31:25] Open
24 PLL lock This is a readback bit only. If Logic 1 is read back, the PLL is locked. Logic 0 represents a nonlocked state.
[23:0] (See description) These bits must always be programmed with the default values listed in the default column in Table 15.
Data Sheet AD9914
OUTLINE DIMENSIONS
Figure 49. 88-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

12 mm × 12 mm Body, Very Thin Quad
(CP-88-5)
Dimensions shown in millimeters
Updated: June 13, 2022

ORDERING GUIDE
Package
Model1 Temperature Range Package Description Packing Quantity Option
AD9914BCPZ -40°C to +85°C 88-Lead LFCSP (12mm x 12mm w/ EP) CP-88-5
AD9914BCPZ-REEL7 -40°C to +85°C 88-Lead LFCSP (12mm x 12mm w/ EP) Reel, 400 CP-88-5
1 Z = RoHS Compliant Part.
EVALUATION BOARDS
Table 30. Evaluation Boards
Parameter1 Description
AD9914/PCBZ Evaluation Board
1 Z = RoHS Compliant Part.
©2012-2022 Analog Devices, Inc. All rights reserved. Trademarks and Rev. G | 48 of 48
registered trademarks are the property of their respective owners.
One Analog Way, Wilmington, MA 01887-2356, U.S.A.

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Data Sheet

FEATURES FUNCTIONAL BLOCK DIAGRAM

Features................................................................ 1 12-Bit DAC Output............................................21

Changes to Figure 39.................................................................................................................................... 26

Figure 2. Detailed Block Diagram

Table 3. THERMAL PERFORMANCE

Figure 3. Pin Configuration

Table 5. Pin Function Descriptions

Table 5. Pin Function Descriptions

Figure 26. Measured Falling Linear Frequency Sweep

Figure 23. SYNC_OUT (fSYSCLK/384)

Figure 29. CMOS Input

Figure 27. DAC Output

Figure 30. CMOS Output

Figure 28. REF CLK input

Table 6. Data Source Priority

Figure 31. DDS Block Diagram

Figure 32. DAC Spectrum vs. Reconstruction Filter Response

CLOCK INPUT (REF_CLK/REF_CLK)

Phase-Locked Loop (PLL) Multiplier

VCO Calibration PLL Loop Filter Components

Figure 37. Digital Ramp Block Diagram

Table 10. DRCTL Pin Functionality

Figure 38. Digital Ramp Generator Detail

Figure 39. Normal Ramp Generation

Figure 40. No-Dwell High Ramp Generation

Fast recovery power-down is especially beneficial when using the

Figure 42. Parallel Port Block Diagram

Figure 43. Serial Port Write Timing, Clock Stall Low

Figure 45. Serial Port Write Timing, Clock Stall High

Figure 47. Parallel Port Read Timing Diagram

Figure 48. Parallel Port Write Timing Diagram

Table 15. Register Map

Table 15. Register Map

Table 15. Register Map

Table 15. Register Map

Table 15. Register Map

REGISTER BIT DESCRIPTIONS

Control Function Register 1 (CFR1)—Address 0x00

Table 16. Bit Description for CFR1

Control Function Register 2 (CFR2)—Address 0x01

Control Function Register 3 (CFR3)—Address 0x02

Control Function Register 4 (CFR4)—Address 0x03

Digital Ramp Lower Limit Register—Address 0x04

Digital Ramp Upper Limit Register—Address 0x05

Table 21. Bit Descriptions for Digital Ramp Limit Register

Rising Digital Ramp Step Size Register—Address 0x06

Falling Digital Ramp Step Size Register—Address 0x07

Digital Ramp Rate Register—Address 0x08

Table 24. Bit Descriptions for Digital Ramp Rate Register

Lower Frequency Jump Register—Address 0x09

Table 25. Bit Descriptions for Lower Frequency Jump Register

Upper Frequency Jump Register—Address 0x0A

Table 26. Bit Descriptions for Upper Frequency Jump Register

USR0 Register—Address 0x1B

Figure 49. 88-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

Updated: June 13, 2022

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