Adsp-Cm402f CM403F CM407F CM408F
Adsp-Cm402f CM403F CM407F CM408F
Adsp-Cm402f CM403F CM407F CM408F
Cortex-M4
TM
processor core with floating-
point unit operating at frequencies up to 240 MHz and integrat-
ing up to 384KB of SRAM memory, 2MB of flash memory,
accelerators and peripherals optimized for motor control and
photo-voltaic (PV) inverter control and an analog module con-
sisting of two 16-bit SAR-type ADCs and two 12-bit DACs. The
ADSP-CM40x family operates from a single voltage supply
(VDD_EXT/VDD_ANA), generating its own internal voltage
supplies using internal voltage regulators and an external pass
transistor.
This family of mixed-signal control processors offers low static
power consumption and is produced with a low-power and low-
voltage design methodology, delivering world class processor
and ADC performance with lower power consumption.
By integrating a rich set of industry-leading system peripherals
and memory (shown in Table 1), the ADSP-CM40x mixed-sig-
nal control processors are the platform of choice for
next-generation applications that require RISC programmabil-
ity, advanced communications and leading-edge signal
processing in one integrated package. These applications span a
wide array of markets including power/motor control, embed-
ded industrial, instrumentation, medical and consumer.
Each ADSP-CM40x family member contains the following
modules.
8 GP timers with PWM output
3-Phase PWM units with up to 4 output pairs per unit
2 CAN modules
1 two-wire interface (TWI) module
3 UARTs
Table 1 provides the additional product features shown by
model.
Table 1. ADSP-CM40x Family Product Features
Generic ADSP-CM402F ADSP-CM403F ADSP-CM407F ADSP-CM408F
Package 120-Lead LQFP 176-Lead LQFP
GPIOs 40 91
EBIU 16-bit Asynchronous/5 Address 16-Bit Asynchronous/24 Address
ADC ENOB (no averaging) 11+ 13+ 11+ 13+
ADC Inputs 24 16
DAC Outputs 2 N/A
SPORTs 3 Half-SPORTs 4 Half-SPORTs
Ethernet N/A 1 N/A N/A 1 N/A
USB N/A 1 1 N/A 1 1
External SPI 1 2
General-Purpose Counters 2 4 (2 with dual-outputs)
Feature Set Code E F C E F A B D A B
L1 SRAM (KB) 128 128 384 128 128 384 384 128 384 384
Flash (KB) 512 256 2048 512 256 2048 2048 1024 2048 2048
Core Clock (MHz) 150 100 240 150 100 240 240 150 240 240
Model
A
D
S
P
-
C
M
4
0
2
B
S
W
Z
-
E
F
A
D
S
P
-
C
M
4
0
2
B
S
W
Z
-
F
F
A
D
S
P
-
C
M
4
0
3
B
S
W
Z
-
C
F
A
D
S
P
-
C
M
4
0
3
B
S
W
Z
-
E
F
A
D
S
P
-
C
M
4
0
3
B
S
W
Z
-
F
F
A
D
S
P
-
C
M
4
0
7
B
S
W
Z
-
A
F
A
D
S
P
-
C
M
4
0
7
B
S
W
Z
-
B
F
A
D
S
P
-
C
M
4
0
7
B
S
W
Z
-
D
F
A
D
S
P
-
C
M
4
0
8
B
S
W
Z
-
A
F
A
D
S
P
-
C
M
4
0
8
B
S
W
Z
-
B
F
Rev. PrE | Page 4 of 84 | September 2013
ADSP-CM402F/CM403F/CM407F/CM408F Preliminary Technical Data
ANALOG SUBSYSTEM
The processors contain two ADCs and two DACs. Control of
these data converters is simplified by a powerful on-chip ana-
log-to-digital conversion controller (ADCC) and a digital-to-
analog conversion controller (DACC). The ADCC and DACC
are integrated seamlessly into the software programming model,
and they efficiently manage the configuration and real-time
operation of the ADCs and DACs.
For technical details, see ADC/DAC Specifications on Page 36.
The ADCC provides the mechanism to precisely control execu-
tion of timing and analog sampling events on the ADCs. The
ADCC supports two-channel (one eachADC0, ADC1) simul-
taneous sampling of ADC inputs with TBD ps time offset
accuracy (aperture delay), and can deliver 16 channels of ADC
data to memory in 3 S. Conversion data from the ADCs may
be either routed via DMA to memory, or to a destination regis-
ter via the processor. The ADCC can be configured so that the
two ADCs sample and convert both analog inputs simultane-
ously or at different times and may be operated in asynchronous
or synchronous modes. The best performance can be achieved
in synchronous mode.
Likewise, the DACC interfaces to two DACs and has purpose of
managing those DACs. Conversion data to the DACs may be
either routed from memory through DMA, or from a source
register via the processor.
Functional operation and programming for the ADCC and
DACC are described in detail in the ADSP-CM40x Mixed-Signal
Control Processor with ARM Cortex-M4 Hardware Reference.
ADC and DAC features and performance specifications differ
by processor model. Simplified block diagrams of the ADCC,
DACC and the ADCs and DACs are shown in Figure 2 and
Figure 3.
Figure 2. CM402F/CM403F Analog Subsystem Block Diagram
DAC1
DAC0 ADC0
ADC1_VIN00
.
.
.
ADC1_VIN01
ADC1_VIN02
ADC1_VIN11
DAC1
ADC0_VIN00
.
.
.
ADC0_VIN01
ADC0_VIN02
ADC0_VIN11
DAC0
M
U
X
M
U
X
ADCC DACC
CONTROL CONTROL
MICRO
CONTROLLER
DMA
SRAM
MEMORY
DATA
VREF1
VREF0
REFCAP
BUF
BUF
BUF
BUF
BUF BUF
DAC1_VOUT
DAC0_VOUT
~
~
~
ADC1
BUF BUF
BAND
GAP
ADC/DAC
LOCAL CONTROLLER
Preliminary Technical Data
Rev. PrE | Page 5 of 84 | September 2013
ADSP-CM402F/CM403F/CM407F/CM408F
Figure 3. CM407F/CM408F Analog Subsystem Block Diagram
DAC1
DAC0
ADC1
ADC0
ADC1_VIN00
.
.
.
ADC1_VIN01
ADC1_VIN02
ADC1_VIN07
DAC1
ADC0_VIN00
.
.
.
ADC0_VIN01
ADC0_VIN02
ADC0_VIN07
DAC0
M
U
X
M
U
X
ADCC DACC
CONTROL CONTROL
MICRO
CONTROLLER
DMA
SRAM
MEMORY
DATA
VREF1
VREF0
REFCAP
BUF
BUF
BUF
BUF
BUF BUF
~
~
NOT PINNED
OUT
BUF BUF
BAND
GAP
ADC/DAC
LOCAL CONTROLLER
Rev. PrE | Page 6 of 84 | September 2013
ADSP-CM402F/CM403F/CM407F/CM408F Preliminary Technical Data
Considerations for Best Converter Performance
As with any high performance analog/digital circuit, to achieve
best performance, good circuit design and board layout prac-
tices should be followed. The power supply and its noise bypass
(decoupling), ground return paths and pin connections, and
analog/digital routing channel paths and signal shielding, are all
of first-order consideration. For application hints of design best
practice, see Figure 4 and the ADSP-CM40x Mixed-Signal Con-
trol Processor with ARM Cortex-M4 Hardware Reference.
ADC Module
The ADC module contains two 16-bit, high speed, low power
successive approximation register (SAR) ADCs, allowing for
dual simultaneous sampling with each ADC proceeded by a
12-channel multiplexer. See ADC Specifications on Page 36 for
detailed performance specifications. Input multiplexers enable
up to a combined 26 analog input sources to the ADCs (12 ana-
log inputs plus 1 DAC loopback input per ADC).
The voltage input range requirement for those analog inputs is
from 0 V to 2.5 V. All analog inputs are of single-ended design.
As with all single-ended inputs, signals from high impedance
sources are the most difficult to control, and depending on the
electrical environment, may require an external buffer circuit
for signal conditioning (Figure 5). An on-chip buffer between
the multiplexer and ADC reduces the need for additional signal
conditioning external to the processor. Additionally, each ADC
has an on-chip 2.5 V reference that can be overdriven when an
external voltage reference is preferred.
DAC Module
The DAC is a 12-bit, low power, string DAC design. The output
of the DAC is buffered, and can drive an R/C load to either
ground or V
DD_ANA
. See DAC Specifications on Page 38 for
detailed performance specifications. It should be noted that on
some models of the processor, the DAC outputs are not pinned
out. However, these outputs are always available as one of the
multiplexed inputs to the ADCs. This feature may be useful for
functional self-check of the converters.
Figure 4. Typical Power Supply Configuration
Figure 5. Equivalent Single-Ended Input (Simplified)
VDD_EXT
VDD_VREG
VDD_INT
BYP_D0
GND
VDD_ANA0
GND_ANA0
BYP_A0
VREF0
VREF_GND0
REFCAP
VREF1_GND
VREF1
BYP_A1
GND_ANA1
VDD_ANA1
V
R
E
G
C
I
R
C
U
I
T
GND_ANA
3.3V
CONNECTED
AT ONE
POINT
GND_DIG
PLANE
GND_ANA
PLANE
GND_DIG
GND_ANA2
GND_ANA3
VREG_BASE
ADSP-CM40x
ANALOG
SOURCE
TO
ADC V
IN
VDD_ANA
C
TBD
OPTIONAL
EXTERNAL
BUFFER
C
HOLD
R
TRACK
C
IN
R
IN
TBD
TBD
ADSP-CM40x
Preliminary Technical Data
Rev. PrE | Page 7 of 84 | September 2013
ADSP-CM402F/CM403F/CM407F/CM408F
Harmonic Analysis Engine (HAE)
The Harmonic Analysis Engine (HAE) block receives 8 kHz
input samples from two source signals whose frequencies are
between 45 Hz and 65 Hz. The HAE will then process the input
samples and produce output results. The output results consist
of power quality measurements of the fundamental and up to
12 additional harmonics.
SINC Filter
The SINC module processes four bit streams using a pair of
configurable SINC filters for each bitstream. The purpose of the
primary SINC filter of each pair is to produce the filtered and
decimated output for the pair. The output may be decimated to
any integer rate between 8 and 256 times lower than the input
rate. Greater decimation allows greater removal of noise and
therefore greater ENOB.
Optional additional filtering outside the SINC module may be
used to further increase ENOB. The primary SINC filter output
is accessible through transfer to processor memory, or to
another peripheral, via DMA.
Each of the four channels is also provided with a low-latency
secondary filter with programmable positive and negative over-
range detection comparators. These limit detection events can
be used to interrupt the core, generate a trigger, or signal a sys-
tem fault.
ARM CORTEX-M4 CORE
The ARM Cortex-M4, core shown in Figure 6, is a 32-bit
reduced instruction set computer (RISC). It uses a single 32-bit
bus for instruction and data. The length of the data can be eight
bits, 16 bits, or 32 bits. The length of the instruction word is
16 or 32 bits. The controller has the following features.
Cortex-M4 Architecture
Thumb-2 ISA Technology
DSP and SIMD extensions
Single cycle MAC (Up to 32 32 + 64 -> 64)
Hardware Divide Instructions
Single-precision FPU
NVIC Interrupt Controller (129 Interrupts and
16 Priorities)
Memory Protection Unit (MPU)
Full CoreSight
TM
Debug, Trace, Breakpoints, Watchpoints,
and Cross-Triggers
Microarchitecture
3-stage pipeline with branch speculation
Low-latency interrupt processing with tail chaining
Configurable For Ultra Low Power
Deep sleep mode, dynamic power management
Programmable Clock Generator Unit
EmbeddedICE
EmbeddedICE
s
)
2 4 5 10 0 6
VDD_ANA = TBD V
12
10
8
6
4
7 8 9
VDD_ANA = TBD V
Preliminary Technical Data
Rev. PrE | Page 43 of 84 | September 2013
ADSP-CM402F/CM403F/CM407F/CM408F
FLASH SPECIFICATIONS
The Flash features include:
100,000 ERASE cycles per sector
20 years data retention
Flash PROGRAM/ERASE SUSPEND Command
Table 19 lists parameters for the Flash suspend command.
Flash AC Characteristics and Operating Conditions
Table 20 identifies Flash specific operating conditions.
Table 19. Suspend Parameters
1,2,3
Parameter Condition Typ Max Units Notes
Erase to suspend Sector erase or erase resume to erase suspend 700 s 1
Program to suspend Program resume to program suspend 5 s 1
Subsector erase to suspend Subsector erase or subsector erase resume to erase suspend 50 s 1
Suspend latency Program 7 s 2
Suspend latency Subsector erase 15 s 2
Suspend latency Erase 15 s 3
1
Timing is not internally controlled.
2
Any READ command accepted.
3
Any command except the following are accepted: SECTOR, SUBSECTOR, or BULK ERASE; WRITE STATUS REGISTER.
Table 20. AC Characteristics and Operating Conditions
Parameter Symbol Min Typ
1
Max Unit
Clock frequency for all commands other than READ (SPI-ER, QIO-SPI protocol) f
C
DC 100 MHz
Clock frequency for READ commands f
R
DC 54 MHz
PAGE PROGRAM cycle time (256 bytes)
2
t
PP
0.5 5 ms
PAGE PROGRAM cycle time (n bytes)
2,3
t
PP
int(n/8) 0.015 5 ms
Subsector ERASE cycle time t
SSE
0.3 1.5 s
Sector ERASE cycle time t
SE
0.7 3 s
Bulk ERASE cycle time t
BE
170 250 s
1
Typical values given for T
J
= 25C.
2
When using the PAGE PROGRAM command to program consecutive bytes, optimized timings are obtained with one sequence including all the bytes versus several sequences
of only a few bytes (1 < n < 256).
3
int(A) corresponds to the upper integer part of A. For example int(12/8) = 2, int(32/8) = 4 int(15.3) =16.
Rev. PrE | Page 44 of 84 | September 2013
ADSP-CM402F/CM403F/CM407F/CM408F Preliminary Technical Data
ABSOLUTE MAXIMUM RATINGS
Stresses greater than those listed in the table may cause perma-
nent damage to the device. These are stress ratings only.
Functional operation of the device at these or any other condi-
tions greater than those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device
reliability.
ESD SENSITIVITY
PACKAGE INFORMATION
The information presented in Figure 32 and Table 22 provides
details about package branding. For a complete listing of prod-
uct availability, see Pre-Release Products on Page 82.
Parameter Rating
Internal Supply Voltage (V
DD_INT
) 0.33 V to +1.32 V
External (I/O) Supply Voltage (V
DD_EXT
) 0.33 V to +3.63 V
Analog Supply Voltage (V
DD_ANA
) 0.33 V to +3.63 V
Digital Input Voltage
1, 2
1
Applies to 100% transient duty cycle. For other duty cycles see Table 21.
2
Applies only when V
DD_EXT
is within specifications. When V
DD_EXT
is outside speci-
fications, the range is V
DD_EXT
0.2 Volts.
0.33 V to +3.63 V
TWI Digital Input Voltage
1, 2, 3
3
Applies to pins TWI_SCL and TWI_SDA.
0.33 V to +5.50 V
Digital Output Voltage Swing 0.33 V to V
DD_EXT
+ 0.5 V
Analog Input Voltage 0.3 V to V
REF0
/V
REF1
+ 0.3 V
USB0_Dx Input 0.33 V to +5.25 V
USB0_VBUS Input Voltage 0.33 V to +6.00 V
Storage Temperature Range 65C to +150C
Junction Temperature Under Bias +125 C
Table 21. Maximum Duty Cycle for Input Transient Voltage
1
1
Applies to all signal pins with the exception of SYS_CLKIN, SYS_XTAL.
V
IN
Min (V) V
IN
Max (V) Maximum Duty Cycle
TBD TBD TBD
TBD TBD TBD
TBD TBD TBD
TBD TBD TBD
TBD TBD TBD
Figure 32. Product Information on Package
Table 22. Package Brand Information
Brand Key Field Description
ADSP-CM40x Product Name
1
1
See available products in Pre-Release Products on Page 82.
t Temperature Range
pp Package Type
Z RoHS Compliant Designation
ccc See Ordering Guide
vvvvvv.x Assembly Lot Code
n.n Silicon Revision
yyww Date Code
ESD (electrostatic discharge) sensitive device.
Charged devices and circuit boards can discharge
without detection. Although this product features
patented or proprietary protection circuitry, damage
may occur on devices subjected to high energy ESD.
Therefore, proper ESD precautions should be taken to
avoid performance degradation or loss of functionality.
D
A
T
A
T
B
D
Preliminary Technical Data
Rev. PrE | Page 45 of 84 | September 2013
ADSP-CM402F/CM403F/CM407F/CM408F
TIMING SPECIFICATIONS
Specifications are subject to change without notice.
Clock and Reset Timing
Table 23 and Figure 33 describe clock and reset operations. Per
the CCLK, SYSCLK, SCLK, DCLK, and OCLK timing specifica-
tions in Table 17 on Page 34, combinations of
SYS_CLKIN and clock multipliers must not select clock rates in
excess of the processors maximum instruction rate.
Table 23. Clock and Reset Timing
Parameter Min Max Unit
Timing Requirements
f
CKIN
SYS_CLKIN Frequency (using a crystal)
1,
2,
3
20 50 MHz
f
CKIN
SYS_CLKIN Frequency (using a crystal oscillator)
1,
2,
3
20 60 MHz
t
CKINL
SYS_CLKIN Low Pulse
1
TBD ns
t
CKINH
SYS_CLKIN High Pulse
1
TBD ns
t
WRST
SYS_HWRST Asserted Pulse Width Low
4
11 t
CKIN
ns
1
Applies to PLL bypass mode and PLL non bypass mode.
2
The t
CKIN
period (see Figure 33) equals 1/f
CKIN
.
3
If the CGU_CTL.DF bit is set, the minimum f
CKIN
specification is 40 MHz.
4
Applies after power-up sequence is complete. See Table 24 and Figure 34 for power-up reset timing.
Figure 33. Clock and Reset Timing
SYS_CLKIN
t
WRST
t
CKIN
t
CKINL
t
CKINH
SYS_HWRST
Rev. PrE | Page 46 of 84 | September 2013
ADSP-CM402F/CM403F/CM407F/CM408F Preliminary Technical Data
Power-Up Reset Timing
In Figure 34, V
DD_SUPPLIES
are V
DD_INT
, V
DD_EXT
,
V
DD_VREG
, V
DD_ANA0
, and V
DD_ANA1
.
Table 24. Power-Up Reset Timing
Parameter Min Max Unit
Timing Requirement
t
RST_IN_PWR
SYS_HWRST Deasserted after V
DD_INT
, V
DD_EXT
, V
DD_VREG
, V
DD_ANA0
, V
DD_ANA1
, and
SYS_CLKIN are Stable and Within Specification
11 t
CKIN
ns
Figure 34. Power-Up Reset Timing
RESET
t
RST_IN_PWR
CLKIN
V
DD_SUPPLIES
Preliminary Technical Data
Rev. PrE | Page 47 of 84 | September 2013
ADSP-CM402F/CM403F/CM407F/CM408F
Asynchronous Read
Table 25. Asynchronous Memory Read (BxMODE = b#00)
Parameter Min Max Unit
Timing Requirements
t
SDATARE
DATA in Setup Before SMC0_ARE High TBD ns
t
HDATARE
DATA in Hold After SMC0_ARE High TBD ns
t
DARDYARE
SMC0_ARDY Valid After SMC0_ARE Low
1,
2
(RAT 2.5) t
SCLK
TBD ns
Switching Characteristics
t
ADDRARE
SMC0_Ax/SMC0_AMSx Assertion Before
SMC0_ARE Low
3
(PREST + RST + PREAT) t
SCLK
TBD ns
t
AOEARE
SMC0_AOE Assertion Before SMC0_ARE Low (RST + PREAT) t
SCLK
TBD ns
t
HARE
Output
4
Hold After SMC0_ARE High
5
RHT t
SCLK
TBD ns
t
WARE
SMC0_ARE Active Low Width
6
RAT t
SCLK
TBD ns
t
DAREARDY
SMC0_ARE High Delay After SMC0_ARDY
Assertion
1
2.5 t
SCLK
3.5 t
SCLK
+ TBD ns
1
SMC0_BxCTL.ARDYEN bit = 1.
2
RAT value set using the SMC_BxTIM.RAT bits.
3
PREST, RST, and PREAT values set using the SMC_BxETIM.PREST bits, SMC_BxTIM.RST bits, and the SMC_BxETIM.PREAT bits.
4
Output signals are SMC0_Ax, SMC0_AMS, SMC0_AOE, SMC0_ABEx.
5
RHT value set using the SMC_BxTIM.RHT bits.
6
SMC0_BxCTL.ARDYEN bit = 0.
Figure 35. Asynchronous Read
SMC0_ARE
SMC0_AMSx
SMC0_Ax
t
WARE
SMC0_AOE
SMC0_Dx (DATA)
SMC0_ARDY
t
AOEARE
t
ADDRARE
t
DARDYARE
t
HARE
t
HDATARE
t
DAREARDY
t
SDATARE
Rev. PrE | Page 48 of 84 | September 2013
ADSP-CM402F/CM403F/CM407F/CM408F Preliminary Technical Data
Asynchronous Flash Read
Table 26. Asynchronous Flash Read
Parameter Min Max Unit
Switching Characteristics
t
AMSADV
SMC0_Ax (Address)/SMC0_AMSx Assertion Before SMC0_AOE Low
1
PREST t
SCLK
TBD ns
t
WADV
SMC0_AOE Active Low Width
2
RST t
SCLK
TBD ns
t
DADVARE
SMC0_ARE Low Delay From SMC0_AOE High
3
PREAT t
SCLK
TBD ns
t
HARE
Output
4
Hold After SMC0_ARE High
5
RHT t
SCLK
TBD ns
t
WARE
6
SMC0_ARE Active Low Width
7
RAT t
SCLK
TBD ns
1
PREST value set using the SMC_BxETIM.PREST bits.
2
RST value set using the SMC_BxTIM.RST bits.
3
PREAT value set using the SMC_BxETIM.PREAT bits.
4
Output signals are SMC0_Ax, SMC0_AMS, SMC0_AOE.
5
RHT value set using the SMC_BxTIM.RHT bits.
6
SMC0_BxCTL.ARDYEN bit = 0.
7
RAT value set using the SMC_BxTIM.RAT bits.
Figure 36. Asynchronous Flash Read
SMC0_Ax
(ADDRESS)
t
AMSADV
t
DADVARE
t
WADV
t
WARE
t
HARE
READ LATCHED
DATA
SMC0_AMSx
(NOR_CE)
SMC0_AOE
(NOR_ADV)
SMC0_ARE
(NOR_OE)
SMC0_Dx
(DATA)
Preliminary Technical Data
Rev. PrE | Page 49 of 84 | September 2013
ADSP-CM402F/CM403F/CM407F/CM408F
Asynchronous Page Mode Read
Table 27. Asynchronous Page Mode Read
Parameter Min Max Unit
Switching Characteristics
t
AV
SMC0_Ax (Address) Valid for First Address Min Width
1
(PREST + RST + PREAT + RAT) t
SCLK
TBD ns
t
AV1
SMC0_Ax (Address) Valid for Subsequent SMC0_Ax
(Address) Min Width
PGWS t
SCLK
TBD ns
t
WADV
SMC0_AOE Active Low Width
2
RST t
SCLK
TBD ns
t
HARE
Output
3
Hold After SMC0_ARE High
4
RHT t
SCLK
TBD ns
t
WARE
5
SMC0_ARE Active Low Width
6
RAT t
SCLK
TBD ns
1
PREST, RST, PREAT and RAT values set using the SMC_BxETIM.PREST bits, SMC_BxTIM.RST bits, SMC_BxETIM.PREAT bits, and the SMC_BxTIM.RAT bits.
2
RST value set using the SMC_BxTIM.RST bits.
3
Output signals are SMC0_Ax, SMC0_AMSx, SMC0_AOE.
4
RHT value set using the SMC_BxTIM.RHT bits.
5
SMC_BxCTL.ARDYEN bit = 0.
6
RAT value set using the SMC_BxTIM.RAT bits.
Figure 37. Asynchronous Page Mode Read
SMC0_AMSx
(NOR_CE)
SMC0_ARE
(NOR_OE)
SMC0_AOE
(NOR_ADV)
SMC0_Dx
(DATA)
A0
t
WADV
t
WARE
t
HARE
D0 D1 D2 D3
A0 + 1 A0 + 2 A0 + 3
t
AV
t
AV1
t
AV1
t
AV1
READ
LATCHED
DATA
READ
LATCHED
DATA
READ
LATCHED
DATA
READ
LATCHED
DATA
SMC0_Ax
(ADDRESS)
Rev. PrE | Page 50 of 84 | September 2013
ADSP-CM402F/CM403F/CM407F/CM408F Preliminary Technical Data
Asynchronous Write
Table 28. Asynchronous Memory Write (BxMODE = b#00)
Parameter Min Max Unit
Timing Requirement
t
DARDYAWE
1
SMC0_ARDY Valid After SMC0_AWE Low
2
(WAT 2.5) t
SCLK
TBD
ns
Switching Characteristics
t
ENDAT
DATA Enable After SMC0_AMSx Assertion TBD ns
t
DDAT
DATA Disable After SMC0_AMSx Deassertion TBD ns
t
AMSAWE
SMC0_Ax/SMC0_AMSx Assertion Before SMC0_AWE
Low
3
(PREST + WST + PREAT) t
SCLK
TBD ns
t
HAWE
Output
4
Hold After SMC0_AWE High
5
WHT t
SCLK
TBD ns
t
WAWE
6
SMC0_AWE Active Low Width
2
WAT t
SCLK
TBD ns
t
DAWEARDY
1
SMC0_AWE High Delay After SMC0_ARDY Assertion 2.5 t
SCLK
3.5 t
SCLK
+ TBD ns
1
SMC_BxCTL.ARDYEN bit = 1.
2
WAT value set using the SMC_BxTIM.WAT bits.
3
PREST, WST, PREAT values set using the SMC_BxETIM.PREST bits, SMC_BxTIM.WST bits, SMC_BxETIM.PREAT bits, and the SMC_BxTIM.RAT bits.
4
Output signals are DATA, SMC0_Ax, SMC0_AMSx, SMC0_ABEx.
5
WHT value set using the SMC_BxTIM.WHT bits.
6
SMC_BxCTL.ARDYEN bit = 0.
Figure 38. Asynchronous Write
SMC0_AWE
SMC0_ABEx
SMC0_Ax
t
DARDYAWE
t
AMSAWE
t
DAWEARDY
t
ENDAT
t
DDAT
t
HAWE
t
WAWE
SMC0_AMSx
SMC0_Dx (DATA)
SMC0_ARDY
Preliminary Technical Data
Rev. PrE | Page 51 of 84 | September 2013
ADSP-CM402F/CM403F/CM407F/CM408F
Asynchronous Flash Write
All Accesses
Table 29. Asynchronous Flash Write
Parameter Min Max Unit
Switching Characteristics
t
AMSADV
SMC0_Ax/SMC0_AMSx Assertion Before SMC0_AOE Low
1
PREST t
SCLK
TBD ns
t
DADVAWE
SMC0_AWE Low Delay From SMC0_AOE High
2
PREAT t
SCLK
TBD ns
t
WADV
SMC0_AOE Active Low Width
3
WST t
SCLK
TBD ns
t
HAWE
Output
4
Hold After SMC0_AWE High
5
WHT t
SCLK
TBD ns
t
WAWE
6
SMC0_AWE Active Low Width
7
WAT t
SCLK
TBD ns
1
PREST value set using the SMC_BxETIM.PREST bits.
2
PREAT value set using the SMC_BxETIM.PREAT bits.
3
WST value set using the SMC_BxTIM.WST bits.
4
Output signals are DATA, SMC0_Ax, SMC0_AMSx, SMC0_ABEx.
5
WHT value set using the SMC_BxTIM.WHT bits.
6
SMC_BxCTL.ARDYEN bit = 0.
7
WAT value set using the SMC_BxTIM.WAT bits.
Figure 39. Asynchronous Flash Write
SMC0_AMSx
(NOR_CE)
SMC0_AWE
(NOR_WE)
SMC0_Ax
(ADDRESS)
SMC0_AOE
(NOR_ADV)
t
AMSADV
t
DADVAWE
SMC0_DX
(DATA)
t
WADV
t
WAWE
t
HAWE
Table 30. All Accesses
Parameter Min Max Unit
Switching Characteristic
t
TURN
SMC0_AMSx Inactive Width (IT + TT) t
SCLK
TBD ns
Rev. PrE | Page 52 of 84 | September 2013
ADSP-CM402F/CM403F/CM407F/CM408F Preliminary Technical Data
Serial Ports
To determine whether communication is possible between two
devices at clock speed n, the following specifications must be
confirmed: 1) frame sync delay and frame sync setup and hold,
2) data delay and data setup and hold, and 3) serial clock
(SPT_CLK) width. In Figure 40 either the rising edge or the fall-
ing edge of SPT_CLK (external or internal) can be used as the
active sampling edge.
Table 31. Serial PortsExternal Clock
Parameter Min Max Unit
Timing Requirements
t
SFSE
Frame Sync Setup Before SPT_CLK
(Externally Generated Frame Sync in either Transmit or Receive
Mode)
1
TBD ns
t
HFSE
Frame Sync Hold After SPT_CLK
(Externally Generated Frame Sync in either Transmit or Receive
Mode)
1
TBD ns
t
SDRE
Receive Data Setup Before Receive SPT_CLK
1
TBD ns
t
HDRE
Receive Data Hold After SPT_CLK
1
TBD ns
t
SCLKW
SPT_CLK Width for External SPT_CLK Data/FS Receive
2
[0.5 t
SCLK
TBD] or [TBD] ns
SPT_CLK Width for External SPT_CLK Data/FS Transmit
2
[0.5 t
SCLK
TBD] or [8TBD] ns
t
SPTCLK
SPT_CLK Period for External SPT_CLK Data/FS Receive
2
[t
SCLK
TBD] or [TBD] ns
SPT_CLK Period for External SPT_CLK Data/FS Transmit
2
[t
SCLK
TBD] or [TBD] ns
Switching Characteristics
t
DFSE
Frame Sync Delay After SPT_CLK
(Internally Generated Frame Sync in either Transmit or Receive
Mode)
3
TBD ns
t
HOFSE
Frame Sync Hold After SPT_CLK
(Internally Generated Frame Sync in either Transmit or Receive
Mode)
3
TBD ns
t
DDTE
Transmit Data Delay After Transmit SPT_CLK
3
TBD ns
t
HDTE
Transmit Data Hold After Transmit SPT_CLK
3
TBD ns
1
Referenced to sample edge.
2
Whichever is greater.
3
Referenced to drive edge.
Preliminary Technical Data
Rev. PrE | Page 53 of 84 | September 2013
ADSP-CM402F/CM403F/CM407F/CM408F
Table 32. Serial PortsInternal Clock
Parameter Min Max Unit
Timing Requirements
t
SFSI
Frame Sync Setup Before SPT_CLK
(Externally Generated Frame Sync in either Transmit or
Receive Mode)
1
TBD
ns
t
HFSI
Frame Sync Hold After SPT_CLK
(Externally Generated Frame Sync in either Transmit or
Receive Mode)
1
TBD
ns
t
SDRI
Receive Data Setup Before SPT_CLK
1
TBD ns
t
HDRI
Receive Data Hold After SPT_CLK
1
TBD ns
Switching Characteristics
t
DFSI
Frame Sync Delay After SPT_CLK (Internally Generated
Frame Sync in Transmit or Receive Mode)
2
TBD ns
t
HOFSI
Frame Sync Hold After SPT_CLK (Internally Generated
Frame Sync in Transmit or Receive Mode)
2
TBD ns
t
DDTI
Transmit Data Delay After SPT_CLK
2
TBD ns
t
HDTI
Transmit Data Hold After SPT_CLK
2
TBD ns
t
SCLKIW
SPT_CLK Width for Internal SPT_CLK Data/FS Transmit
3
[0.5 t
SCLK
TBD] or [TBD] ns
SPT_CLK Width for Internal SPT_CLK Data/FS Receive [0.5 t
SCLK
TBD] or [TBD] ns
t
SPTCLK
SPT_CLK Period for Internal SPT_CLK Data/FS Transmit
3
[t
SCLK
TBD] or [TBD] ns
t
SPTCLK
SPT_CLK Period for Internal SPT_CLK Data/FS Receive
3
[t
SCLK
TBD] or [TBD] ns
1
Referenced to the sample edge.
2
Referenced to drive edge.
3
Whichever is greater.
Rev. PrE | Page 54 of 84 | September 2013
ADSP-CM402F/CM403F/CM407F/CM408F Preliminary Technical Data
Figure 40. Serial Ports
DRIVE EDGE SAMPLE EDGE
SPT_A/BDx
(DATA CHANNEL A/B)
SPT_A/BFS
(FRAME SYNC)
SPT_A/BCLK
(SPORT CLOCK)
t
HOFSI
t
HFSI
t
HDRI
DATA RECEIVEINTERNAL CLOCK
DRIVE EDGE SAMPLE EDGE
t
HFSI
t
DDTI
DATA TRANSMITINTERNAL CLOCK
DRIVE EDGE SAMPLE EDGE
t
HOFSE
t
HOFSI
t
HDTI
t
HFSE
t
HDTE
t
DDTE
DATA TRANSMITEXTERNAL CLOCK
DRIVE EDGE SAMPLE EDGE
t
HOFSE
t
HFSE
t
HDRE
DATA RECEIVEEXTERNAL CLOCK
t
SCLKIW
t
DFSI
t
SFSI
t
SDRI
t
SCLKW
t
DFSE
t
SFSE
t
SDRE
t
DFSE
t
SFSE
t
SFSI
t
DFSI
t
SCLKIW
t
SCLKW
SPT_A/BDx
(DATA CHANNEL A/B)
SPT_A/BFS
(FRAME SYNC)
SPT_A/BCLK
(SPORT CLOCK)
SPT_A/BDx
(DATA CHANNEL A/B)
SPT_A/BFS
(FRAME SYNC)
SPT_A/BCLK
(SPORT CLOCK)
SPT_A/BDx
(DATA CHANNEL A/B)
SPT_A/BFS
(FRAME SYNC)
SPT_A/BCLK
(SPORT CLOCK)
Preliminary Technical Data
Rev. PrE | Page 55 of 84 | September 2013
ADSP-CM402F/CM403F/CM407F/CM408F
Table 33. Serial PortsEnable and Three-State
Parameter Min Max Unit
Switching Characteristics
t
DDTEN
Data Enable from External Transmit SPT_CLK
1
TBD ns
t
DDTTE
Data Disable from External Transmit SPT_CLK
1
TBD ns
t
DDTIN
Data Enable from Internal Transmit SPT_CLK
1
TBD ns
t
DDTTI
Data Disable from Internal Transmit SPT_CLK
1
TBD ns
1
Referenced to drive edge.
Figure 41. Serial PortsEnable and Three-State
DRIVE EDGE DRIVE EDGE
t
DDTIN
t
DDTEN
t
DDTTE
SPT_CLK
(SPORT CLOCK
INTERNAL)
SPT_A/BDx
(DATA
CHANNEL A/B)
SPT_CLK
(SPORT CLOCK
EXTERNAL)
SPT_A/BDx
(DATA
CHANNEL A/B)
DRIVE EDGE DRIVE EDGE
t
DDTTI
Rev. PrE | Page 56 of 84 | September 2013
ADSP-CM402F/CM403F/CM407F/CM408F Preliminary Technical Data
The SPT_TDV output signal becomes active in SPORT multi-
channel mode. During transmit slots (enabled with active
channel selection registers) the SPT_TDV is asserted for com-
munication with external devices.
Table 34. Serial PortsTDV (Transmit Data Valid)
Parameter Min Max Unit
Switching Characteristics
t
DRDVEN
Data-Valid Enable Delay from Drive Edge of External Clock
1
TBD ns
t
DFDVEN
Data-Valid Disable Delay from Drive Edge of External Clock
1
TBD ns
t
DRDVIN
Data-Valid Enable Delay from Drive Edge of Internal Clock
1
TBD ns
t
DFDVIN
Data-Valid Disable Delay from Drive Edge of Internal Clock
1
TBD ns
1
Referenced to drive edge.
Figure 42. Serial PortsTransmit Data Valid Internal and External Clock
DRIVE EDGE DRIVE EDGE
SPT_CLK
(SPORT CLOCK
EXTERNAL)
t
DRDVEN
t
DFDVEN
DRIVE EDGE DRIVE EDGE
SPT_CLK
(SPORT CLOCK
INTERNAL)
t
DRDVIN
t
DFDVIN
SPT_A/BTDV
SPT_A/BTDV
Preliminary Technical Data
Rev. PrE | Page 57 of 84 | September 2013
ADSP-CM402F/CM403F/CM407F/CM408F
Table 35. Serial PortsExternal Late Frame Sync
Parameter Min Max Unit
Switching Characteristics
t
DDTLFSE
Data Delay from Late External Transmit Frame Sync or External Receive Frame
Sync with MCE = 1, MFD = 0
1
TBD ns
t
DDTENFS
Data Enable for MCE = 1, MFD = 0
1
TBD ns
1
The t
DDTLFSE
and t
DDTENFS
parameters apply to left-justified as well as standard serial mode, and MCE = 1, MFD = 0.
Figure 43. External Late Frame Sync
DRIVE SAMPLE
2ND BIT 1ST BIT
DRIVE
t
DDTE/I
t
HDTE/I
t
DDTLFSE
t
DDTENFS
t
SFSE/I
t
HFSE/I
SPT_A/BDx
(DATA CHANNEL A/B)
SPT_A/BFS
(FRAME SYNC)
SPT_A/BCLK
(SPORT CLOCK)
Rev. PrE | Page 58 of 84 | September 2013
ADSP-CM402F/CM403F/CM407F/CM408F Preliminary Technical Data
Serial Peripheral Interface (SPI) PortMaster Timing
Table 36 and Figure 44 describe SPI port master operations.
Note that:
In dual mode data transmit the SPI_MISO signal is also an
output.
In quad mode data transmit the SPI_MISO, SPI_D2, and
SPI_D3 signals are also outputs.
In dual mode data receive the SPI_MOSI signal is also an
input.
In quad mode data receive the SPI_MOSI, SPI_D2, and
SPI_D3 signals are also inputs.
Table 36. Serial Peripheral Interface (SPI) PortMaster Timing
Parameter Min Max Unit
Timing Requirements
t
SSPIDM
Data Input Valid to SPI_CLK Edge (Data Input Setup) TBD ns
t
HSPIDM
SPI_CLK Sampling Edge to Data Input Invalid TBD ns
Switching Characteristics
t
SDSCIM
SPI_SEL low to First SPI_CLK Edge
1
[0.5 t
SCLK
TBD] or [TBD] ns
t
SPICHM
SPI_CLK High Period for Data Transmit
1
[0.5 t
SCLK
TBD] or [TBD] ns
SPI_CLK High Period for Data Receive
1
[0.5 t
SCLK
TBD] or [TBD] ns
t
SPICLM
SPI_CLK Low Period for Data Transmit
1
[0.5 t
SCLK
TBD] or [TBD] ns
SPI_CLK Low Period for Data Receive
1
[0.5 t
SCLK
TBD] or [TBD] ns
t
SPICLK
SPI_CLK Period for Data Transmit
1
[t
SCLK
TBD] or [TBD] ns
SPI_CLK Period for Data Receive
1
[t
SCLK
TBD] or [TBD] ns
t
HDSM
Last SPI_CLK Edge to SPI_SEL High 2 t
SCLK
TBD ns
t
SPITDM
Sequential Transfer Delay
1,
2
[t
SCLK
TBD] or [TBD] ns
t
DDSPIDM
SPI_CLK Edge to Data Out Valid (Data Out Delay) TBD ns
t
HDSPIDM
SPI_CLK Edge to Data Out Invalid (Data Out Hold) TBD ns
1
Whichever is greater.
2
Applies to sequential mode with STOP 1.
Preliminary Technical Data
Rev. PrE | Page 59 of 84 | September 2013
ADSP-CM402F/CM403F/CM407F/CM408F
Figure 44. Serial Peripheral Interface (SPI) PortMaster Timing
t
SDSCIM
t
SPICLK
t
HDSM
t
SPITDM
t
SPICLM
t
SPICHM
t
HDSPIDM
t
HSPIDM
t
SSPIDM
SPI_SEL
(OUTPUT)
SPI_CLK
(OUTPUT)
DATA OUTPUTS
(SPI_MOSI)
CPHA = 1
CPHA = 0
t
DDSPIDM
t
HSPIDM
t
SSPIDM
t
HDSPIDM
t
DDSPIDM
DATA INPUTS
(SPI_MISO)
DATA OUTPUTS
(SPI_MOSI)
DATA INPUTS
(SPI_MISO)
Rev. PrE | Page 60 of 84 | September 2013
ADSP-CM402F/CM403F/CM407F/CM408F Preliminary Technical Data
Serial Peripheral Interface (SPI) PortSlave Timing
Table 37 and Figure 45 describe SPI port slave operations. Note
that:
In dual mode data transmit the SPI_MOSI signal is also an
output.
In quad mode data transmit the SPI_MOSI, SPI_D2, and
SPI_D3 signals are also outputs.
In dual mode data receive the SPI_MISO signal is also an
input.
In quad mode data receive the SPI_MISO, SPI_D2, and
SPI_D3 signals are also inputs.
Table 37. Serial Peripheral Interface (SPI) PortSlave Timing
Parameter Min Max Unit
Timing Requirements
t
SPICHS
SPI_CLK High Period for Data Transmit
1
[0.5 t
SCLK
TBD] or [TBD] ns
SPI_CLK High Period for Data Receive
1
[0.5 t
SCLK
TBD] or [TBD] ns
t
SPICLS
SPI_CLK Low Period for Data Transmit
1
[0.5 t
SCLK
TBD] or [TBD] ns
SPI_CLK Low Period for Data Receive
1
[0.5 t
SCLK
TBD] or [TBD] ns
t
SPICLK
SPI_CLK Period for Data Transmit
1
[t
SCLK
TBD] or [TBD] ns
SPI_CLK Period for Data Receive
1
[t
SCLK
TBD] or [TBD] ns
t
HDS
Last SPI_CLK Edge to SPI_SS Not Asserted TBD ns
t
SPITDS
Sequential Transfer Delay 0.5 t
SPICLK
TBD ns
t
SDSCI
SPI_SS Assertion to First SPI_CLK Edge TBD ns
t
SSPID
Data Input Valid to SPI_CLK Edge (Data Input Setup) TBD ns
t
HSPID
SPI_CLK Sampling Edge to Data Input Invalid TBD ns
Switching Characteristics
t
DSOE
SPI_SS Assertion to Data Out Active TBD TBD ns
t
DSDHI
SPI_SS Deassertion to Data High Impedance TBD TBD ns
t
DDSPID
SPI_CLK Edge to Data Out Valid (Data Out Delay) TBD ns
t
HDSPID
SPI_CLK Edge to Data Out Invalid (Data Out Hold) TBD ns
1
Whichever is greater.
Preliminary Technical Data
Rev. PrE | Page 61 of 84 | September 2013
ADSP-CM402F/CM403F/CM407F/CM408F
Figure 45. Serial Peripheral Interface (SPI) PortSlave Timing
t
SPICLK
t
HDS
t
SPITDS
t
SDSCI
t
SPICLS
t
SPICHS
t
DSOE
t
DDSPID
t
DDSPID
t
DSDHI
t
HDSPID
t
SSPID
t
DSDHI
t
HDSPID
t
DSOE
t
HSPID
t
SSPID
t
DDSPID
SPI_SS
(INPUT)
SPI_CLK
(INPUT)
t
HSPID
DATA OUTPUTS
(SPI_MISO)
CPHA = 1
CPHA = 0
DATA INPUTS
(SPI_MOSI)
DATA OUTPUTS
(SPI_MISO)
DATA INPUTS
(SPI_MOSI)
Rev. PrE | Page 62 of 84 | September 2013
ADSP-CM402F/CM403F/CM407F/CM408F Preliminary Technical Data
Serial Peripheral Interface (SPI) PortSPI_RDY Slave
Timing
Table 38. SPI PortSPI_RDY Slave Timing
Parameter Min Max Unit
Switching Characteristics
t
DSPISCKRDYSR
SPI_RDY De-assertion from Valid Input SPI_CLK Edge in Slave Mode Receive 2.5 t
SCLK
3.5 t
SCLK
+ TBD ns
t
DSPISCKRDYST
SPI_RDY De-assertion from Valid Input SPI_CLK Edge in Slave Mode Transmit 3.5 t
SCLK
4.5 t
SCLK
+ TBD ns
Figure 46. SPI_RDY De-assertion from Valid Input SPI_CLK Edge in Slave Mode Receive (FCCH = 0)
Figure 47. SPI_RDY De-assertion from Valid Input SPI_CLK Edge in Slave Mode Transmit (FCCH = 1)
SPI_CLK
(CPOL = 0)
SPI_CLK
(CPOL = 1)
t
DSPISCKRDYSR
SPI_RDY (O)
SPI_CLK
(CPOL = 0)
SPI_CLK
(CPOL = 1)
CPHA = 1
CPHA = 0
SPI_CLK
(CPOL = 1)
SPI_CLK
(CPOL = 0)
t
DSPISCKRDYST
SPI_RDY (O)
SPI_CLK
(CPOL = 1)
SPI_CLK
(CPOL = 0)
CPHA = 1
CPHA = 0
Preliminary Technical Data
Rev. PrE | Page 63 of 84 | September 2013
ADSP-CM402F/CM403F/CM407F/CM408F
Serial Peripheral Interface (SPI) PortOpen Drain Mode
Timing
In Figure 48 and Figure 49, the outputs can be SPI_MOSI
SPI_MISO, SPI_D2, and/or SPI_D3 depending on the mode of
operation.
Table 39. SPI Port ODM Master Mode Timing
Parameter Min Max Unit
Switching Characteristics
t
HDSPIODMM
SPI_CLK Edge to High Impedance from Data Out Valid TBD ns
t
DDSPIODMM
SPI_CLK Edge to Data Out Valid from High Impedance TBD TBD ns
Figure 48. ODM Master
Table 40. SPI PortODM Slave Mode
Parameter Min Max Unit
Timing Requirements
t
HDSPIODMS
SPI_CLK Edge to High Impedance from Data Out Valid TBD ns
t
DDSPIODMS
SPI_CLK Edge to Data Out Valid from High Impedance TBD ns
Figure 49. ODM Slave
SPI_CLK
(CPOL = 0)
t
HDSPIODMM
SPI_CLK
(CPOL = 1)
t
DDSPIODMM
t
DDSPIODMM
t
HDSPIODMM
OUTPUT
(CPHA = 1)
OUTPUT
(CPHA = 0)
t
HDSPIODMS
t
DDSPIODMS
t
DDSPIODMS
t
HDSPIODMS
SPI_CLK
(CPOL = 0)
SPI_CLK
(CPOL = 1)
OUTPUT
(CPHA = 1)
OUTPUT
(CPHA = 0)
Rev. PrE | Page 64 of 84 | September 2013
ADSP-CM402F/CM403F/CM407F/CM408F Preliminary Technical Data
Serial Peripheral Interface (SPI) PortSPI_RDY Timing
Table 41. SPI PortSPI_RDY Timing
Parameter Min Max Unit
Timing Requirements
t
SRDYSCKM0
Minimum Setup Time for SPI_RDY De-assertion in Master
Mode Before Last SPI_CLK Edge of Valid Data Transfer to
Block Subsequent Transfer with CPHA = 0
(2.5 + 1.5 BAUD
1
) t
SCLK
+
TBD
ns
t
SRDYSCKM1
Minimum Setup Time for SPI_RDY De-assertion in Master
Mode Before Last SPI_CLK Edge of Valid Data Transfer to
Block Subsequent Transfer with CPHA = 1
(1.5 BAUD
1
) t
SCLK
+ TBD ns
Switching Characteristic
t
SRDYSCKM
Time Between Assertion of SPI_RDY by Slave and First Edge
of SPI_CLK for New SPI Transfer with CPHA = 0 and BAUD = 0
(STOP, LEAD, LAG = 0)
3 t
SCLK
4 t
SCLK
+ TBD ns
Time Between Assertion of SPI_RDY by Slave and First Edge
of SPI_CLK for New SPI Transfer with CPHA = 0 and BAUD 1
(STOP, LEAD, LAG = 0)
(4 + 1.5 BAUD
1
) t
SCLK
(5 + 1.5 BAUD
1
) t
SCLK
+
TBD
ns
Time Between Assertion of SPI_RDY by Slave and First Edge
of SPI_CLK for New SPI Transfer with CPHA = 1 (STOP, LEAD,
LAG = 0)
(3 + 0.5 BAUD
1
) t
SCLK
(4 + 0.5 BAUD
1
) t
SCLK
+
TBD
ns
1
BAUD value set using the SPI_CLK.BAUD bits.
Figure 50. SPI_RDY Setup Before SPI_CLK with CPHA = 0
Figure 51. SPI_RDY Setup Before SPI_CLK with CPHA = 1
SPI_CLK
(CPOL = 0)
SPI_CLK
(CPOL = 1)
t
SRDYSCKM0
SPI_RDY
SPI_CLK
(CPOL = 0)
SPI_CLK
(CPOL = 1)
t
SRDYSCKM1
SPI_RDY
Preliminary Technical Data
Rev. PrE | Page 65 of 84 | September 2013
ADSP-CM402F/CM403F/CM407F/CM408F
Figure 52. SPI_CLK Switching Diagram after SPI_RDY Assertion, CPHA = x
SPI_CLK
(CPOL = 0)
SPI_CLK
(CPOL = 1)
t
SRDYSCKM
SPI_RDY
Rev. PrE | Page 66 of 84 | September 2013
ADSP-CM402F/CM403F/CM407F/CM408F Preliminary Technical Data
General-Purpose Port Timing
Table 42 and Figure 53 describe general-purpose
port operations.
Timer Cycle Timing
Table 43 and Figure 54 describe timer expired operations. The
input signal is asynchronous in width capture mode and
external clock mode and has an absolute maximum input fre-
quency of (f
SCLK
/4) MHz. The Width Value value is the timer
period assigned in the TMx_TMRn_WIDTH register and can
range from 1 to 2
32
1.
Table 42. General-Purpose Port Timing
Parameter Min Max Unit
Timing Requirement
t
WFI
General-Purpose Port Pin Input Pulse Width 2 t
SCLK
ns
Figure 53. General-Purpose Port Timing
GPIO INPUT
t
WFI
Table 43. Timer Cycle Timing
Parameter Min Max Unit
Timing Requirements
t
WL
Timer Pulse Width Input Low (Measured In SCLK Cycles)
1
2 t
SCLK
ns
t
WH
Timer Pulse Width Input High (Measured In SCLK Cycles)
1
2 t
SCLK
ns
Switching Characteristics
t
HTO
Timer Pulse Width Output (Measured In SCLK Cycles) t
SCLK
Width Value TBD t
SCLK
Width Value + TBD ns
1
The minimum pulse widths apply for TMx signals in width capture and external clock modes.
Figure 54. Timer Cycle Timing
TMR OUTPUT
TMR INPUT
t
WH
, t
WL
t
HTO
Preliminary Technical Data
Rev. PrE | Page 67 of 84 | September 2013
ADSP-CM402F/CM403F/CM407F/CM408F
Up/Down Counter/Rotary Encoder Timing
Pulse Width Modulator (PWM) Timing
Table 45 and Figure 56 describe PWM operations.
Table 44. Up/Down Counter/Rotary Encoder Timing
Parameter Min Max Unit
Timing Requirement
t
WCOUNT
Up/Down Counter/Rotary Encoder Input Pulse Width 2 t
SCLK
ns
Figure 55. Up/Down Counter/Rotary Encoder Timing
CNT_UD
CNT_DG
CNT_ZM
t
WCOUNT
Table 45. PWM Timing
Parameter Min Max Unit
Timing Requirement
t
ES
External Sync Pulse Width 2 t
SCLK
ns
Switching Characteristics
t
DODIS
Output Inactive (OFF) After Trip Input
1
TBD ns
t
DOE
Output Delay After External Sync
1,
2
2 t
SCLK
+ TBD 5 t
SCLK
+ TBD ns
1
PWM outputs are: PWMx_AH, PWMx_AL, PWMx_BH, PWMx_BL, PWMx_CH, and PWMx_CL.
2
When the external sync signal is synchronous to the peripheral clock, it takes fewer clock cycles for the output to appear compared to when the external sync signal is
asynchronous to the peripheral clock. For more information, see the ADSP-CM40x Microcontroller Hardware Reference.
Figure 56. PWM Timing
PWM_TRIP
PWM_SYNC
(AS INPUT)
t
ES
t
DOE
OUTPUT
t
DODIS
Rev. PrE | Page 68 of 84 | September 2013
ADSP-CM402F/CM403F/CM407F/CM408F Preliminary Technical Data
Universal Asynchronous Receiver-Transmitter
(UART) PortsReceive and Transmit Timing
The UART ports receive and transmit operations are described
in the ADSP-CM40x Mixed-Signal Control Processor with ARM
Cortex-M4 Hardware Reference.
CAN Interface
The CAN interface timing is described in the ADSP-CM40x
Mixed-Signal Control Processor with ARM Cortex-M4 Hardware
Reference.
Universal Serial Bus (USB) On-The-GoReceive and
Transmit Timing
The USB interface timing is described in the ADSP-CM40x
Mixed-Signal Control Processor with ARM Cortex-M4 Hardware
Reference.
Preliminary Technical Data
Rev. PrE | Page 69 of 84 | September 2013
ADSP-CM402F/CM403F/CM407F/CM408F
10/100 Ethernet MAC Controller Timing
Table 46 through Table 48 and Figure 57 through Figure 59
describe the 10/100 Ethernet MAC Controller operations.
Table 46. 10/100 Ethernet MAC Controller Timing: RMII Receive Signal
Parameter
1
Min Max Unit
Timing Requirements
t
REFCLKF
ETHx_REFCLK Frequency (f
SCLK
= SCLK Frequency) None 50 + 1% MHz
t
REFCLKW
ETHx_REFCLK Width (t
REFCLK
= ETHx_REFCLK Period) t
REFCLK
35% t
REFCLK
65% ns
t
REFCLKIS
Rx Input Valid to RMII ETHx_REFCLK Rising Edge (Data In Setup) TBD ns
t
REFCLKIH
RMII ETHx_REFCLK Rising Edge to Rx Input Invalid (Data In Hold) TBD ns
1
RMII inputs synchronous to RMII REF_CLK are ERxD10, RMII CRS_DV, and ERxER.
Figure 57. 10/100 Ethernet MAC Controller Timing: RMII Receive Signal
Table 47. 10/100 Ethernet MAC Controller Timing: RMII Transmit Signal
Parameter
1
Min Max Unit
Switching Characteristics
t
REFCLKOV
RMII ETHx_REFCLK Rising Edge to Transmit Output Valid (Data Out Valid) TBD ns
t
REFCLKOH
RMII ETHx_REFCLK Rising Edge to Transmit Output Invalid (Data Out Hold) TBD ns
1
RMII outputs synchronous to RMII REF_CLK are ETxD10.
Figure 58. 10/100 Ethernet MAC Controller Timing: RMII Transmit Signal
t
REFCLKIS
t
REFCLKIH
ETHx_RXD10
ETHx_CRS
ETHx_RXERR
RMII_REF_CLK
t
REFCLKW
t
REFCLK
t
REFCLKOV
t
REFCLKOH
RMII_REF_CLK
ETHx_TXD10
ETHx_TXEN
t
REFCLK
Rev. PrE | Page 70 of 84 | September 2013
ADSP-CM402F/CM403F/CM407F/CM408F Preliminary Technical Data
Table 48. 10/100 Ethernet MAC Controller Timing: RMII Station Management
Parameter
1
Min Max Unit
Timing Requirements
t
MDIOS
ETHx_MDIO Input Valid to ETHx_MDC Rising Edge (Setup) TBD ns
t
MDCIH
ETHx_MDC Rising Edge to ETHx_MDIO Input Invalid (Hold) TBD ns
Switching Characteristics
t
MDCOV
ETHx_MDC Falling Edge to ETHx_MDIO Output Valid t
SCLK
+ TBD ns
t
MDCOH
ETHx_MDC Falling Edge to ETHx_MDIO Output Invalid (Hold) t
SCLK
TBD ns
1
ETHx_MDC/ETHx_MDIO is a 2-wire serial bidirectional port for controlling one or more external PHYs. ETHx_MDC is an output clock whose minimum period is
programmable as a multiple of the system clock SCLK. ETHx_MDIO is a bidirectional data line.
Figure 59. 10/100 Ethernet MAC Controller Timing: RMII Station Management
ETHx_MDIO
(INPUT)
ETHx_MDIO
(OUTPUT)
ETHx_MDC
(OUTPUT)
t
MDIOS
t
MDCOH
t
MDCIH
t
MDCOV
Preliminary Technical Data
Rev. PrE | Page 71 of 84 | September 2013
ADSP-CM402F/CM403F/CM407F/CM408F
JTAG Test And Emulation Port Timing
Table 49 and Figure 60 describe JTAG port operations.
Table 49. JTAG Port Timing
Parameter Min Max Unit
Timing Requirements
t
TCK
JTG_TCK Period 20 ns
t
STAP
JTG_TDI, JTG_TMS Setup Before JTG_TCK High TBD ns
t
HTAP
JTG_TDI, JTG_TMS Hold After JTG_TCK High TBD ns
t
SSYS
System Inputs Setup Before JTG_TCK High
1
TBD ns
t
HSYS
System Inputs Hold After JTG_TCK High
1
TBD ns
t
TRSTW
JTG_TRST Pulse Width (measured in JTG_TCK cycles)
2
TBD TCK
Switching Characteristics
t
DTDO
JTG_TDO Delay from JTG_TCK Low TBD ns
t
DSYS
System Outputs Delay After JTG_TCK Low
3
TBD ns
1
System Inputs = PA_150, PB_150, PC_150, PD_150, PE_150, PF_100, SYS_BMODE01, SYS_HWRST, SYS_FAULT, SYS_NMI, TWI0_SCL, TWI0_SDA.
2
50 MHz Maximum.
3
System Outputs = PA_150, PB_150, PC_150, PD_150, PE_150, PF_100, SMC0_AMS0, SMC0_ARE, SMC0_AWE, SYS_CLKOUT, SYS_FAULT, SYS_RESOUT.
Figure 60. JTAG Port Timing
JTG_TCK
JTG_TMS
JTG_TDI
JTG_TDO
SYSTEM
INPUTS
SYSTEM
OUTPUTS
t
TCK
t
STAP
t
HTAP
t
DTDO
t
SSYS
t
HSYS
t
DSYS
Rev. PrE | Page 72 of 84 | September 2013
ADSP-CM402F/CM403F/CM407F/CM408F Preliminary Technical Data
OUTPUT DRIVE CURRENTS
Figure 61 and Figure 62 show typical current-voltage character-
istics for the output drivers of the processors. The curves
represent the current drive capability of the output drivers as a
function of output voltage.
Capacitive Loading
Output delays and holds are based on standard capacitive loads
of an average of 6 pF on all pins (see Figure 63). V
LOAD
is equal
to (V
DD_EXT
)/2.
The graph of Figure 64 shows how output rise and fall times
vary with capacitance. The delay and hold specifications given
should be derated by a factor derived from these figures. The
graphs in these figures may not be linear outside the ranges
shown.
Figure 61. Driver Type A Current
Figure 62. Driver Type B Current
0
S
O
U
R
C
E
C
U
R
R
E
N
T
(
m
A
)
SOURCE VOLTAGE (V)
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
200
120
80
200
120
40
4.0
V
DDEXT
= TBDV @ 40C
V
DDEXT
= 3.3V @ 25C
80
160
40
160
V
DDEXT
= TBDV @ 105C
TBD
0
S
O
U
R
C
E
C
U
R
R
E
N
T
(
m
A
)
SOURCE VOLTAGE (V)
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
160
120
80
160
40
4.0
V
DDEXT
= TBDV @ 40C
V
DDEXT
= 3.3V @ 25C
80
120
40
V
DDEXT
= TBDV @ 105C
TBD
Figure 63. Equivalent Device Loading for AC Measurements
(Includes All Fixtures)
Figure 64. Driver Type A Typical Rise and Fall Times (10%-90%) vs. Load
Capacitance
T1
ZO = 50 (impedance)
TD = 4.04 1.18 ns
2pF
50
0.5pF
70
400
45
4pF
NOTES:
THE WORST CASE TRANSMISSION LINE DELAY IS SHOWN AND CAN BE USED
FOR THE OUTPUT TIMING ANALYSIS TO REFELECT THE TRANSMISSION LINE
EFFECT AND MUST BE CONSIDERED. THE TRANSMISSION LINE (TD), IS FOR
LOAD ONLY AND DOES NOT AFFECT THE DATA SHEET TIMING SPECIFICATIONS.
ANALOG DEVICES RECOMMENDS USING THE IBIS MODEL TIMING FOR A GIVEN
SYSTEM REQUIREMENT. IF NECESSARY, A SYSTEM MAY INCORPORATE
EXTERNAL DRIVERS TO COMPENSATE FOR ANY TIMING DIFFERENCES.
V
LOAD
DUT
OUTPUT
LOAD CAPACITANCE (pF)
12
0
14
8
4
2
6
R
I
S
E
A
N
D
F
A
L
L
T
I
M
E
S
(
n
s
)
10
0 250 200 50 100 150
16
t
FALL
= 3.3V @ 25C
t
RISE
= 3.3V @ 25C
TBD
Preliminary Technical Data
Rev. PrE | Page 73 of 84 | September 2013
ADSP-CM402F/CM403F/CM407F/CM408F
ENVIRONMENTAL CONDITIONS
To determine the junction temperature on the application
printed circuit board use:
where:
T
J
= Junction temperature (C)
T
CASE
= Case temperature (C) measured by customer at top
center of package.
+
JT
= From Table 50 and Table 51
P
D
= Power dissipation (see Total Power Dissipation on Page 35
for the method to calculate P
D
)
Values of u
JA
are provided for package comparison and printed
circuit board design considerations. u
JA
can be used for a first
order approximation of T
J
by the equation:
where:
T
A
= Ambient temperature (C)
Values of u
JC
are provided for package comparison and printed
circuit board design considerations when an external heat sink
is required.
In Table 50 and Table 51, airflow measurements comply with
JEDEC standards JESD51-2 and JESD51-6. The junction-to-
case measurement complies with MIL-STD-883 (Method
1012.1). All measurements use a 2S2P JEDEC test board.
Table 50. Thermal Characteristics (120-Lead LQFP)
Parameter Condition Typical Unit
u
JA
0 linear m/s air flow 21.5 C/W
u
JA
1 linear m/s air flow 19.2 C/W
u
JA
2 linear m/s air flow 18.4 C/W
u
JC
9.29 C/W
+
JT
0 linear m/s air flow 0.25 C/W
+
JT
1 linear m/s air flow 0.40 C/W
+
JT
2 linear m/s air flow 0.56 C/W
Table 51. Thermal Characteristics (176-Lead LQFP)
Parameter Condition Typical Unit
u
JA
0 linear m/s air flow 21.5 C/W
u
JA
1 linear m/s air flow 19.3 C/W
u
JA
2 linear m/s air flow 18.5 C/W
u
JC
9.24 C/W
+
JT
0 linear m/s air flow 0.25 C/W
+
JT
1 linear m/s air flow 0.37 C/W
+
JT
2 linear m/s air flow 0.48 C/W
T
J
T
CASE
+
JT
P
D
( ) + =
T
J
T
A
u
JA
P
D
( ) + =
Rev. PrE | Page 74 of 84 | September 2013
ADSP-CM402F/CM403F/CM407F/CM408F Preliminary Technical Data
120-LEAD LQFP LEAD ASSIGNMENTS
Table 52 lists the 120-lead LQFP package by lead number and
Table 53 lists the 120-lead LQFP package by signal.
Table 52. 120-lead LQFP Lead Assignment (Numerical by Lead Number)
Lead No. Signal Name Lead No. Signal Name Lead No. Signal Name Lead No. Signal Name
1 PA_13 32 JTG_TRST 63 ADC1_VIN05 94 DAC0_VOUT
2 VDD_EXT 33 JTG_TDO/SWO 64 ADC1_VIN06 95 VDD_EXT
3 PA_12 34 JTG_TMS/SWDIO 65 ADC1_VIN07 96 VDD_INT
4 PA_11 35 PC_07 66 ADC1_VIN08 97 VDD_EXT
5 PA_10 36 VDD_EXT 67 ADC1_VIN09 98 GND
6 PA_09 37 PC_06 68 ADC1_VIN10 99 SYS_NMI
7 PA_08 38 PC_05 69 ADC1_VIN11 100 VDD_EXT
8 PA_07 39 PC_04 70 VDD_ANA1 101 VDD_EXT
9 VDD_EXT 40 PC_03 71 GND_ANA1 102 PB_10
10 PA_06 41 PC_02 72 BYP_A1 103 PB_08
11 PA_05 42 PC_01 73 VREF1 104 PB_09
12 PA_04 43 VDD_EXT 74 GND_VREF1 105 PB_06
13 PA_03 44 VDD_INT 75 REFCAP 106 PB_07
14 PA_02 45 PC_00 76 GND_VREF0 107 PB_05
15 PA_01 46 PB_14 77 VREF0 108 VDD_INT
16 VDD_INT 47 PB_15 78 BYP_A0 109 VDD_EXT
17 VDD_EXT 48 PB_13 79 GND_ANA0 110 PB_04
18 SYS_RESOUT 49 VDD_EXT 80 VDD_ANA0 111 PB_03
19 PA_00 50 PB_11 81 ADC0_VIN11 112 PB_02
20 SYS_FAULT 51 PB_12 82 ADC0_VIN10 113 PB_01
21 SYS_HWRST 52 GND 83 ADC0_VIN09 114 PB_00
22 VDD_EXT 53 VDD_EXT 84 ADC0_VIN08 115 PA_15
23 SYS_XTAL 54 VDD_INT 85 ADC0_VIN07 116 VDD_EXT
24 SYS_CLKIN 55 BYP_D0 86 ADC0_VIN06 117 PA_14
25 VREG_BASE 56 DAC1_VOUT 87 ADC0_VIN05 118 SYS_CLKOUT
26 VDD_VREG 57 ADC1_VIN00 88 ADC0_VIN04 119 SYS_BMODE1
27 VDD_EXT 58 ADC1_VIN01 89 ADC0_VIN03 120 SYS_BMODE0
28 TWI0_SCL 59 ADC1_VIN02 90 GND_ANA2 121* GND
29 TWI0_SDA 60 ADC1_VIN03 91 ADC0_VIN02
30 JTG_TDI 61 GND_ANA3 92 ADC0_VIN01
31 JTG_TCK/SWCLK 62 ADC1_VIN04 93 ADC0_VIN00
* Pin no. 121 is the GND supply (see Figure 66) for the processor; this pad must connect to GND.
Preliminary Technical Data
Rev. PrE | Page 75 of 84 | September 2013
ADSP-CM402F/CM403F/CM407F/CM408F
Table 53. 120-lead LQFP Lead Assignment (Alphabetical by Signal Name)
Signal Name Lead No. Signal Name Lead No. Signal Name Lead No. Signal Name Lead No.
ADC0_VIN00 93 GND 121* PB_03 111 TWI0_SCL 28
ADC0_VIN01 92 GND_ANA0 79 PB_04 110 TWI0_SDA 29
ADC0_VIN02 91 GND_ANA1 71 PB_05 107 VDD_ANA0 80
ADC0_VIN03 89 GND_ANA2 90 PB_06 105 VDD_ANA1 70
ADC0_VIN04 88 GND_ANA3 61 PB_07 106 VDD_EXT 2
ADC0_VIN05 87 GND_VREF0 76 PB_08 103 VDD_EXT 9
ADC0_VIN06 86 GND_VREF1 74 PB_09 104 VDD_EXT 17
ADC0_VIN07 85 JTG_TCK/SWCLK 31 PB_10 102 VDD_EXT 22
ADC0_VIN08 84 JTG_TDI 30 PB_11 50 VDD_EXT 27
ADC0_VIN09 83 JTG_TDO/SWO 33 PB_12 51 VDD_EXT 36
ADC0_VIN10 82 JTG_TMS/SWDIO 34 PB_13 48 VDD_EXT 43
ADC0_VIN11 81 JTG_TRST 32 PB_14 46 VDD_EXT 49
ADC1_VIN00 57 PA_00 19 PB_15 47 VDD_EXT 53
ADC1_VIN01 58 PA_01 15 PC_00 45 VDD_EXT 95
ADC1_VIN02 59 PA_02 14 PC_01 42 VDD_EXT 97
ADC1_VIN03 60 PA_03 13 PC_02 41 VDD_EXT 100
ADC1_VIN04 62 PA_04 12 PC_03 40 VDD_EXT 101
ADC1_VIN05 63 PA_05 11 PC_04 39 VDD_EXT 109
ADC1_VIN06 64 PA_06 10 PC_05 38 VDD_EXT 116
ADC1_VIN07 65 PA_07 8 PC_06 37 VDD_INT 16
ADC1_VIN08 66 PA_08 7 PC_07 35 VDD_INT 44
ADC1_VIN09 67 PA_09 6 REFCAP 75 VDD_INT 54
ADC1_VIN10 68 PA_10 5 SYS_BMODE0 120 VDD_INT 96
ADC1_VIN11 69 PA_11 4 SYS_BMODE1 119 VDD_INT 108
BYP_A0 78 PA_12 3 SYS_CLKIN 24 VDD_VREG 26
BYP_A1 72 PA_13 1 SYS_CLKOUT 118 VREF0 77
BYP_D0 55 PA_14 117 SYS_FAULT 20 VREF1 73
DAC0_VOUT 94 PA_15 115 SYS_HWRST 21 VREG_BASE 25
DAC1_VOUT 56 PB_00 114 SYS_NMI 99
GND 98 PB_01 113 SYS_RESOUT 18
GND 52 PB_02 112 SYS_XTAL 23
* Pin no. 121 is the GND supply (see Figure 66) for the processor; this pad must connect to GND.
Rev. PrE | Page 76 of 84 | September 2013
ADSP-CM402F/CM403F/CM407F/CM408F Preliminary Technical Data
Figure 65 shows the top view of the 120-lead LQFP package lead
configuration and Figure 66 shows the bottom view of the 120-
lead LQFP package lead configuration.
Figure 65. 120-Lead LQFP Package Lead Configuration (Top View)
Figure 66. 120-Lead LQFP Package Lead Configuration (Bottom View)
LEAD 1
LEAD 30
LEAD 90
LEAD 61
LEAD 120 LEAD 91
LEAD 31 LEAD 60
LEAD 1
120-LEAD LQFP_EP
TOP VIEW
INDICATOR
LEAD 30
LEAD 1
LEAD 61
LEAD 90
LEAD 31
LEAD 60
LEAD 120
120-LEAD LQFP_EP
BOTTOM VIEW
LEAD 91
GND PAD
(LEAD 121)
Preliminary Technical Data
Rev. PrE | Page 77 of 84 | September 2013
ADSP-CM402F/CM403F/CM407F/CM408F
176-LEAD LQFP LEAD ASSIGNMENTS
Table 54 lists the 176-lead LQFP package by lead number and
Table 55 lists the 176-lead LQFP package by signal.
Table 54. 176-lead LQFP Lead Assignment (Numerical by Lead Number)
Lead No. Signal Name Lead No. Signal Name Lead No. Signal Name Lead No. Signal Name
1 PA_13 46 JTG_TRST 91 PE_05 136 VDD_EXT
2 VDD_EXT 47 JTG_TDO/SWO 92 PE_04 137 VDD_EXT
3 PA_12 48 JTG_TMS/SWDIO 93 VDD_EXT 138 PD_12
4 PA_11 49 PC_07 94 VDD_INT 139 PD_13
5 PC_15 50 VDD_EXT 95 BYP_D0 140 PD_10
6 PA_10 51 PC_05 96 GND_ANA3 141 PD_11
7 PC_14 52 PC_06 97 ADC1_VIN00 142 PD_08
8 VDD_EXT 53 PF_10 98 ADC1_VIN01 143 PD_09
9 PC_13 54 PC_04 99 ADC1_VIN02 144 VDD_EXT
10 PC_11 55 PF_08 100 ADC1_VIN03 145 PD_07
11 PC_12 56 PF_09 101 ADC1_VIN04 146 PD_06
12 PA_09 57 VDD_EXT 102 ADC1_VIN05 147 SMC0_AMS0
13 PA_08 58 PF_06 103 ADC1_VIN06 148 SMC0_AWE
14 PA_07 59 PF_07 104 ADC1_VIN07 149 SMC0_ARE
15 VDD_EXT 60 PC_03 105 VDD_ANA1 150 VDD_EXT
16 PA_06 61 PF_05 106 GND_ANA1 151 PB_10
17 PA_05 62 PC_01 107 BYP_A1 152 PB_09
18 PA_04 63 PC_02 108 VREF1 153 PB_08
19 PA_03 64 VDD_EXT 109 GND_VREF1 154 PB_07
20 PA_02 65 VDD_INT 110 REFCAP 155 PB_06
21 PA_01 66 PC_00 111 GND_VREF0 156 PB_05
22 VDD_INT 67 PF_04 112 VREF0 157 VDD_INT
23 VDD_EXT 68 PF_03 113 BYP_A0 158 VDD_EXT
24 SYS_RESOUT 69 PF_02 114 GND_ANA0 159 PB_03
25 PA_00 70 PF_01 115 VDD_ANA0 160 PB_04
26 SYS_FAULT 71 PF_00 116 ADC0_VIN07 161 PD_05
27 SYS_HWRST 72 VDD_EXT 117 ADC0_VIN06 162 PB_02
28 VDD_EXT 73 PE_15 118 ADC0_VIN05 163 PD_03
29 SYS_XTAL 74 PE_14 119 ADC0_VIN04 164 PD_04
30 SYS_CLKIN 75 PE_13 120 ADC0_VIN03 165 VDD_EXT
31 VREG_BASE 76 PB_14 121 ADC0_VIN02 166 PD_01
32 VDD_VREG 77 PB_15 122 ADC0_VIN01 167 PD_02
33 VDD_EXT 78 PB_13 123 ADC0_VIN00 168 PB_01
34 USB0_DM 79 VDD_EXT 124 GND_ANA2 169 PD_00
35 USB0_DP 80 PB_11 125 VDD_EXT 170 PA_15
36 USB0_VBUS 81 PB_12 126 PE_03 171 PB_00
37 USB0_ID 82 PE_12 127 PE_02 172 VDD_EXT
38 PC_10 83 GND 128 VDD_INT 173 PA_14
39 PC_08 84 PE_11 129 VDD_EXT 174 SYS_CLKOUT
40 PC_09 85 PE_10 130 PE_01 175 SYS_BMODE1
41 VDD_EXT 86 VDD_EXT 131 GND 176 SYS_BMODE0
* Pin no. 177 is the GND supply (see Figure 68) for the processor; this pad must connect to GND.
Rev. PrE | Page 78 of 84 | September 2013
ADSP-CM402F/CM403F/CM407F/CM408F Preliminary Technical Data
42 TWI0_SCL 87 PE_09 132 SYS_NMI 177* GND
43 TWI0_SDA 88 PE_08 133 PE_00
44 JTG_TDI 89 PE_07 134 PD_15
45 JTG_TCK/SWCLK 90 PE_06 135 PD_14
Table 54. 176-lead LQFP Lead Assignment (Numerical by Lead Number)
Lead No. Signal Name Lead No. Signal Name Lead No. Signal Name Lead No. Signal Name
* Pin no. 177 is the GND supply (see Figure 68) for the processor; this pad must connect to GND.
Preliminary Technical Data
Rev. PrE | Page 79 of 84 | September 2013
ADSP-CM402F/CM403F/CM407F/CM408F
Table 55. 176-lead LQFP Lead Assignment (Alphabetical by Signal Name)
Signal Name Lead No. Signal Name Lead No. Signal Name Lead No. Signal Name Lead No.
ADC0_VIN00 123 PA_12 3 PD_09 143 SYS_RESOUT 24
ADC0_VIN01 122 PA_13 1 PD_10 140 SYS_XTAL 29
ADC0_VIN02 121 PA_14 173 PD_11 141 TWI0_SCL 42
ADC0_VIN03 120 PA_15 170 PD_12 138 TWI0_SDA 43
ADC0_VIN04 119 PB_00 171 PD_13 139 USB0_DM 34
ADC0_VIN05 118 PB_01 168 PD_14 135 USB0_DP 35
ADC0_VIN06 117 PB_02 162 PD_15 134 USB0_ID 37
ADC0_VIN07 116 PB_03 159 PE_00 133 USB0_VBUS 36
ADC1_VIN00 97 PB_04 160 PE_01 130 VDD_ANA0 115
ADC1_VIN01 98 PB_05 156 PE_02 127 VDD_ANA1 105
ADC1_VIN02 99 PB_06 155 PE_03 126 VDD_EXT 2
ADC1_VIN03 100 PB_07 154 PE_04 92 VDD_EXT 8
ADC1_VIN04 101 PB_08 153 PE_05 91 VDD_EXT 15
ADC1_VIN05 102 PB_09 152 PE_06 90 VDD_EXT 23
ADC1_VIN06 103 PB_10 151 PE_07 89 VDD_EXT 28
ADC1_VIN07 104 PB_11 80 PE_08 88 VDD_EXT 33
BYP_A0 113 PB_12 81 PE_09 87 VDD_EXT 41
BYP_A1 107 PB_13 78 PE_10 85 VDD_EXT 50
BYP_D0 95 PB_14 76 PE_11 84 VDD_EXT 57
GND 131 PB_15 77 PE_12 82 VDD_EXT 64
GND 83 PC_00 66 PE_13 75 VDD_EXT 72
GND 177* PC_01 62 PE_14 74 VDD_EXT 79
GND_ANA0 114 PC_02 63 PE_15 73 VDD_EXT 86
GND_ANA1 106 PC_03 60 PF_00 71 VDD_EXT 93
GND_ANA2 124 PC_04 54 PF_01 70 VDD_EXT 125
GND_ANA3 96 PC_05 51 PF_02 69 VDD_EXT 129
GND_VREF0 111 PC_06 52 PF_03 68 VDD_EXT 136
GND_VREF1 109 PC_07 49 PF_04 67 VDD_EXT 137
JTG_TCK/SWCLK 45 PC_08 39 PF_05 61 VDD_EXT 144
JTG_TDI 44 PC_09 40 PF_06 58 VDD_EXT 150
JTG_TDO/SWO 47 PC_10 38 PF_07 59 VDD_EXT 158
JTG_TMS/SWDIO 48 PC_11 10 PF_08 55 VDD_EXT 165
JTG_TRST 46 PC_12 11 PF_09 56 VDD_EXT 172
PA_00 25 PC_13 9 PF_10 53 VDD_INT 22
PA_01 21 PC_14 7 REFCAP 110 VDD_INT 65
PA_02 20 PC_15 5 SMC0_AMS0 147 VDD_INT 94
PA_03 19 PD_00 169 SMC0_ARE 149 VDD_INT 128
PA_04 18 PD_01 166 SMC0_AWE 148 VDD_INT 157
PA_05 17 PD_02 167 SYS_BMODE0 176 VDD_VREG 32
PA_06 16 PD_03 163 SYS_BMODE1 175 VREF0 112
PA_07 14 PD_04 164 SYS_CLKIN 30 VREF1 108
PA_08 13 PD_05 161 SYS_CLKOUT 174 VREG_BASE 31
PA_09 12 PD_06 146 SYS_FAULT 26
PA_10 6 PD_07 145 SYS_HWRST 27
PA_11 4 PD_08 142 SYS_NMI 132
* Pin no. 177 is the GND supply (see Figure 68) for the processor; this pad must connect to GND.
Rev. PrE | Page 80 of 84 | September 2013
ADSP-CM402F/CM403F/CM407F/CM408F Preliminary Technical Data
Figure 67 shows the top view of the 176-lead LQFP lead config-
uration and Figure 68 shows the bottom view of the 176-lead
LQFP lead configuration.
Figure 67. 176-Lead LQFP_EP Lead Configuration (Top View)
LEAD 1
LEAD 44
LEAD 132
LEAD 89
LEAD 176 LEAD 133
LEAD 45 LEAD 88
LEAD 1 INDICATOR
176-LEAD LQFP_EP
TOP VIEW
Figure 68. 176-Lead LQFP_EP Lead Configuration (Bottom View)
LEAD 132
LEAD 89
LEAD 1
LEAD 44
LEAD 133 LEAD 176
LEAD 88 LEAD 45
176-LEAD LQFP_EP
BOTTOM VIEW
GND PAD
(LEAD 177)
Preliminary Technical Data
Rev. PrE | Page 81 of 84 | September 2013
ADSP-CM402F/CM403F/CM407F/CM408F
OUTLINE DIMENSIONS
Dimensions in Figure 69 (for the 120-lead LQFP) and in
Figure 70 (for the 176-lead LQFP) are shown in millimeters.
Figure 69. 120-Lead Low Profile Quad Flat Package, Exposed Pad [LQFP_EP]
1
(SW-120-3)
Dimensions shown in millimeters
1
For information relating to the SW-120-3 packages exposed pad, see the table endnote in 120-Lead LQFP Lead Assignments on Page 74.
120
60
90
61
31
1
30
91
BOTTOM VIEW
(PINS UP)
COMPLIANT TO JEDEC STANDARDS MS-026-BEE-HD
*
NOTE: EXPOSED PAD DIMENSIONS ARE PRELIMINARY AND FOR ENG
GRADE MATERIAL ONLY. THE PAD SIZE MAY CHANGE FOR VOLUME PRODUCTION
MATERIAL. TO MAINTAIN COMPATIBILITY PCB DESIGNERS MUST OBSERVE
THE SPECIFIED KEEP-OUT AREA.
1.45
1.40
1.35
0.15
0.10
0.05
TOP VIEW
(PINS DOWN)
91
1 90
31
30
60
61
120
0.23
0.18
0.13
0.40
BSC
LEAD PITCH
11.60 REF
SQ
1.60
MAX
16.20
16.00 SQ
15.80
14.10
14.00 SQ
13.90
VIEW A
0.08
COPLANARITY
VIEW A
ROTATED 90 CCW
12
7
0
0.20
0.15
0.09
0.75
0.60
0.45
1.00 REF
*
EXPOSED
PAD
5.40
REF
7.675
REF
3.50
REF
0.10 REF
U-GROOVE
*
SEE NOTE
(10 8 mm AREA)
2.25 REF 3.15 REF
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
PIN 1
SEATING
PLANE
Rev. PrE | Page 82 of 84 | September 2013
ADSP-CM402F/CM403F/CM407F/CM408F Preliminary Technical Data
PRE-RELEASE PRODUCTS
Figure 70. 176-Lead Low Profile Quad Flat Package, Exposed Pad [LQFP_EP]
1
(SW-176-3)
Dimensions shown in millimeters
1
For information relating to the SW-176-3 packages exposed pad, see the table endnote in 176-Lead LQFP Lead Assignments on Page 77.
Model
Temperature
Range
1,
2
1
Referenced temperature is ambient temperature. The ambient temperature is not a specification. Please see Operating Conditions on Page 34 for the junction temperature
(TJ) specification which is the only temperature specification.
2
Actual temperature range for ENG grade product is subject to change, and will be provided to the customer at the time of shipment. The production target for ambient
temperature is 40C to +85C.
Package Description
Package
Option
Processor Instruction Rate
(Max)
ADSP-CM403FBSWZENG TBD 120-Lead Low-profile Quad Flat
Package Exposed Pad
SW-120-3 TBD MHz
ADSP-CM408FBSWZENG TBD 176-Lead Low-profile Quad Flat
Package Exposed Pad
SW-176-3 TBD MHz
COMPLIANT TO JEDEC STANDARDS MS-026-BGA-HD
0.15
0.10
0.05
0.08
COPLANARITY
0.20
0.15
0.09
1.45
1.40
1.35
7
0
VIEW A
ROTATED 90 CCW
0.27
0.22
0.17
0.75
0.60
0.45
0.50
BSC
LEAD PITCH
24.10
24.00 SQ
23.90
26.20
26.00 SQ
25.80
TOP VIEW
(PINS DOWN)
BOTTOM VIEW
(PINS UP)
1
44
1
44
45
89
88 45 88
132
89
132
176 133 176 133
1.60 MAX
1.00 REF
SEATING
PLANE
VIEW A
5.80
REF
7.56
REF
3.50
REF
3.027 REF 2.225 REF
21.50 REF
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
PIN 1
*
EXPOSED
PAD
0.10 REF
*
NOTE: EXPOSED PAD DIMENSIONS ARE PRELIMINARY AND FOR ENG
GRADE MATERIAL ONLY. THE PAD SIZE MAY CHANGE FOR VOLUME PRODUCTION
MATERIAL. TO MAINTAIN COMPATIBILITY PCB DESIGNERS MUST OBSERVE
THE SPECIFIED KEEP-OUT AREA.
U-GROOVE
*
SEE NOTE
(12 8 mm AREA)
Preliminary Technical Data
Rev. PrE | Page 83 of 84 | September 2013
ADSP-CM402F/CM403F/CM407F/CM408F
Rev. PrE | Page 84 of 84 | September 2013
Preliminary Technical Data
2013 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
PR11805-0-9/13(PrE)
ADSP-CM402F/CM403F/CM407F/CM408F