NCP81215P

Three Output Controller

with Single SVID Interface
for Desktop and Notebook
CPU Applications
The NCP81215P (4 + 2 + 1 phase) three−output buck solution is
optimized for Intel’s IMVP8 CPUs. www.onsemi.com
The two multi−phase rail control systems are based on Dual−Edge
pulse−width modulation (PWM) combined with DCR current sensing
providing an ultra fast initial response to dynamic load events and
reduced system cost.
The single−phase rail makes use of ON Semiconductor’s patented
high performance RPM operation. RPM control maximizes transient 1 52
response while allowing for smooth transitions between QFN52 6  6, 0.4P
discontinuous−frequency−scaling operation and continuous−mode CASE 485BE
full−power operation. The NCP81215P has an ultra−low offset current
monitor amplifier with programmable offset compensation for MARKING DIAGRAM
high−accuracy current monitoring.
PIN 1 ON
Multi−Phase Rail Features NCP81215P
• Dual Edge Modulation for Fastest Initial Response to Transient FAWLYYWW
Loading Pb−Free
Designator
• High Performance Operational Error Amplifier
F = Wafer Fab
• Digital Soft Start Ramp A = Assembly Site
• Dynamic Reference Injection (Patent #US7057381) WL = Lot ID
YY = Year
• Accurate Total Summing Current Amplifier (Patent #US6683441) WW = Work Week
• Dual High Impedance Differential Voltage and Total Current Sense = Pb−Free Designator
Amplifiers
• Phase−to−Phase Dynamic Current Balancing ORDERING INFORMATION
• True Differential Current Balancing Sense Amplifiers for Each Phase Device Package Shipping†
• Adaptive Voltage Positioning (AVP)
NCP81215PMNTXG 52 QFN 2500 / Tape & Reel
• Switching Frequency Range of 300 kHz – 1.2 MHz
• Vin range 4.5 V to 25 V †For information on tape and reel specifications,
including part orientation and tape sizes, please
• Startup into Pre−Charged Loads While Avoiding False OVP refer to our Tape and Reel Packaging Specification
• UltraSonic Operation Brochure, BRD8011/D.

Single−Phase Rail Features

• Enhanced RPM Control System
• Ultra Low Offset IOUT Monitor
• Dynamic VID Feed−Forward
• Programmable Droop Gain
• Zero Droop Capable

Applications
• Desktop & Notebook Processors
• Gaming

© Semiconductor Components Industries, LLC, 2019 1 Publication Order Number:

March, 2019 − Rev. 0 NCP81215P/D
 NCP81215P

Figure 1.

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 NCP81215P

Pinout

PWM1_1PH/ICCMAX_1PH
COMP_1PH

IMON_1PH
CSN_1PH
VSN_1PH

CSP_1PH
VSP_1PH

ILIM_1PH

VR_RDY

ALERT#
SCLK

SDIO
EN
52 51 50 49 48 47 46 45 44 43 42 41 40
VSP_4PH 1 39 VRHOT#
VSN_4PH 2 38 VSP_2PH
IMON_4PH 3 37 VSN_2PH
DIFFOUT_4PH 4 36 IMON_2PH
FB_4PH 5 35 DIFFOUT_2PH
COMP_4PH 6 34 FB_2PH
NCP81215P
ILIM_4PH 7 33 COMP_2PH
CSCOMP_4PH 8 32 ILIM_2PH
CSSUM_4PH 9 31 CSCOMP_2PH
CSREF_4PH 10 30 CSSUM_2PH
CSP1_4PH 11 29 CSREF_2PH
CSP2_4PH 12 28 CSP1_2PH
CSP3_4PH 13 27 CSP2_2PH
14 15 16 17 18 19 20 21 22 23 24 25 26
PWM4_4PH/ROSC_MPH
PWM2_2PH/ROSC_1PH
PWM1_4PH/ICCMAX_4PH

PWM3_4PH/VBOOT

TTSENSE_1PH/PSYS
PWM2_4PH/ADDR

TTSENSE_2PH
TSENSE_4PH

CSP_4PH
VRMP
VCC
DRON

PWM1_2PH/CCMAX_2PH

Figure 2. Pinout Diagram

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Pin Function Description

Table 1. QFN52 PIN LIST DESCRIPTION

Pin Name Description
1 VSP_4PH Differential output voltage sense positive for four− phase rail
2 VSN_4PH Differential output voltage sense negative for four− phase rail
3 IMON_4PH A resistor to ground programs IOUT gain for four− phase rail
4 DIFFOUT_4PH Output of four phase rail differential remote sense amplifier
5 FB_4PH Error amplifier voltage feedback for four− phase rail
6 COMP_4PH Error amplifier output and PWM comparator inverting input for four− phase rail
7 ILIM_4PH A resistor to CSCOMP_4PH programs the over−current threshold for four− phase rail
8 CSCOMP_4PH Total−current−sense amplifier output for four− phase rail
9 CSSUM_4PH Inverting input of total−current−sense amplifier for four− phase rail
10 CSREF_4PH Total−current−sense amplifier reference voltage input for four− phase rail
11 CSP1_4PH Current−balance amplifier positive input for four− phase rail
12 CSP2_4PH Current−balance amplifier positive input for four− phase rail
13 CSP3_4PH Current−balance amplifier positive input for four− phase rail
14 TSENSE_4PH Temperature sense input for four− phase rail
15 VRMP Vin feed−forward input. Controls a current used to generate the ramps of the modulators
16 VCC Power for the internal control circuits. A decoupling capacitor is connected from this pin to
ground
17 DRON External FET driver enable for discrete driver or DrMOS
18 PWM1_4PH / Phase 1 PWM output of four− phase rail. /
ICCMAX_4PH A resistor to ground programs ICCMAX for four− phase rail
19 PWM2_4PH / ADDR Phase 2 PWM output of four− phase rail. /
A resistor to ground configures SVID addresses for all 3 rails (ADDR)
20 PWM3_4PH / VBOOT Phase 3 PWM output of four− phase rail. /
A resistor to ground configures boot voltage for all 3 rails (VBOOT)
21 PWM4_4PH / Phase 4 PWM output of four− phase rail. /
ROSC_MPH A resistor to ground configures Fsw for both four− phase rail and the two−phase
rail.(ROSC_MPH)
22 PWM2_2PH / Phase 2 PWM output of two− phase rail. /
ROSC_1PH A resistor to ground configures Fsw for 1ph rail (ROSC_1ph)
23 PWM1_2PH / Phase 1 PWM output of two−phase rail. /
ICCMAX_2PH A resistor to ground programs ICCMAX for two− phase rail
24 TTSENSE_1PH / Temperature sense input for the single−phase rail /
PSYS System input power monitor. A resistor to ground scales this signal
25 TTSENSE_2PH Temperature sense input for two phase rail
26 CSP4_4PH Current−balance amplifier positive input for Phase 4 of four− phase rail
27 CSP2_2PH Current−balance amplifier positive input for Phase 2 of two − phase rail
28 CSP1_2PH Current−balance amplifier positive input for Phase 1 of two− phase rail
29 CSREF_2PH Total−current−sense amplifier reference voltage input for two− phase rail
30 CSSUM_2PH Inverting input of total−current−sense amplifier for two− phase rail
31 CSCOMP_2PH Total−current−sense amplifier output for two− phase rail
32 ILIM_2PH A resistor to CSCOMP_2PH programs the over−current threshold for two− phase rail
33 COMP_2PH Error amplifier output and PWM comparator inverting input for two− phase rail
34 FB_2PH Error amplifier voltage feedback for two− phase rail
35 DIFFOUT_2PH Output of two− phase rail differential remote sense amplifier
36 IMON_2PH A resistor to ground programs IOUT gain for two− phase rail
37 VSN_2PH Differential output voltage sense negative for two− phase rail
38 VSP_2PH Differential output voltage sense positive for two− phase rail
39 VR_HOT# Thermal logic output for over−temperature condition on TTSENSE pins

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 NCP81215P

Table 1. QFN52 PIN LIST DESCRIPTION (continued)

Pin Name Description
40 SDIO Serial VID data interface
41 ALERT# Serial VID ALERT#
42 SCLK Serial VID clock
43 EN Enable input. High enables all three rails
44 PWM_1PH / PWM output of the single−phase rail /
ICCMAX_1PH A resistor to ground programs ICCMAX for the single−phase rail
45 VR_RDY VR_RDY indicates all three rails are ready to accept SVID commands
46 IMON_1PH A resistor to ground programs IOUT gain for the single−phase rail
47 CSP_1PH Differential current sense positive for the single−phase rail
48 CSN_1ph Differential current sense negative for the single−phase rail
49 ILIM_1ph A resistor to ground programs ILIM gain for the single−phase rail
50 COMP_1ph Compensation for single−phase rail
51 VSN_1ph Differential output voltage sense negative for single−phase rail
52 VSP_1ph Differential output voltage sense positive for single−phase rail
53 Tab GND

Electrical Information

Table 2. ABSOLUTE MAXIMUM RATINGS

Pin Symbol VMAX VMIN ISOURCE ISINK
COMPX VCC + 0.3 V −0.3 V 2 mA 2 mA
CSCOMPX VCC + 0.3 V −0.3 V 2 mA 2 mA
VSN GND + 300 mV GND – 300 mV 1 mA 1 mA
VRDY VCC + 0.3 V −0.3 V N/A 2 mA
VCC 6.5 V −0.3 V N/A N/A
VRMP +25 V −0.3 V
All Other Pins VCC + 0.3 V −0.3 V
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. All signals referenced to GND unless noted otherwise.

Thermal Information

Table 3. THERMAL INFORMATION

Description Symbol Typ Unit
Thermal Characteristic
RJA 68 _C/W
QFN Package (Note 2)
Operating Junction Temperature Range (Note 3) TJ −10 to 125 _C
Operating Ambient Temperature Range −10 to 100 _C
Maximum Storage Temperature Range TSTG − 40 to +150 _C
Moisture Sensitivity Level
MSL 1
QFN Package
ESD Human Body Model HBM 2000 V
ESD Machine Model MM 200 V
ESD Charged device model CDM 1000 V
1. The maximum package power dissipation must be observed
2. JESD 51−5 (1S2P Direct−Attach Method) with 0 LFM
3. JESD 51−7 (1S2P Direct−Attach Method) with 0 LFM

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 NCP81215P

Table 4. ELECTRICAL CHARACTERISTICS

(Unless otherwise stated: −10°C < TA < 100°C; 4.75 V < VCC < 5.25 V; CVCC = 0.1 μF)

Parameter Test Conditions MIN TYP MAX Units

ERROR AMPLIFIER
Input Bias Current −900 900 nA
Open Loop DC Gain CL = 20 pF to GND, 80 dB
RL = 10 KΩ to GND
Open Loop Unity Gain Bandwidth CL = 20 pF to GND, 20 MHz
RL = 10 KΩ to GND
Slew Rate ΔVin = 100 mV, G = −10 V/V, 5 V/μs
ΔVout = 0.75 V – 1.52 V,
CL = 20 pF to GND,
DC Load = 10 k to GND
Maximum Output Voltage ISOURCE = 2.0 mA 3.5 V
Minimum Output Voltage ISINK = 2.0 mA 1 V
DIFFERENTIAL SUMMING AMPLIFIER
Input Bias Current −25 25 nA
VSP Input Voltage Range −0.3 3.0 V
VSN Input Voltage Range −0.3 0.3 V
−3 dB Bandwidth CL = 20 pF to GND, 22.5 MHz
RL = 10 KΩ to GND
Closed Loop DC gain VS+ to VS− = 0.5 to 1.3 V 1.0 V/V
VS to DIFF
Maximum Output Voltage ISOURCE = 2 mA 3.5 V
Minimum Output Voltage ISINK = 2 mA 0.8 V
CURRENT SUMMING AMPLIFIER
Offset Voltage (Vos) −300 300 μV
Input Bias Current CSSUM = CSREF = 1 V −7.5 7.5 μA
Open Loop Gain 80 dB
Current Sense Unity Gain Bandwidth CL = 20 pF to GND, 15 MHz
RL = 10 KΩ to GND
Maximum CSCOMP (A) Output Voltage Isource = 2 mA 3.5 V
Minimum CSCOMP(A) Output Voltage Isink = 500 μA 0.15 V
CURRENT BALANCE AMPLIFIER
Input Bias Current CSPX − CSPX + 1 = 1.2 V −50 50 nA

Common Mode Input Voltage Range CSPx = CSREF 0 2.3 V

Differential Mode Input Voltage Range CSNx = 1.2 V −100 100 mV
Closed loop Input Offset Voltage Matching CSPx = 1.2 V, −1.5 1.5 mV
Measured from the average

Current Sense Amplifier Gain 0 V < CSPx < 0.1 V 5.7 6.0 6.3 V/V
Multiphase Current Sense Gain Matching CSREF = CSP = 10 mV to −3 3 %
30 mV
−3dB Bandwidth 8 MHz
BIAS SUPPLY
Supply Voltage Range 4.75 5.25 V
VCC Quiescent Current PS0 33 45 mA
VCC Quiescent Current PS3 20 mA
VCC Quiescent Current PS4 at 25°C only 400 μA
VCC Quiescent Current Enable low 60 μA

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 NCP81215P

Table 4. ELECTRICAL CHARACTERISTICS (continued)

(Unless otherwise stated: −10°C < TA < 100°C; 4.75 V < VCC < 5.25 V; CVCC = 0.1 μF)

Parameter Test Conditions MIN TYP MAX Units

BIAS SUPPLY
UVLO Threshold VCC rising 4.5 V
VCC falling 4 V
VCC UVLO Hysteresis 250 mV
VRMP
Supply Range 4.5 20 V
UVLO Threshold VRamp rising 4.25 V
VRamp falling 3 V
UVLO Hysteresis 675 mV
DAC SLEW RATE
Slew Rate Fast >10 mV/μs
Soft Start Slew Rate 1/2 SR mV/μs
Fast
Slew Rate Slow 1/2 SR mV/μs
Fast
ENABLE INPUT
Enable High Input Leakage Current Enable = 0 −1 1 μA
Upper Threshold VUPPER 0.8 V
Lower Threshold VLOWER 0.3 V
Enable Delay Time Measure time from Enable 2.5 ms
transitioning HI , VBOOT is
not 0 V
DRON
Output High Voltage Sourcing 500 μA 3.0 V
Output Low Voltage Sinking 500 μA 0.1 V
Pull Up Resistances 2.0 kΩ

Rise/Fall Time CL (PCB) = 20 pF, 160 ns

ΔVo = 10% to 90%
Internal Pull Down Resistance VCC =0 V 70 kΩ
OVERCURRENT PROTECTION
Ilim Threshold Current PS0 9 10 11 μA
(delayed OCP shutdown)
PS1, PS2, PS3 10/N μA
(N = PS0 phase count)
Ilim Threshold Current PS0 13.5 15 16.5 μA
(immediate OCP shutdown)
PS1, PS2, PS3 15/N μA
(N = PS0 phase count)
Shutdown Delay Immediate 300 ns
Delayed 50 μs
ILIM Output Voltage Offset Ilim sourcing 10 μA −3 3 mV
Measured relative to CSRef
IOUT_4PH /IOUT_2PH OUTPUT
Output Offset Current VIlim = 5 V 0.25 μA
Output current max Ilimit sink current 20 μA 200 μA
Current Gain (Iout current)/(Ilimit Current) 10 10.5 A/A
Rlim = 20 K, Riout = 5 K
DAC = 0.8 V, 1.25 V, 1.52 V 9.5

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 NCP81215P

Table 4. ELECTRICAL CHARACTERISTICS (continued)

(Unless otherwise stated: −10°C < TA < 100°C; 4.75 V < VCC < 5.25 V; CVCC = 0.1 μF)

Parameter Test Conditions MIN TYP MAX Units

OSCILLATOR
Switching Frequency Range 300 1200 kHz
Switching Frequency Accuracy 300 KHz < Fsw < 1 MHz −10 10 %
PSYS
Input Current Rpsys = 20 kΩ 100 μA
ADC resolution 8 bit 7.81 mV/LS
B
Register update rate 500 μs
Disable Threshold 4.7 V
OUTPUT OVER VOLTAGE & UNDER VOLTAGE PROTECTION (OVP & UVP)
Over Voltage Threshold During Soft−Start 1.9 2.0 2.1 V
Over Voltage Threshold Above DAC VSP rising 370 400 430 mV
Over Voltage Delay VSP rising to PWMx low 25 ns
Under Voltage Threshold Below DAC−DROOP VSP falling 225 300 370 mV
Under−voltage Hysteresis VSP rising 25 mV
Under−Voltage Delay 5 μs
SVID DAC
System Voltage Accuracy .75 V ≤ DAC < 1.52 V −0.5 0.5 %
0.5 V < DAC < .745 V −8 8 mV
0.25 V DAC < 0.495 V −10 10 mV
MODULATORS (PWM COMPARATORS) FOR A RAIL & B RAIL
Minimum Pulse Width Fsw = 350 KHz 40 ns
0% Duty Cycle COMP voltage when the 1.3 V
PWM outputs remain LO
100% Duty Cycle COMP voltage when the 2.5 V
PWM outputs remain HI
VRMP = 12.0 V
PWM Phase Angle Error Between adjacent phases ±5 °
TSENSE
VRHOT Assert Threshold 468 mV
VRHOT Rising Threshold 488 mV
Alert Assertion Threshold 488 mV
Alert Rising Threshold 510 mV
TSENSE Bias Current 115 120 125 μA
VR_HOT
Output Low Saturation Voltage IVR_HOT = −4 mA 0.3 V
Output Leakage Current High Impedance State −1 1 μA
ADC
Voltage Range 0 2 V
Total Unadjusted Error (TUE) −1 1 %
Differential Nonlinearity (DNL) 8−bit 1 LSB
Power Supply Sensitivity +/−1 %
Conversion Time 7.4 μs
Round Robin 206 μs
VRDY OUTPUT
Output Low Saturation Voltage IVR_RDY = 4 mA, 0.3 V

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 NCP81215P

Table 4. ELECTRICAL CHARACTERISTICS (continued)

(Unless otherwise stated: −10°C < TA < 100°C; 4.75 V < VCC < 5.25 V; CVCC = 0.1 μF)

Parameter Test Conditions MIN TYP MAX Units

VRDY OUTPUT
Rise Time External pull−up of 1 KΩ to 150 ns
3.3 V
CTOT = 45pF,
ΔVo = 10% to 90%
Fall Time External pull−up of 1 KΩ to 150 ns
3.3 V
CTOT = 45 pF,
ΔVo = 90% to 10%
Output Leakage Current When High VR_RDY = 5.0 V −1 1 μA
VR_RDY Delay (rising) En rising to VR_RDY rising 2.5 ms
(TA)
VR_RDY Delay (falling) Due to OCP or OVP 0.3 μs
En falling to VR_RDY falling 1.5 μs
(TD + TE)
PWM OUTPUTS
Output High Voltage Sourcing 500 μA VCC − 0.2 V V
Output Mid Voltage No Load 1.7 1.8 1.9 V
Output Low Voltage Sinking 500 μA 0.3 V
Rise and Fall Time CL (PCB) = 50 pF, 5 ns
ΔVo =10% to 90% of VCC
Tri−State Output Leakage Gx = 2.0 V, x = 1−2, −1 1 μA
EN = Low
PHASE DETECTION
CSPX Phase Disable Voltage 4.75 V
SCLK, SDIO, ALERT#
VIL Input Low Voltage .45 V
VIH Input High Voltage .65 V
VOH Output High Voltage 1.05 V
VOL SDIO, ALERT# 0.3 V
Leakage Current −5 5 μA
Pin Capacitance @25°C only 9 pF
VR clock to data delay (Tco) 12 ns
Setup time (Tsu) 7 ns
Hold time (Thld) 14 ns
ERROR AMPLIFIER
Input Bias Current −25 25 nA
VSP Input Voltage Range −0.3 3.0 V
VSN Input Voltage Range −0.3 0.3 V
gm 1.34 1.6 1.85 mS
Output Offset Current −15 15 μA
Open loop Gain Load= 1nF in series with 70 73 dB
1 kΩ in parallel with 10pF to
ground
Source Current Input Differential −200 mV 280 μA
Sink Current Input Differential 200 mV 280 μA
−3 dB Bandwidth Load = 1 nF in series with 1 20 MHz
kΩ in parallel with 10 pF to
ground

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 NCP81215P

Table 4. ELECTRICAL CHARACTERISTICS (continued)

(Unless otherwise stated: −10°C < TA < 100°C; 4.75 V < VCC < 5.25 V; CVCC = 0.1 μF)

Parameter Test Conditions MIN TYP MAX Units

IOUT
gm 0.97 1 1.03 mS
Output Offset Current CSP = CSN −1.5 250 nA
DROOP
gm 0.96 1 1.04 mS
Output Offset Current CSP = CSN −1.5 1.5 μA
OVERCURRENT PROTECTION
ILIMIT Threshold 1.275 1.3 1.325 V
ILIMIT Delay 200 ns
ILIMIT Gain IILIMIT/(CSP - CSN) 0.925 1 1.075 mS
CSP - CSN = 20 mV
OUTPUT OVER VOLTAGE & UNDER VOLTAGE PROTECTION (OVP & UVP)
Over Voltage Threshold During Soft-Start 2.0 V
Over Voltage Threshold Above DAC VSP - VSN - VID setting 370 430 mV
Over Voltage Delay VSP rising to PWMx low 25 ns
Over Voltage VR_RDY Delay VSP rising to VR_RDY low 350 ns
Under Voltage Threshold VSP - VSN falling 215 300 385 mV
Under-voltage Hysteresis VSP - VSN falling/rising 25 mV
Under-voltage Blanking Delay VSP - VSN falling to VR_RDY 5 μs
falling
CSP−CSN ZCD COMPARATOR
Offset Accuracy ±1.5 mV

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 NCP81215P

Table 5. IMVP8 VID CODES

VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 Voltage Hex
0 0 0 0 0 0 0 0 Off 00
0 0 0 0 0 0 0 1 0.25 01
0 0 0 0 0 0 1 0 0.255 02
0 0 0 0 0 0 1 1 0.26 03
0 0 0 0 0 1 0 0 0.265 04
0 0 0 0 0 1 0 1 0.27 05
0 0 0 0 0 1 1 0 0.275 06
0 0 0 0 0 1 1 1 0.28 07
0 0 0 0 1 0 0 0 0.285 08
0 0 0 0 1 0 0 1 0.29 09
0 0 0 0 1 0 1 0 0.295 0A
0 0 0 0 1 0 1 1 0.3 0B
0 0 0 0 1 1 0 0 0.305 0C
0 0 0 0 1 1 0 1 0.31 0D
0 0 0 0 1 1 1 0 0.315 0E
0 0 0 0 1 1 1 1 0.32 0F
0 0 0 1 0 0 0 0 0.325 10
0 0 0 1 0 0 0 1 0.33 11
0 0 0 1 0 0 1 0 0.335 12
0 0 0 1 0 0 1 1 0.34 13
0 0 0 1 0 1 0 0 0.345 14
0 0 0 1 0 1 0 1 0.35 15
0 0 0 1 0 1 1 0 0.355 16
0 0 0 1 0 1 1 1 0.36 17
0 0 0 1 1 0 0 0 0.365 18
0 0 0 1 1 0 0 1 0.37 19
0 0 0 1 1 0 1 0 0.375 1A
0 0 0 1 1 0 1 1 0.38 1B
0 0 0 1 1 1 0 0 0.385 1C
0 0 0 1 1 1 0 1 0.39 1D
0 0 0 1 1 1 1 0 0.395 1E
0 0 0 1 1 1 1 1 0.4 1F
0 0 1 0 0 0 0 0 0.405 20
0 0 1 0 0 0 0 1 0.41 21
0 0 1 0 0 0 1 0 0.415 22
0 0 1 0 0 0 1 1 0.42 23
0 0 1 0 0 1 0 0 0.425 24
0 0 1 0 0 1 0 1 0.43 25
0 0 1 0 0 1 1 0 0.435 26
0 0 1 0 0 1 1 1 0.44 27
0 0 1 0 1 0 0 0 0.445 28
0 0 1 0 1 0 0 1 0.45 29
0 0 1 0 1 0 1 0 0.455 2A
0 0 1 0 1 0 1 1 0.46 2B
0 0 1 0 1 1 0 0 0.465 2C
0 0 1 0 1 1 0 1 0.47 2D
0 0 1 0 1 1 1 0 0.475 2E

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Table 5. IMVP8 VID CODES (continued)

VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 Voltage Hex
0 0 1 0 1 1 1 1 0.48 2F
0 0 1 1 0 0 0 0 0.485 30
0 0 1 1 0 0 0 1 0.49 31
0 0 1 1 0 0 1 0 0.495 32
0 0 1 1 0 0 1 1 0.5 33
0 0 1 1 0 1 0 0 0.505 34
0 0 1 1 0 1 0 1 0.51 35
0 0 1 1 0 1 1 0 0.515 36
0 0 1 1 0 1 1 1 0.52 37
0 0 1 1 1 0 0 0 0.525 38
0 0 1 1 1 0 0 1 0.53 39
0 0 1 1 1 0 1 0 0.535 3A
0 0 1 1 1 0 1 1 0.54 3B
0 0 1 1 1 1 0 0 0.545 3C
0 0 1 1 1 1 0 1 0.55 3D
0 0 1 1 1 1 1 0 0.555 3E
0 0 1 1 1 1 1 1 0.56 3F
0 1 0 0 0 0 0 0 0.565 40
0 1 0 0 0 0 0 1 0.57 41
0 1 0 0 0 0 1 0 0.575 42
0 1 0 0 0 0 1 1 0.58 43
0 1 0 0 0 1 0 0 0.585 44
0 1 0 0 0 1 0 1 0.59 45
0 1 0 0 0 1 1 0 0.595 46
0 1 0 0 0 1 1 1 0.6 47
0 1 0 0 1 0 0 0 0.605 48
0 1 0 0 1 0 0 1 0.61 49
0 1 0 0 1 0 1 0 0.615 4A
0 1 0 0 1 0 1 1 0.62 4B
0 1 0 0 1 1 0 0 0.625 4C
0 1 0 0 1 1 0 1 0.63 4D
0 1 0 0 1 1 1 0 0.635 4E
0 1 0 0 1 1 1 1 0.64 4F
0 1 0 1 0 0 0 0 0.645 50
0 1 0 1 0 0 0 1 0.65 51
0 1 0 1 0 0 1 0 0.655 52
0 1 0 1 0 0 1 1 0.66 53
0 1 0 1 0 1 0 0 0.665 54
0 1 0 1 0 1 0 1 0.67 55
0 1 0 1 0 1 1 0 0.675 56
0 1 0 1 0 1 1 1 0.68 57
0 1 0 1 1 0 0 0 0.685 58
0 1 0 1 1 0 0 1 0.69 59
0 1 0 1 1 0 1 0 0.695 5A
0 1 0 1 1 0 1 1 0.7 5B
0 1 0 1 1 1 0 0 0.705 5C
0 1 0 1 1 1 0 1 0.71 5D

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Table 5. IMVP8 VID CODES (continued)

VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 Voltage Hex
0 1 0 1 1 1 1 0 0.715 5E
0 1 0 1 1 1 1 1 0.72 5F
0 1 1 0 0 0 0 0 0.725 60
0 1 1 0 0 0 0 1 0.73 61
0 1 1 0 0 0 1 0 0.735 62
0 1 1 0 0 0 1 1 0.74 63
0 1 1 0 0 1 0 0 0.745 64
0 1 1 0 0 1 0 1 0.75 65
0 1 1 0 0 1 1 0 0.755 66
0 1 1 0 0 1 1 1 0.76 67
0 1 1 0 1 0 0 0 0.765 68
0 1 1 0 1 0 0 1 0.77 69
0 1 1 0 1 0 1 0 0.775 6A
0 1 1 0 1 0 1 1 0.78 6B
0 1 1 0 1 1 0 0 0.785 6C
0 1 1 0 1 1 0 1 0.79 6D
0 1 1 0 1 1 1 0 0.795 6E
0 1 1 0 1 1 1 1 0.8 6F
0 1 1 1 0 0 0 0 0.805 70
0 1 1 1 0 0 0 1 0.81 71
0 1 1 1 0 0 1 0 0.815 72
0 1 1 1 0 0 1 1 0.82 73
0 1 1 1 0 1 0 0 0.825 74
0 1 1 1 0 1 0 1 0.83 75
0 1 1 1 0 1 1 0 0.835 76
0 1 1 1 0 1 1 1 0.84 77
0 1 1 1 1 0 0 0 0.845 78
0 1 1 1 1 0 0 1 0.85 79
0 1 1 1 1 0 1 0 0.855 7A
0 1 1 1 1 0 1 1 0.86 7B
0 1 1 1 1 1 0 0 0.865 7C
0 1 1 1 1 1 0 1 0.87 7D
0 1 1 1 1 1 1 0 0.875 7E
0 1 1 1 1 1 1 1 0.88 7F
1 0 0 0 0 0 0 0 0.885 80
1 0 0 0 0 0 0 1 0.89 81
1 0 0 0 0 0 1 0 0.895 82
1 0 0 0 0 0 1 1 0.9 83
1 0 0 0 0 1 0 0 0.905 84
1 0 0 0 0 1 0 1 0.91 85
1 0 0 0 0 1 1 0 0.915 86
1 0 0 0 0 1 1 1 0.92 87
1 0 0 0 1 0 0 0 0.925 88
1 0 0 0 1 0 0 1 0.93 89
1 0 0 0 1 0 1 0 0.935 8A
1 0 0 0 1 0 1 1 0.94 8B
1 0 0 0 1 1 0 0 0.945 8C

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 NCP81215P

Table 5. IMVP8 VID CODES (continued)

VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 Voltage Hex
1 0 0 0 1 1 0 1 0.95 8D
1 0 0 0 1 1 1 0 0.955 8E
1 0 0 0 1 1 1 1 0.96 8F
1 0 0 1 0 0 0 0 0.965 90
1 0 0 1 0 0 0 1 0.97 91
1 0 0 1 0 0 1 0 0.975 92
1 0 0 1 0 0 1 1 0.98 93
1 0 0 1 0 1 0 0 0.985 94
1 0 0 1 0 1 0 1 0.99 95
1 0 0 1 0 1 1 0 0.995 96
1 0 0 1 0 1 1 1 1 97
1 0 0 1 1 0 0 0 1.005 98
1 0 0 1 1 0 0 1 1.01 99
1 0 0 1 1 0 1 0 1.015 9A
1 0 0 1 1 0 1 1 1.02 9B
1 1 0 1 0 0 0 0 1.285 D0
1 1 0 1 0 0 0 1 1.29 D1
1 1 0 1 0 0 1 0 1.295 D2
1 1 0 1 0 0 1 1 1.3 D3
1 1 0 1 0 1 0 0 1.305 D4
1 1 0 1 0 1 0 1 1.31 D5
1 1 0 1 0 1 1 0 1.315 D6
1 1 0 1 0 1 1 1 1.32 D7
1 1 0 1 1 0 0 0 1.325 D8
1 1 0 1 1 0 0 1 1.33 D9
1 1 0 1 1 0 1 0 1.335 DA
1 1 0 1 1 0 1 1 1.34 DB
1 1 0 1 1 1 0 0 1.345 DC
1 1 0 1 1 1 0 1 1.35 DD
1 1 0 1 1 1 1 0 1.355 DE
1 1 0 1 1 1 1 1 1.36 DF
1 1 1 0 0 0 0 0 1.365 E0
1 1 1 0 0 0 0 1 1.37 E1
1 1 1 0 0 0 1 0 1.375 E2
1 1 1 0 0 0 1 1 1.38 E3
1 1 1 0 0 1 0 0 1.385 E4
1 1 1 0 0 1 0 1 1.39 E5
1 1 1 0 0 1 1 0 1.395 E6
1 1 1 0 0 1 1 1 1.4 E7
1 1 1 0 1 0 0 0 1.405 E8
1 1 1 0 1 0 0 1 1.41 E9
1 1 1 0 1 0 1 0 1.415 EA
1 1 1 0 1 0 1 1 1.42 EB
1 1 1 0 1 1 0 0 1.425 EC
1 1 1 0 1 1 0 1 1.43 ED
1 1 1 0 1 1 1 0 1.435 EE
1 1 1 0 1 1 1 1 1.44 EF

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 NCP81215P

Table 5. IMVP8 VID CODES (continued)

VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 Voltage Hex
1 1 1 1 0 0 0 0 1.445 F0
1 1 1 1 0 0 0 1 1.45 F1
1 1 1 1 0 0 1 0 1.455 F2
1 1 1 1 0 0 1 1 1.46 F3
1 1 1 1 0 1 0 0 1.465 F4
1 1 1 1 0 1 0 1 1.47 F5
1 1 1 1 0 1 1 0 1.475 F6
1 1 1 1 0 1 1 1 1.48 F7
1 1 1 1 1 0 0 0 1.485 F8
1 1 1 1 1 0 0 1 1.49 F9
1 1 1 1 1 0 1 0 1.495 FA
1 1 1 1 1 0 1 1 1.5 FB
1 1 1 1 1 1 0 0 1.505 FC
1 1 1 1 1 1 0 1 1.51 FD
1 1 1 1 1 1 1 0 1.515 FE
1 1 1 1 1 1 1 1 1.52 FF

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 NCP81215P

TA
VCC

IMVP8 EN
TB VBOOT

VSP

VR_RDY

SVID ALERT

SVID bis idle

SVC

SVD Status PKT

Figure 3.

VR_EN
(at the pin)
RESET
TD TF
VR_EN
(Internal)

TE
VR_READY
(open drain)

Figure 4. Startup Timing

Table 6.
MIN TYP MAX
TA 2.5 ms
TB VID / Slow
TD 0 μs 1 μs
TE 500 ns

CPU Driving, Single Data Rate VR Driving, Single Data Rate

SCLK SCLK

CPU send VR latch VR send CPU latch

SDIO SDIO

TCO_CPU tSU thld TCO_CPU TCO_VR tSU thld

TCO_CPU = clock to data delay in CPU TCO_VR = clock to data delay in VR
tsu = 0.5 × T − Tco_CPU tsu =T − 2 × Tfly − Tco_VR
thld = 0.5 × T + Tco_CPU thld =2 × Tfly + Tco_VR
Tfly propagation time on Serial VID bus

Figure 5. SVID Timing Diagram

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 NCP81215P

GENERAL
The NCP81215P is a three rail 4 + 2 + 1 phase PWM wires (SCLK, SDIO, ALERT#). The table of supported
controller with a single serial SVID control interface. registers for Domains 00h, 01h, and 02/03h is shown below.
The SVID register set for Domain 0Dh is smaller and
Serial VID contains the following registers: 00h, 01h, 02h, 05h, 10h,
The NCP81215P supports the Intel serial VID interface. 11h, and 1Bh.
It communicates with the microprocessor through three

Table 7.
Default
Index Name Description Access 00h/01h/02h PSYS 0Dh
00h Vendor ID Uniquely identifies the VR vendor. The vendor ID R 1Ah 1Ah
assigned by Intel to ON Semiconductor is 0x1A

01h Product ID Uniquely identifies the VR product. The VR vendor R 25h 25h
assigns this number.
25h = NCP81215P
02h Product Uniquely identifies the revision or stepping of the VR R
Revision control IC. The VR vendor assigns this data.

03h Product R
date code
ID
05h Protocol ID Identifies the SVID Protocol the controller supports. R 05h 05h
05h = IMVP8
06h Capability Informs the Master of the controller’s Capabilities R D1h N/A
Bit0 = Iout ADC (15h) = 1
Bit1 = Vout ADC (16h) = 0
Bit2 = Pout ADC (18h) = 0
Bit3 = I input ADC (19h) = 0
Bit4 = V input ADC (1Ah) = 1
Bit5 = P input ADC (1Bh) = 0
Bit6 = Temperature ADC (17h) = 1
Bit7 = 1 if (15h) is Iout = 1
10h Status_1 Data register read after the ALERT# signal is asserted. R 00h 00h
Conveying the status of the VR

11h Status_2 Data register showing optional status_2 data R 00h 00h
12h Temp zone Data register showing temperature zones the system is R 00h N/A
operating in
15h I_out 8 bit binary word ADC of current. This register reads R N/A
0xFF when the output current is at Icc_Max
17h VR_Temp 8 bit binary word ADC of voltage. Binary format in deg C, R N/A
IE 100C = 64h. A value of 00h indicates this function is
not supported
1Bh Input Required for Input Power Domain Address 0Dh R N/A
Power
1Ch Status2_la When the status 2 register is read its contents are R 00h N/A
st read copied into this register. The format is the same as the
Status 2 Register
21h Icc_Max Data register containing the Icc_Max the platform R 00h N/A
supports. The value is measured on the ICCMAX pin on
power up and placed in this register. From that point on
the register is read only
22h Temp_Max Data register containing the max temperature the plat- R/W 64h N/A
form supports and the level VR_hot asserts. This value
defaults to 100°C and programmable over the SVID
Interface
24h SR_fast Slew Rate for SetVID_fast commands. Binary format in R 1Eh N/A
mV/us
25h SR_slow Slew Rate for SetVID_slow commands. Determined by R 0Fh N/A
SR_Slow selector register (2Ah)

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 NCP81215P

Table 7. (continued)
Default
Index Name Description Access 00h/01h/02h PSYS 0Dh
26h Vboot Vboot is resistor programmed at startup. The controller R 00h N/A
will ramp to Vboot and hold at Vboot until it receives a
new SetVID command to move to a different voltage.
2Ah SR_Slow Fast_SR/2: default R/W 01h N/A
selector Fast_SR/4
Fast_SR/8
Fast_SR/16
2Bh PS4 exit Reflects the latency of exiting PS4 state. The exit latency R 8Ch N/A
latency is defined as the time duration, in μs, from the ACK of
the SETVID Slow/Fast command to the output voltage
beginning to ramp
2Ch PS3 exit Reflects the latency of exiting PS3 state. The exit latency R 55h N/A
latency is defined as the time duration, in μs, from the ACK of
the SETVID/SetPS command until the controller is capa-
ble of supplying max current of the command PS state.
2Dh EN to Reflects the latency from enable assertion to the VR R CAh N/A
Ready for controller being ready to accept SVID commands.
SVID
command
(TA)
2Eh Pin Max Input Power Sensor Scaling RW N/A FFh
30h Vout_Max Programmed by master and sets the maximum VID the RW FBh N/A
VR will support. If a higher VID code is received, the VR
should respond with “not supported” acknowledge.
IMVP8 VID format
31h VID setting Data register containing currently programmed VID volt- RW 00h N/A
age. VID data format
32h Pwr State Register containing the current programmed power state RW 00h N/A
33h Offset Sets offset in VID steps added to the VID setting for volt- RW 00h N/A
age margining. Bit 7 is sign bit, 0=positive margin, 1=
negative margin. Remaining 7 BITS are # VID steps for
margin 2s complement.
00h = no margin
01h = +1 VID step
02h = +2 VID steps
Ffh = −1 VID step
Feh = −2 VID steps
34h MultiVR 01h N/A
Config
42h IVID1−VID RW 00h N/A
43h IVID1−I Maximum instantaneous current for single phase RW N/A
operation
44h IVID2−VID RW 00h N/A
45h IVID2−I Maximum instantaneous current for IVID 2 state RW N/A
46h IVID3−VID RW 00h N/A
47h IVID3−I Maximum instantaneous current for DCM/CCM decision RW N/A
threshold

VID code change is supported by SVID interface with

three options as below:

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 NCP81215P

Table 8.
Register Address
(Indicating the slew rate
Option SVID Command Code Feature Description of VID code change)
SetVID_Fast 01h 30 mV/us 24h

SetVID_Slow 02h Adjustable 25h

Default setting is 1/2 of Fast Slew Rate
SetVID_Decay 03h No control, VID code down N/A

The NCP81215P is optimized to meet Intel’s IMVP8

specification and implements PS0, PS1, PS2, PS3 and PS4
power saving states.

Table 9.
Power State PWM Output Operating Mode of 2−Phase Rails
PS0 Multi−phase PWM interleaving output
PS1 Single−phase RPM CCM mode
PS2 Single−phase RPM DCM mode
PS3 Single−phase RPM DCM mode
PS4 Vout to 0 V, no phase state

NCP81215P Configurations
The NCP81215P has four Configuration pins that are ♦Options to enable doubling on the A rail is provided
secondary−functions on PWM pins. On power up a 10 μA in the Vboot configuration table
current is sourced from these pins through a resistor • Switching Frequency
connected to this pin and the resulting voltage is measured. ♦ Both multi−phase rails’ per−phase switching
The following features will be programmed: frequency will be the same programmable value
• SVID address ♦ The 1−phase Fsw is programmed independently
♦ 00h (IA) and 01h (GT) options for both multi−phase ♦ The Fsw values are shown in the ROSC table
rails • Vboot
♦ Single−phase rail can be 02h (SA) or 03h (GTUS) ♦ Addresses 00h, 01h, and 03 POR Vboot is 0 V
• Phase doubler ♦ Address 02h POR Vboot is 1.05 V
♦ The multi−phase A rail can use a Phase Doubler ♦ Vboot options are shown in the VBOOT table
from ON Semiconductor

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 NCP81215P

Boot Voltage measured. This value cannot be changed after the initial
Vboot for the NCP81215P is externally programmed power up sequence is complete.
using a single resistor.
See Vboot pin voltages and the corresponding Vboot level
in the table below. During startup, the pin voltage is

Table 10. VBOOT PIN 20 CONFIGURATION

Resistor 2PH_A VBOOT 2PH_B VBOOT 1PH VBOOT Rail A Doubler
6.19 kΩ 0V 0V 0V No
14.7 kΩ 0V 0V 0V Yes
24.9 kΩ 0V 0V 1.05 V No
37.4 kΩ 0V 0V 1.05 V Yes
53.6 kΩ 0V 0V 0.95 V No
73.2 kΩ 0V 0V 0.95 V Yes
97.6 kΩ 0V 0V 0.8 V No
130 kΩ 0V 0V 0.8 V Yes
169 kΩ 1.05 V 1.05 V 1.05 V No
215 kΩ 1.05 V 1.05 V 1.05 V Yes

SVID Address Pin 19 Configuration

Table 11. NCP81215P (4 + 2 + 1, PIN 21 = PWM4_4PH, PIN 26 = CSP4_4PH)

Pull−Down Slew Rate 4PH 2PH 1PH Pin 24 4PH Max 2PH Max
Resistor mV/ms Address Address Address TSENSE/PSYS Phases Phases
4.3 kΩ 00h 01h 02h PSYS 4 2
12.1 kΩ 00h 01h 03h TSENSE 4 2
30
19.6 kΩ 01h 00h 02h PSYS 4 2
31.6 kΩ 01h 00h 03h TSENSE 4 2
49.9 kΩ 00h 01h 02h PSYS 4 2
78.7 kΩ 00h 01h 03h TSENSE 4 2
10
121 kΩ 01h 00h 02h PSYS 4 2
174 kΩ 01h 00h 03h TSENSE 4 2

PSYS Remote Sense Amplifier (Multiphase)

The PSYS pin is an analog input to the NCP81215P. It is A high performance high input impedance true
a system input power monitor that facilitates the monitoring differential amplifier is provided to accurately sense the
of the total platform system power. The system power is output voltage of the regulator. The VSP and VSN inputs
sensed at the platform charging device, the NCP81215P should be connected to the regulator’s output voltage sense
facilitates reporting back current and through the SVID points. The remote sense amplifier takes the difference of
interface at address 0Dh. the output voltage with the DAC voltage and adds the droop
voltage to:
V DIFOUT + (V VSP * V VSN) ) (1.3 V * V DAC) ) (V DROOP * V CSREF) (eq. 1)
This signal then goes through a standard error High Performance Voltage Error Amplifier (Multiphase)
compensation network and into the inverting input of the A high performance error amplifier is provided for high
error amplifier. The non−inverting input of the error bandwidth transient performance. A standard type III
amplifier is connected to the same 1.3 V reference used for compensation circuit is normally used to compensate the
the differential sense amplifier output bias. system.

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 NCP81215P

Differential Current Feedback Amplifiers (Multiphase) 0.5 mOhm for accurate current balance. Fine tuning of this
Each phase has a low offset differential amplifier to sense time constant is generally not required. The individual phase
that phase current for current balance. The inputs to the current is summed into the PWM comparator feedback this
CSPx pins are high impedance inputs. It is also way current is balanced via a current mode control approach.
recommended that the voltage sense element be no less than

CSNx
CSPx
RCSN CCSN

L PHASE
SWNx VOUT R CSN + (eq. 2)
C CSN DCR

DCR LPHASE
1 2

Figure 6.

Total Current Sense Amplifier (Multiphase) low impedance virtual ground. The amplifier actively filters
The NCP81215P uses a patented approach to sum the and gains up the voltage applied across the inductors to
phase currents into a single temperature compensated total recover the voltage drop across the inductor series resistance
current signal. This signal is then used to generate the output (DCR). Rth is placed near an inductor to sense the
voltage droop, total current limit, and the output current temperature of the inductor. This allows the filter time
monitoring functions. The total current signal is floating constant and gain to be a function of the Rth NTC resistor
with respect to CSREF. The current signal is the difference and compensate for the change in the DCR with
between CSCOMP and CSREF. The Ref(n) resistors sum temperature.
the signals from the output side of the inductors to create a

CSN1 Rref1 Cref

1n
Rref2
CSN2

Rref3
CSN3

CSREF
+ CSCOMP
SWN1 Rph1
CSSUM −
Ccs1
SWN2 Rph2
Ccs2

SWN3 Rph3
Rcs2 Rcs1

150 k 75 k
Rth

220 k
Figure 7.

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 NCP81215P

The DC gain equation for the current sensing:

R CS1 R th
R CS2 )
R CS1)R th (eq. 3)
V CSCOMP*CSREF + * (Iout Total DCR)
R ph
Set the gain by adjusting the value of the Rph resistors. inductor and should not need to be changed. The NTC
The DC gain should be set to the output voltage droop. If the should be placed near the closest inductor. The output
voltage from CSCOMP to CSREF is less than 100 mV at voltage droop should be set with the droop filter divider.
ICCMAX then it is recommend increasing the gain of the The pole frequency in the CSCOMP filter should be set
CSCOMP amp. This is required to provide a good current equal to the zero from the output inductor. This allows the
signal to offset voltage ratio for the ILIMIT pin. When no circuit to recover the inductor DCR voltage drop current
droop is needed, the gain of the amplifier should be set to signal. Ccs1 and Ccs2 are in parallel to allow for fine tuning
provide ~100 mV across the current limit programming of the time constant using commonly available values. It is
resistor at full load. The values of Rcs1 and Rcs2 are set best to fine tune this filter during transient testing.
based on the 220 k NTC and the temperature effect of the
DCR@25C
FZ + (eq. 4)
2 PI L Phase
Programming the Current Limit (Multiphase) 100% current limit trips if the ILIMIT sink current exceeds
The current limit thresholds are programmed with a 10 μA for 50 μs. The 150% current limit trips with minimal
resistor between the ILIMIT and CSCOMP pins. The delay if the ILIMIT sink current exceeds 15 μA. Set the
ILIMIT pin mirrors the voltage at the CSREF pin and value of the current limit resistor based on the
mirrors the sink current internally to IOUT (reduced by the CSCOMP−CSREF voltage as shown below.
IOUT Current Gain) and the current limit comparators. The
R 1 R th
R CS2) CS
R CS1)R th
(Iout Total DCR)
R ph V CSCOMP * CSREF@ILIMIT (eq. 5)
R LIMIT + OR R LIMIT +
10 m 10 m
Programming DAC Feed−Forward Filter (Multiphase) constant to cancel the time constant of the system per the
The DAC feed−forward implementation is realized by following equations. Cout is the total output capacitance and
having a filter on the VSN pin. Programming Rvsn sets the Rout is the output impedance of the system.
gain of the DAC feed−forward and Cvsn provides the time

VSN
2

R68 C76
R vsn + C out R out 453.6 10 6
R out C out (eq. 6)
2.1 K 510 pF C vsn +
R vsn
1

VSS_SENSE

Figure 8.

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 NCP81215P

Programming DROOP (Multiphase)

The signals CSCOMP and CSREF are differentially
summed with the output voltage feedback to add precision
voltage droop to the output voltage.

DROOP
CSREF 5
+ 7 CSCOMP
CSSUM 6
−

Droop + DCR (R CSńR ph) (eq. 7)

Figure 9.

Programming IOUT (Multiphase) scaled with an external resistor to ground such that a load
The IOUT pin sources a current in proportion to the equal to ICCMAX generates a 2 V signal on IOUT. A
ILIMIT sink current. The voltage on the IOUT pin is pull−up resistor from 5 V VCC can be used to offset the
monitored by the internal A/D converter and should be IOUT signal positive if needed.
2.0V R LIMIT (eq. 8)
R IOUT +
R 1 R th
R CS2) CS
R CS1)R th
10 (Iout ICC_MAX DCR)
R ph
Programming ICC_MAX (Multiphase) Programming TSENSE
The SVID interface provides the platform ICC_MAX A temperature sense inputs are provided. A precision
value at register 21h for. A resistor to ground on the IMAX current is sourced out the output of the TSENSE pin to
pin programs these registers at the time the part is enabled. generate a voltage on the temperature sense network. The
10 μA is sourced from these pins to generate a voltage on the voltage on the temperature sense input is sampled by the
program resistor. The value of the register is 1 A per LSB internal A/D converter. A 100 k NTC similar to the VISHAY
and is set by the equation below. The resistor value should ERT−J1VS104JA should be used. Rcomp1 is mainly used
be no less than 10 k. for noise. See the specification table for the thermal sensing
R 10 mA 256 A voltage thresholds and source current.
ICC_MAX 21h + (eq. 9)
2V

TSENSE

Rcomp1
0.0

Cfilter
0.1uF

Rcomp2 RNTC
8.2 K 100 K

AGND AGND

Figure 10.

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 NCP81215P

Precision Oscillator is between 300 KHz/phase to 1.2 MHz/phase. The ROSC

A programmable precision oscillator is provided. The pin provides approximately 2 V out and the source current
clock oscillator serves as the master clock to the ramp is mirrored into the internal ramp oscillator. The oscillator
generator circuit. This oscillator is programmed by a resistor frequency is approximately proportional to the current
to ground on the ROSC pin. The oscillator frequency range flowing in the ROSC resistor.

Table 12. 4 PHASE / 2 PHASE / 1 PHASE FSW V ROSC (PIN21 / PIN22)

Resistor Per phase Fsw MPH Per phase Fsw 1PH
6.19 kΩ 1.2 MHz 1.2 MHz
14.7 kΩ 1.1 MHz 1.1 MHz
24.9 kΩ 1.0 MHz 1.0 MHz
37.4 kΩ 900 kHz 900 kHz
53.6 kΩ 800 kHz 800 kHz
73.2 kΩ 700 kHz 700 kHz
97.6 kΩ 600 kHz 600 kHz
130 kΩ 500 kHz 500 kHz
169 kΩ 400 kHz 400 kHz
215 kΩ 300 kHz 300 kHz

The oscillator generates triangle ramps that are 0.5~2.5 V Programming the Ramp Feed−Forward Circuit
in amplitude depending on the VRMP pin voltage to provide The ramp generator circuit provides the ramp used by the
input voltage feed forward compensation. The ramps are PWM comparators. The ramp generator provides voltage
equally spaced out of phase with respect to each other and feed−forward control by varying the ramp magnitude with
the signal phase rail is set half way between phases 1 and 2 respect to the VRMP pin voltage. The VRMP pin also has
of the multi−phase rail for minimum input ripple current. a 4 V UVLO function. The VRMP UVLO is only active after
For use with ON Semiconductor’s phase doubler, the the controller is enabled. The VRMP pin is high impedance
NCP81215P offers the user the ability to multiply the input when the controller is disabled.
frequency of multiphase rail A. On the NCP81215P, the The PWM ramp time is changed according to the
switching frequency is increased by a factor of 2 when the following:
phase doubler configuration is used. V RAMP + 0.1 V VRMP (eq. 10)
PP

Vin

Comp−IL

Duty

Figure 11.

PWM Comparators Pase Detection Sequence

The non−inverting input of the comparator for each phase The NCP81215P normally operates as a 4−ph VccCORE
is connected to the summed output of the error amplifier + 2−ph VccGT + 1−ph VccSA. Phases of the multi−phase
(COMP) and each phase current (IL*DCR*Phase Balance rails can be disabled by pulling up CSP pins to VCC.
Gain Factor). The inverting input is connected to the For example, to configure one of the 2 phase rails of the
oscillator ramp voltage with a 1.3 V offset. The operating NCP81215P as a 1 phase rail, CSP2 of that rail must be
input voltage range of the comparators is from 0 V to 3.0 V pulled up to Vcc on startup.
and the output of the comparator generates the PWM output Both the single−phase rail and the 2−phase rail B can be
During steady state operation, the duty cycle is centered disabled by pulling all of their associated CSP pins to Vcc.
on the valley of the sawtooth ramp waveform. The steady Phase 1 of 4PH rail A cannot be disabled.
state duty cycle is still calculated by approximately The PWM outputs are logic−level devices intended for
Vout/Vin. During a transient event, the controller will driving fast response external gate drivers or DrMOS. As
operate in a hysteretic mode with the duty cycles pull in for each phase is monitored independently, operation
all phases as the error amp signal increases with respect to approaching 100% duty cycle is possible. In addition, more
all the ramps. than one PWM output can be on at the same time to allow
overlapping phases.

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 NCP81215P

PROTECTION FEATURES

Under voltage Lockouts

There are several under voltage monitors in the system. DRON low and prevents the controller from being enabled.
Hysteresis is incorporated within the comparators. The gate driver will hold DRON low for a minimum period
NCP81215P monitors the 5 V VCC supply. The gate driver of time to allow the controller to hold off its startup
monitors both the gate driver VCC and the BST voltage. sequence. In this case the PWM is set to the MID state to
When the voltage on the gate driver is insufficient it will pull begin soft start.

DAC If DRON is pulled low the

controller will hold off its
startup

Gate Driver Pulls DRON

Low during driver UVLO
and Calibration

Figure 12. Gate Driver UVLO Restart

Soft start the PWMs will be set to 2.0 V MID state to indicate that the
Soft start is implemented internally. A digital counter drivers should be in diode mode. DRON will then be
steps the DAC up from zero to the target voltage based on the asserted. As the DAC ramps the PWM outputs will begin to
predetermined rate in the spec table. The PWM signals will fire. Each phase will move out of the MID state when the
start out open with a test current to collect data on phase first PWM pulse is produced. When the controller is
count and for setting internal registers. After the disabled the PWM signal will return to the MID state.
configuration data is collected, if the controller is enabled

PWM Driver Disabled

Internal Test Current MID Stats Until first
Applied PWM pulse Or DAC PWM returns to MID State
reaches target when controller is disabled

PWMx

DRON

VCC

Figure 13.

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 NCP81215P

Over Current Latch− Off Protection (Multiphase) The voltage swing of CSCOMP cannot go below ground.
The NCP81215P compares a programmable This limits the voltage drop across the DCR through the
current−limit set point to the voltage from the output of the current balance circuitry. An inherent per−phase current
current−summing amplifier. The level of current limit is set limit protects individual phases if one or more phases stop
with the resistor from the ILIM pin to CSCOMP. The current functioning because of a faulty component. The
through the external resistor connected between ILIM and over−current limit is programmed by a resistor on the ILIM
CSCOMP is then compared to the internal current limit pin. The resistor value can be calculated by the following
current ILC. If the current generated through this resistor into equations,
the ILIM pin (Ilim) exceeds the internal current−limit Equation related to the NCP81215P multiphase rails:
threshold current ILC, an internal latch−off counter starts, I LIM DCR R CSńR PH
and the controller shuts down if the fault is not removed after R ILIM + (eq. 11)
I CL
50 μs(shut down immediately for 150% load current) after
Where ICL = 10 μA
which the outputs will remain disabled until the Vcc voltage
or EN is toggled.

CSSUM

R1 R2

R1

R1

R1

CSCOMP

RLIM

ILIM
CSREF

Figure 14.

Under Voltage Monitor comparator will trip sending the VR_RDY signal low. The
The output voltage is monitored at the output of the 300 mV limit can be reprogrammed using the
differential amplifier for UVLO. If the output falls more VR_Ready_Low Limit register.
than 300 mV below the DAC−DROOP voltage the UVLO

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 NCP81215P

Over Voltage Protection VR_RDY flag goes low, and the output voltage will be
The output voltage is also monitored at the output of the ramped down to 0V. The part will stay in this mode until the
differential amplifier for OVP. During normal operation, if Vcc voltage or EN is toggled
the output voltage exceeds the DAC voltage by 400 mV, the

Figure 15. OVP During Normal Operation Mode

During start up, the OVP threshold is set to 2.0 V. This

allows the controller to start up without false triggering the
OVP.

Figure 16. OVP Behavior at Startup

Single−phase Rail frequency is digitally stabilized to remove frequency drift

The architecture of the single−phase rail makes use of a under all continuous mode operating conditions. At light
digitally enhanced, high performance, current mode RPM load the single−phase rail automatically transitions into
control method that provides excellent transient response DCM operation to save power.
while minimizing transient aliasing. The average operating

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 NCP81215P

Single−phase Rail Remote Sense Error Amplifier I COMP + gm[V DAC * (V VSP * V VSN)] (eq. 12)
A high performance, high input impedance, true This current is applied to a standard Type II compensation
differential transconductance amplifier is provided to network.
accurately sense the regulator output voltage and provide
high bandwidth transient performance. The VSP and VSN Single−phase rail voltage compensation
inputs should be connected to the regulator’s output voltage The Remote Sense Amplifier outputs a current that is
sense points through filter networks described in the applied to a Type II compensation network formed by
following Droop section and the DAC Feedforward filter external tuning components CLF, RZ and CHF.
section. The remote sense error amplifier outputs a current
proportional to the difference between the output voltage
and the DAC voltage:

DAC
− VSN
gm VSN
+
VSP

M
− VSP

COMP
CHF RZ
CLF

Figure 17.

Single−phase Rail – Differential Current Feedback match the inductor L/DCR time constant by setting the filter
Amplifier pole frequency equal to the zero of the output inductor. This
The single−phase controller has a low offset, differential makes the filter AC output mimic the product of AC inductor
amplifier to sense output inductor current. An external current and DCR, with the same gain as the filter DC output.
lowpass filter can be used to superimpose a reconstruction It is best to perform fine tuning of the filter pole during
of the AC inductor current onto the DC current signal sensed transient testing.
across the inductor. The lowpass filter time constant should
DCR@25C 1 (eq. 13)
Fz + FP +
2 p L R PHSP (R th)R CSSP)
2 p ( ) C CSSP
R PHSP)R th)R CSSP
Forming the lowpass filter with an NTC thermistor (Rth) Using 2 parallel capacitors in the lowpass filter allows fine
placed near the output inductor, compensates both the DC tuning of the pole frequency using commonly available
gain and the filter time constant for the inductor DCR change capacitor values.
with temperature. The values of RPHSP and RCSSP are set The DC gain equation for the current sense amplifier
based on the effect of temperature on both the thermistor and output is:
inductor. The CSP and CSN pins are high impedance inputs, R th ) R CSSP
but it is recommended that the lowpass filter resistance not V CURR + Iout DCR (eq. 15)
R PHSP ) R th ) R CSSP
exceed 10 kOhm in order to avoid offset due to leakage
To improve the noise immunity of the current feedback
current. It is also recommended that the voltage sense
amplifier, it is recommended to use an RC low pass filter (RF
element (inductor DCR) be no less than 0.5 mOhm for
and CF in Figure below) on the CSN pin of the amplifier
sufficient current accuracy. Recommended values for the
placed as close as possible to the controller. The bandwidth
external filter components are:
of this filter should be ~5 MHz with RF < 20 Ω. To mitigate
RPHSP = 7.68 kOhm
against noise due to excessive ringing that may be present on
RCSSP = 14.3 kOhm
the inductor side of RPHSP, it is recommended to use a
Rth = 100 kOhm, Beta = 4300
capacitor in parallel with the inductor. The value of the
1 capacitor should be chosen such that:
FP + (eq. 14)
R PHSP (R th)R CSSP)
2 p ( ) C CSSP ǸL 1
R PHSP)R th)R CSSP CƠ
2 p Ringing Fraquency (eq. 16)

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 NCP81215P

Rphsp
+ CSP
Av=1
− CSN
Rcssp
Ccssp To Inductor
t
Rth
COMP Rf

Cf
PWM CURR
t
Generator
Rth

RAMP PWM

Figure 18.

The amplifier output signal is combined with the COMP maintain output voltage within limits during load transients
and RAMP signals at the PWM comparator inputs to faster than those to which the regulation loop can respond.
produce the Ramp Pulse Modulation (RPM) PWM signal. In the NCP81215P, a loadline is produced by adding a signal
proportional to output load current (VDROOP) to the output
Single−phase Rail – Loadline Programming (DROOP) voltage feedback signal – thereby satisfying the voltage
An output loadline is a power supply characteristic regulator at an output voltage reduced proportional to load
wherein the regulated (DC) output voltage decreases by a current. VDROOP is developed across a resistance between
voltage VDROOP, proportional to load current. This the VSP pin and the output voltage sense point.
characteristic can reduce the output capacitance required to

+ VSN VSN
+
VSP RDRPSP
M

− VSP CSNSSP
TO VCC_SENSE
CORPSP

gm

RPHSP
CSP
+
CURRENT
Av=1 CSN RCSSP
SENSE AMP
− t TO INDUCTOR
Rth
CCSSP

Figure 19.

R th ) R CSSP
V Droop + R DRPSP gm I out DCR (eq. 17)
R PHSP ) R TH ) R CSSP
The loadline is programmed by choosing RDRPSP such
that the ratio of voltage produced across RDRPSP to output
current is equal to the desired loadline.
Loadline R PHSP ) R th ) R CSSP
R DRPSP + (eq. 18)
gm DCR R th ) R CSSP

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 NCP81215P

Single−phase Rail − Programming the DAC decrease the voltage between VSP and VSN. This causes the
Feed−Forward Filter output voltage during DVID to be regulated slightly higher,
The DAC feed−forward implementation for the in order to compensate for the response of the Droop
single−phase rail is the same as for the multi−phase rails. The function to the inductor current flowing into the charging
NCP81215P outputs a pulse of current from the VSN pin output capacitors. RFFSP sets the gain of the DAC
upon each increment of the internal DAC following a DVID feed−forward and CFFSP provides the time constant to
UP command. A parallel RC network inserted into the path cancel the time constant of the system per the following
from VSN to the output voltage return sense point, equations. Cout is the total output capacitance of the system.
VSS_SENSE, causes these current pulses to temporarily

DAC FEED- DAC FEEDFORWARD

FORWARD CURRENT
DAC CFFSP
FROM SVID TO
INTERFACE DAC CSS_SENSE
+ VSN VSN
gm
+
RFFSP

M
VSP CSNSSP
− VSP

Figure 20.

Loadline C out 20
R FFSP + C FFSP +
1.35 10 *9 W R FFSP nF (eq. 19)

Single−phase Rail – Programming the Current Limit current limit resistor based on the equation shown below. A
The current limit threshold is programmed with a resistor capacitor can be placed in parallel with the programming
(RILIMSP) from the ILIM pin to ground. The current limit resistor to slightly delay activation of the latch if some
latches the single−phase rail off immediately if the ILIM pin tolerance of short overcurrent events is desired.
voltage exceeds the ILIM Threshold. Set the value of the

RPHSP
CSP
+
CURRENT
Av=1 CSN RCSSP
SENSE AMP
− t TO INDUCTOR
Rth
CCSSP

gm
OVERCURRENT ILIM
PROGRAMMING
OVERCURRENT RILIMSP
COMPARATORS
OCP OCP REF

Figure 21.

1.3 V
R ILIMSP + (eq. 20)
R th)R CSSP
gm Iout LIMIT DCR
R PHSP)R th)R CSSP
When selecting the current limit it is necessary to take into VID changes, as this excess current may cause the OCP limit
account the additional inductor current due to the slew rate to be exceeded. This excess current is given by:
of the output voltage across the output capacitance during
dVout dVout
I + Cout , where is the maximum slew rate (eq. 21)
dt dt

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 NCP81215P

Single−phase Rail – Programming IOUT scaled with an external resistor to ground such that a load
The IOUT pin sources a current in proportion to the equal to ICCMAX generates a 2 V signal on IOUT. A
ILIMIT sink current. The voltage on the IOUT pin is pull−up resistor from 5 V VCC can be used to offset the
monitored by the internal A/D converter and should be IOUT signal positive if needed.

RPHSP
CSP
+
CURRENT
Av=1 CSN RCSSP
SENSE AMP
− t TO INDUCTOR
Rth
CCSSP

gm
IOUT

CURRENT
IOUT MONITOR ROUTSP

Figure 22.

2V
R IOUTSP +
R th)R CSSP (eq. 22)
gm IccMax DCR
R PHSP)R th)R CSSP
Single−phase Rail PWM Comparator Programming ICC_MAX (Single Phase)
A PWM pulse starts when the error amp signal (COMP The SVID interface provides the platform ICC_MAX
voltage) rises above the trigger threshold plus gained−up value at register 21h for. A resistor to ground on the IMAX
inductor current, and stops when the artificial ramp plus pin programs these registers at the time the part is enabled.
gained−up inductor current crosses the COMP voltage. Both 10 μA is sourced from these pins to generate a voltage on the
edges of the PWM signals are modulated. During a transient program resistor. The value of the register is 1 A per LSB
event, the duty cycle can increase rapidly as the COMP and is set by the equation below. The resistor value should
voltage increases with respect to the ramps, to provide a be no less than 10 k.
highly linear and proportional response to the step load.
Rmax 10 mA 256 A
ICC_MAX 21h + (eq. 23)
4 2V

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 NCP81215P

PACKAGE DIMENSIONS

QFN52 6  6, 0.4P
CASE 485BE
ISSUE B

NOTES:
1. DIMENSIONING AND TOLERANCING PER

ÉÉÉÉ
ASME Y14.5M, 1994.
D A B L L 2. CONTROLLING DIMENSIONS: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED

ÉÉÉÉ
TERMINAL AND IS MEASURED BETWEEN
PIN ONE L1 0.15 AND 0.30mm FROM TERMINAL TIP

ÉÉÉÉ
LOCATION 4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.

ÉÉÉÉ
DETAIL A MILLIMETERS
E ALTERNATE TERMINAL DIM MIN MAX
CONSTRUCTIONS A 0.80 1.00
A1 0.00 0.05

ÉÉÉ
A3 0.20 REF
0.10 C EXPOSED Cu MOLD CMPD b 0.15 0.25

ÉÉÉ
D 6.00 BSC
D2 4.60 4.80
0.10 C TOP VIEW E 6.00 BSC
E2 4.60 4.80
A
DETAIL B (A3) DETAIL B
e 0.40 BSC
0.10 C K 0.30 REF
ALTERNATE L 0.25 0.45
CONSTRUCTION
L1 0.00 0.15
L2 0.15 REF
0.08 C A1
NOTE 4 SIDE VIEW SEATING
C PLANE SOLDERING FOOTPRINT*
6.40 52X
4.80 0.63

L2
DETAIL C
D2 K L2
14 DETAIL A
DETAIL C
27 8 PLACES
4.80 6.40

E2 0.11
0.49
52X L PKG DETAIL D
OUTLINE 8 PLACES
DETAIL D
1 0.40 52X
52 40 PITCH 0.25
52X b DIMENSIONS: MILLIMETERS
e 0.07 C A B *For additional information on our Pb−Free strategy and soldering
BOTTOM VIEW 0.05 C NOTE 3
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.

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