4.

Design Examples

Dr Alister Hamilton

4-1
 Introduction
 In any design:
 State the problem.
 Obtain clear design specifications.
 Define basic building blocks necessary to
accomplish what is specified, e.g., adders, shift
registers, counters, etc.

A Verilog solution is provided to the first example in this set of notes.

Refer to the main reference text book for VHDL solutions to many of the
remaining examples. HDL solution of these examples is beyond the
scope of this course.
4-2
 Introduction (continued)
 Traditional design methodology:
 Data path: hardware that performs the data
processing.
 For microprocessor: the arithmetic logic unit (ALU)
 Controller: sends control signals to the data
path and can obtain feedback in the form of
status signals from the data path.
 Many modifications can be made here.

4-3
 Binary Coded Decimal (BCD)
 4-bit code word represents decimal 0-9
 Code word uses binary natural number bit weighting

A B C D Dec. A B C D Dec.
0 0 0 0 0 1 0 0 0 8
0 0 0 1 1 1 0 0 1 9
0 0 1 0 2 1 0 1 0 Nu
0 0 1 1 3 1 0 1 1 Nu
0 1 0 0 4 1 1 0 0 Nu
0 1 0 1 5 1 1 0 1 Nu
0 1 1 0 6 1 1 1 0 Nu
0 1 1 1 7 1 1 1 1 Nu
4-4
NU: code word not used. Dec.: Decimal value
BCD to 7-Segment Display Decoder
 Binary coded decimal (BCD): each decimal
digit is encoded into binary.
 7-segment displays are often used to display
digits in digital counters, watches, and clocks.
 Block diagram of a BCD to 7-segment display
decoder:

4-5
BCD to 7-Segment Display Decoder
(continued)
 Each digit is encoded into 4-bit binary
representation. This decoder is a purely
combinational circuit (no state machine).
 We can create a behavioral Verilog
architectural description by using a single
module with a case statement.

4-6
BCD to 7-Seg. Decoder (continued)
module bcd_seven (
input [3:0] bcd,
output reg [6:0] seven
);
always@ (bcd) begin
case (bcd)
4’h0: seven <= 7’b0111111;
4’h1: seven <= 7’b0000110;
4’h2: seven <= 7’b1011011;
4’h3: seven <= 7’b1001111;
4’h4: seven <= 7’b1100110;
4’h5: seven <= 7’b1101101;
4’h6: seven <= 7’b1111101;
4’h7: seven <= 7’b0000111;
4’h8: seven <= 7’b1111111;
4’h9: seven <= 7’b1101111;
default: seven <= 7’b0000000;
endcase
end
endmodule
4-7
 BCD Adder
 In BCD representation:
 A to F are not used. As 6 out of 16 representations
possible with 4 binary bits are skipped, a BCD
number will take more bits than the binary
representation.
 When BCD numbers are added:
 Each sum digit should be adjusted to skip the six
unused codes.
 Example: if 6 is added with 8, the sum is 14 in decimal
form. A binary adder would yield 1110, but the lowest
digit of the BCD sum should read 4. In order to obtain the
correct BCD digit, 6 should be added to the sum whenever
it is greater than 9.

4-8
 BCD Adder (continued)
 Addition of 2 BCD numbers:

4-9
 Full Adder (FA)
 Truth table
 defining carry status regions D, P and G.

A B Cin Cout S
0 0 0 0 0
Delete
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
Propagate
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
Generate
1 1 1 1 1

4-10
 4-bit ripple carry adder schematic

Bin[0] Ain[0] Bin[1] Ain[1] Bin[2] Ain[2] Bin[3] Ain[3]

fa0 fa1 fa2 fa3

A FA A FA A FA A FA
B Cy B Cy B Cy B Cy
Cin
Ci S Ci S Ci S Ci S
Cy[0] Cy[1] Cy[2]

Sum[0] Sum[1] Sum[2] Sum[3] Co

11
 32-Bit Adders
 Ripple-Carry Adder:
 32 copies of a 1-bit adder are connected in
succession.
 The carry “ripples” from the least significant bit
to the most significant bit.
 If gate delays are tg, a 1-bit adder delay is 2tg.
 A 32 bit ripple-adder will take 64 gate delays. If
gate delays are 1 ns, then the max frequency
of the operation is 16 MHz. Hence, many use
faster adders.

4-12
 32-Bit Adders (continued)
 Carry Look-Ahead Adder:
 Carry signals are calculated in advance, based on the
input signals.
 For any stage i, the carry-out is: Ci 1  Ai Bi  ( Ai  Bi ) Ci
 Carry generate (Gi): Gi  Ai Bi
 Carry propagate (Pi): Pi  Ai  Bi or Pi  Ai  Bi
 Sum signal: Si  Ai  Bi  Ci  Pi  Ci
 Carry-out equation can be rewritten by substituting the
carry generate (Gi) and carry propagate (Pi) equations.
Thus: Ci 1  Gi  PC
i i

 In a 4-bit adder, the Ci’s can be generated by repeating the

equation above.

4-13
 32-Bit Adders (continued)
 4-bit carry look-ahead adder:

gets quite complicated for more than 4 bits.

For that reason, carry look-ahead adders are
usually implemented as 4-bit modules and
are used in a hierarchical structure to realize
adders that have multiples of 4 bits.

4-14
 32-Bit Adders (continued)
 Disadvantage of the carry look-ahead adder:
 Logic gets quite complicated for more than 4 bits. Usually
implemented as 4-bit modules and used in a hierarchical
structure to realise adders that have multiples of 4 bits.
 Block carry look-ahead logic: generates input
carry bits to be fed to each 4-bit adder using a
group propagate (PG) and group generate (GG)
signal, which is produced by each 4-bit adder. The
next level uses PG and GG and generates the
required carry bits in parallel.

4-15
 32-Bit Adders (continued)
 The group propagate PG and generate GG will
be available after 3 and 4 gate delays (1 or 2
additional delays than the Pi and Gi signals).

4-16
 32-Bit Adders (continued)
 Equations for block carry look-ahead:
C4  GG 0  PG 0C0
C8  GG1  PG1GG 0  PG1 PG 0C0
C12  GG 2  PG 2GG1  PG 2 PG1GG 0  PG 2 PG1 PG 0C0

 C16, which is a final carry of 16-bit CLA, is:

C16  GG  PGC0
 Verilog code for a 16-bit carry look-ahead
adder can be done by instantiating 4 copies of
the 4-bit carry look-ahead adder and 1 more
copy of the carry look-ahead logic.

4-17
 32-Bit Adders (continued)
 Parallel Prefix Adders:
 Involve usage of propagate and generate bits,
as well as a primitive operation on the
propagate and generate bits.
 Examples: Kogge-Stone, Ladner-Fisher, Brent-
Kung, Han Carlson

4-18
 32-Bit Adders (continued)
 Parallel Prefix Adders: Kogge-Stone

4-19
 32-Bit Adders (continued)
 Delays of adders for a gate-based
implementation:

CLA adder includes 3 and 4 input logic gates with delay tg. Kogge Stone
adder uses 2 input logic gates with delay Tg.

4-20
 Traffic Light Controller
 Design a traffic light controller for the
intersection of streets A and B.
 Sa = 1: a vehicle is approaching on street A;
Sb = 1: a vehicle is approaching on street B.
 Street A has a green light until a vehicle
approaches on street B.
 Ga, Ya, and Ra drive street A lights; Gb, Yb,
and Rb drive street B lights.

4-21
Traffic Light Controller (continued)
 Block diagram and state graph:

4-22
 State Graphs for Control Circuits
 Notations and conditions used on control state
graphs:
 Variable names are used, not 0’s and 1’s
 Label of arc on a Mealy state graph XiXj/ZpZq:
means if inputs Xi and Xj are 1, the outputs Zp
and Zq are 1 (other outputs are 0).

4-23
 State Graphs for Control Circuits
(continued)
 To ensure next states are uniquely defined for
inputs, we must have constraints on the input
labels for every state Sk:
 1. If Ii and Ij are any pair of input labels on arcs
exiting state Sk, then Ii Ij = 0 if i ≠ j.
 At most one input label can be 1 at any given time.
 2. If n arcs exit state Sk and have input labels
I1, I2, . . ., In, respectively, then I1+I2+. . .+ In
= 1.
 At least one input label will be 1 at any given time.

4-24
 Scoreboard and Controller
 Display scores from 0 to 99.
 Inputs: reset, increment, and decrement.
 Output: current score on 7-segment displays.
 Must press reset for 5 cycles to reset display.
 Data path:

4-25
 Scoreboard and Controller
(continued)
 Controller:
 FSM with 2 states: initialisation S0 and counting
S1.
 State graph:

4-26
 Synchronisation and Debouncing
 Issues in systems with external inputs:
 Synchronisation: outputs from a keypad or push-
button switches are not synchronous to the system
clock signal.
 Switch bounce: when a mechanical switch is
closed or opened, the switch contact will bounce,
causing noise in the switch output. After switch
closure, must wait for the bounce to settle before
reading the key (several milliseconds).
 Flip-flops are very useful devices when contacts
must be synchronised and debounced.

4-27
 Synchronisation and Debouncing
(continued)
 Single pulser:
 It is very difficult for humans to produce a
signal that only lasts for a clock pulse.
 Solution: develop a circuit that generates a
single pulse for a human action of pressing a
button or switch.
 State diagram with 2 states:

4-28
 Synchronisation and Debouncing
(continued)
 Since there are only two states for this circuit,
it can be implemented using one flip-flop.
 Equation for single pulse:
SP = S0∙SYNCPRESS
 Single pulser and synchroniser circuit:

4-29
 Add-and-Shift Multiplier
 In A × B, the first operand (A) is called the
multiplicand, and the second operand (B) is
called the multiplier.
 Binary multiplication process:
 Multiplicand is shifted.
 Next bit of multiplier is examined (also a
shifting step).
 If this bit is 1, the shifted multiplicand is added
to the product.

4-30
 Add-and-Shift Multiplier
(continued)
 Example: multiply 1310 by 1110 in binary:

 Sometimes called a serial-parallel multiplier, as

the multiplier bits are processed serially while
addition takes place in parallel.

4-31
 Add-and-Shift Multiplier
(continued)
 Example reworked to show the location of the
bits in the registers at clock time:

4-32
 Add-and-Shift Multiplier
(continued)
 State graph for control circuit (designed to
output the proper sequence of add and shift
signals):

4-33
 Add-and-Shift Multiplier
(continued)
 As the state graph for the multiplier indicates,
the control performs 2 functions—generating
add or shift signals as needed and counting
the number of shifts. If the number of bits is
large, it is convenient to divide the control
circuit into a counter and an add-shift control:

4-34
 Add-and-Shift Multiplier
(continued)
 First, derive a state graph for the add-shift control
that tests St and M and outputs the proper
sequence of add and shift signals.

 Then we will add a completion signal (K) from the

counter that stops the multiplier after the proper
number of shifts have been completed.

4-35
 Add-and-Shift Multiplier
(continued)
 The counter is incremented each time a shift signal is
generated. If the multiplier is n bits, n shifts are
required.
 Design the counter so that a completion signal (K) is
generated after n - 1 shifts have occurred.
 When K = 1, the circuit should perform one more
addition, if necessary, and then do the final shift.
 Final state graph for add-shift control:

4-36
 Array Multiplier
 Array multiplier: a parallel multiplier that
generates the partial products in a parallel
fashion. Partial products are added as soon as
they are available.

4-37
 Array Multiplier (continued)
 4-bit multiplier partial products:

4-38
Array Multiplier (continued)

4-39
 Array Multiplier (continued)
 The longest path (from input to output): 8
adders. If tad is the worst-case delay through
an adder, and tg is the longest AND gate
delay, then the worst-case time to complete
the multiplication is 8tad + tg.
 An n-bit-by-n-bit array multiplier requires n2
AND gates, n(n - 2) full adders, and n half-
adders.

4-40
 Array Multiplier (continued)
 For an n × n array multiplier, the longest path
from input to output goes through n adders in
the top row, n-1 adders in the bottom row
and n-3 adders in the middle rows.
 Worst-case multiply time: (3n - 4)tad + tg.
 The longest delay in a circuit: critical path.
 Worse-case can be improved to 2ntad + tg by
forwarding carry from each adder to the
diagonally lower adder.

4-41
A Signed Integer/Fraction Multiplier
 Binary fixed point:
 1. Split number into integer and fraction parts
of pre-defined widths (fixed-point).
 2. Define number of significant digits along with
an indicator—the exponent—of where to set the
point (floating-point).

4-42
A Signed Integer/Fraction Multiplier
(continued)
 Binary fixed point example:
 Need to have at least 5 bits for the integer for
the sign. So in 9-bit format:
Value Fixed 1’s 2’s
complement complement
-13.45 01101.0111 10010.1000 10010.1001

4-43
A Signed Integer/Fraction Multiplier
(continued)
 When both the multiplicand and the multiplier
are positive, standard binary multiplication is
used:

4-44
A Signed Integer/Fraction Multiplier
(continued)
 When the multiplicand is negative and the
multiplier is positive, extend the sign bit of
the multiplicand so that the partial products
and final product will have the proper
negative sign:

4-45
A Signed Integer/Fraction Multiplier
(continued)
 When the multiplicand is positive and the
multiplier is negative, make a slight change in
the multiplication procedure. A negative
fraction of the form 1.g has a numeric value -
1 + 0.g:
 So, for 1.g: treat .g as a positive fraction, but
the sign bit is treated as -1.
 When we reach the negative sign bit, we must
add in the 2’s complement of the multiplicand
instead of the multiplicand itself.

4-46
A Signed Integer/Fraction Multiplier
(continued)
 When the multiplicand is positive and the
multiplier is negative:

4-47
A Signed Integer/Fraction Multiplier
(continued)
 When both the multiplicand and the multiplier
are negative, the procedure is the same as
before. Preserve the proper negative sign,
and at the final step, add in the 2’s
complement of the multiplicand:

4-48
A Signed Integer/Fraction Multiplier
(continued)
 Hardware required to multiply two 4-bit
fractions (includes sign bit):

4-49
A Signed Integer/Fraction Multiplier
(continued)
 State diagram for the control circuit:

4-50
A Signed Integer/Fraction Multiplier
(continued)

4-51
A Signed Integer/Fraction Multiplier
(continued)
 To speed up the operation
of the multiplier: move
wires from the adder
output one position to the
right, so the adder output
is shifted over one position
when it is loaded into the
accumulator.
 With this arrangement, the
add and shift operations
can occur at the same
clock time.

4-52
A Signed Integer/Fraction Multiplier
(continued)
 To test the multiplier, test not only the four
standard cases (++,+-,-+, and --), but also
special cases and limiting cases.
 Test values for the multiplicand and multiplier
should include 0, the largest positive fraction,
the most negative fraction, and all 1’s.
 The test bench will provide a sequence of
values for the multiplicand and the multiplier.
It can also check for the correctness of the
multiplier output.

4-53
A Signed Integer/Fraction Multiplier
(continued)
 Interface between multiplier and its test
bench:

4-54
 Keypad Scanner
 Design for scanner for keypad will include:
 Three columns and four rows. The keypad is
wired in matrix form with a switch at
intersections.
 Purpose of scanner: to determine which key
has been pressed and to output a binary
number (N = N3N2N1N0) that corresponds to
the key number. When a valid key has been
detected, the scanner should output a signal V
for one clock time.
 Hardware to protect the circuitry from
malfunction due to keypad bounces.

4-55
 Keypad Scanner (continued)
 Block diagram:

4-56
 Keypad Scanner (continued)
 Divide the design into modules:
 Scanner: scans rows and columns of keypad.
 Keyscan module: creates the column signals to
scan the keyboard.
 Debounce module: creates a signal K when a
key has been pressed and a signal Kd after it’s
been debounced.
 Decoder: determines the key number from the
row and column numbers upon selection of a
valid key.

4-57
 Keypad Scanner (continued)
 Scanner procedure:
 Apply logic 1’s to columns C0, C1, and C2 and wait. If any
key is pressed, a 1 will appear on R0, R1, R2, or R3. Apply
a 1 to column C0 only. If any of the Ri’s is 1, a valid key is
detected. If R0 is received, one knows that switch 1 was
pressed.
 If R1, R2, or R3 is received, it indicates switch 4, 7, or *
was pressed. If so, set V = 1 and output the
corresponding N.
 If no key is detected in the first column, apply a 1 to C1
and repeat.
 If no key is detected in the second column, repeat for C2.
 When a valid key is detected, apply 1’s to C0, C1, and C2
and wait until no key is pressed.

4-58
 Keypad Scanner (continued)
 Debounce and synchronise the circuit to avoid
malfunctions:

4-59
 Keypad Scanner (continued)
 Decoder: a combinational circuit; determines
the key number from the row and column
numbers using a truth table that has one row
for each of the 12 keys. The remaining rows
have don’t care outputs as it is assumed that
only one key is pressed at a time.

4-60
 Keypad Scanner (continued)
 Truth table and logic equations for decoder:

4-61
 Keypad Scanner (continued)
 Controller: waits in S1 with outputs
C0=C1=C2=1 until a key is pressed.

4-62
 Keypad Scanner (continued)
 Timing issues with preceding state diagram:
 1. Is K true whenever a button is pressed? No.
 2. Can Kd be false when a button continues to
be pressed? Yes.
 3. Can you go from S5 to S1 when a button is
still pressed? S4-to-S5 transition could happen
when Kd is false. Kd might have become false
while scanning C0 and C1. Hence, it is possible
that one reaches back to S1 when the key is
still being pressed.

4-63
 Keypad Scanner (continued)
 Timing issues (continued):
 4. What if a key is pressed for only one or two
clock cycles? If the key is pressed and released
very quickly, there would be problems,
especially if the key is in the third column. By
the time the scanner reaches state S4, the key
might have been released already.

4-64
 Keypad Scanner (continued)
 Issues can be fixed by assuring that one can
reach S5 only if Kd is true. Modified state
diagram:

4-65
 Keypad Scanner (continued)
 Test Bench:
 Simulates a key press by supplying the
appropriate R signals in response to the C
signals from the scanner. When test bench
receives V = 1 from the scanner, it checks to
see whether the value of N corresponds to the
key that was pressed.

4-66
 Keypad Scanner (continued)
 Test process:
 1. Read a key number from the array to
simulate pressing a key.
 2. Wait until V = 1 and the rising edge of the
clock occurs.
 3. Verify that the N output from the scanner
matches the key number.
 4. Set KN = 15 to simulate no key pressed.
(Since 15 is not a valid key number, all R’s will
go to 0.)
 5. Wait until Kd = 0 before selecting a new key.

4-67
 Binary Dividers
 Binary division process:
 Shift dividend left.
 Enter the quotient bit-by-bit into the right end of
the dividend register as dividend is shifted left.
 If divisor is going to be negative, shift dividend one
place to the left before subtraction.
 Subtract to get new dividend.
 Shift dividend left. If result will be negative, repeat
shift then subtract.
 Perform final shift.
 If the quotient contains more bits than are available
for storing the quotient, an overflow has occurred.

4-68
 Binary Dividers (continued)
 Unsigned divider:
 Example: divide an 8-bit dividend by a 4-bit
divisor to obtain a 4-bit quotient:

4-69
 Binary Dividers (continued)
 9-bit dividend register and a 4-bit divisor
register:

 Initially, the dividend and divisor are entered

as:

4-70
 Binary Dividers (continued)
 Shift dividend left:

 Subtract. First quotient digit of 1 is stored in the

unused position of the dividend register:

 Shift dividend one place left:

4-71
 Binary Dividers (continued)
 Subtraction would yield a negative result, so
shift dividend left again (2nd quotient remains
zero):

 Subtract. Third quotient digit of 1 is stored in

the unused position of the dividend register:

 Final shift. Fourth quotient bit is set to 0.

4-72
 Binary Dividers (continued)
 State diagram and table for unsigned divider :

4-73
 Binary Dividers (continued)
 Signed Divider:
 Example: design of a divider for signed (2’s
complement) binary numbers that divides a 32-
bit dividend by a 16-bit divisor to give a 16-bit
quotient.
 Can complement the dividend and divisor if
they are negative; when division is complete,
complement the quotient if it should be
negative.

4-74
 Binary Dividers (continued)
 Block diagram for signed divider:

4-75
 Binary Dividers (continued)
 Control signals:

4-76
 Binary Dividers (continued)
 Signed divider (2’s complement) process:
 1. Load the upper half of the dividend from the bus,
and copy the sign of the dividend into the sign flip-
flop.
 2. Load the lower half of the dividend from the bus.
 3. Load the divisor from the bus.
 4. Complement the dividend if it is negative.
 5. If an overflow condition is present, go to the
done state.
 6. Otherwise carry out the division by a series of
shifts and subtracts.
 7. When division is complete, complement the
quotient if necessary and go to the done state.

4-77
 Binary Dividers (continued)
 Signed divider: testing for overflow:
 Consider all positive numbers. Since the divisor
and quotient are each 15 bits plus sign, their
maximum value is 7FFFh. Since the remainder
must be less than the divisor, its maximum
value is 7FFEh. Therefore, the maximum
dividend for no overflow is:
 Divisor × quotient + remainder = 7FFFh ×
7FFFh + 7FFEh = 3FFF7FFFh
 If the dividend is 1 larger (3FFF8000h), division
by 7FFFh (or smaller) will give an overflow.

4-78
 Binary Dividers (continued)
 Test for overflow condition:
 Shift the dividend left one place and then
compare the upper half of the dividend (divu)
with the divisor.
 If divu  divisor , the quotient would be greater
than the maximum value, which is an overflow
condition.

4-79
 Binary Dividers (continued)
 State diagram for signed divider:

4-80
 Summary
 Traditional design methodology splits a design
into a “data path” (the ALU) and a “controller.”
 Non-arithmetic circuit examples:
 BCD (binary code display) to 7-segment display
 BCD adder
 Keypad scanner
 Arithmetic circuit examples:
 Shift-and-Add Multiplier (and serial-parallel
multiplier)
 Array multiplier

4-81
 Summary (continued)
 Notations and conditions used on control state
graphs were outlined.
 Issues in systems with external inputs:
 Synchronisation
 Debouncing
 Many design examples included a block
diagram and state graph
 Verilog code for first example only
 VHDL code and test bench for others in
reference text book (beyond the scope of this
course).

4-82
 Summary (continued)
 Algorithms described:
 Addition
 Multiplication
 Division of unsigned and signed binary
numbers. Discussion of overflow.

4-83