Physical Layer Architecture for 1-Wire Sensor

Communication Bus
Binary Channel Code Division Multiple Access

Benjamin Peiffer, Anton Kruger

Department of Electrical Engineering
The University of Iowa
Iowa City, IA USA
{bmpeiffe,akruger}@engineering.uiowa.edu

Abstract—Researchers at The University of Iowa have sensors or instruments via a terminal emulator and
encountered the need for an efficient 1-wire interrogate the sensor for wind-speed and direction.
communication protocol for use in embedded systems and Commercial data loggers have a number of serial
distributed wired sensors. One possible solution for this interfaces including RS-232.
problem is the use of a Wired Code Division Multiple
Thus far, a star configuration has been assumed—all
Access (CDMA). Although this approach has been
investigated before, a key simplification can made with the the sensors interface directly to a data logger.
use of a binary wired-OR channel. This paper develops However, there are also sensor bus interfaces available.
the theory for such a protocol, including a mathematical The advantages of using a bus are clear: it simplifies the
formulation of the Bit Error Rate, and describes physical interconnection, it is cost effective, and it is
experiments that are being conducted to determine the flexible. One widely used and well-documented bus is
validity of this approach, including a software simulation the RS-485 standard. Another common bus is Serial
to calculate expected Bit Error Rate and prototype Data Interface At 1200 Baud (SDI-12). All busses,
hardware to verify the practicality of this design. including SDI-12 and RS-485, need some form of
medium access control (MAC). This is typically
I. INTRODUCTION
implemented using Time Division Multiple Access
The most basic interface for commonly used sensors (TDMA) with a bus master that manages access to the
in environmental and geosciences research, such as communication channel. The use of TDMA for MAC
temperature and humidity sensors, and optical has several problems. Only one user at a time can own
radiometers is a simple analog voltage output. The the bus, and timing is absolutely critical. The timing
attendant data logger samples and digitizes the voltages. constraint is especially problematic because it dictates
The signal levels and the analog nature of the signals slew rates, cable capacitance and, consequently, cable
limit the distance between sensors and data logger, length.
since long wires can cause voltage drops and are In [4], the author uses TDMA to provide the
susceptible to noise. To address the issues, many physical layer communication among a wired soil
sensors have associated electronics that amplify, moisture network. Although this was a successful
modulate and otherwise manipulate the signals making approach, it came at the cost of high software
them more amenable to transmission. For example, in complexity and the need for a common clock at each
one scheme the voltage at the sensor is converted to a node in the network. Ideally, a system could be
square wave with a frequency proportional to the developed that requires no strict synchronization, low
voltage. The data logger measures the frequency of the hardware complexity, low software complexity, and
square wave. Other schemes include pulse-width- supports multiple transceivers on a single wire.
modulated square waves and current loops. One way to implement such a system would be with
The sensor interfaces discussed up to this point are the use of Code Division Multiple Access (CDMA),
essentially analog. Many expensive sensors and rather than TDMA. In [7], the authors describe the use
virtually all full-blown instrumentation have digital of a CDMA protocol within the context of Very Large
interfaces. In this instance, electronics at the sensor Scale Integration (VLSI) and System on a Chip (SoC).
digitize the sensor voltage and provide the information In this case, CDMA is used to communicate over either
in digital format to the data logger. Thus, a wind- a k-bit wide peripheral bus or a 1-wire analog channel.
speed and wind-direction sensor may have an RS-232 In the k-bit wide bus, a receiver can view the k-lines as
interface that one can connect to, for example, a PC. bits of a signal with 2k possible values. At each time
One would then send simple ASCII commands to the

This project has been funded through the Iowa Flood Center at The
University of Iowa

978-1-4244-8064-7/11/$26.00 ©2011 IEEE

instant, the receiver identifies the inpuut value, and then
behaves exactly as a wireless CDMA reeceiver.
While both of the approaches desccribed in [7] are
valid and appropriate for VLSI systems, they do not
accomplish the goals outlined in thiss paper. In the
single-wire case, the hardware complexxity can be high,
as is shown in [1] and [6]. In either case, a true bus
interface is no longer being implem mented. Instead,
there are two star configuratiions that are
interconnected, by either 1 or k wires. Figure 1. System Block Diiagram
As an alternative to the commoon TDMA-based
busses and the multi-wire or analog C CDMA, we will the channel.
discuss the design of a simple buus interface for Based on these requirements, it is logical that a
environmental instrumentation. The buus is a 1-wire, all binary channel must be used. In order to further reduce
digital, CDMA implementation. Theree is no bus master complexity, a wired-OR is chossen as the channel
or TDMA involved in the protocol. Deevices on the bus model. This channel model can be b implemented with
can transmit and receive asynchroonously without very inexpensive and simple hardware components, and
interfering with other channel sharers. the implementation does not depen nd on the number of
users. With these assumptions, each
e transmitter can
II. BINARY CHANNEL WIREED CDMA behave exactly as in a wireless CDM
MA environment.
In order to understand the reasons for choosing an B. Transmitter Scheme
interface like the one described in section I, stricter
In the proposed system, the trransmitter takes the
requirements must be formed. The aanalysis of these
Exclusive-OR (XOR) of each bit of o the message with
requirements leads to the conclusion that the use of
each bit of the codeword c[n] (bits of
o the codeword will
CDMA with a Binary Channel model, rather than an
be referred to as chipping bits). Because the transmitter
Additive Channel Model, would bee convenient in
and receiver are Linear Time-Invaariant, the length of
sensor systems.
the message, m[n] is irrelevant to ouro discussion. The
A. Binary Channel Assumption length of the codeword will be N ch hipping bits. Each of
1) No Strict Synchronization the data chips passes into the chann nel through a wired-
The protocol should have no requirrement for phase OR circuit. Thus, the output of onee transmitter is ORed
synchronization. Transmitters and reeceivers need to with the outputs of all other transm mitters on the bus at
agree on a data rate only. the same time instant. We model th he output of all other
2) Low Hardware Complexity transmitters, referred to as the co-cchannel interference,
Each wire on the bus should have digital values to as a noise signal r[n].
minimize the amount of analog circuitryy needed. C. Codeword Probability Distributtion
3) Low Software Complexity Initially, we will consider the co
ode word’s chipping
The transmitter and receiver algorithhms should be as bits to be pseudo-random, agaain with an equal
similar to wireless CDMA as possible. likelihood of all possible values.. This simplifying
4) Multiple Users on a Single Data Wire assumption is shown in (1). In n (2) more general
The system should operate full duuplex on a single equations for the codeword chipp ping bit values are
wire and should be operable when mulltiple users share shown. We will consider (2) to be the first system
design equation, which could be ad djusted to manipulate
the co-channel interference.

P (c[n0 ] = 0 ) = P (c[n0 ] = 1) = 0.5 (1)

P (c[n0 ] = 0 ) = p
(2)
P (c[n0 ] = 1) = 1 − p

Thus, at any instant in time when w the system is

transmitting, the probability of the transmitted message
Figure 2. Conceptual Drawing of 1-Wire Comm
munication System 2).
being either a 1 or a 0 is given by (2
 Figure 4. Decode Threshold Concep
pt Illustrated
the vectors are completed uncorrelaated; in other words,
the receiver should reject the signaal because it is not a
message to be received. If the correlation
c is 0, the
codeword and the message signal are a identical and thus
Figure 3. Basic Receiver Algorithhm
a ‘1’ bit has been decoded. If the correlation is N, the
codeword and the message signal are a opposite and thus
D. Noise Characterization
a ‘0’ bit has been decoded.
Because the noise signal is the ORR of the output of In order to provide some degreee of noise immunity,
all other transmitters using the chhannel, we can the receiver could also include a threshold
t concept as
continue to use (2). The noise signal will be the chip- shown in Fig. 4. If the correlation is less than 0 plus the
wise OR of M-1 transmitted signals, where M is the threshold value, the signals are nearrly identical and thus
number of simultaneous channel transm mitters. It is also there is a high probability that a ‘1’ bit has been
important to note that when the ranndom noise is 0 decoded. If the correlation is greatter than N minus the
valued, it does not affect the message signal; so in that threshold value, then there is a hig gh probability that a
case, the message chip is always coorrectly received. ‘0’ bit has been decoded.
The message chip is also correctly receeived whenever it Finally, the receiver could prov vide additional noise
is a 1. A random variable R can be uused to represent immunity by implementing an algorithm a to detect
the number of noise chips, 1s, assserted by M-1 “illegal” message chips. For insstance, imagine the
transmitters in the system during an N chip interval. A transmitter codeword is (1010). At A the receiver, the
probability density function representinng the probability message (1000) is received. Thee XOR operation is
of noise on the bus can be written as iin (3). It is clear performed on these two vectorss is (0010). The
that we can adjust the amount of noise in the system by Hamming weight of this result iss 1. If the system
adjusting the overall probability of 0s or 1s in a correlation threshold offset is 1, this vector will be
codeword. decoded as a 0 bit sent from the traansmitter. However,
P ( R > 0 ) = 1 − ( p ) M −1 (3) since the only type of channel errror possible is 0→1,
the received word (1000) could no ot correspond to the
E. Receiver Scheme code word (1010) since a 1→0 errror is implied in the
One obvious scheme for decoding messages would third chip. This concept tak kes advantage the
be to design a receiver that behaves exactly like a unidirectional nature of errors in thee channel.
receiver in a wireless CDMA system. To accomplish
this, a shift register of length N is impllemented and the III. CDMA BUS SIMULATION ENGINE
incoming channel bits are shifted into the register at In order to validate the analysiss of the CDMA Bus
each time instant. The correlation of the received bits system design, a simulation engine has been developed
with the relevant codeword is calculatted by taking the using the Java programming languaage. The simulation
Exclusive-OR of the two and then calculating the engine was designed to allow experimentation
e and
Hamming weight of the resultant vectorr. investigation of the bit error rate of message signals
For binary vectors of length N, thee correlation will being passed through the system. The system allows
be between 0 and N. A correlation of N N/2 indicates that for the adjustment of the numb ber of simultaneous

Figure 5. Java Simulator Results for Lenggth 32 Codes Figure 6. Java Simulator Results for Length
L 1024 Codes
 Figure 8. Hardware System Bllock Diagram
varied to gain an understanding of the system capacity.
Figure 7. Simulator Console Ouutput Two different test cases are shown in Fig. 5 and Fig. 6.
channel users, code word length, and ddecoder threshold Fig. 5 shows simulation data for a 32-bit codeword
levels. After detailed use of the simullation engine, the length, the same code length as the hardware of section
results support the viability of such a system. The IV, and a varying number of userss. The vertical axis
simulator has four components, which w will be discussed shows the bit error rate (BER). In I this case, the Bit
here. Error rate refers to both the num mber of incorrectly
A. Simulation Engine Design decoded bits and the number off dropped bits. As
shown in Fig. 7, the system also reecords the number of
1) CDMA Transceiver dropped bits, so this could be subtrracted from the BER
The CDMA Transceiver represennts one message to gain an idea of the system capaabilities if Automatic
node. It is assigned a purely random codeword and a Repeat Query (ARQ) functionality was added. For the
random message of the required length.. 32-bit codeword test case, the sy ystem maintains 0%
2) Message Encoder BER up to 2 simultaneous userss. The system has
The simulator encoder encodes a given message reasonably low BER up to 3 userss, but at this point it
with a given codeword. In order to doo this it performs would be useful to implement chan nnel coding at the bit
the XOR operation each bit of the meessage with each level. Beyond 3 users, the errore rate increases
chip of the code word that has been assigned. exponentially and it would be neceessary to implement
3) Binary Channel Model ARQ and error coding.
The binary channel takes in M messsages and Fig. 6 shows a test case for 1024-bit codeword
performs a bitwise OR operation on theem. It then length. In this case, up to 6 userss can simultaneously
outputs an array representing the time sseries that the share the channel with a 0% BER. As the number of
channel output would see. users increases, it again becomes clear that ARQ and
4) Message Decoder error coding are necessary.
The message decoder implementts the decoding
algorithm that has been developed. It returns the IV. PROTOTYPE HARDWARE
E INVESTIGATION
decoded message for post processing.
A. Protototype Hardware Design
B. Preliminary Simulation Results In order to prove the practicality of the Binary
The simulator has been used to investigate the Channel CDMA system design in sensor and embedded
properties of the system. The code llength, threshold systems applications, a hardwaree design has been
offset and number of simultaneous uusers have been developed. The hardware was designed to allow
experimentation and investigation of
o the bit error rate of
message signals being passed throu ugh the system with
additional noise degradation fro om real hardware
components. The system supports up to 8 users, has a
32-bit codeword length, and co ontains a software
adjustable decoder threshold leveel. For the initial
investigation, random 32-bit integerrs were generated as
codes. After preliminary use of the prototype hardware,
the results of the mathematical anaalysis and simulation
engine experiments have been empiirically verified.
The basic prototype hardware contains two Atmel
ATMEGA164P microcontrollers. As shown in Fig. 8,
Figure 9. Binary Channel CDMA Prototyype Hardware
one of these processors is wired to perform
p receive path
Digital Signal Processing (DSP) opeerations and the
other is wired to perform both transmit and receive path
DSP operations. To establish the wiired-OR channel,
each transmitter is connected to thee gate of an N-
Channel MOSFET in an inverter confiiguration. If any
transmitter on the channel outputs hiigh-valued logic,
the channel will be pulled low. As shoown in Fig. 8, the
channel data line is also connected to tthe gate of an N-
Channel MOSFET in an inverter connfiguration. The
drain of this FET is connected to the receive path DSPs.
Thus, when the channel goes low, the receiver reads a Figure 11. Two Channel User Test Case
high value.
V. FUTURE WORK AND CONCLUSIONS
B. Prototype Hardware Testing It has been shown that the use of a wired CDMA-
Two testing scenarios have been coonducted with the OR channel can allow
like protocol with a binary wired-O
prototype hardware. First, a looppback test was a small number of users to share s a bus while
conducted. In this scenario, a trransceiver sends maintaining reasonable bit-error-rattes. Under a system
messages to itself. A PC is used to control the node with these assumptions, there arre no strict timing
over RS-232. The PC can thenn command the requirements for users, only the data rate must be
transmitter to send certain messagess and view the common between a transmitter and d receiver. With the
messages as the receiver decodes them m. This allows for binary-channel assumption, the system
s hardware is
verification of the test setup, prototypee hardware build- simplistic, requiring only a few NMOS FETs per
quality, software correctness aand that the transceiver. The software at the transmitter can be
communication system will work iin a noise free nearly identical to a wireless CDMA A and at the receiver
environment. After minor debuggiing, the system can be very similar to a wireless CDMA, with some
operated with a 0% Bit Error Rate. T This matches our special considerations that have been discussed.
expectations from the simulation enviroonment. Finally, the system can be implem mented using a single
The second hardware test places tw wo transceivers on data-wire.
the same bus. One of these transceiivers is operated The authors are currently in nvestigating coding
identically to the first test that was described. The schemes that will optimize the bit b error rate of the
second transmitter is programmed with a special system. More work will also be do one on the simulation
software load as a “noise generator”. This transmitter engine and the design of thee receiver decoder
continuously takes the XOR of its ccodeword with a algorithms. A two-wire system wherew one wire is a
random message bit and sends thhis information. connected to a wired-OR channeel and the other is
Preliminary tests of the system w with two users connected to a wired-AND chaannel will also be
transmitting simultaneously have shoown the receiver investigated. Finally, the current hardware
h design will
connected to the test PC is able to ddecode messages be miniaturized in preparation for use in sensor
with approximately a 10% Bit Errror Rate. This applications at the IIHR-Hydroscien nce and Engineering
empirical result shows a similar outcom me to the results and the Iowa Flood Center at The University
U of Iowa.
of the simulator, where the simulatorr shows slightly
better results than the real hardwaree. This can be ACKNOWLEDGMEN
NTS
explained by slight differences in the ssimulator and the The authors would like to thaank the Iowa Flood
real hardware, which can be rectifiedd with additional Center and IIHR for providing the support
s and need for
development of the decoding algorithm m. this project. We would also like to
o thank S. Dasgupta,
R. Mudumbai, and M. Andersland of o The University of
Iowa Department of Electrical En ngineering for their
valuable input.
REFERENCES
[1] B. Tan, et al. (2010, Oct. 12). An Effficient Data Transmission
Interface for VLSI Systems using Code-Division Multiple Access
Technique [Online]. Available:
http://www.imec.be/esscirc/esscirc2001/C01_Presentations/184.
pdf
[2] H. Schulze, C. Lüders, Theory and Ap pplications of OFDM and
Figure 10. Single Channel User Test Case CDMA: Wideband Wireless Commu unications, West Sussex,
England: Wiley, 2005.
[3] J. Kim, I. Verbauwhede, M.-C.F. Chang, "Design of an
Interconnect Architecture and Signaling Technology for
Parallelism in Communication," Very Large Scale Integration
(VLSI) Systems, IEEE Transactions on , vol.15, no.8, pp.881-
894, Aug. 2007.
[4] J. Niemeier, “Embedded instrumentation for soil temperature
and soil moisture monitoring,” M.S. thesis, Dept. of Elect. Eng.,
Univ. of Iowa, Iowa City, IA, 2007.
[5] J. Proakis, M. Salehi, “Wireless Communications,” in
Communications Systems Engineering, 2nd ed.Upper Saddle
River: Prentice Hall, 2002.
[6] R. Bell Jr., et al. (2010, Oct 12). CDMA as a Multiprocessor
Interconnect Strategy [Online]. Available:
http://lca.ece.utexas.edu/pubs/asilomar0.pdf
[7] T. Nikoclic, G. Djordjevic, M. Stojcev, "Simultaneous data
transfers over peripheral bus using CDMA technique,"
Microelectronics, 2008. MIEL 2008. 26th International
Conference on , pp.437-440, 11-14 May 2008.
[8] T. Nikolic, M. Stojcev, G. Djordjevic, “CDMA bus-based on-
chip interconnect infrastructure,” Microelectronics Reliability,
vol. 49, no. 4, pp. 448-459, April 2009.
[9] V. Ipatov, Spread Spectrum and CDMA: Principles and
Applications, West Sussex, England: Wiley, 2005.