Pulse & Digital Circuits

Unit-I
1. Draw the RC high pass circuit and derive gain response for a sinusoidal input.

𝑉 (𝑠) 𝑅 1
A=𝑉0(𝑠)= 1 = 1
𝑖 𝑅+ 1+
𝐶𝑠 𝑅𝐶𝑠
Substitute s =jω
1 1
A= 1 = 1
1−𝑗 1−𝑗
𝜔𝑅𝐶 2𝜋𝑓𝑅𝐶

1
|A|= 1
√(1+( )2
2𝜋𝑓𝑅𝐶

1
At lower cut-off frequency f1, |A| =
√2
1 1
1 =
√(1+( )2) √2
2𝜋𝑓𝑅𝐶

1
Hence f1 =2𝜋𝑅𝐶

Draw the RC low pass circuit and derive gain response for a sinusoidal input

Sinusoidal Input:
For the circuit shown above, if sinusoidal signal is applied as an input, the output Vo is given by
1
𝑉0 𝐶𝑠 1 1
= 1 = = 1+𝑗2𝜋𝑓𝑅𝐶
𝑉𝑖 𝑅+ 1+𝑗𝜔𝑅𝐶
𝐶𝑠

1
|A| =
√[1+(2𝜋𝑓𝑅𝐶)2]
 1
At upper cut-off frequency f2,/A/ = √2
1 1
=
√2 √[1+(2𝜋𝑓2𝑅𝐶)2]

1
f2 =2𝜋𝑅𝐶
1
A = 𝑗
1+𝑗
𝑓2

Draw the RC high pass circuit and explain its response for a step input.

Step Input:

A step input of amplitude V is applied to the RC high pass circuit at t = 0. Since the
voltage across the capacitor cannot change instantaneously, V0 = Vi at t = 0. Later the capacitor
charges exponentially and hence the output decays exponentially. Therefore, at steady state
voltage across the capacitor is equal to applied voltage. The output voltage for t > 0 is given by
V0(t) = Vf–(Vf - Vi) e-t/RC
1. = 0 – (0 - V)e-t/RC = Ve-t/RC
Draw the RC low pass circuit and explain its response for a step input.
Step Input:
Step voltage is defined as, Vi= 0 for t < 0
and Vi=V for t > 0
When a step voltage is applied as in put to the low pass circuit the output will be appeared as
shown. we have V0(t) = Vf +(Vf – Vi )e-t/RC

.Where Vi = 0
Vf= V
V0(t) = V - V e-t/RC
= V(1 - e-t/RC)
As V→ ∞ , V0(t) → V
Rise time tr:
It is time required by the output response to rise from 10% to 90% of its final steady state
value.
V0(t) = V(1 - e-t/RC)
At t = t1 ,V0= 0.1 V
V = V (1-e-t/RC)
−𝑡
= ln(0.9)
𝑅𝐶
t = 0.1RC
Similarly time required for the output to reach 90% of its final value is t = 2.3RC
tr = 2.3RC -0.1RC = 2.2RC
tr= 2.2τ
1
But f2 = 2𝜋𝑅𝐶
2.2 0.35
tr =2𝜋f2 = f2

Sketch the output waveform of an RC high-pass circuit with a square wave input under
different time constants. Derive the expression for percentage of tilt
A square wave shown in Figure (a) is a periodic waveform, which maintains itself at one
constant level V with respect to ground for a time T{ and then changes abruptly to another level
V" and remains constant at that level for a time T2, and then repeats itself at regular intervals of
T = T\ + T2. A square wave may be treated as a series of positive and negative steps. The shape
of the output depends on the time constant of the
circuit. Figures (b), (c),(d), and (e) show the output waveforms of the high-pass RC circuit under
.steady-state conditions for the cases (a) RC » T, (b) RC > T, (c) RC - T, and (d) RC « T
respectively.
When the time constant is arbitrarily large the output is same as the input but with zero dc level.
When RC > T, the output is in the form of a tilt. When RC is comparable to T, the
output rises and falls exponentially. When RC « T (i.e. RCIT\ and RC/T2 are very small
in comparison to unity), the output consists of alternate positive and negative spikes. In
this case the peak-to-peak amplitude of the output is twice the peak-to-peak value of the
input. In fact, for any periodic input waveform under steady-state conditions.
Expression for the percentage tilt We will derive an expression for the percentage tilt when the
time constant RC of the circuit is very large compared to the period of the input waveform, i.e.
RC » T. For a symmetrical square wave with zero average value.

V1 – V’1
Percentage tilt p = 𝑉 ×100
2
At t= 0, V0 = V1
For t >0 , V0 = V1e-t/RC --- (1)
At t = T/2, V0 = V’1
Therefore V’1 = V1e-T/2RC --- (2)
We have V = V’1 + V2 --- (3)
Also V1 = V2 and V’1 = V’2
Substituting V’1 = V1e-T/2RC and V2 = V1 in (3)
V = V1e-T/2RC +V1
= V1(1+e-T/2RC)
V
Or V1 = 1+e−T/2RC --- (4)
V1 – V’1
Therefore, Percentage Tilt P = 𝑉 ×100
2
V1 – V1e−T/2RC
P= ×100
𝑉/2
𝑉
From (4), V1 = 1+e−T/2RC
(1 – e−T/2RC)
P= × 200
1+ e−T/2RC
𝑇 𝑇
If <<1 , then e-T/2RC = 1- 2𝑅𝐶 because ex = 1- x
2𝑅𝐶
𝑇
1−(1− )
2𝑅𝐶
% P= 𝑇 × 200
1+(1+ )
2𝑅𝐶

𝑇
%P= ×100
2𝑅𝐶

πf1
= ×100
f

Explain the working of RC high pass circuit as a differentiator.

The High Pass RC Circuit as a differentiator:

Applying KVL, Vi = VC + VR
1
But VC = 𝐶 ∫ 𝑖 𝑑𝑡 and VR = V0
1 0 𝑉
𝐶
∫ 𝑖 𝑑𝑡 +V0 = Vi where I = 𝑅
1 V0
Vi = 𝐶 ∫ 𝑑𝑡 +V0
R
Differentiating w.r.t t
1 𝑉0 𝑑𝑉0 𝑑𝑉𝑖
( ) + 𝑑𝑡 = 𝑑𝑡 --- (1)
C 𝑅
1 𝑑𝑉0 𝑑𝑉𝑖 𝑑𝑉0 1
(𝐶𝑅) V0 + 𝑑𝑡 = 𝑑𝑡 where 𝑑𝑡 is transient response and (𝑅𝐶)𝑉0is steady state response.
If RC << T, transient response is ignored.
1 𝑑𝑉𝑖 𝑑𝑉𝑖
(𝐶𝑅)V0 = 𝑑𝑡 or V0 = RC 𝑑𝑡
If RC << T, the output is proportional to the derivative of the input.

Explain the working of RC low pass circuit as an integrator

The Low Pass RC Circuit as an Integrator:
Circuit:
If the time constant of the low pass RC circuit is very large compared to the time period
of the signal, then the circuit acts as an integrator. In such a case the drop across C is negligible
compared to the drop across R. the entire input appears across R.
VR = Vi = iR
𝑉𝑖
i= 𝑅
∫ idt
V0 = VC = 𝐶
1
= ∫Vidt, the output is proportional to the integral of input
𝑅𝐶

Draw an attenuator circuit with RC components and explain the condition for perfect
compensation.
Compensated Attenuator:
A Compensated attenuator is shown below. The compensation is provided by shunting
R1 by a capacitance C1.
The compensated attenuator is represented in a bridge form as shown below. The bridge will be
balanced when
R1C1 = R2C2
Under balanced condition no current will be flowing through XY hence omitted. Then the output
is V0 = a × Vi which is independent of frequency. For precise adjustment C1 is kept adjustable.

Step Response:
Consider a step input of magnitude ‘A’ is applied at t = 0 to the compensated attenuator.
The input changes from 0 to ‘A’ at t = 0.But the voltage across the capacitors cannot change
abruptly. They act as short circuits at t = 0 and charge to q at t = 0+.

At t = 0+, using Kirchoff ‘s law,

𝑞 𝑞
A = C1 + C2
C1 +C2
A=q[ ] ---(1)
C1C2

Output voltage = voltage across capacitor C2 at t = 0+

𝑞
Vo(0+) = C
2

Substituting q from (1)

AC1 C2
Vo(0+) = (C
1 +C2 )C2

AC1
Vo(0+) = This is the initial value of output voltage.
(C1 +C2 )

In the steady state at t = ∞, the capacitors act as open circuits. Hence the final value of the
output voltage is determined by the resistors.
AR2
Vo(∞) = R
1 +R2

For perfect compensation

Vo(0+) = Vo(∞)
AC1 AR2
=R
C1 +C2 1 +R2

(R1+R2) C1 = R2(C1+C2)
R1 C1 = R2C2

Application of Attenuator in CRO Probe:

The attenuator probe reduces the level of the signal such that it can be perfectly displayed
on the CRO. A shielded cable is used to connect the signal to the CRO. The capacitance of such
cable is about 100 to 150 pF.

A CRO probe is shown above. It consists of metal shield along with a shielded cable. The
metal shield is of few inches and shielded cable is few feet long. The input capacitance of probe
assembly is 20 to 10 F. The attenuation factor is 10 or 20.

Unit-II
Classify different types of diode clippers and explain shunt type clipper.

Classification of clippers:

Parallel clipper:
 𝑅𝐿
If R1<<RL, the output is V0 = Vin[𝑅 ] = Vin
1 +𝑅𝐿

Parallel clipper with reference voltage VR:

The parallel positive clipper with additional battery as reference voltage is shown in the
fig. During the positive half cycle of the input but less than VR, the diode is reverse biased, and
output is
𝑉𝑅
V0 = 𝑅 𝑖+𝑅𝐿 = Vi
𝐼 𝐿

Input is positive and greater than VR, the diode is forward bias acts as a short. The output is
V0 = VR.
When Vi again becomes less than VR, diode is OFF and V0 =VR.

Draw and explain the clipping at two independent levels

Double Diode Clipping:
In single diode clipping circuit, the wave form is selected either above or below (but not
on both sides) reference level. Two diode clippers may be used in parallel, series, or
Series - parallel to limit the output at two independent levels.

Consider the circuit shown in the Fig.

The transfer curve has two break points, one at Vo = Vi = VR1 and a second at Vo = Vi =
VR2 has the following characteristics Vo
Input voltage Output Voltage Diode states
Vi >VR2, Vo =VR1 D1 is OFF and D2 is ON,
Vi < VR1, Vo =Vi D1 is ON D2 is OFF,
VR1< Vi < VR2, Vo =VR2D1 and D2 are OFF

A combination of a positive peak clipper and a negative peak clipper, clipping the input
Symmetrically at the top and the bottom is called a limiter.

The transfer characteristic of limiter is as shown below.

Two zener diodes in series opposing, constitutes double-ended clipper. If the diodes have
identical characteristics, then a symmetrical limiter is obtained. If the breakdown voltage is VZ
and if the cut-in voltage in the forward direction is Vγ, then the transfer characteristic is as shown
below.
Draw and explain the working of emitter coupled clipper using transistors.
Emitter-coupled transistor clipper:

Initially the input voltage Vi is negative enough to ensure that Q1 is in Cut-off. Then Q2 is
carrying current. The VBB has been adjusted so that Q2 is in its active region. As Vi increases Q1
will come out of cut-off, both transistors will be carrying current and the input signal will appear
at the output, amplified but not inverted. As Vi continues in the positive direction the common
emitter will follow the base of Q1.The base of Q2 is fixed, a point will be reached when the rising
emitter cuts off Q2. Finally, the input signal is amplified but twice limited, once by the cutoff of
Q1 and once by the cutoff in Q2.
The transfer characteristic is shown in fig. Thus, this circuit behaves as a two-level clipper. The
region of linearity can be controlled by the choice of VBB.

Draw the circuit of negative clamper and explain its working with waveforms.
Negative clamper:
 A negative clamper which adds a negative level to the ac output is shown in the fig.
During the first quarter of the positive cycle, the diode is forward biased and the capacitor
charges instantaneously to the maximum value Vm. The charged capacitor acts as a battery of
voltage Vm as shown.
V0 = Vin-Vm

When the diode conducts, V0 = 0

During negative half cycle the diode is reverse biased but the capacitor remains charged at Vm
due to large time constant.

V0 = Vin – Vc= Vin – Vm

V0 = - Vm for Vin = 0
V0 = 0 for Vin = Vm
V0 = - 2Vm for Vin = - Vm

Draw the circuit of positive clamper and explain its working with waveforms.
Positive clamper:

During the first quarter of the negative half cycle, the diode is forward biased and the
capacitor charges instantaneously to the maximum value Vm. The charged capacitor acts as a
battery of voltage Vm as shown.

V0 = Vm for Vin = 0
V0 = 2Vm for Vin = Vm
V0 = 0 for Vin = - Vm
State and prove clamping circuit theorem.
Under steady state, for any input waveform, the ratio of the area under the output curve in
𝐴 𝑅
forward direction to the area under the output curve in reverse direction.𝐴𝐹 = 𝑅𝑓
𝑅

During T1 , diode is OFF. The capacitor discharges. Discharging currentisiR

𝑉
Charge lost QL = ∫ iRdt whereiR = 𝑅𝑅
𝑉
QL = ∫ 𝑅𝑅 dt
𝑉
During T2 charge gained QC = ∫ ifdt where if = 𝑅𝑓
𝑓
Under steady state QL = QC
𝐴𝐹 𝑅𝑓
=
𝐴𝑅 𝑅

Explain the effect of diode characteristics on clamping voltage.

The fig shows the clamper circuit with Rs and Rf.
Consider the input is a square wave as shown above.

When the input suddenly raises, the capacitor charges through the forward biased diode. The
equivalent circuit as shown below. The resistance is (Rs+Rf).

When the input decreases, the diode is OFF and capacitor discharges through R as shown.

The output has over shoot and under shoot when the input changes suddenly and
increases/decreases when the input is constant.
V11 = V1e-T1/(Rs+Rf)C
V21 = V2e-T2/(R+Rs)C
Compare between clippers and clampers.
clippers clampers
Limits or clips a portion of the Shifts the DC level of the
waveform waveform
Remove unwanted portions of Shift the waveform to a certain
the signal level
Positive or negative Positive or negative
Voltage level is limited or DC level is added or shifted
clipped
Used in Audio and video Used in Audio and video
processing, signal processing, signal
conditioning, communications conditioning, communications

UNIT-III

Junction diode switching times:

Let the diode be ON for some time, as a result there is a large current due to injected hole or
electron density
 When the diode is ON the number of minority carriers is large. When the polarity of the
external voltage is suddenly reversed, the diode forward current when ON being large is to be
reduced to reverse current which is very small. But this is not happened as it takes a finite time
delay for the minority carrier density distribution to take the form shown in fig. During this
period the injected minority carrier density will drop to zero and the minority carrier density
reaches the equilibrium value.

As long as the voltage Vi = VF till t1, the diode is ON. The forward resistance of the
 𝑉
diode being negligible when compared to RL, therefore I = 𝑅𝐹. At t = t1, the polarity
𝐿

−𝑉𝐹
of Vi is abruptly reversed, i.e.Vi= -VR and –I = 𝑅 until t = t2 at which time minority carrier
𝐿

density pnat x = 0 has reached the equilibrium value pn0.At t = t2 the charge carriers have been
swept, the polarity of the diode voltage reverses, the diode current starts to decrease.
The time duration, t1 to t2, during which period the stored minority charge becomes zero
is called the storage time ts.
The time interval from t2 to the instant that the diode has recovered (V = -VR) is called
the transition time, tt. The sum total of the storage time, ts and the transition time, tt is called the
reverse recovery time of the diode, trr.
Trr = ts + tr
TRANSISTOR AS A SWITCH
A transistor can be used as a switch. It has three regions of operation. When both emitter base
and collector-base junctions are reverse biased, the transistor operates in the cut-off region and it
acts as an open switch. When the emitter base junction is forward biased and the
collector base junction is reverse biased, it operates in the active region and acts as auf amplifier.
When both the emitter-base and collector-base junctions are forward biased, it! operates
in the saturation region and acts as a closed switch. When the transistor is switched!
from cut-off to saturation and from saturation to cut-off with negligible active region, then
transistor is operated
as a switch. When the transistor is in saturation, junction voltages are very small but the
operating currents are large. When the transistor is in cut-off, the currents are zero
(except small leakage current) but the junction voltages are large.
In Figure the transistor Q can be used to connect and disconnect the load RL from the source
Vcc When Q is saturated it is like a closed switch from collector to emitter and when Q is cut-
off it is like an open switch from collector to emitter.
Referring to the output characteristics shown in Figure 3.6(b), the region below the IB = 0 curve
is the cut-off region. The intersection of the load line with IB = 0 curve is the cut-off
point. At this point, the base current is zero and the collector current is negligible. The
emitter diode comes out of forward bias and the normal transistor action is lost, i.e, VCE(cut-off)
= Vcc. The transistor appears like an open switch.

The intersection of the load line with the IB - Ie(sat) curve is called the saturation point. At this
point, the base current is IB(sat) and the collector current is maximum. 'At saturation,
the collector diode comes out of cut-off and again the normal transistor action is lost, i.e. Ic(sat)
=
Vcc/RL.Ie(sat) represents the minimum base current required to bring the transistor into
saturation. For 0 < IB < IB(sat), the transistor operates in the active region. If the base current is
greater than IB(sat), the collector current approximately equals VCC/IC and the transistor
appears like a closed switch.
Transistor switching times:
Let the input to the transistor switch be a pulse of duration T. When a pulse is applied,
because of stray capacitances, collector current will not reach the steady state value
instantaneously. To know exactly when the device switches into the ON state and also into the
OFF state we define the following switching times of the Transistor.
Delay Time, td: It is the time taken for the collector current to reach from its initial valueto 10%
of its final value

If the rise of the collector current is linear, the time required to rise to 10%IC(sat) is 1/8 the
time required for the current to rise from 10% to 90% IC(sat).
It is given as
1
td = 8trwheretr is the rise time

Rise Time, tr :It is the time taken for the collector current to reach from 10% of its finalvalue to
90% of its final value.
However, because of the stored charges, the current remains unaltered for sometime
interval ts1 and then begins to fall. The time taken for this current to fall from its initial value at
ts1 to 90% of its initial value is ts2. The sum of these ts1 and ts2 is approximately ts1 and is called
the storage time.
Storage time, ts :It is the time taken for the collector current to fall from its initial value to 90%
of its initial value.

Fall time, tf :It is the time taken for the collector current to fall from 90% of its initial value to
10% of its initial value.
Explain the procedure of designing a transistor switch

Fixed bias binary:

The circuit uses two npn transistors Q1 and Q2. The collector of Q2 is coupled to the base
of Q1 through R1 and the collector of Q1 is connected to the base of Q2 through another resistance
R1. Let us assume Q2 starts conducting ahead of Q1 hence current through Q2 is more than
current through Q1. This is a cumulative process hence current through Q2 increases and that
through Q1 decreases.
 Finally, Q1 is cut off and Q2 is saturation. This is a stable state of the multi. It will remain
in this stable state until an external pulse is applied. If a positive pulse is applied at the base of
Q1, it will drive Q1 to saturation and Q2 to cut off. This is the second stable state of the multi. The
multi continue in this stable state even the external pulse is removed.
Hence the two stable states of the bistable multi are
1. Q1 off and Q2 on
2. Q2 off and Q1 on.
When Q1 is on : VC1 = VCesat , VB1 = VBesat
When Q2 off : VC2 = VCC, VB2 = VBecut off
Output voltage swing = VC2-VC1

Design of a fixed bias binary:

Design a fixed bias binary with supply voltages +12V, NPN silicon devices having VCE(sat)=
0.2V , VBE(sat)= 0.7V and hFemin = 50 are used. Assume IC = 5mA.

𝑉𝐶𝐶 −𝑉𝐶𝐸𝑠𝑎𝑡 12−0.2𝑉 11.8𝑉

RC = = = = 2.36KΩ
𝐼𝐶 2 5𝑚𝐴 5𝑚𝐴
 = 2.2 K
𝑉𝜎 –(−(𝑉𝐵𝐵 )
R2 = 𝐼2
1
Choose I2 = IC2 = 0.5mA
10
0.7+12
R2 = 25.4KΩ = 22 KΩ
0.5
𝐼𝐶2 5𝑚𝐴
IB2min = = = 0.1mA.
ℎ𝐹𝐸𝑚𝑖𝑛 50

If Q2 is in saturation

IB2 = 1.5 IB2min

= 0.15 mA
I1 = I2 + IB2
= 0.5 mA + 0.15 mA = 0.65 mA
𝑉𝐶𝐶 − 𝑉𝜎 12−0.7 11.3𝑉
R C + R1 = = 0.65𝑚𝐴 = 0.65𝑚𝐴 = 17.38KΩ
𝐼1

R1 = (RC + R1) – RC
= 17.38 – 2.36 = 15.02KΩ
Choose R1 = 15 KΩ
The designed circuit with component values is shown below

To verify whether Q2 is in saturation and Q1 is OFF or not.

𝑉𝐶𝐶 −𝑉𝐶𝐸𝑠𝑎𝑡
IC2 = = 5.36mA.
2.2𝐾
5.36𝑚𝐴
IB2min = = 0.107mA.
50
 𝑉𝜎 + 𝑉𝐵𝐵 12.7
I2 = = = 0.58mA.
𝑅2 22𝐾

𝑉𝐶𝐶 − 𝑉𝜎 12−0.7
I1 = = = 0.94mA.
𝑅𝐶 + 𝑅1 2+10

IB2 = I1 – I2
= 0.94 – 0.58 = 0.36mA.

IB2 ≥IB2min
Hence Q2 is in saturation
𝑅2 𝑅1
VB1 = VCesat𝑅 – VBB𝑅
1 +𝑅2 1 +𝑅2

22 10
= 0.2× – 12× 10+22
10+22

= 0.137 – 3.75
= - 3.61V
Hence Q1 is OFF

Emitter coupled binary (Schmitt trigger circuit):

A Schmitt trigger or emitter coupled binary is shown in the fig. It differs from the
bistable circuit that the coupling from the collector of Q2 to the input of Q1 is missing. The two
emitters are connected together and grounded through RE. The RE provides the feedback. The
Schmitt trigger is also called as regenerative comparator.

Let a sinusoidal input Vi is applied. When Vi = 0, Q1 is cut off and forces Q2 into
conduction. Hence V0 = VCC – IC2RC2
 When Vi increases to VBE1 + VE (upper threshold point, UTP), Q1 is ON and Q2 is OFF.
Hence V0 = VCC. The output remains constant even if the Vi is further increased. This is one
stable state.
When Vi starts decreasing and equal to VB2 then Q2 becomes ON and this input level is
called lower threshold point, LTP. This is another stable state. The output changes from VCC to
VCC –IC2RC2. The output has two stable states hence used as a voltage comparator.
Hysteresis:
The transfer characteristics of the Schmitt trigger is shown in the fig. Once the output
changes its state, it remains there indefinitely until input voltage another threshold point. So, the
output changes its state from low to high at UTP, it remains there till input crosses LTP and vice
versa. This is called hysteresis.

The difference between UTP and LTP is called width of hysteresis.W = UTP – LTP.
Explain how triggering is used to change the state of the multivibrator with necessary sketches.
To change the binary from one stable state to the other, a pulse of short durationwith sufficient
amplitude (called trigger) of proper polarity should be applied at theinput (output) of an active
device the circuit. The trigger can be a dc trigger, or it can be apulse trigger. There are two
triggering methods to change the state of multivibrator.
1. Unsymmetrical triggering
2. Symmetrical triggering.
Unsymmetrical triggering:
In unsymmetrical triggering, one trigger pulse, taken from a source, is applied atone point
in the circuit. The next trigger pulse taken from a different source is applied ata different point in
the circuit as shown below.
 Let the trigger be applied to the collector C1 of the circuit at t=0. If Q1 is OFF, D1 is ON
and this negative pulse appears at the base of Q2 as the first collector and second base are
connected. Q2 goes into the OFF state and Q1 into the ON state. The next through C1 trigger
pulse, i.e. the Reset pulse, is applied through D2 at the second collector C2 which is coupled to
the first base through C1. Q1 now goes into the OFF state and Q2 into the ON state.
Unsymmetrical triggering is used to generate a gated output; the width of this gate must
be at least equal to the spacing between two successive triggers. To prevent the loading down
problem from the trigger source, R should be large. But when a trigger is applied, a charge is
built up on Ci. If the charge is to be quickly removed before the application of the next trigger
signal at this terminal, R should be small. So while choosing the value of resistance R a
compromise is necessary.
A single resistance cannot simultaneously satisfy these two requirements. Hence in place of R,
diodes D3 and D4 are used. When a pulse appears, the diode is OFF (D3 or D4), a large reverse
resistance of the diode appears in place of R. Otherwise the diode is ON offering negligible
resistance so that the charge on the capacitance can be quickly removed
With suitable diagram, explain the function of a bistable multivibrator using collector catching
diodes.
Collector catching diodes:

Practically the output collector voltage of a multi is used to drive another circuit which
will act as a load. Such a load decreases the output voltage. The multivibrator is modified as
shown below. Let Q1 is off and Q2 is on. To maintain Q2 on IB2 is maintained above a particular
level (i.e. VC1 is to be maintained above a particular level). But due to loading if VC1 decreases,
IB2 also decreases and Q2 may not be in saturation.
The two diodes D1 and D2 are called collector catching diodes, connected to an auxiliary
voltage V < VCC. When Q1 is off, VC1 increases towards VCC. When VC1 = V, the D1 conducts.
Hence VC1 = V. It is ensured that the circuit is not get loaded.

UNIT-IV
Draw and explain the working of a monostable multivibrator with necessary waveforms.

Monostable Multivibrator has one stable state and one quasi stable state. When an
external trigger is applied the circuit changes its state from stable to quasi stable state and
automatically returns back to the original state.Thus this circuit generates a gate pulse of duration
T that depends on circuit components.
The collector coupled monostable is shown in the fig. The collector of Q1 is coupled to
the base of Q2 through a capacitive coupling C. The resistance R is returned to VCC. The values
of R2 and –VBB are such that in the stable state Q1 is OFF and Q2 is ON . This is stable state
VC1 = VCC , VC2 = VCE(sat) , VB2=VBE(sat) = Vσ

When a positive trigger is applied at the base of Q1, the Q1 starts conducting. The voltage
at collector VC1 decreases. This is coupled to the base of Q2 through C. But the voltage across the
capacitor cannot change instantaneously, Decrease in VC1 causes a decrease (I1RC) in the base
voltage of Q2.Q2 becomes less conductive and I2 decreases and collector voltage increases and
applied to the base of Q1 through R1. Finally Q2 is cut off. This is a quasi stable state.

The circuit remains in the quasi stable state for a finite time T. In the quasi stable state the
capacitor starts charging towards VCC through R and on transistor Q1.As base of Q2becomes
more than cut in voltage of Q2, then Q2 starts conducting. Finally Q1 is off. Thus the circuit
returns to its stable state.
.

Derivation for pulse width:

Initially Q2 is in saturation, hence VB2 = VB2sat = Vσ = 0.8V. When a trigger pulse is
applied at t = 0, the capacitor cannot change instantaneously and the voltage VB2 decreases by
I1RC. The capacitor charges exponentially towards VCC. When VB2 = Vγ then Q2 starts
conducting and the circuit comes back to stable state.The time duration T can be calculated as
T= 0.69RC, and I1RC = VCC –VCE(sat)

Gatewidth of a collector coupled monostable:

Vi = Vσ – I1RC
Vf= VCC
VC=Vf – (Vf– Vi)e-t/RC
VB2 = VCC – (VCC – Vσ + I1RC)e-t/RC
At t = T
VB2 = Vγ
𝑉𝐶𝐶 +I1 RC−V
σ
T = RC ln 𝑉𝐶𝐶−𝑉𝛾

If Q1 is in saturation, VC1 = VCesat , and I1RC = VCC – VCE sat then

T = 0.69RC
Waveforms of monostable multivibrator:
Explain Triggering of monostable multivibrator
Triggering of monostable multivibrator:

.
The negative pulse is applied through a capacitor Ci and a diode D1. The normal state is
Q1 is OFF and Q2 is ON. The capacitor Ci and forward resistance of D2 act as a differentiator and
produces positive and negative spikes. The diode D1 allows negative spike to the collector of Q2
which in turn applied to the base of Q1. This decreases the current and turns Q2 OFF. This is a
quasi stable state. During this state, C charges through R and Q1 towards VCC. As the base
voltage of Q2 rises, Q2 starts conducting and turns ON. This is the normal stable state.

Explain the working of a monostable multivibrator as voltage to time converter.

Fig.shows the circuit diagram of a Monostable multivibrator as a voltageto-time converter. By
varying the auxiliary supply voltage V, the pulse width can be changed. The waveform of the
voltage vB2 at the base of Q2 is shown in Fig.

The waveform of the voltage vB2 at the base of Q2 is shown in Fig.

The voltage across base of Q2 In the interval 0 < t < T, VB2 is given by
VB2 = Vf - (Vf - Vi )e - t/τ
VB2 = V - (V - (-Vcc )e - t/τ
VB2 = V - (V + Vcc )e - t/τ
At t = T, VB2 = Vϒ = 0
0 = V-(V+Vcc)e-T/τ
V = (V+Vcc)e-T/τ

T/τ = ln(1 + Vcc/V)

T = τln(1+Vcc/V
T = RCln(1 + Vcc/V)

AstableMultivibrator:

Astablemultivibrator has two states both are quasi stable states. Without external trigger
the multivibrator keeps on alternating the states. Therefore, it is also called Free running
multivibrator.
The collector of Q1 is coupled to the base of Q2 through capacitor C1. The capacitive
coupling is used between the stages due to which neither transistor can remain permanently cut
off. Hence the astablemultivibrator is essentially a square wave generator.
 Let Q2 is ON and Q1 is OFF. The capacitor C2 charges towards VCC through the path RC,
C2 and ON Q2. Finally, voltage across C2 becomes VCC with proper polarity.

At the same time C1 is charged to VCC in the earlier state, starts discharging through the
path Q2 ,VCC, R1,C1. The base of Q1is –VCC at the beginning. As C1 starts discharging it become
less negative. Finally equals to Vγ. Now Q1 starts conducting and becomes ON. Simultaneously
Q2 is OFF.
During this, the capacitor C1 starts charging again through RC, C1 and ON Q1. As C2 discharges,
B2 becomes positive equal to Vγ. Q2 starts conducting and becomes ON, and Q1 OFF. The wave
forms are shown in the fig.

The output of the circuit is a square wave, having two timeperiods, T1 and T2. If T1 = T2=T/2
then the circuit is a symmetrical astablemultivibrator. If T1≠ T2, then it is called unsymmetrical
astablemultivibrator.

Explain how astable multivibrator is used as voltage to frequency converter.

Astablemultivibrator as V/F converter:
The astable multi is modified as shown in the fig. the VB2 when the capacitor C2 discharges is
shown in the fig.

Initially VB = Vi = -VCC
Finally, VB = Vf = V
VB = Vf – (Vf–Vi)e-t/τ
VB = V – (V- [VCC])e-t/R2C2

At t = T2, VB = Vγ = 0
𝑉+𝑉𝐶𝐶
e- T2/R2C2 = 𝑉
𝑉𝐶𝐶
T2 = R2C2 ln [1 + ]
𝑉
𝑉𝐶𝐶
Similarly, T1 = R1C1 ln [1+ ]
𝑉

T = T1 + T2
If R1 = R2= R and C1 = C2 = C
𝑉𝐶𝐶
T = 2RC ln [1+ ]
𝐶
1
f = 𝑉
2RC ln [1+ 𝐶𝐶 ]
𝐶

Derive the Expression for the frequency of oscillation of an astable multivibrator.

The capacitor voltage equation is
V0 = Vf – (Vf–Vi)e-t/τ
i.e, VB2 = VCC–(VCC –(-VCC))e-t/R2C2
Vγ = VCC(1-2e-t/R2C2) = 0
T2 = 0.69R2C2
Similarly, T1 = 0.69R1C1
If R1 = R2 =R and C1 = C2 =C
T = T1 +T2 = 1.38RC
1
f =1.38𝑅𝐶

UNIT-V

Time Base Generators

Circuits used to generate a linear variation of voltage with time are called voltage time base generators.
Circuits used to generate a linear variation of current with time are called current time base generators. Since the
output is linear variation of voltage with time, they are called as linear time base generators. Such circuits are used
in TV, CRO, radar, precision time measurement of time and in time modulation.

General features of time base signal:

 The voltage starting from some initial value increases linearly with time to a maximum value, after which it
returns to its initial value. The time required for the return to the initial value is called the restoration time or fly
back time Tr. the period during which voltage increase linearly is called sweep time T s. generally,Tr<Ts.

Displacement Error ed:

It is the max difference between the actual sweep voltage and linear sweep which passes through the
beginning and end points of actual sweep.

Transmission Error et:

It is defined as the difference between the input and output divided by the input.

With neat sketch, explain about transistor miller time base generator.
Transistor Miller Sweep:
The Miller sweep generates a negative ramp. It uses a high gain amplifier and
incorporates negative feedback.Consider the triggered transistor Miller’s Sweep generator as
shown below.
 Q1 acts as ON-OFF switch and Q2 is a high gain amplifier. The input vi is a rectangular
voltage. The circuit conditions are adjusted such that when the input is positive Q1is ON and is in
saturation. Therefore the voltage at C1 (collector of Q1) is V CE(sat) =0 Transistor Q2is OFF.

The voltage across Cs is

vs = VCC.

When the input signal goes negative, Q is OFF and the voltage at C1rises and Q2goes ON.
The charge on the capacitor s C discharges. Hence the output is a negative going ramp. Again at
the end of the input pulse, Q1 goes ON,Q2 goes OFF and the output again reaches VCC .The
waveforms are shown in fig

Derive the expression for sweep time of sweep circuit using UJT.
Bootstrap circuit:
The circuit of a Bootstrap sweep generator is shown in fig. below. Transistor Q1 acts as 0N-OFF switch and
Q2 acts as an emitter follower.
The input vi is rectangular wave. When vi is positive, Q1 is ON and collector voltage = VCesat
V0 = VCesat – VBeact
= 0.2 – 0.6 = -0.4V
Emitter of Q2 is connected to collector of Q1 through C3, hence point K becomes more negative w.r.t to VCC. When
D1 conducts,VC1 = VCC
When input goes negative, Q1 is OFF and the potential collector1 rises and transmitted to B 2 and C3. This is called
bootstrap. Thus, VB rises from VCC to (VCC+VC1)
𝑉𝐶𝐶
I1 = . Since VCC and R1 are fixed I1 is constant. Since Q2 is an emitter follower, the input impedance is large and
𝑅𝐶1

gain = 1. Hence the output voltage is a ramp voltage.

If Ts<Tg (ie V0 reaches VCC before Tg)

Then at t = Ts, Vs = VCC
Ts = R1C1
Miller sweep circuit Bootstrap sweep circuit
circuit diagram : Miller sweep circuit
circuit diagram : Bootstrap sweep circuit

In miller sweep circuit the polarity of sweep voltage In bootstrap sweep circuit the polarity of sweep
is negative. voltage is positive.
The inverting amplifier is used in this circuit. The non inverting amplifier is used in this circuit.
The open circuit gain of the amplifier is A = – ∞ The open circuit gain of the amplifier is A = + 1
The linearity of the sweep voltage is better than that The linearity of the sweep voltage is poor than that of
of the bootstrap sweep circuit. the miller sweep circuit.
A voltage source V is simulated like that V is always A voltage source V is suggested like that V is forever
equal to the instantaneous capacitor voltage VC. equal to the immediate capacitor voltage VC.