13/Jul/23

Microcontroller and
Interfacing
Compiled by
Prof. Hiren J. Patel

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• Data Bus
• Address Bus
• Control Bus
• Memory
– RAM
– ROM
• Peripherals

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Microprocessor Vs Microcontroller

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Embedded Systems

Examples of
Applications/Embedded Systems

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PC is an Embedded Systems???

• If the CPU reads hex 0C01, R0 and R1 is added

and the result is written to register R0. This is
executed like demonstrated in the picture.

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Embedded Processors
• Although microcontrollers are the preferred choice for many embedded systems,
sometimes a microcontroller is inadequate for the task.
• For this reason, in recent years many manufacturers of general-purpose
microprocessors such as Intel, Freescale Semiconductor (formerly Motorola). and
AMD (Advanced Micro Devices, Inc.) have targeted their microprocessors for the
high end of the embedded market.
• Intel and AMD push their x86 processors for both the embedded and desktop PC
markets.
• In the early 1990s, Apple computer began using the PowerPC microprocessors (604,
603, 620, etc.) in place of the 680x0 for the Macintosh. In 2007 Apple switched to the
x86 CPU for use in the Mac computers.
• The PowerPC microprocessor is a joint venture between IBM and Freescale, and is
targeted for the high end of the embedded market.
• It must be noted that when a company targets a general-purpose microprocessor for
the embedded market it optimizes the processor used for embedded systems. For this
reason these processors are often called high-end embedded processors.
• Another chip widely used in the high end of the embedded system design is the ARM
(Advanced RISC Machine) microprocessor. Very often the terms embedded
processor and microcontroller are used interchangeably.

Criteria for Choosing a Microcontroller

1. The first and foremost criterion in choosing a microcontroller is
that it must meet the task at hand efficiently and cost
effectively. In analyzing the needs of a microcontroller-based
project, we must first see whether an 8-bit, 16-bit, or 32-bit
microcontroller can best handle the computing needs of the task
most effectively. Among other considerations in this category are:
a) Speed. What is the highest speed that the microcontroller supports?
b) Packaging. Does it come in a DIP (dual inline package) or a QFP (quad flat
package), or some other packaging format? This is important in terms of space.
assembling, and prototyping the end product.
c) Power consumption. This is especially critical for battery-powered products.
d) The amount of RAM and ROM on the chip.
e) The number of 1/0 pins and the timer on the chip.
f) Ease of upgrade to higher-performance or lower-power-consumption versions.
g) Cost per Unit. This is important in terms of the final cost of the product in which a
microcontroller is used. For example, some microcontrollers cost 50 cents per unit
when purchased 100,000 units at a time.

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Criteria for Choosing a Microcontroller (contd.)

2. The second criterion in choosing a microcontroller is how easy
it is to develop products around it. Key considerations include
– the availability of an assembler, a debugger, a code-efficient C language
compiler, an emulator, technical support, and both in-house and outside expertise.
– In many cases, third-party vendor (i.e., a supplier other than the chip
manufacturer) support for the chip is as good as, if not better than, support from
the chip manufacturer.
3. The third criterion in choosing a microcontroller is its ready
availability in needed quantities both now and in the future.
– For some designers this is even more important than the first two criteria.
Currently, of the leading 8-bit micro- controllers, the 8051 family has the largest
number of diversified (multiple source) suppliers. (Supplier means a producer
besides the originator of the microcontroller.) In the case of the 8051. which was
originated by Intel, many companies also currently produce the 8051.

Any Questions???
• When comparing a system board based on a microcontroller and a
general- purpose microprocessor, which one is cheaper?

• A microcontroller normally has which of the following devices on-

chip?
(a) RAM (b) ROM (c) I/O (d) all of the above

• A general-purpose microprocessor normally needs which of the

following devices to be attached to it?
(a) RAM (b) ROM (c) I/O (d) all of the above

• An embedded system is also called a dedicated system. Why?

• What does the term embedded system mean?

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AVR Atmega32 - History

• The basic architecture of AVR was designed by two students of
Norwegian Institute of Technology (NTH), Aif-Egil Bogen and
Vegard Wollan, and then was bought and developed by Atmel in
1996.
• You may ask what AVR stands for; AVR can have different
meanings for different people!
• Atmel says that it is nothing more than a product name, but it might
stand for
– Advanced Virtual RISC, or
– Alf and Vegard RISC (the names of the AVR designers).

AVR Features
• The AVR is a modified Harvard architecture 8-bit RISC
single-chip microcontroller, which was developed by Atmel in
1996. Now it is Microchip.
• The AVR was one of the first microcontroller families to use
on-chip flash memory for program storage, as opposed to one-
time programmable ROM, EPROM, or EEPROM used by
other microcontrollers at the time.
• megaAVR chips became popular after they were designed into
the 8-bit Arduino platform.

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Simplified View of AVR

Microcontroller

ALU
PC
Instructio
n
dec.

AVR Families
• AVRs are generally classified into following:
• tinyAVR — the ATtiny series
– 0.5–16 kB program memory
– 6–32-pin package
– Limited peripheral set
• megaAVR — the ATmega series
– 4–512 kB program memory
– 28–100-pin package
– Extended instruction set (multiply instructions and instructions for handling
larger program memories); - Extensive peripheral set
• XMEGA — the ATxmega series
– 16–384 kB program memory
– 44–64–100-pin package (A4, A3, A1)
– Extended performance features, such as DMA, "Event System", and
cryptography support.
– Extensive peripheral set with ADCs

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AVR Family(contd.)
• Application-specific AVR
– megaAVRs with special features not found on the other members of the
AVR family, such as LCD controller, USB controller, advanced PWM,
CAN, etc.
• FPSLIC (AVR with FPGA)
– FPGA 5K to 40K gates
– SRAM for the AVR program code, unlike all other AVRs
– AVR core can run at up to 50 MHz[7]
• 32-bit AVR UC3
• All AVRs are of 8-bit except 32-bit AVRS UC3

AVR Product Number Scheme

• All of the product numbers start with AT, which stands for
Atmel.
• Now, look at the number located at the end of the product
number, from left to right, and find the biggest number that is a
power of 2. This number most probably shows the amount of
the microcontroller’s ROM.
• For example,
– In ATmega1280 the biggest power of 2 that we can find is
128; so it has 128K bytes of ROM.
– In ATtiny44, the amount of memory is 4K, and so on.
– Although this rule has a few exceptions such as
AT9OPWM2I6, which has 16K of ROM instead of 2K, it
works in most of the cases.

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AVR Family

AVR Family (contd.)

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Features of ATmega32
• High-performance, Low-power Atmel ®AVR®
8-bit Microcontroller
• Advanced RISC Architecture
– 131 Powerful Instructions – Most Single-clock Cycle Execution
– 32 × 8 General Purpose Working Registers
– Up to 16 MIPS Throughput at 16MHz
– On-chip 2-cycle Multiplier

Features of ATmega32(Contd.)
High Endurance Non-volatile Memory segments
– 32Kbytes of In-System Self-programmable Flash program memory
– 1024Bytes EEPROM
– 2Kbytes Internal SRAM
– Write/Erase Cycles: 10,000 Flash/100,000 EEPROM
– Data retention: 20 years at 85°C/100 years at 25°C
– Optional Boot Code Section with Independent Lock Bits
In-System Programming by On-chip Boot Program
True Read-While-Write Operation
– Programming Lock for Software Security
JTAG (IEEE std. 1149.1 Compliant) Interface
– Boundary-scan Capabilities According to the JTAG Standard
– Extensive On-chip Debug Support
– Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG
Interface

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Features of ATmega32(Contd.)
Peripheral Features
– Two 8-bit Timer/Counters with Separate Prescalers and Compare
Modes
– One 16-bit Timer/Counter with Separate Prescaler, Compare Mode,
and Capture Mode
– Real Time Counter with Separate Oscillator (RTC)
– Four PWM Channels
– 8-channel, 10-bit ADC
8 Single-ended Channels
7 Differential Channels in TQFP Package Only
2 Differential Channels with Programmable Gain at 1x, 10x, or 200x
– Byte-oriented Two-wire Serial Interface
– Programmable Serial USART
– Master/Slave SPI Serial Interface
– Programmable Watchdog Timer with Separate On-chip Oscillator
– On-chip Analog Comparator

Features of ATmega32(Contd.)
Special Microcontroller Features
– Power-on Reset and Programmable Brown-out Detection
– Internal Calibrated RC Oscillator
– External and Internal Interrupt Sources
– Six Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-
down, Standby and Extended Standby
I/O and Packages
– 32 Programmable I/O Lines
– 40-pin PDIP, 44-lead TQFP, and 44-pad QFN/MLF
Operating Voltages
– 2.7V - 5.5V for ATmega32L
– 4.5V - 5.5V for ATmega32
Speed Grades
– 0 - 8MHz for ATmega32L
– 0 - 16MHz for ATmega32

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BUS
Data
AVR CPU

Data BUS
BUS
Data BUS
Data

AVR CPU

Data BUS

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RISC architecture
• In the early 1980s, a controversy broke out in the computer design
community
• Since the 1960s, in all mainframes and minicomputers, designers put as
many instructions as they could think of into the CPU.
– Some of these instructions performed complex tasks.
– An example is adding data memory locations and storing the sum into
memory. Naturally, microprocessor designers followed the lead of
minicomputer and mainframe designers.
– Because these microprocessors used such a large number of instructions,
many of which performed highly complex activities, they came to be
known as CISC (complex instruction set computer) processors.
• According to several studies in the 1970s, many of these complex
instructions etched into CPUs were never used by programmers and
compilers.
– The huge cost of implementing a large number of instructions
– plus the fact that a good portion of the transistors on the chip are used by the
instruction decoder,
• Designers think of simplifying and reducing the number of instructions. As
this concept developed, the resulting processors came to be known as
RISC (reduced instruction set computer).

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The architecture
RISC vs. CISC
• CISC (Complex Instruction Set Computer)
– Put as many instruction as you can into the CPU
• RISC (Reduced Instruction Set Computer)
– Reduce the number of instructions, and use your facilities in
a more proper way.

RISC CISC
1. RISC stands for Reduced Instruction 1. CISC stands for Complex Instruction
Set Computer. Set Computer.
2. CSIC processor has complex
2. RISC processors have simple
instructions that take up multiple clocks
instructions taking about one clock
for execution. The average clock cycle
cycle. The average clock cycle per
per instruction (CPI) is in the range of 2
instruction (CPI) is 1.5
and 15.
3. Performance is optimized with more 3. Performance is optimized with more
focus on software focus on hardware.
4. It has a hard-wired unit of
4. It has a microprogramming unit.
programming.
5. The instruction set is reduced i.e. it
5. The instruction set has a variety of
has only a few instructions in the
different instructions that can be used
instruction set. Many of these
for complex operations.
instructions are very primitive.
6. CISC has many different addressing
6. The instruction set has a variety of
modes and can thus be used to
different instructions that can be used
represent higher-level programming
for complex operations.
language statements more efficiently.

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RISC CISC
7. Complex addressing modes are 7. CISC already supports complex
synthesized using the software. addressing modes
8. Multiple register sets are present 8. Only has a single register set
9. They are normally not pipelined or
9. RISC processors are highly pipelined
less pipelined
10. Execution time is very less 10. Execution time is very high
11. Decoding of instructions is simple. 11. Decoding of instructions is complex
12. The most common RISC 12. Examples of CISC processors are
microprocessors are Alpha, ARC, ARM, the System/360, VAX, PDP-11,
AVR, MIPS, PA-RISC, PIC, Power Motorola 68000 family, AMD and Intel
Architecture, and SPARC. x86 CPUs.
13. RISC architecture is used in high-
13. CISC architecture is used in low-
end applications such as video
end applications such as security
processing, telecommunications and
systems, home automation, etc.
image processing.

What is RISC?
• Reduced Instruction Set Computer
– As compared to Complex Instruction Set Computers, i.e. x86
• Assumption: Simpler instructions execute faster
• Optimized most used instructions
• Other RISC machines: ARM, PowerPC, SPARC
• Became popular in mid 1990s

Characteristics of RISC
• Faster clock rates
• Single cycle instructions (20 MIPS @ 20 MHz)
• Better compiler optimization
• Typically no divide instruction in core

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Features of RISC :Feature I

• RISC processors have a fixed instruction size.
– In a CISC microcontroller such as the 8051, instructions can be 1,
2, or even 3 bytes.
• This variable instruction size makes the task of the instruction
decoder very difficult because the size of the incoming
instruction is never known.
• In a RISC architecture, the size of all instructions is fixed.
Therefore, the CPU can decode the instructions quickly. This
is like a bricklayer working with bricks of the same size as
opposed to using bricks of variable sizes. Of course, it is
much more efficient to use bricks of ’ the same size. In the last
section we saw how the AVR uses 2-byte instructions with
very few 4-byte instructions.

Features of RISC :Feature 2

• One of the major characteristics of RISC architecture is a
large number of registers.
• All RISC architectures have at least 32 registers. Of these 32
registers, only a few are assigned to a dedicated function.
• One advantage of a large number of registers is that it avoids
the need for a large stack to store parameters. Although a
stack can be implemented on a RISC processor, it is not as
essential as in CISC because so many registers are available.
• In the AVR microcontrollers the use of 32 general purpose
registers satisfies this RISC feature. The stack for the AVR is
cove red in the next chapter.

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Features of RISC :Feature 3

• RISC processors have a small instruction set.
• RISC processors have only basic instructions such as ADD, SUB,
MUL, LOAD, STORE, AND, OR, FOR, CALL, JUMP, and so on.
• The limited number of instructions is one of the criticisms leveled at
the RISC processor because it makes the job of Assembly language
programmers much more tedious and difficult compared to CISC
Assembly language programming.
• This is one reason that RISC is used more commonly in high-level
language environments such as the C programming language rather
than Assembly language environments.
• The limited number of instructions in RISC leads to programs that are
large. Although these programs can use more memory, this is not a
problem because memory is cheap.
• In the ATmega we have around 131 instructions.

Features of RISC :Feature 4

• At this point, one might ask, with all the difficulties
associated with RISC programming, what is the gain?
• The most important characteristic of the RISC
processor is that more than 95% of instructions are
executed with only one clock cycle, in contrast to
CISC instructions.
• Even some of the 5% of the RISC instructions that are
executed with two clock cycles can be executed with
one clock cycle by juggling instructions around (code
scheduling).
• Code scheduling is most often the job of the compiler.

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Features of RISC :Feature 5

• RISC processors have separate buses for data and code. i.e.
Harvard Architecture
• In all the x86 processors, like all other CISC computers, there is
one set of buses for the address (e.g., AO—A24 in the 80286) and
another set of buses for data (e.g., D0—D15 in the 80286)
carrying opcodcs and operands in and out of the CPU.
• In RISC processors, there are four sets of buses:
– (I) a set of data buses for carrying data (operands) in and out of the
CPU,
– (2) a set of address buses for accessing the data,
– (3) a set of buses to carry the opcodes, and
– (4) a set of address buses to access the opcodes.
• The use of separate buses for code and data operands is
commonly referred to as Harvard architecture.

Harvard Architecture in AVR

ALU
PC
Instructio
n
dec.

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Modified Harvard Architecture

• Special instructions can access data from
program space.
• Data memory is more expensive than program
memory
• Don’t waste data memory for non-volatile data

Features of RISC :Feature 6

• Because CISC has such a large number of instructions, each with
so many different addressing modes, microinstructions
(microcode) are used to implement them.
• The implementation of microinstructions inside the CPU
employs more than 40-60% of transistors in many CISC
processors.
• RISC instructions, however, due to the small set of instructions,
are implemented using the hardwire method. Hardwiring of
RISC instructions takes no more than 10% of the transistors.

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Features of RISC :Feature 7

• RISC uses load/store architecture.
– In CISC microprocessors, data can be manipulated while it is still in memory.
• For example, in instructions such as “ADD Reg, Memory”,
– the microprocessor must bring the contents of the external memory location
into the CPU, add it to the contents of the register, then move the result back
to the external memory location.
– The problem is there might be a delay in accessing the data from external
memory. Then the whole process would be stalled, preventing other
instructions from proceeding in the pipeline.
• In RISC, instructions can only load from external memory into registers or
store registers into external memory locations.
– There is no direct way of doing arithmetic and logic operations between a
register and the contents of external memory locations.
– All these instructions must be performed by first bringing both operands into
the registers inside the CPU, then performing the arithmetic or logic
operation, and then sending the result back to memory.
• This idea was first implemented by the Cray 1 supercomputer in 1976 and
is commonly referred to as load/store architecture.

RISC architecture
LDS R20, 0x100 ; R20 = [0x100]
ADD R20, R21
ADD R20,R21 ; R20 = R20 + R21
• Feature 5 (Harvard architecture): separate buses for
LDS R20, 0x100

opcodes and operands

– Advantage: opcodes and operands can go inFetch
and out of the CPU
together.
– Disadvantage: leads to more cost in general purpose computers.
Execute

Control bus Control bus

Code Data
Memory Data bus CPU Data bus Memory
Address bus Address bus

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Little Endian Vs. Big Endian War

• Examine the placing of the code in the AVR ROM, shown in Figure 2-20.
– The low byte goes to the low memory location, is called little endian
– the high byte goes to the low memory address is called big endian
• In the big endian method, the high byte goes to the low address, whereas
in the little endian method, the high byte goes to the high address and
the low byte to the low address.
• The origin of the terms big endian and hide endian is from an argument in a
Gulliver’s Travels story over how an egg should be opened: from the big
end or the little end.
• All Intel microp rocessors and many microcontrollers use the little
endian convention. Freescale (formerly Motorola) microprocessors,
along with some mainframes, use big endian. The difference might
seem as trivial as whether to break an egg from the big end or the little end,
but it is a nuisance in converting software from one camp to be run on a
computer of the other camp. Some microprocessors, such as the PowerPC
from IBM/Freescalc, let the software designer choose little endian or big
endian convention.

Little Endian Vs. Big Endian War

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Little Endian Vs. Big Endian War

Fetch and execute

• Old Architectures 00
01
E205
E314
02 E321
Instruct 4
03 0F01
Instruct 3
04 0F02
Instruct 2
0516-bit
E01B
Instruct 1
06 0F01
07 9300
08 0300 RAM EEPROM Timers
Fetch
09 940C
PROGRAM
0A
Flash0009
ROM ALU

PC: Data
CPU Bus
Execute
Instruction dec.
Program
Bus

Interrupt Other
OSC Ports
Unit Peripherals

I/O
PINS

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Pipelined Execution

non-pipeline fetch1 exec 1 fetch2 exec 2 fetch3 exec 3 fetch4 exec 4

Pipeline fetch1 exec 1

fetch2 exec 2
fetch3 exec 3
fetch4 exec 4
T1 T2 T3 T4 T5 T6 T7 T8

Pipelining
• Pipelining
00 E205
01 E314
02 E321
Instruct 4 03 0F01
Instruct 3 04 0F02
Instruct 2 0516-bit
E01B
Instruct 1 06 0F01
07 9300
08 0300 RAM EEPROM Timers
Fetch 09 940C
PROGRAM
0A
Flash0009
ROM ALU

PC: Data
CPU Bus
Execute Program Instruction dec.

Bus

Interrupt Other
OSC Ports
Unit Peripherals

I/O
PINS

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Avr Multistage Execution Pipeline

Inst.1 fetch1 R P W
Inst.2 fetch2 R P W
Inst.3 fetch3 R P W
Inst.4 fetch4 R P W
Tim
T1 T2 T3 T4 T5 e

R= read the operand

P = Process
W= Write the result to destination

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Directives

Assembler Directives
.EQU and .SET
• .EQU name = value
– Example:
.EQU COUNT = 0x25
LDI R21, COUNT ;R21 = 0x25
LDI R22, COUNT + 3 ;R22 = 0x28

• .SET name = value

– Example:
.SET COUNT = 0x25
LDI R21, COUNT ;R21 = 0x25
LDI R22, COUNT + 3 ;R22 = 0x28
.SET COUNT = 0x19
LDI R21, COUNT ;R21 = 0x19

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Assembler Directives
.INCLUDE

• .INCLUDE "filename.ext"
M32def.inc
.equ SREG = 0x3f
.equ SPL = 0x3d
.equ SPH = 0x3e
....
.equ INT_VECTORS_SIZE = 42 ; size in words

Program.asm
.INCLUDE "M32DEF.INC"
LDI R20, 10
OUT SPL, R20

Assembler Directives
.ORG
• .ORG address

00 E205
01 0000
Program.asm 02 0000

.ORG 0 03 0000

LDI R16, 0x25 04 0000

.ORG 0x7
assembler 05 0000
LDI R17, 0x34 06 0000
LDI R18, 0x31 07 E314
08 E321
09 0000
0A 0000

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Assembler Assembly

EDITOR
PROGRAM assembler

myfile.asm

ASSEMBLER
PROGRAM
Machine
Language

myfile.eep myfile.hex myfile.map myfile.lst myfile.obj

DOWNLOAD TO DOWNLOAD TO
AVR’s EEPROM AVR ’s FLASH

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Hex file

MEMORIES OF ATMEGA32

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Status Register

Status Register (SREG)

C: Carry Flag
Z: Zero Flag
N: Negative Flag
V: Two’s complement overflow indicator
S: N ⊕ V, For signed tests
H: Half Carry Flag
T: Transfer bit used by BLD and BST instructions
I: Global Interrupt Enable/Disable Flag

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• The status register bits are:

• C Carry flag. This is a borrow flag on subtracts.
• Z Zero flag. Set to 1 when an arithmetic result is zero.
• N Negative flag. Set to a copy of the most significant bit of an
arithmetic result.
• V Overflow flag. Set in case of two's complement overflow.
• S Sign flag. Unique to AVR, this is always N⊕V, and shows the
true sign of a comparison.
• H Half carry. This is an internal carry from additions and is
used to support BCD arithmetic.
• T Bit copy storage:. Special bit load and bit store instructions
use this bit.
• I Global Interrupt Enable flag. Set when interrupts are to be
enabled.

For Atmega32

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Not for Atmega32

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Stack

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Stack
Address Code
ORG 0

0000 LDI R16,HIGH(RAMEND)

0001 OUT SPH,R16

R20: $10
$00 R22: $30
$00
LDI R16,LOW(RAMEND)
0002
R21: $00
$20 R0: $00 0003 OUT SPL,R16

0004 LDI R20,0x10

0005 LDI R21, 0x20

0006 LDI R22,0x30

SP 0000 0007 PUSH $10
R20

0008 PUSH $20

R21

0009 PUSH $30

R22

000A POP R21

000B POP R0

000C POP R20

000D L1: RJMP L1

Memory

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Calling a Function

• To execute a call: Address Code

0000 LDI R16,HIGH(RAMEND)

– Address of the next
0001 OUT SPH,R16
instruction is saved 0002 LDI R16,LOW(RAMEND)
– PC is loaded with 0003 OUT SPL,R16
the appropriate 0004 LDI R20,15

value Machine code: 0005 LDI R21,5

940E 000A
000A 0006
0006 CALL FUNC_NAME
opCode operand 0008
00 08 INC R20
0009 L1: RJMP L1
000A FUNC_NAME:
000A ADD R20,R21
SP 000B SUBI R20,3
PC: 000C
000B
0006
0005
0004
0009
0008 000C RET
000D
Stack

Hardware
Connections

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Pins for minimum connection

Reset circuit

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Clock Source

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Minimum Hardware connections

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OCD = Open Ckt Debug

44