21 LEVEL CASCADED H-BRIDGE GRID-TIED

INVERTER

A PROJECT REPORT

Submitted by
ALEX A 822319105001
CHANDRU T 822319105002
HARIHARAN B 822319105004
SARABOJI R 822319105007

In partial fulfillment for the award of the degree

of

BACHELOR OF ENGINEERING

IN
ELECTRICAL AND ELECTRONICS ENGINEERING

VANDAYAR ENGINEERING COLLEGE,.

ANNA UNIVERSITY: CHENNAI 600 025

MAY 2023

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1
 ANNA UNIVERSITY: CHENNAI 600 025
BONAFIDE CERTIFICATE

Certified that this project report “21 LEVEL CASCADED H-BRIDGE

GRID-TIEDINVERTER” is the bonafide work of

ALEX A 822319105001
CHANDRU T 822319105002
HARIHARAN B 822319105004
SARABOJI R 822319105007
Who carried out the project work under my supervision.

SIGNATURE SIGNATURE
MR.I.MOHAMEDSIDDIK,M.E., MR.S.SUBHASANKAR,M.E.,
HEAD OF THE DEPARTMENT SUPERVISOR
Dept of EEE Assistant Professor /Dept of EEE
Vandayar Engineering College Vandayar Engineering College
Pulavarnatham Pulavarnatham

Submitted to the project viva-voce examination held on ……………………

INTERNAL EXAMINER EXTERNAL EXAMINER

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 ACKNOWLEDGEMENT

This project has been under taken and completed with direct and indirect

help of many people and I would like to acknowledge the same.

I extend my sincere thanks to our honourable chairman Thiru

S.GunasekaranVandayar M.COM., Vandayar group of institutions, for offering

me to attaining my most cherished goal.

I extend my deepest gratitude to Thiru G.Vijayaprakash M.TECH

secretary and correspondent, vandayar group of institutions for giving

permission to do the project work successfully. I also wish to thank our

Principal Dr.S.Samundeeswari M.E., Ph.D. for her encouragement to do

the project.

I am grateful to express my profound thanks to

Mr.I.MOHAMEDSIDDIK M.E., Head of the Department, Electrical and

Electronics Engineering who has been a source of encouragement and

moral strength.

It gives immense pleasure to extend my sincere and heartfelt

thanks to internal project guide and my project coordinator

MR.S.SUBHASANKAR,M.E, Assistant Professor, Electrical and

Electronics Engineering, Vandayar group of institutions, for their untiring

valuable and timely suggestions in indispensable situation. I also extend my

sincere thanks to my Staff members of EEE Department. I am extremely

thankful to my parents for enlightening me by providing professional

education and for their prayerful support that makes me to complete

the project phase successfully.

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 ABSTRACT

This project emphasis the best efforts and technique in reduction

of harmonic content of the sinusoidal waveform in ac voltage. Multilevel

inverters with a desired number of levels (here 21 levels) can generate high

quality waveforms, good enough to be considered voltage template

generators. This is done by increasing the number of steps. In general,

number of levels are determined by the formula 2N+1=Levels, where N is

the number of bridges, which leads to 10 bridges. But this project makes

use of only 4 H-Bridges which is probably having the advantage of

reducing the switching losses. This is achieved by making use of

asymmetrical multilevel inverter of different voltage source. Also the use

of PWM is eliminated, which further reduces the harmonic content in the

waveform .The simulation of the model is done using MATLAB software

and the experimental results of the phase-II project are obtained as

simulation results.

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 LIST OF CONTENTS

CHAPTER TITLE PAGE

NO NO

ACKNOWLEDGEMENT iii

ABSTRACT iv

LIST OF FIGURES viii

LIST OF ABBREVIATION ix

LIST OF SYMBOLS x

1 INTRODUCTION 1

1.1 DESCRIPTION FOR MULTI LEVEL INVERTERS 1

1.2 OBJECTIVES 1

1.3 CLASSFICATION OF INVERTERS 2

1.4 MERITS OF MULTILEVEL INVERTERS 2

2 LITERATURE SURVEY 4

3 GENESIS OF MULTI LEVEL INVERTERS 6

3.1 MULTILEVEL INVERTER CHARACTERISTICS 6

3.2 TYPES OF MULTI-LEVEL INVERTERS 8

3.2.1 Cascaded multi level inverter 8

3.2.1(a) Different topologies of H-bridge 8

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 3.3 ASYMMETRICAL MULTILEVEL INVERTER 12

3.3.1 Merits of asymmetric multilevel inverter 13

3.4 APPLICATIONS 13

4 HARDWARE IMPLEMENTATION 15

4.1 Organization Of Control Circuit 15

4.2 Power Supply

4.2.1 Block diagram of power supply 16

4.2.2 Unregulated power supply calculation 17

4.2.3 Regulated power supply 18

4.3 DRIVER UNIT 19

4.3.1 Opto-couplers 19

4.4 PIC MICROCONTROLLER 21

4.4.1 Features 22

4.4.2 Block Diagram Of Microcontroller 89c51 23

4.4.3a. Pin Configuration 24

4.4.3b. Pin Description 24

4.4.4 Control Circuit With Real Time I/O 29

4.5 MOSFET 30

4.5.1 Basics of MOSFET 30

4.5.2 Advantages of Power MOSFET 31

4.5.3 MOSFET Symbol 32

5 MATLAB SIMULATION 33

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 5.1 INTRODUCTION 34

5.2 FEATURES OF MAT LAB 34

5.2.1 Quickly Prove the System Works 34

5.2.2 Semiconductors 35

5.2.3 Enhanced Analog and Mixed-Signal System 35

design
5.3 BLOCK LIBRARIES 36

5.4 SIMULINK MODEL CONVERTER 38

5.5 MODELING PROCEDURE 38

5.6 RUNNING THE SIMULATION 39

5.7 SIM POWER SYSTEMS 41

5.8 SUBSYSTEMS 43

5.9 MODELING ELECTRICAL POWER SYSTEMS 43

44
5.10 APPLICATIONS

5.11 SIMULATION OF MULTI-LEVEL INVERTER 45

6 HARDWARE RESULTS 48

6.1 HARDWARE CIRCUIT FOR TWENTY ONE 48

LEVEL INVERTER

7 CONCLUSION 52

REFERENCES 53

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 LIST OF FIGURES

3.1 BASIC MULTILEVEL INVERTERS 6

3.2 VOLTAGE WAVEFORM FOR 7-LEVEL INVERTER 7

3.3 BLOCK OF A H-BRIDGE MULTI-LEVEL INVERTER 9

3.4 CIRCUIT DIAGRAM OF 4 –LEVEL CASCADE MULTI- 10

LEVEL INVERTER

3.5 HYBRID H-BRIDGE INVERTER 11

4.1 PROPOSED METHOD BLOCK DIAGRAM 15

4.2 SINGLE LINE DIAGRAM 15

4.3 CIRCUIT DIAGRAM FOR 5V POWER SUPPLY 16

4.4 THE BRIDGE RECTIFIER 16

4.4.2 BLOCK DIAGRAM OF MICROCONTROLLER 89C51 23

5.2 THD ANALYSIS 43

5.3 TWENTY ONE LEVEL INVERTER SIMULATION 44

DIAGRAM

5.4 SIMULATION OUTPUT FOR 21 LEVELS 45

6.1 HARDWARE CIRCUIT FOR TWENTY ONE LEVEL 48

INVERTER

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 LIST OF ABBREVIATIONS

SVC - Static VAR Compensator

DC - Direct Current

PWM - Pulse Width Modulation

AC - Alternating Current

MLI - Multi Level Inverter

CM - Common Mode

MOSFET - Metal-Oxide Semiconductor Field Effect Transistor

MATLAB - Matrix Laboratory

FACTS - Flexible AC Transmission System

PIC - Peripheral Interface Controller

THD - Total Harmonic Distortion

EMI - Electro Magnetic Interference

GTO - Gate Turn- off Thyristor

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 LIST OF SYMBOLS

Q - Quality Factor

L - Inductance

Lf - Filter Inductance

CB - Snubber Capacitor

CO - Output side filter Capacitor

Vdc - Supply voltage

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 CHAPTER 1

INTRODUCTION

1.1 DESCRIPTION OF MULTILEVEL INVERTER:

Power electronic devices contribute an important part of harmonics in all kind of

applications, such as power rectifiers, thyristor converters, and Static VAR Compensators (SVC). Even
updated pulse-width modulation (PWM) techniques used to control modern static converters such as
machine drives, power factor compensators, or active power filters do not produce perfect waveforms,
which strongly depend on the semiconductors switching frequency. Voltage or current converters, as they
generate discrete output waveforms, force the use of machines with special isolation, and in some
applications large inductances connected in series with the respective load. In other words, neither the
voltage nor the current waveforms are as expected. Also, it is well known that distorted voltages and
currents waveforms produce harmonic contamination, additional power losses and high frequency noise that
can affect not only the power load but also the associated controllers. All these unwanted operating
characteristics associated with PWM converters can be overcome with multilevel converters, in addition to
the fact that higher voltage levels can be achieved.

1.2 OBJECTIVES:

The main objectives of this project work is

1. The function of the proposed inverter is to convert the DC into AC by means of fast switching.
2. Main objective of the project is to achieve 21 levels with reduced number of bridges using
asymmetric operation.
3. A multi-level inverter can be considered as a voltage source which can switch among a finite set of
levels.
4. It provides high-quality output power due to its high number of output levels.
5. The multilevel switching schemes inherently provide the opportunity to eliminate lower order
harmonics.
6. It is done by varying the time at which certain switches are turned “on” and turned “off” (i.e.
varying the switching angles).

1.3 CLASSIFICATION OF INVERTERS:

In general depending on the number of voltage levels of the output voltage waveforms, the
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inverters can be classified as:
• Two level inverters
and
• Multi-level inverters (MLI).

The basic two level inverters have some of the following demerits:
▪ More harmonic distortion.
▪ High rating of switches/devices required.
▪ dv/dt stress is high .
▪ Failure of a single switch/device will lead to power loss to the load.
▪ Increased heat loss in transformers and hence cooling becomes complex.

Thus induction machines fed by classical two level inverters have a poor quality of current and
voltage. This leads to the use of multilevel inverters in the drives community, for high power adjustable
speed systems etc.

1.4 MERITS OF MULTILEVEL INVERTERS:

The multi-level inverters are those which perform power conversion in multiple voltage steps to
obtain improved power quality, lower switching losses, better electromagnetic compatibility and higher
voltage capability. The most attractive features of multilevel inverters are as follows:
• They can generate voltages with extremely low distortion and lower dv/dt.
• They draw input current with very low distortion.
• They generate smaller common-mode (CM) voltage. In addition, using
Sophisticated modulation methods, CM voltages can be eliminated.
• It can operate with a lower switching frequency.
Their unique structure allows them to reach high voltages and power levels without the use of
transformers. They are specially suited to high voltage vehicle drives where low output voltage total
harmonic distortion (THD) and electromagnetic interference (EMI) are needed.

The general function of the multilevel inverter is to synthesize a desired voltage from several
levels of dc voltages. As the number of levels increases, the synthesized output waveform has more steps,
which produces a staircase wave that approaches the desired waveform. Also, as more steps are added to the
waveform, the harmonic distortion of the output wave decreases, approaching zero as the number of levels
increases. As the number of levels increases, the voltage that can be spanned by connecting devices in series
also increases. The structure of the multilevel inverter is such that no voltage sharing problems are
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encountered by the active devices.

Multilevel inverters can significantly improving the quality of the output voltage
waveform. With this, low frequency voltage harmonics are eliminated, generating almost perfect sinusoidal
waveforms, with a total harmonic distortion (THD) lower than 5%.

Another important characteristic is that each converter operates at a low switching

frequency, reducing the semiconductor stresses, and therefore reducing the switching losses. The principle
objective of this paper is to determine the simplest converter topology in terms of the number of power
semiconductors for a given number of levels. The “redundant” levels are minimized, and the combination of
bridges to maximize the number of levels and minimize power sources and semiconductors are analyzed.

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 CHAPTER 2

LITERATURE SURVEY

1] J. Rodriguez, S. Bernet, Bin Wu, J. O. Pontt, S. Kouro, “Multilevel Voltage-Source- Converter

Topologies for Industrial Medium-Voltage Drives, ” IEEE Transactions on Industrial Electronics, vol.
54, no. 6,pp. 2930-2945, Dec. 2007

➢ This paper covers the high-power voltage-source inverter and the most used multilevel-inverter
topologies, including the neutral-point-clamped, cascaded H-bridge, and flying-capacitor
converters. This paper presents the operating principle of each topology and a review of the most
relevant modulation methods, focused mainly on those used by industry. It is concluded that each
particular application leaving a space on the market for all the different solutions, depending on
their unique features and limitations like power or voltage level, dynamic performance,
reliability, costs, and other technical specifications.

2] M. Manjrekar, P. K. Steimer, and T. Lipo, “Hybrid multilevel power conversion system: A

competitive solution for high-power applications,” IEEE Transactions on Industry Applications, vol.
36, no. 3, pp. 834–841, May/June 2000

➢ This paper is devoted to the investigation of a hybrid multilevel power conversion system
typically suitable for high-performance high-power applications. The hybrid seven-level inverter
on the load side consists of a high-voltages low-switching IGBT inverter and a low-voltage fast-
switching IGBT inverter. A detailed analysis of a novel hybrid modulation technique for the
inverter, which incorporates stepped synthesis in conjunction with variable pulse width of the
consecutive steps is included.
3] K. A. Corzine, F. A. Hardrick, and Y. L. Familiant, “A cascaded multi-level H-bridge inverter
utilizing capacitor voltages sources,” in Proceedings of the IASTED International Conference. Palm
Springs CA, 2003, pp. 290–295
➢ A method is presented showing that a cascade multilevel inverter can be implemented using only
a single DC power source and capacitors. A standard cascade multilevel inverter requires q DC
sources for 2q + 1 level. Without requiring transformers, the scheme proposed here allows the
use of a multiple DC power source (e.g., a battery or a fuel cell stack).

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 CHAPTER-3

GENESIS OF MULTI LEVEL INVERTERS

In this chapter, the multilevel inverter and its types are discussed. The principle function of the
inverters is to generate an ac voltage from a dc source voltage. If the dc voltage is composed by many small
voltage sources connected in series, it becomes possible to generate an output voltage with several steps.

3.1 MULTILEVEL INVERTER CHARACTERISTICS:

Multi-level inverters include an arrangement of semiconductors and dc voltage sources required to

generate a staircase output voltage waveform. Fig. 3.1 shows the schematic diagram of voltage source-
inverters with a different number of levels.

Fig. 3.1 Basic Multilevel Inverters (a) Two levels (b) Three levels (c) m Levels

It is well known that a two level inverter, such as the one shown in Fig. 3.1(a), generates an output
voltage with two different values (levels), VC and “zero,” with respect to the negative terminal of the dc
source (“0”), while a three-level module, Fig.3.1(b) generates three different voltages at the output (2VC, VC,
and “zero”). The different positions of the ideal switches are implemented with a number of semiconductors
that are in direct relation with the output voltage number of levels. Multilevel inverters are implemented
with small dc sources to form a staircase ac waveform, which follows a given reference template. For
example, having three dc sources with magnitudes equal to 10 V each, a composed 7-level waveform can be
obtained (three positive, three negatives, and zero with respect to the middle point between the ten sources),
generating a sinusoidal waveform with 60-V amplitude as shown in Fig. 3.2, and with very low THD.

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 Fig. 3.2 Voltage Waveform for 7-Level Inverter

It can be observed that the larger the number of the inverter dc supplies, the greater the number of
steps that can be generated, obtaining smaller harmonic distortion.

However, the number of dc sources is directly related to the number of levels through the equation:

n = m-1

Where ‘n’ is the number of dc supplies connected in series and ‘m’ is the number of the output voltage
levels. In order to get a 21-level inverter output voltage, 30-V supplies would be required, which is too
much for a simple topology. Besides the problem of having to use too many power supplies to get a
multilevel inverter, there is a second problem which is also important, the number of power semiconductors
required to implement the commutation circuit, as shown in Fig.3.1 Technical literature has proposed two
converter topologies for the implementation of the power commutation, using force-commutated devices
transistors or gate turnoff thyristors (GTOs).

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3.2 TYPES OF MULTI-LEVEL INVERTERS:

The general structure of multi-level converter is to synthesize a near sinusoidal voltage from
several levels of dc voltages, typically from capacitor voltage sources. As number of levels increases, the
synthesized output waveform has more steps, which provides a staircase wave that approaches a desired
waveform. Also, as steps are added to waveform, the harmonic distortion of the output wave decreases,
approaching zero as the number of voltage levels increases.

The Multi-level inverters can be classified into three types.

• Diode–clamped Multi-level inverter

• Flying–capacitor Multi-level inverter
• Cascade Multi-level inverter

3.2.1 Cascaded Multi-level inverter:

A relatively new converter structure called Cascaded Multi-level inverter, can avoid extra
clamping diodes or voltage balancing capacitors. The converter topology used here is based on the
series connection of single phase inverters with separate DC sources.

3.2.1(a) Different topologies of H-bridge

1. Cascade H-bridge
2. Hybrid H-bridge

1. Cascade H-bridge:
Figure 3.3 shows the basic block of cascade H-bridge Multi-level inverter and its associated
switching instants .As shown it consists of four power devices and a DC source. The switching states for
four power devices are constant i.e., When S1 is on, S2 cannot be on and vice versa similarly with S3 and
S4.

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 Fig 3.3 Block of a H-bridge Multi-level inverter

Figure 3.3shows the power circuit for one phase of multi level inverter. The resulting voltage
ranges from +3Vdcto-3Vdc and the staircase are nearly sinusoidal, even without filtering.

2. Hybrid H-bridge:

A hybrid H-bridge inverter consists of a series of H-bridge inverter units. The general function of
this Multi-level inverter is to synthesize a desired voltage form several DC sources (SDCSs). Each
SDCS is connected to an H-bridge inverter. The AC terminal voltages of different level inverters are
connected in series. Unlike diode clamp or flying capacitors inverters the hybrid H-bridge inverter does not
require any voltage- clamping diodes or voltage-balancing capacitors.

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Fig 3.4 Circuit diagram of 4-level cascade multi-level invert

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2 (a). Single phase Hybrid H-bridge inverter:

Principle of operation:

Figure 3.2 shows the synthesized phase voltage waveform of five-level hybrid H-bridge
inverter with four SDCSs. The phase output voltage is synthesized by the sum of the four inverter
outputs, Van=Va1+Va2+Va3+Va4. Each inverter circuit can generate three different outputs,
+Vdc,0,-Vdc, by connecting the dc source to the ac output side by different combinations of four
GTOs,S1,S2,S3,S4. Turning on S1and S4 yields Va4=+Vdc. Turning on S2 and S3 yields Va4=-
Vdc. By passing the source yields Va4=0. Similarly ac output voltage at each level can be obtained
in the same manner.

The circuit connections of hybrid H-bridge and cascade H-bridge are same but the basic
difference between them is that we can have only voltage source of same magnitude in cascade H-
bridge whereas in hybrid h-bridge we can have voltage source of different magnitude in the hybrid
H-bridge. Figure 3.5 shows a single phase leg of the hybrid multilevel inverter

Fig 3.5 Hybrid H-Bridge inverter

Advantages:

▪ Requires the least number of components among all multi-level converters to achieve
the same number voltage levels.

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 ▪ Modularized circuit layout and packaging is possible because each level has the
structure, and there are no extra clamping diodes or Voltage balancing capacitors.
▪ Soft switching can be used in this structure to avoid bulky and loss in resistor,
capacitor, diode, snubbers.

Disadvantages:

▪ The limitation of h-bridge is the provision of the isolated power supply for each
individual H-bridge cell.

▪ For applications, where, isolated power supply cannot be

provided.

▪ The requirement of capacitors and complexity of its control increases as the number
of voltage levels increases, which restrict its applications.

The multilevel inverters can also be classified as follows:

• Symmetrical multilevel inverters.
• Asymmetrical multilevel inverters.

3.3 ASYMMETRICAL MULTILEVEL INVERTERS:

A multi-level inverter can be considered as a voltage source which can switch among a finite set
of levels and a multilevel inverter with different cell steps is called as asymmetric multilevel Inverter.
Asymmetric multi-level inverters have different input voltages in the bridges used.

3.3.1 Merits of asymmetric multi level inverter:

Asymmetric configuration is generally preferred than the symmetric one because of the following points:
• By addition and subtraction of these voltages, different output-voltage levels can be generated
with the same number of components, compared to a symmetric multi-level inverter.
• It achieves the high quality output voltage with less number of semiconductor devices, space
and costs than the symmetric topology.
• Output filters can be remarkably shrunk or even eliminated.

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 • The asymmetry of the input voltages can reduce or when properly designed, eliminate
redundant output levels.

But the only disadvantage is that switching is not easy in asymmetric MLI when compared to
symmetric inverters

3.4 APPLICATIONS:
1. Reactive power compensator

When a Multi-level inverter draws pure reactive power, the phase voltage and current are 90
degrees apart, and the capacitor charge and discharge can be balanced. Such a converter, when
serving for reactive power compensation is called Static Var Generator.
The multi-level structure allows all the converter to be directly connected to a high voltage
distribution or transmission system without the need of a step down transformer. All the
three Multi–level inverters can be used in reactive power compensation without having voltage
unbalanced problem.

2. Back to Back intertie

Inter connection of two Multi-level inverter with a DC link in between is called as a
Back to back intertie. In this type of circuit the left hand side converter servers as rectifier, while the
right hand side serves as the inverter. The purpose of the back to back intertie is to connect to
synchronous systems of different frequencies. It can be treated as a) frequency connector b) phase
shifter c) a power flow controller.

3. Utility compatible adjustable speed drives

An ideal utility compatible adjustable speed drives requires unity power factor,
negligible harmonics and high efficiency. By extended the back to back intertie, the multi- level
inverter can be used for a utility compatible adjustable speed drive with the input as constant
frequency AC source and the output has the variable frequency AC source. The major differences
when using as a utility compatible adjustable speed drives and for back to back intertie, are the
control design and size of capacitor.

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 CHAPTER 4
HARDWARE IMPLEMENTATION

In this chapter, hardware implementation of control circuit, power supply, driver

circuit and the components used and its working are discussed.
4.1 ORGANIZATION OF CONTROL CIRCUIT:

The control circuit employs the following blocks. These are explained in the
forthcoming topics.

➢ Power supply

➢ Driver circuit

➢ Microcontroller

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Input MLI
Levels

Driver
Circuit

Micro
Control
ler

Fig 4.1 Proposed method block diagram

The supply is taken from the DC source (Battery) and the ripple is removed by the capacitor.
The rectified dc is given to the multilevel inverter already designed for giving stepped ac which is
given to load. The microcontroller is programmed to generate the pulses according to the designed
switching sequence. Then the drive circuit is used to gives the threshold voltage for the semiconductor
devices. The above said circuit design are discussed below in detailed manner.

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4.2 POWER SUPPLY:

Step Down 12 VDC

240 VAC 12 V Bridge Capacitor 12 VDC Regulator 5 VDC
AC Rectifier 1000µf
INPUT Transformer Pulsating Corrected 7805 OUTPUT

Fig.4.2 Single line diagram

4.2.1 Block diagram of power supply:

The transformer does not add power, so it follows that the power (V × I) on
either side must be constant. That is the reason why the winding with more turns has higher voltage
but lower current, while the winding with less turns has lower voltage but higher current. The step
down transformer converts the AC input with the higher level to some lower level. A bridge rectifier
converts the AC voltage into DC voltage. A four-transistor converter (Bridge Rectifier) can generate
the highest output power than other types of rectifiers. The filter circuit resists the unwanted AC
signals. The regulator down-convert a DC voltage to a lower DC voltage of the same polarity.

Fig.4.3 Circuit Diagram for 5V power Supply

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 Fig. 4.4 The bridge rectifier

This circuit can give +5V output at about 150mA current, but it can be increased to
1A when good cooling is added to 7805 regulator chip. The circuit has overload and terminal
protection. This uses one single winding as the secondary and four diodes - two are conducting at any
one time. Note the configuration of the diodes: Diodes on parallel sides "point" in the same direction.
The AC signal is fed to the points where a cathode and anode join. The positive output is taken from
the junction of two cathodes. The other end of the load goes to the junction of two anodes. The
operation is simple: Parallel-side diodes conduct at the same time. Note that the two points are
connected by a diode - same as in the two previous cases. The other end of the load returns to the
transformer via the other parallel diode. When the polarity changes the other two diodes conduct. The
output waveform is the same as the full-wave rectifier. The main advantage of this rectifier is that it
has no centre-tap and no extra winding. Diodes can be small and cheap. A bridge rectifier can be
purchased as a "block" with four wire connections.

4.2.2 Unregulated power supply calculation:

Supply voltage - 240V

Secondary voltage - 12V
DC output approx. = 1.41xVac - (2x0.7)
=15.52V, after rectification
Where,
Vac is the rms transformer secondary voltage and
0.7 is the voltage drop across rectifier as there are two diodes conducting for each half cycle.

For bridge rectification,

Dc voltage is given by:

Vdc = Vp - I/4 CF,

Where,
Vp - peak voltage value,
C- Capacitance,
F-supply frequency, and
I-load current

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Vdc =15.52 - 900mA/4 x 1000π x 50
=11.02V

4.2.3 Regulated power supply:

Fig.4.5 LM 7805
This circuit can give +5V output at about 150 mA current, but it can be
increased to 1A when good cooling is added to 7805 regulator chip. The circuit has over overload and
terminal protection.

4.3 DRIVER UNIT:

The driver unit usually isolates the control circuit and the power circuit and
ensures the safe operation of the equipment.

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4.3.1 Opto-couplers:

The PIC Microcontroller is operated at 5 V whereas the converter circuit will be

operating at 220 V. There is a need of isolation between low voltage side and high voltage side in
order to avoid heavy in rush current. The heavy inrush current will occur when there is a short circuit
in the load side. This will affect the control circuit also. There are different ways to isolate the control
and power circuit. Opto-coupler is one of its kinds. Opto-couplers typically come in a small 6-pin or
8-pin IC package, but are essentially a combination of two distinct devices: an optical transmitter,
typically a gallium arsenide LED (light-emitting diode) and an optical receiver such as a
phototransistor or light-triggered diac. The two are separated by a transparent barrier which blocks
any electrical current flow between the two, but does allow the passage of light.

17
 MCT2E is an opto-coupler integrated circuit in which an infrared emitter diode
drives a phototransistor. They are also known as opto isolators since they separate two circuits
optically. These are used to couple two circuits without any ohmic contact. They allow one of the
circuits to switch another one while they are completely separate. The first circuit is connected to IR
diode while the other circuit with the phototransistor. The isolation ensures that no damage occurs in
either of the circuits while the other one has a fault.

An opto-coupler is analogous to a relay which isolates two circuits magnetically.

They differ with relays in the sense that they are smaller in size and allow fast operation. MCT2Es are
commonly used in interfacing an electronic circuit with the parallel port of a computer.

There are many situations where signals and data need to be transferred
from one subsystem to another within a piece of electronics equipment, or from one piece of
equipment to another, without making a direct ohmic electrical connection. Opto-couplers
typically come in a small 6-pin or 8-pin IC package, but are essentially a combination of two
distinct devices: an optical transmitter, typically a gallium arsenide LED (light-emitting
diode) and an optical receiver such as a phototransistor or light-triggered diac. The two are

18
separated by a transparent barrier which blocks any electrical current flow between the two,
but does allow the passage of light. The basic idea is shown in Fig.1, along with the usual
circuit symbol for an opto-coupler. Usually the electrical connections to the LED section are
brought out to the pins on one side of the package and those for the phototransistor or diac to
the other side, to physically separate them as much as possible. This usually allows opto-
couplers to withstand voltages of anywhere between 500V and 7500V between input and
output. Opto-couplers are essentially digital or switching devices, so they’re best for
transferring either on-off control signals or digital data. Analog signals can be transferred by
means of frequency or pulse-width modulation.

4.4 PIC MICROCONTROLLER AT89C51:

The AT89C51 is a low-power, high-performance CMOS 8-bit microcomputer with
4K bytes of Flash Programmable and Erasable Read Only Memory (PEROM). The device is
manufactured using Atmel’s high density nonvolatile memory technology and is compatible with the
industry standard MCS-51™ instruction set and pin out. The on-chip Flash allows the program
memory to be reprogrammed in-system or by a conventional nonvolatile memory programmer. By
combining a versatile 8-bit CPU with Flash on a monolithic chip, the Atmel AT89C51 is a powerful
microcomputer which provides a highly flexible and cost effective solution to many embedded control
applications The AT89C51 provides the following standard features: 4Kbytes of Flash, 128 bytes of
RAM, 32 I/O lines, two 16-bittimer/counters, a five vector two-level interrupt architecture full duplex
serial port, on-chip oscillator and clock circuitry. In addition, the AT89C51 is designed with static
logic for operation down to zero frequency and supports two software selectable power saving modes.
The device is manufactured using ATMEL high-density nonvolatile memory technology and is
compatible with the industry standard MCS-51 instruction set. By combining a versatile 8-bit CPU
with flash on a monolithic chip, the Atmel AT89C51 is a powerful microcomputer, which provides a
highly flexible and cost effective solution to many embedded control applications.

The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port and
interrupt system to continue functioning. The Power down Mode saves the RAM contents but freezes
the oscillator disabling all other chip functions until the next to the hardware set.

19
 Microcontroller
Circuit

4.4.1 FEATURES

➢ Compatible with MCS-51™ Products

➢ 4K Bytes of In-System Reprogrammable Flash Memory
➢ Fully Static Operation: 0 Hz to 24 MHz
➢ Three-Level Program Memory Lock
➢ 128 x 8-Bit Internal RAM
➢ 32 Programmable I/O Lines
➢ Two 16-Bit Timer/Counters
➢ Six Interrupt Sources
➢ Programmable Serial Channel
➢ Low Power Idle and Power Down Modes
➢ Endurance: 1,000 Write/Erase Cycles

4.4.2 BLOCK DIAGRAM OF MICROCONTROLLER 89C51

20
 Fig. 4.4.2 Block diagram of 8 bit microcontroller AT89c51

4.4.3A. Pin Configuration

21
 Fig. 4.4.3 Pin diagram of AT89C51

4.4.3B. Pin Description

Vcc

Supply voltage.

GND
Ground.

Port 0
Port 0 is an 8-bit open drain bidirectional I/O port. As an output port each pin can sink eight
TTL puts. When 1s are written to port 0 pins, the pins can be used as high impedance inputs. Port 0
may also be configured to be the multiplexed low order address/data bus during accesses to external
program and data memory. In this mode P0 has internal pullups.Port 0 also receives the code bytes
during Flash programming, and outputs the code bytes during program verification. External pull-ups
are required during program verification.

Port 1
Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. The Port 1 output buffers can
sink/source four TTL inputs. When 1s are written to Port 1 pins they are pulled high by the internal
pull-ups and can be used as inputs. As inputs, Port 1 pins that are externally being pulled low will

22
source current (IIL) because of the internal pullups. Port 1 also receives the low-order address bytes
during Flash programming and verification.
Port 2
Port 2 is an 8-bit bidirectional I/O port with internal pullups.The Port 2 output buffers can
sink/source four TTL inputs. When 1s are written to Port 2 pins they are pulled high by the internal
pull-ups and can be used as inputs. As inputs, Port 2 pins that are externally being pulled low will
source current (IIL) because of the internal pullups. Port 2 emits the high-order address byte during
fetches from external program memory and during accesses to external data memory that uses 16-bit
addresses (MOVX @ DPTR). In this application it uses strong internal pull-ups when emitting 1s.
During accesses to xternal data memory that use 8-bit addresses (MOVX @ RI), Port 2 emits the
contents of the P2 Special Function Register. Port 2 also receives the high-order address bits and
some control signals during Flash programming and verification.
Port 3
Port 3 is an 8-bit bidirectional I/O port with internal pullups.The Port 3 output buffers can
sink/source four TTL inputs. When 1s are written to Port 3 pins they are pulled high by the internal
pull-ups and can be used as inputs. As inputs, Port 3 pins that are externally being pulled low will
source current (IIL) because of the pull-ups. Port 3 also serves the functions of various special features
of the AT89C51 as listed below:

Port 3 also receives some control signals for Flash programming and verification.
RST
Reset input. A high on this pin for two machine cycles while the oscillator is running resets
the device.
ALE/PROG
Address Latch Enable output pulse for latching the low byte of the address during accesses to
external memory. This pin is also the program pulse input (PROG) during Flash programming.
In normal operation ALE is emitted at a constant rate of 1/6 the oscillator frequency, and may
be used for external timing or clocking purposes. Note, however, that one ALE pulse is skipped
during each access to external Data Memory.If desired, ALE operation can be disabled by setting bit 0
of SFR location 8EH. With the bit set, ALE is active only during a MOVX or MOVC instruction.
Otherwise, the pin is weakly pulled high. Setting the ALE-disable bit has no effect if the
microcontroller is in external execution mode.
PSEN
Program Store Enable is the read strobe to external program memory. When the AT89C51 is
executing code from external program memory, PSEN is activated twice each machine cycle, except
that two PSEN activations are skipped during each access to external data memory. EA/VPP External
Access Enable. EA must be strapped to GND in order to enable the device to fetch code from external
program memory locations starting at 0000H up to FFFFH. Note, however, that if lock bit 1 is

23
programmed, EA will be internally latched on reset. EA should be strapped to VCC for internal
program executions. This pin also receives the 12-volt programming enable voltage (VPP) during
Flash Programming, for parts that require 12-volt VPP.
XTAL1
Input to the inverting oscillator amplifier and input to the internal clock operating circuit.
XTAL2
Output from the inverting oscillator amplifier.
Oscillator Characteristics
XTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier which
can be configured for use as an on-chip oscillator, as shown in Figure 1. Either a quartz crystal or
ceramic resonator may be used. To drive the device from an external clock source, XTAL2 should be
left unconnected while XTAL1 is driven as shown in Figure 2.There are no requirements on the duty
cycle of the external clock signal, since the input to the internal clocking circuitry is through a divide-
by-two flip-flop, but minimum and maximum voltage high and low time specifications must be
observed.

Idle Mode
In idle mode, the CPU puts itself to sleep while all the on chip peripherals remain active. The
mode is invoked by software. The content of the on-chip RAM and all the special functions registers
remain unchanged during this mode. The idle mode can be terminated by any enabled interrupt or by a
hardware reset. It should be noted that when idle is terminated by a hardware reset, the device
normally resumes program execution, from where it left off, up to two machine cycles before the
internal reset algorithm takes control. On-chip hardware inhibits access to internal RAM in this event,
but access to the port pins is not inhibited. To eliminate the possibility of an unexpected write to a port
pin when Idle is terminated by reset, the instruction following the one that invokes Idle should not be
one that writes to a port pin or to external memory.
Power down Mode
In the power down mode the oscillator is stopped, and the instruction that invokes power
down is the last instruction executed. The on-chip RAM and Special Function Registers retain their
values until the power down mode is terminated. The only exit from power down is a hardware reset.
Reset redefines the SFRs but does not change the on-chip RAM. The reset should not be activated
before VCC is restored to its normal operating level and must be held active long enough to allow the
oscillator to restart and stabilize.
Program Memory Lock Bits
On the chip are three lock bits which can be left unprogrammed (U) or can be programmed
(P) to obtain the additional features listed in the table below:
When lock bit 1 is programmed, the logic level at the EA pin is sampled and latched during reset. If
the device is powered up without a reset, the latch initializes to a random value, and holds that value

24
until reset is activated. It is necessary that the latched value of EA be in agreement with the current
logic level at that pin in order for the device to function properly.
Programming Algorithm:
Before programming the AT89C51, the address, data and control signals should be set up
according to the Flash programming mode table and Figures 3 and 4. To program the AT89C51, take
the following steps.
1. Input the desired memory location on the address lines.
2. Input the appropriate data byte on the data lines.
3. Activate the correct combination of control signals.
4. Raise EA/VPP to 12V for the high-voltage programming mode.

5. Pulse ALE/PROG once to program a byte in the Flash array or the lock bits. The byte-write cycle is
self-timed
And typically takes no more than 1.5 ms. Repeat steps 1 through 5, changing the address and data for
the entire array or until the end of the object file is reached.
Data Polling:
The AT89C51 features Data Polling to indicate the end of a write cycle. During a write cycle,
an attempted read of the last byte written will result in the complement of the written datum on PO.7.
Once the write cycle has been completed, true data are valid on all outputs, and the next cycle may
begin. Data Polling may begin any time after a write cycle has been initiated.
Ready/Busy:
The progress of byte programming can also be monitored by the RDY/BSY output signal.
P3.4 is pulled low after ALE goes high during programming to indicate BUSY. P3.4 is pulled high
again when programming is done to indicate READY.
Program Verify:
If lock bits LB1 and LB2 have not been programmed, the programmed code data can be read
back
via the address and data lines for verification. The lock bits cannot be verified directly. Verification of
the lock bits is achieved by observing that their features are enabled.

Chip Erase:
The entire Flash array is erased electrically by using the proper combination of control signals
and by holding ALE/PROG low for 10 ms. The code array is written with all “1”s. The chip erase
operation must be executed before the code memory can be re-programmed.
Reading the Signature Bytes:
The signature bytes are read by the same procedure as a normal verification of locations 030H,
031H, and 032H, except that P3.6 and P3.7 must be pulled to a logic low. The values returned are as
follows.

25
(030H) = 1EH indicates manufactured by Atmel
(031H) = 51H indicates 89C51
(032H) = FFH indicates 12V programming
(032H) = 05H indicates 5V programming

Programming Interface
Every code byte in the Flash array can be written and the entire array can be erased by using
the appropriate combination of control signals. The write operation cycle is self timed and once
initiated, will automatically time itself to completion. All major programming vendors offer
worldwide support for the Atmel microcontroller series. Please contact your local programming
vendor for the appropriate software revision.
Flash programming

There are three methods of erasing or programming of the FLASH memory that may be used.
First, the FLASH may be programmed or erased in the end-user application by calling low level
routine through a common entry point in the Boot ROM. The end user application, through, must be
execution code from different block then the blocked that is being erased or programmed.

4.4.4 Control Circuit with Real Time Inputs, Outputs

Fig. 4.4.4 Configuration diagram

In the configuration diagram the crystal oscillator is connected between XTAL1 and XTAL2.
The two series capacitors are connected parallel with crystal. The 10th pin of the microcontroller is
grounded. The regulator R7805 output (3-pin of R7805) is given to the 20th pin of microcontroller.
The data is transferred from the PC to the microcontroller through the interface. The program is

26
written using pinnacle software. In the program port 1 is used as the input port.

4.5 MOSFET:

MOSFET has a less value of on - state resistance at higher frequency. Hence

MOSFET is used as a switch in this project work. The basics of the MOSFET are as follows.

4.5.1 Basics of MOSFET:

The MOSFET or Metal Oxide Semiconductor Field Effect Transistors by far, is the
most common field effect transistor used in both digital and analog circuits. The MOSFET is
composed of a channel of n-type or p-type semiconductor material, and is accordingly called as N-
MOSFET or a PMOSFET. Unfortunately, many semiconductors with better electrical properties than
silicon such as gallium arsenide do not form good gate oxides and thus are not suitable for
MOSFETS. The gate terminal is a layer of poly silicon (polycrystalline silicon) or aluminums placed
over a channel, but separated from the channel by a thin layer of insulating silicon dioxide.

A simplified diagram of the N-channel enhancement MOSFETS is shown in figure

4.7. Drain and source connections are made to higher conduction high doped regions. The metal gate
is electrically isolated from the P-type substrate by a layer of non-conducting silicon di-oxide (SiO2).

When a positive voltage is applied to the gate with respect to the source an electric
field will be created pointing away from the base and across the P-region directly under the base. The
electric field will cause positive charges in the P-region to move away from the base inducing or
enhancing an N-region in its place. Conduction can then take place between the N+ (drain) N
(enhanced region) N+ (sources). Increasing or decreasing in size thus controlling conduction. Varying
the voltage between the gate and body modulates the conductivity of this layer and makes it possible
to control the current flow between drain and source.

27
 DRAIN N+

Z
VDS
GATE
P
VGS
N+

L
SOURCE O
A
D

Fig. 4.7 Simple model of an N-channel enhancement type MOSFET

In practice, a fairly large current in the order of 1-2A can be required to charge
the gate capacitance at turn ON to ensure that switching times are small. Due to gate leakage current,
nano-amps are needed to maintain the gate voltage once the device is ON.A negative voltage is often
applied at turn OFF to discharge the gate for speedy switch OFF. It is obvious that faster switching
speeds can be obtained with well designed gate driver circuits.

4.5.2 Advantages of Power MOSFET:

➢ Power MOSFET has lower switching losses but its conduction losses are more.

➢ MOSFET is a voltage-controlled device.

➢ MOSFET has positive temperature co-efficient for resistance. This makes parallel
operation of MOSFET easy. If a MOSFET shares increased current initially, it
heats up faster its resistance rises and this increased resistance causes this current
to shift to other devices in parallel

➢ In MOSFET secondary break down does not occur, because it has positive
temperature co-efficient.

➢ Power MOSFETS in higher voltage ratings have more conduction losses

4.5.3 MOSFET Symbol:

28
Fig 4.8 Symbol of MOSFET

29
 CHAPTER 5

MATLAB SIMULATION

5.1. INTRODUCTION TO MAT LAB:

MATLAB (for matrix laboratory) is a numerical computing environment and fourth-

generation programming language. Developed by Math Works, MATLAB allows matrix
manipulations, plotting of functions and data, implementation of algorithms, creation of user
interfaces, and interfacing with programs written in other languages, including C, C++, and Fortran.
To develop smaller, more efficient devices that integrate audio, wireless communications, electronics
and semiconductor engineers rely on MATLAB/ Simulink. They use the tools to explore and validate
algorithms and system designs in hours or days rather than weeks.
MATLAB /Simulink are widely used in electronics and semiconductor companies, as
well as the major industries that integrate electronic components, such as aerospace and defense,
automotive, and communications . Although MATLAB is intended primarily for numerical
computing, an optional toolbox uses the MuPAD symbolic engine, allowing access to symbolic
computing capabilities. An additional package, Simulink, adds graphical multi-domain simulation
and Model-Based Design for dynamic and embedded systems.
In 2004, MATLAB had around one million users across industry and academia.
MATLAB users come from various backgrounds of engineering, science, and economics.
MATLAB is widely used in academic and research institutions as well as industrial enterprises.

SIMULINK, now incorporated into MATLAB, can also be used to analyze and
design of power systems. During last four decade’s simulation of power systems have gained more
importance.

5.1.1 MATLAB History:

Cleve Moler, the chairman of the computer-science department at the University

of New Mexico, started developing MATLAB in the late 1970s. He designed it to give his

30
student’s access to LINPACK and EISPACK without them having to learn Fortran. It soon
spread to other universities and found a strong audience within the applied mathematics
community. Jack little, an engineer, was exposed to it during a visit Moler made to Stanford
University in 1983. Recognizing its commercial potential, he joined with Moler and Steve
Bangert. They rewrote MATLAB in C and founded Math Works in 1984 to continue its
development. These rewritten libraries were known as JACKPAC. In 2000, MATLAB was
rewritten to use a newer set of libraries for matrix manipulation, LAPACK.

MATLAB was first adopted by researchers and practitioners in control

engineering, Little's specialty, but quickly spread to many other domains. It is now also used
in education, in particular the teaching of linear algebra and numerical analysis, and is
popular amongst scientists involved in image processing.

5.2. FEATURES OF MAT LAB:

The features of the MATLAB toolboxes used in the analysis of power systems
are, facilitating future revision and expansion of software. This is very important for
researches that are interesting in developing and testing new for various power system
applications.

It provides an avenue to easily prepare input data files in commonly accepted

formats for networks that are created and the results produced by one application can be
easily used either fully or partially by any other application supported by the package.

5.2.1 Quickly Prove the System Works

Testing overall system behavior using traditional methods cannot begin until the
implementation is complete. By contrast, Simulink enables engineers to create one model that
includes analog, digital, and mechanical components, and begin system verification early in the
design process.
The MATLAB/Simulink system models serve as a golden reference and link directly
to popular third-party development tools to simplify test harness construction.

5.2.2 Semiconductors

Semiconductor engineering teams designing analog, mixed-signal, and other complex

devices must include more functionality, in less time, and with fewer engineers than ever before.

31
 To improve efficiency, these teams increasingly rely on Math Works products. By
sharing MATLAB/Simulink models, organizations improve collaboration between analog and digital
designers, and between design and verification engineers. As a result, verification is more through and
teams find errors earlier.

5.2.3 Enhanced Analog and Mixed-Signal System Design

Modeling analog/mixed-signal systems in low-level languages is time-consuming, and

therefore limits the number of design alternatives engineers can evaluate. By contrast, MATLAB and
Simulink provide a higher level of design abstraction and faster design and simulation, which enables
engineers to evaluate many different designs. For system models involving feedback, Simulink
substantially reduces simulation time compared to alternatives such as SPICE simulators. As a result,
teams are more efficient at designing and simulating mixed-signal components such as phase-locked
loops and analog-to-digital converters

32
5.3. BLOCK LIBRARIES:

The PSB is a graphic tool that allows building schematics and simulation of power
systems in the SIMULINK environment. The block set uses the SIMULINK environment to represent
common components and devices found in electrical power networks. It consists of a block library
that includes electrical models such as RLC branches and loads, transformers, lines, surge arrester,
electric machines, power electronics devices, etc. Diagrams can be assembled simply by using click
and drag procedures into SIMULINK windows.

The Power System Block set uses the same drawing and interactive dialogue boxes to
enter parameters as in standard SIMULINK blocks. Simulation results can be visualized with
SIMULINK scopes connected to outputs of measurement blocks available in the PSB library. These
measurement blocks acts as an interface between the electrical blocks and the SIMULINK blocks.

The voltage and current measurement blocks can be used at selected points in the circuit
to convert electrical signals into SIMULINK signals. Nonlinear elements requiring control, such as
power electronic devices, have a SIMULINK inputs that allow control from a SIMULINK system.
Elements in the PSB block library are classified in various groups according to their
nature: Application Libraries, Electrical Sources, Elements, Extra Library, Machines, Power
Electronics, Connectors, Measurements and Power guide. Application libraries consist of Distributed
resources library, Electric drives library and Flexible AC transmission library.

Electrical Sources group contains A.C. current source, A.C. and D.C. voltage source,
Controlled voltage and current source, Three-phase programmable voltage source, three phase source
and Battery.

The Elements group contains single-phase models RLC branches and loads, linear and
saturable transformers, mutual inductances, n-section lines, MOV type surge arrester, circuit breaker
and n-phase distributed-parameter line model. Using the masking facility of SIMULINK, the user can
easily add more complex elements built from the basic PSB building blocks and associate a dialog
box.

33
 This technique has been used to develop a three-phase library which is also
provided. The Power Electronics group contains common semiconductor devices. Each element in
this group (except Diode) has a SIMULINK gating control input and a SIMULINK output returning
switch current and voltage. Extra library consist of Control blocks, discrete control blocks, discrete
measurements and Phasor Library.

The Machines group contains simplified and detailed models of synchronous

machine, an asynchronous machine, a permanent magnet synchronous machine, a model of hydraulic
turbine governor, and an excitation system. Each machine block has a SIMULINK output returning
measurements of internal variables.

The PSB graphical interface (Powerful) includes an interactive tool to set initial
conditions. This allows simulation with initial conditions, or to start the simulation with steady-state.
A load-flow computational engine allows initializing three-phase circuits containing synchronous and
asynchronous machines, so that the simulation directly starts in steady-state.

Fig 5.1Block Diagram

34
5.4 SIMULINK MODEL CONVERTER:

System modeling is probably the most important phase in any form of system control design
work. The choice of a circuit model depends upon the objectives of the simulation. If the goal is to
predict the behavior of a circuit before it is built. A good system model provides a designer with
valuable information about the system dynamics. Due to the difficulty
involved in solving general nonlinear equations, all the governing equations will be put together in
block diagram form and then simulated using MATLAB Simulink program.

Simulink, developed by Math Works, is a commercial tool for modeling, simulating and
analyzing multi-domain dynamic systems. Its primary interface is a graphical block diagramming tool
and a customizable set of block libraries. It offers tight integration with the rest of the MATLAB
environment and can either drive MATLAB or be scripted from it. Simulink is widely used in control
theory and digital signal processing for multi-domain simulation and Model-Based Design.

Simulink is a block diagram environment for multi-domain simulation and Model-Based

Design. It supports system-level design, simulation, automatic code generation, and continuous test
and verification of embedded systems. Simulink provides a graphical editor, customizable block
libraries, and solvers for modeling and simulating dynamic systems. It is integrated with MATLAB,
enabling you to incorporate MATLAB algorithms into models and export simulation results to
MATLAB for further analysis.

Simulink will solve these nonlinear equations numerically, and provide a simulated response
of the system dynamic.

5.5 MODELING PROCEDURE:

To obtain a nonlinear model for power electronic circuit laws and to avoid the use of
complex mathematics, the electrical and semiconductor devices must be represented as ideal
components (zero ON voltages, zero OFF currents, zero switching times). Therefore, auxiliary binary
variables can be used to determine the state of the switches. It must be ensuring that the equations
states due to power semiconductor devices being ON or OFF.

The steps to obtain a system-level modeling and simulation of power electronic converters are
listed below.

35
 1) Determine the state variables of the power circuit in order to write its switched state-
space model e.g., inductor current and capacitor voltage.

2) Assign integer variables to the power semiconductor (or to each switching cell) ON and OFF
states.

3) Determine the conditions governing the states of the power semiconductors or the switching
cell.

4) Assume the main operating modes of the converter (continuous or discontinuous conduction
or both) or the modes needed to describe all the possible circuit operational modes.

5) Write this model in the integral form, or transform the differential form to include the
semiconductors logical variables in the control vector: the converter will be represented by a set of
nonlinear differential equations.

6) Implement the derived equations with "SIMULINK" blocks (open loop system simulation is
then possible to check the obtained mode.

7) Use the obtained switched space-state model to design linear or nonlinear controllers for the
power converter.

8) Perform closed-loop simulations and evaluate converter performance.

9) The algorithm for solving the differential equations and the step size should be chosen before
running any simulation.

5.6 RUNNING THE SIMULATION:

We can run your simulation interactively from the Simulink Editor or systematically from the
MATLAB command line. The following simulation modes are available:

• Normal (the default), which interpretively simulates the model

• Accelerator, which increases simulation performance by creating and executing compiled
target code but still provides the flexibility to change model parameters during simulation
• Rapid Accelerator, which can simulate models faster than Accelerator mode by creating an
executable that can run outside Simulink on a second processing core

To reduce the time required to run multiple simulations, we can run those simulations in parallel
on a multi-core computer or computer cluster.

5.6.1 Analyzing Simulation Results

36
 After running a simulation, we can analyze the simulation results in MATLAB
and Simulink. Simulink includes debugging tools to help to understand the
simulation behavior.
5.6.2 Viewing Simulation Results

We can visualize the simulation behavior by viewing signals with the displays and
scopes provided in Simulink. We can also view simulation data within the Simulation Data
Inspector, where we can compare multiple signals from different simulation runs. Scope is
the block in Simulink by which we can measure and view the voltage, current, and power in
electrical domain. Result shows the output of a multilevel converter through scope.

5.6.3 Debugging the Simulation

Simulink supports debugging with the Simulation Stepper, which lets we step back
and forth through your simulation viewing data on scopes or inspecting how and when the
system changes states. With the Simulink debugger we can step through a simulation one
method at a time and examine the results of executing that method. As the model simulates,
you can display information on block states, block inputs and outputs, and block method
execution within the Simulink Editor.

5.7 SIM POWER SYSTEMS:

Sim Power Systems provides component libraries and analysis tools for modeling and
simulating electrical power systems. The libraries include models of electrical power components,
including three-phase machines, electric drives, and components for applications such as flexible AC
transmission systems (FACTS) and renewable energy systems. Harmonic analysis, calculation of total
harmonic distortion (THD), load flow, and other key electrical power system analyses are automated.
Sim Power Systems was developed by Hydro-Québec of Montreal.

Sim Power Systems models as shown in it can be used to develop control systems and test
system-level performance. We can parameterize the models using MATLAB® variables and
expressions, and design control systems for the electrical power system in Simulink®. We can add

37
mechanical, hydraulic, pneumatic, and other components to the model using Sims cape™ and test
them all in a single simulation environment. To deploy models to other simulation environments,
including hardware-in-the-loop (HIL) systems, Sim Power Systems supports C-code generation.

Starting with Math Works Release 13, Sim Power Systems and Sim Mechanics of the
Physical Modeling product family work together with Simulink to model electrical, mechanical, and
control systems. Electrical power systems are combinations of electrical circuits and
electromechanical devices like motors and generators. Engineers working in this discipline are
constantly improving the performance of the systems. Requirements for drastically increased
efficiency have forced power system designers to use power electronic devices and sophisticated
control system concepts that tax traditional analysis tools and techniques. Further complicating the
analyst’s role is the fact that the system is often so non linear that the only way to understand it is
through simulation.

Land-based power generation from hydroelectric, steam, or other devices is not the only use
of power systems. A common attribute of these systems is their use of power electronics and control
systems to achieve their performance objectives. Sim Power Systems was designed to provide a
modern design tool that allows scientists and engineers to rapidly and easily build models that
simulate power systems.

Sim Power Systems uses the Simulink environment, allowing you to build a model using
simple click and drag procedures. Not only can you draw the circuit topology rapidly, but your
analysis of the circuit can include its interactions with mechanical, thermal, control, and other
disciplines. This is possible because all the electrical parts of the simulation interact with the extensive
Simulink modeling library. Since Simulink uses MATLAB as its computational engine, designers can
also use MATLAB toolboxes and Simulink block sets. Sim Power Systems and Sim Mechanics share
a special Physical Modeling block and connection line interface.

Users can rapidly put Sim Power Systems to work. The libraries contain models
of typical power equipment such as transformers, lines, machines, and power electronics.
These models are proven ones coming from textbooks, and their validity is based on the
experience of the Power Systems Testing and Simulation Laboratory of Hydro-Québec, a
large North American utility located in Canada. The capabilities of Sim Power Systems for
modeling a typical electrical grid are illustrated in demonstration files. And for users who
want to refresh their knowledge of power system theory, there are also self-learning case
studies.

38
5.8 SUBSYSTEMS:

Each of the power electronic models represents subsystems within the simulation environment.
These blocks have been developed so they can be interconnected in a consistent and simple manner
for the construction of complex systems.

The subsystems are masked, meaning that the user interface displays only the complete
subsystem, and user prompts gather parameters for the entire subsystem. Relevant parameters can be
set by double-clicking a mouse or pointer on each subsystem block, then entering the appropriate
values in the resulting dialogue window.

To facilitate the subsequent simulation analysis and feedback controller verification, the
pulse-width-modulation signal to control the ideal switch can also be built into the masked subsystem.
For each converter to verity it’s working in open loop configuration trigger pulses have been derived
using a repeating sequence generator and duty cycle block.

An input to the switch control, hence inputs for the masked subsystem are duty ratio and
input voltage, and the outputs are chosen to be inductor current, capacitor voltage, and output voltage.
When double-clicking the pointer on the masked subsystem, one enters parameter values of the
switching converter circuit in a dialogue window.

5.9 MODELING ELECTRICAL POWER SYSTEMS:

With Sim Power Systems, we build a model of a system just as we would assemble a physical
system. The components in the model are connected by physical connections that represent ideal
conduction paths. This approach describes the physical structure of the system rather than deriving
and implementing the equations for the system. From the model, which closely resembles a schematic,
Sim Power Systems automatically constructs the differential algebraic equations (DAEs) that
characterize the behavior of the system. These equations are integrated with the rest of the Simulink
model.
We can use the sensor blocks in Sim Power Systems to measure current and voltage in your
power network, and then pass these signals into standard Simulink blocks. Source blocks enable
Simulink signals to assign values to the electrical variables current and voltage. A sensor and source
block connects a control algorithm developed in Simulink to a Sim Power Systems network.

5.10 APPLICATIONS:

A number of Math Works and third-party hardware and software products are
available for use with Simulink. For example, State flow extends Simulink with a design

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environment for developing state machines and flow charts. Coupled with Simulink Coder,
another product from Math Works, Simulink can automatically generate C source code for
real-time implementation of systems. As the efficiency and flexibility of the code improves,
this is becoming more widely adopted for production systems, in addition to being a popular
tool for embedded system design work because of its flexibility and capacity for quick
iteration. Embedded Coder creates code efficient enough for use in embedded systems.

XPC Target together with x86-based real-time systems provides an environment to

simulate and test Simulink and State flow models in real-time on the physical system.
Embedded Coder also supports specific embedded targets, including Infineon C166,
Motorola68HC12, Motorola MPC 555, TI C2000, TI C6000, RenesasV850 and Renesas
Super H.With HDL Coder, also from Math Works, Simulink and State flow can automatically
generate synthesizable VHDL and Verilog.

Simulink Verification and Validation enables systematic verification and validation of

models through modeling style checking, requirements traceability and model coverage
analysis. Simulink Design Verifier uses formal methods to identify design errors like integer
overflow, division by zero and dead logic, and generates test case scenarios for model
checking within the Simulink environment.

The systematic testing tool TPT offers one way to perform formal test- verification
and validation process to stimulate Simulink models but also during the development phase
where the developer generates inputs to test the system. By the substitution of the Constant
and Signal generator blocks of Simulink the stimulation becomes reproducible.

Sim Events adds a library of graphical building blocks for modeling queuing systems to the
Simulink environment. It also adds an event-based simulation engine to the time-based simulation
engine in Simulink.

5.11 SIMULATION OF MULTI-LEVEL INVERTER:

The multi-level inverter system is a very promising device in AC power drives when
both reduced content and high power are required. Up to now several multi- level topologies have
been introduced. The main topologies are diode clamped inverter, flying capacitor inverter, hybrid

40
H-bridge inverter in order to generate a high voltage waveform using low voltage devices. In this
chapter, we are considering the simulation of H- bridge inverters. Compared with diode clamped
inverter and flying capacitor inverter ,H- bridge inverters requires the least number of components
to achieve the same number of voltage levels and H-bridge inverters does not require any extra
clamping diodes or voltage balancing capacitors. Optimized circuit layout and packaging are
possible in H- bridge multi-level inverter because each level has the same structure.

The general structure of the H-bridge multi-level inverter is to synthesize a near sinusoidal
voltage form several levels of DC voltages. As the number of levels are increased, the synthesize
output waveform has more steps which produce a staircase wave that approaches the desired
waveform. Also as the steps are added to the waveform the harmonic distortion of the output wave
decreases.

Fig 5.2 THD Analysis

From the above analysis, THD was found to be 18.65%.

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Fig 5.3 Twenty one level inverter simulation diagram

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Fig 5.4 Simulation output for 21 levels

CHAPTER 6

43
 HARDWARE RESULTS

6.1 HARDWARE CIRCUIT FOR TWENTY ONE LEVEL INVERTER

The following pictures show the actual hardware implementation of the Optimized twenty one
Level Cascaded Inverter. The components used are described in the previous chapters.

Fig 6.6 Overall circuit

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45
Different Voltage Sources through Regulated power supplies

46
Fig 6.7 Waveform after connecting load closer view

Fig 6.8 Waveform after connecting load in CRO

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 CHAPTER 7

CONCLUSION

Multilevel inverters with a large number of steps or levels have been

analyzed. The problem has been focused in minimizing the number of H-Bridges for a given
number of levels. The optimization process shows that the numbers of levels are increased to
21 levels by use of four H-bridges.

In my project, I proposed a circuit to eliminate the selected harmonics

from the output obtained. The software implementation of the circuit was done using
MATLAB, where the circuit was designed and the output was simulated. I implemented the
same circuit using hardware. The harmonics were eliminated from the Twenty-One level
output using a set of inverters. The result obtained from the MATLAB simulation matched
with the output of the hardware designed by me.

7.1 ADVANTAGES:

The major advantage of my project is that it is simple and easy to

implement. The total expense incurred in designing the circuit was relatively less. The
proposed circuit for harmonic elimination effectively eliminated the harmonics of selected
order which makes it useful for various applications.

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 REFERNCES

1. J. M. Carrasco, L. G. Franquelo, J. T. Bialasiewicz, E. Galvan, R. C. P. Guisado, Ma. A. M. Prats,

J. I. Leon, N. Moreno-Alfonso, “Power-Electronic Systems for the Grid Integration of Renewable
Energy Sources: A Survey,” IEEE Transactions on Industrial Electronics, vol. 53, no. 4, pp.
1002-1016, June 2006.

2. A. J. Morrison, “Global Demand Projections for Renewable Energy Resources,” IEEE Canada
Electrical Power Conference, 25-26 Oct. 2007, pp 537-542.

3. J. Rodriguez, S. Bernet, Bin Wu, J. O. Pontt, S. Kouro, “Multilevel Voltage-Source-Converter

Topologies for Industrial Medium-Voltage Drives, ” IEEE Transactions on Industrial Electronics,
vol. 54, no. 6, pp. 2930-2945, Dec. 2007.

4. S. A. Khajehoddin, A. Bakhshai, P. Jain, “The Application of the Cascaded Multilevel Converters

in Grid Connected Photovoltaic Systems,” IEEE Canada Electrical Power Conference, 25-26
Oct. 2007, pp. 296-301.

5. J.S. Lai, F. Z. Peng, “Multilevel Converters - A New Breed of Power Converters,” IEEE
Transactions on Industry Applications, vol. 32, no. 3, May/Jun. 1996, pp. 509-517.

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