Verilog Interview Questions with

Answers
1. Difference between blocking and non-blocking assignments
Blocking Assignments: The blocking assignment statements are executed
sequentially by evaluating the RHS operand and finishes the assignment to LHS
operand without any interruption from another Verilog statement. Hence, it blocks
other assignments until the current assignment completes and is named a
“blocking assignment”.
Ex: a = 5;
Non-Blocking Assignments: The non-blocking assignment statement starts its
execution by evaluating the RHS operand at the beginning of a time slot and
schedules its update to the LHS operand at the end of a time slot. Other Verilog
statements can be executed between the evaluation of the RHS operand and the
update of the LHS operand. As it does not block other Verilog statement
assignments, it is called a non-blocking assignment.
Ex: a <= 5;

2. Difference between wire and reg

Net types:

1. The net (wire, tri) is used for physical connection between structural elements.

2. Value is assigned by a continuous assignment or a gate output or port of a

module.

3. It can not store any value. The values can be either read or assigned.

4. Default value – z

Register type:

1. The register (reg, integer, time, real, real-time) represents an abstract data
storage element and they are not the physical registers.

Verilog Interview Questions with Answers 1

 2. Value is assigned only within an initial or an always statement.

3. It can store the value.

4. Default value – x

3. What is an automatic keyword in the task?

The automatic keyword specifies the variable’s scope within a task i.e. memory is
allocated for the variables in the task and deallocated once the task completes
execution. All variables declared in an automatic task are automatic variables
unless they are specifically mentioned as a static variable.

4. Difference between $stop and $finish.

$stop suspends the simulation and puts a simulator in an interactive mode.
$finish exits the simulation.

5. Difference between $random and $urandom

Both generate 32-bit pseudorandom numbers, but $random generates signed
whereas $urandom generates unsigned numbers.

6. What is the default value of wire and reg?

The default value of the wire or net is z

The default value of the reg is x

7. Explain Regular delay control, Intra-assignment delay control

Regular delay control:

The regular delay control delays the execution of the entire statement by a
specified value. The non-zero delay is specified at the LHS of the procedural
statement.

Example: #5 data = i_value;

Verilog Interview Questions with Answers 2

 In this case, the result signal value will be updated after 5-time units for change
happen in its input.
Intra-assignment delay:

Intra-assignment delay control delays computed value assignment by a specified

value. The RHS operand expression is evaluated at the current simulation time and
assigned to the LHS operand after a specified delay value.

Example: data = #5 i_value;

8. Difference between full and parallel case

Full Case:

In a full case statement, case statements cover every possible input value is
explicitly specified and there are no unspecified or “don’t care” conditions.
Example:

case (input)
3'b000: ………
3'b001: ………
3'b010: ………
3'b011: ………
3'b100: ………
3'b101: ………
3'b110: ………
3'b110: ………
default: // any other input case which is not covered
endcase

Parallel Case:

In a parallel case statement, multiple case items can match the input value
simultaneously and the corresponding behaviors for that will be executed in
parallel.

Example:

Verilog Interview Questions with Answers 3

 case (input)
4'b0?: ………
4'b1?: ………
// other cases
default: // any other input case which is not covered
endcase

9. What is synchronous and asynchronous reset? Can you explain using DFF
and write their Verilog code?

In asynchronous reset, a flip flop gets reset as soon as the ‘reset’ signal is
asserted. Thus, in Verilog implementation, the ‘reset’ signal has to be written in the
sensitivity list of always block.

In synchronous reset, a flip flop gets reset at the active ‘clock’ edge when the
‘reset’ signal is asserted.
Thus, in Verilog implementation, the ‘reset’ signal must not be written in the
sensitivity list of the always block.

10. What is #0 in Verilog and its usage?

Zero delay control is used to control execution order when multiple procedural
blocks try to update values of the same variable. Both always and initial blocks
execution order is non-deterministic as they start evaluation at the same
simulation time. The statement having zero control delay executes last, thus it
avoids race conditions.
Example:

reg [2:0] data;

initial begin
data = 2;
end
initial begin

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 #0 data = 3;
end

Without zero delay control, the ‘data’ variable may have a value of either 2 or 3
due to race conditions. Having zero delay statements as specified in the above
code guarantees the outcome to be 3. However, it is not recommended to assign
value to the variable at the same simulation time.

11. How to generate two different clocks in the testbench?

module tb;
bit clk1, clk2;
initial forever #5ns clk1 = ~clk1;
initial forever #4ns clk2 = ~clk2;
endmodule

12. Write a Verilog code for D-Latch.

The latch has two inputs ‘data (D)’ and ‘clock (clk)’

One output data (Q)

If clk = 1, then data passes to the output Q

If clk = 0, then data is not passed to the output Q

module d_latch (input d, en, rst_n, output reg q);

always @(en or rst_n or d) begin
if(!rst_n) begin
q <= 0;
end
else begin
if(en) q <= d;
end
end
endmodule

Verilog Interview Questions with Answers 5

 13. What is Synthesis?

The process of converting hardware description language like Verilog code into
the equivalent netlist design that has flip-flops, logic gates, and required digital
circuit components.

14. Write an RTL code to generate 60% duty cycle clock.

`define CLK_PERIOD 10ns

module clk_gen;
realtime on_t = `CLK_PERIOD * 0.6;
realtime off_t = `CLK_PERIOD * 0.4;
bit clk;

always begin
#on_t clk = 0;
#off_t clk = 1;
end

initial begin
clk = 1;
#50 $finish;
end

initial begin
// Dump waves
$dumpfile("dump.vcd");
$dumpvars(0);
end
endmodule

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 15. Write an RTL code to generate 100MHz clock.

To generate clock frequency, time period needs to be calculated.

Time Period = 1/frequency = 1/100MHz = 10ns

With a 50% duty cycle, clock has to flip a bit after every 5ns.

module clk_gen;
reg clk;
always #5 clk = ~clk;
endmodule

16. Difference between `define and `include.

`define is a compiler directive that substitutes itself in the code with a defined
context. In simple words, wherever macro is used, it is replaced with macro
context and gives compilation error in case of misuse.
The `include is also a compiler directive is used to include another filename. The
double quote “<file_name>” is used in the `include directive. It is widely used to
include library files, and common code instead of pasting the same code
repeatedly.

17. Why always block is not used inside a program block?

The program block is generally used to develop a test case that initiates a stimulus
and then it should end. But the ‘always’ block does not have any provision to end
by itself. Thus, we can not have a program block. Even if you try to do so, a
compilation error is expected.

For a need basic, we can use the ‘forever’ loop as a work-around with a ‘break’
statement to terminate the loop as per requirement.

18. What is FIFO? What are underflow and overflow conditions in FIFO? Write
Verilog code for the design.

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 FIFO stands for first in first out which means that the first element enters into the
buffer and comes out first.
Underflow: When an attempt is made to read data from an empty FIFO, it is called
an underflow. The design should have an ‘empty’ flag to avoid getting invalid
values
Overflow: When an attempt is made to write data into the already full FIFO, it is
called an overflow. The design should have a ‘full’ flag to avoid losing the data
sent from the previous module.

19. What are all different applications of FIFO?

Buffers: To hold data immediately till we get acknowledgment whether previous

data is processed by a design or not.
Clock domain crossing: To exchange data between two systems that work on
different clock frequencies
Ordering requirement in design: FIFO helps to process the data in the required
order which ensures data is not overridden mistakenly. This is very helpful in
microprocessors, and GPU designs, etc.
Pipeline Stages: FIFO makes sure the data flows in different pipeline stages to
process multiple instructions concurrently.

20. What will happen if there is no else part in if-else?

In such a case, the missing ‘else’ (i.e. valid = 0 in the below case) infers to latch in
synthesis.
Example:

always@(*) begin
if(en) begin
data <= 8‘hFF;
end
end

Verilog Interview Questions with Answers 8

 21. Swap register content with and without using an extra register.
Without using an extra register:

always @(posedge clk) begin

m <= n;
n <= m;
end

Using an extra register (in case the interviewer asks):

Here, temp is an extra register used.

always @(posedge clk) begin

temp = n;
n = m;
m = temp;
end

22. What is infer latch means? How can you avoid it?

Infer latch means creating a feedback loop from the output back to the input due
to missing if-else condition or missing ‘default’ in a ‘case’ statement.
Infer latch indicates that the design might not be implemented as intended and
can result in race conditions and timing issues.
How to avoid it?

1. Always use all branches in the ‘if’ and ‘case’ statements.

2. Use default in the ‘case’ statement.

3. Have a proper code review.

4. Use lint tools and logical-equivalence-check tools

23. What is parameter overriding in Verilog?

Verilog Interview Questions with Answers 9

 Verilog parameter is used to pass a constant to the module when it is instantiated.
The parameter value can not be changed at run time.
There are two ways to override the parameters in Verilog

1. During module instantiation

module param_example #(parameter DATA_WIDTH = 8, ID_WIDTH = 3

2) (data, id);
param_example #(4, 16) p2(.data(3), .id(2));

2. Using defparam

defparam p4.DATA_WIDTH = 10;

defparam p4.ID_WIDTH = 16;

24. Write a Verilog code for 5:1 MUX

5:1 MUX selects one out of 5 signals based on 3-bit select input and forwards it to
single-bit output.

module mux_5_1 (input [4:0] i_data, [2:0] sel, output reg ou

t);
always@(*) begin
case(sel)
5'h0: out = i_data[0];
5'h1: out = i_data[1];
5'h2: out = i_data[2];
5'h3: out = i_data[3];
default: out = i_data[4];
endcase
end
endmodule

25. What will be the output of m, n, o if c is the clock?

Verilog Interview Questions with Answers 10

 logic m = c;
reg n = c;
wire o = c;

Since clock c needs to be generated, it has to be of reg type. If we do direct

assignment as above, then m and n will have default values as x and wire o will be
the same as how clock is driven.
But if we do declaration and assignment in the ‘always’ block then m and n can be
driven same as a clock, but ‘o = c’ assignment can not be possible inside ‘always’
block as the ‘o’ variable is a wire type.

26. Difference between dual port ram and FIFO.

Dual Port RAM FIFO

Concurrent access to different FIFO stands for first in first out

memory access for read and write which means that the first element
Functionality
operations without causing enters into the buffer and comes
interference. out first.

It has two separate ports for It has one end for writing into the
Access
read/write simultaneous access. FIFO and another end for reading.

The operation takes care using

The operation takes care using
Control signals signals like Read/Write enable
read/write pointers.
signals.

Useful where simultaneous access Useful as a buffer to exchange

to the memory is required like data between two systems that
Applications
shared memory among processors, work on different clock
GPU, etc frequencies.

27. What Is The Difference Between === And == ?

output of “==” can be 1, 0 or X.

output of “===” can only be 0 or 1.

When you are comparing 2 nos using “==” and if one/both the numbers have one
or more bits as “x” then the output would be “X” . But if use “===” outpout would

Verilog Interview Questions with Answers 11

 be 0 or 1.

e.g A = 3’b1x0
B = 3’b10x
A == B will give X as output.

A === B will give 0 as output.

“==” is used for comparison of only 1’s and 0’s .It can’t compare Xs. If any bit of
the input is X output will be X

“===” is used for comparison of X also.

28. Write A Verilog Code To Swap the Contents Of Two Registers With And
Without A Temporary Register?
With temp reg ;

always @ (posedge clock)

begin
temp=b;
b=a;
a=temp;
end

Without temp reg;

always @ (posedge clock)

begin
a <= b;
b <= a;
end

29. What Is Sensitivity List?

The sensitivity list indicates that when a change occurs to any one of the elements
in the list change, the begin…end statement inside that always block will get

Verilog Interview Questions with Answers 12

 executed.

30. What Is The Difference Between The Following Lines Of Verilog Code?

#5 a = b;
a = #5 b;
#5 a = b;

Wait five-time units before doing the action for “a = b;”.

a = #5 b; The value of b is calculated and stored in an internal temp register,After

five time units, assign this stored value to a.

Verilog Interview Questions with Answers 13