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1. Question 1. Write A Verilog Code To Swap Contents Of Two Registers With

And Without A Temporary Register?
Answer :
With temp reg ;
always @ (posedge clock)
begin 
temp=b;
b=a;
a=temp;
end
Without temp reg;
always @ (posedge clock)
begin 
a <= b;
b <= a;
end 
2. Question 2. Difference Between Task And Function?
Answer :
Function: 
o A function is unable to enable a task however functions can enable other
functions. 
o A function will carry out its required duty in zero simulation time. ( The
program time will not be incremented during the function routine)
o Within a function, no event, delay or timing control statements are
permitted 
o In the invocation of a function their must be at least one argument to be
passed.
o Functions will only return a single value and can not use either output or
inout statements. 
Tasks: 
o Tasks are capable of enabling a function as well as enabling other
versions of a Task 
o Tasks also run with a zero simulation however they can if required be
executed in a non zero simulation time. 
o Tasks are allowed to contain any of these statements. 
 o A task is allowed to use zero or more arguments which are of type
output, input or inout. 
o A Task is unable to return a value but has the facility to pass multiple
values via the output and inout statements . 
Perl Scripting Interview Questions
3. Question 3. Difference Between Inter Statement And Intra Statement Delay?
Answer :
//define register variables
reg a, b, c;
//intra assignment delays
initial
begin
a = 0; c = 0;
b = #5 a + c; //Take value of a and c at the time=0, evaluate
//a + c and then wait 5 time units to assign value
//to b.
end 
//Equivalent method with temporary variables and regular delay control
initial
begin
a = 0; c = 0;
temp_ac = a + c;
#5 b = temp_ac; //Take value of a + c at the current time and
//store it in a temporary variable. Even though a and c
//might change between 0 and 5,
//the value assigned to b at time 5 is unaffected.
end
4. Question 4. Difference Between $monitor,$display & $strobe?
Answer :
These commands have the same syntax, and display text on the screen during
simulation. They are much less convenient than waveform display tools like
cwaves?. $display and $strobe display once every time they are executed, whereas
$monitor displays every time one of its parameters changes. 
The difference between $display and $strobe is that $strobe displays the parameters
at the very end of the current simulation time unit rather than exactly where it is
executed. The format string is like that in C/C++, and may contain format characters.
Format characters include %d (decimal), %h (hexadecimal), %b (binary), %c
(character), %s (string) and %t (time), %m (hierarchy level). %5d, %5b etc. would give
 exactly 5 spaces for the number instead of the space needed. Append b, h, o to the
task name to change default format to binary, octal or hexadecimal. 
Syntax:
$display (“format_string”, par_1, par_2, ... );
$strobe (“format_string”, par_1, par_2, ... );
$monitor (“format_string”, par_1, par_2, ... );
Perl Scripting Tutorial
5. Question 5. What Is Difference Between Verilog Full Case And Parallel Case?
Answer :
A "full" case statement is a case statement in which all possible case-expression
binary patterns can be matched to a case item or to a case default. If a case
statement does not include a case default and if it is possible to find a binary case
expression that does not match any of the defined case items, the case statement is
not "full." 
A "parallel" case statement is a case statement in which it is only possible to match a
case expression to one and only one case item. If it is possible to find a case
expression that would match more than one case item, the matching case items are
called "overlapping" case items and the case statement is not "parallel." 

Shell Scripting Interview Questions

6. Question 6. What Is Meant By Inferring Latches,how To Avoid It?
Answer :
Consider the following : 
always @(s1 or s0 or i0 or i1 or i2 or i3)
case ({s1, s0}) 
2'd0 : out = i0;
2'd1 : out = i1;
2'd2 : out = i2;
endcase
in a case statement if all the possible combinations are not compared and default is
also not specified like in example above a latch will be inferred ,a latch is inferred
because to reproduce the previous value when unknown branch is specified. 
For example in above case if {s1,s0}=3 , the previous stored value is reproduced for
this storing a latch is inferred. 
The same may be observed in IF statement in case an ELSE IF is not specified. 
To avoid inferring latches make sure that all the cases are mentioned if not default
condition is provided. 
7. Question 7. Tell Me How Blocking And Non Blocking Statements Get
Executed?
Answer :
Execution of blocking assignments can be viewed as a one-step process:
1. Evaluate the RHS (right-hand side equation) and update the LHS (left-hand side
expression) of the blocking assignment without interruption from any other Verilog
statement. A blocking assignment "blocks" trailing assignments in the same always
block from occurring until after the current assignment has been completed 
Execution of nonblocking assignments can be viewed as a two-step process: 
o Evaluate the RHS of nonblocking statements at the beginning of the time
step.
o Update the LHS of nonblocking statements at the end of the time step. 
Shell Scripting Tutorial   System Administration Interview Questions
o Question 8. Variable And Signal Which Will Be Updated First?
Answer :
Signals
o Question 9. What Is Sensitivity List?
Answer :
The sensitivity list indicates that when a change occurs to any one of elements in the
list change, begin…end statement inside that always block will get executed.

System Verilog Interview Questions

o Question 10. In A Pure Combinational Circuit Is It Necessary To
Mention All The Inputs In Sensitivity Disk? If Yes, Why?
Answer :
Yes in a pure combinational circuit is it necessary to mention all the inputs in
sensitivity disk other wise it will result in pre and post synthesis mismatch. 

VLSI Design Tutorial

o Question 11. Tell Me Structure Of Verilog Code You Follow?
Answer :
A good template for your Verilog file is shown below. 
// timescale directive tells the simulator the base units and precision of the
simulation 
`timescale 1 ns / 10 ps 
module name (input and outputs); 
// parameter declarations 
parameter parameter_name = parameter value; 
 // Input output declarations 
input in1; 
input in2; // single bit inputs 
output [msb:lsb] out; // a bus output 
// internal signal register type declaration - register types (only assigned within
always statements). reg register
variable 1; 
reg [msb:lsb] register variable 2; 
// internal signal. net type declaration - (only assigned outside always statements)
wire net variable 1; 
// hierarchy - instantiating another module 
reference name instance name ( 
.pin1 (net1), 
.pin2 (net2), 
. 
.pinn (netn) 
); 
// synchronous procedures 
always @ (posedge clock) 
begin 
. 
end 
// combinatinal procedures 
always @ (signal1 or signal2 or signal3) 
begin 
. 
end 
assign net variable = combinational logic; 
endmodule 
VHDL Interview Questions
o Question 12. Difference Between Verilog And Vhdl?
Answer :
Compilation
VHDL. Multiple design-units (entity/architecture pairs), that reside in the same
system file, may be separately compiled if so desired. However, it is good design
practice to keep each design unit in it's own system file in which case separate
compilation should not be an issue. 
Verilog. The Verilog language is still rooted in it's native interpretative mode.
Compilation is a means of speeding up simulation, but has not changed the original
 nature of the language. As a result care must be taken with both the compilation
order of code written in a single file and the compilation order of multiple files.
Simulation results can change by simply changing the order of compilation. 
Data types 
VHDL. A multitude of language or user defined data types can be used. This may
mean dedicated conversion functions are needed to convert objects from one type to
another. The choice of which data types to use should be considered wisely,
especially enumerated (abstract) data types. This will make models easier to write,
clearer to read and avoid unnecessary conversion functions that can clutter the code.
VHDL may be preferred because it allows a multitude of language or user defined
data types to be used. 
Verilog. Compared to VHDL, Verilog data types a re very simple, easy to use and very
much geared towards modeling hardware structure as opposed to abstract hardware
modeling. Unlike VHDL, all data types used in a Verilog model are defined by the
Verilog language and not by the user. There are net data types, for example wire, and
a register data type called reg. A model with a signal whose type is one of the net
data types has a corresponding electrical wire in the implied modeled circuit.
Objects, that is signals, of type reg hold their value over simulation delta cycles and
should not be confused with the modeling of a hardware register. Verilog may be
preferred because of it's simplicity. 
Design reusability 
VHDL. Procedures and functions may be placed in a package so that they are avail
able to any design-unit that wishes to use them. 
Verilog. There is no concept of packages in Verilog. Functions and procedures used
within a model must be defined in the module. To make functions and procedures
generally accessible from different module statements the functions and procedures
must be placed in a separate system file and included using the `include compiler
directive. 

Perl Scripting Interview Questions

o Question 13. Can You Tell Me Some Of System Tasks And Their
Purpose?
Answer :
$display, $displayb, $displayh, $displayo, $write, $writeb, $writeh, $writeo. 
The most useful of these is $display.This can be used for displaying strings,
expression or values of variables. 
Here are some examples of usage. 
 $display("Hello oni");
--- output: Hello oni
$display($time) // current simulation time.
--- output: 460
counter = 4'b10;
$display(" The count is %b", counter);
--- output: The count is 0010
$reset resets the simulation back to time 0; $stop halts the simulator and puts it in
interactive mode where the user can enter commands; $finish exits the simulator
back to the operating system
o Question 14. Can You List Out Some Of Enhancements In Verilog 2001?
Answer :
In earlier version of Verilog ,we use 'or' to specify more than one element in
sensitivity list . In Verilog 2001, we can use comma as shown in the example below.
// Verilog 2k example for usage of comma
always @ (i1,i2,i3,i4)
Verilog 2001 allows us to use star in sensitive list instead of listing all the variables in
RHS of combo logics . This removes typo mistakes and thus avoids simulation and
synthesis mismatches,  Verilog 2001 allows port direction and data type in the port
list of modules as shown in the example below
module memory (
input r,
input wr,
input [7:0] data_in,
input [3:0] addr,
output [7:0] data_out
);
o Question 15. Write A Verilog Code For Synchronous And Asynchronous
Reset?
Answer :
Synchronous reset, synchronous means clock dependent so reset must not be
present in sensitivity disk
eg: always @ (posedge clk )
begin if (reset)
. . . end
Asynchronous means clock independent so reset must be present in sensitivity list.
Eg: Always @(posedge clock or posedge reset)
 begin
if (reset)
. . . end
VLSI Interview Questions
o Question 16. What Is Pli?why Is It Used?
Answer :
Programming Language Interface (PLI) of Verilog HDL is a mechanism to interface
Verilog programs with programs written in C language. It also provides mechanism
to access internal databases of the simulator from the C program. 
PLI is used for implementing system calls which would have been hard to do
otherwise (or impossible) using Verilog syntax. Or, in other words, you can take
advantage of both the paradigms - parallel and hardware related features of Verilog
and sequential flow of C - using PLI. 
o Question 17. There Is A Triangle And On It There Are 3 Ants One On
Each Corner And Are Free To Move Along Sides Of Triangle What Is Probability That
They Will Collide?
Answer :
Ants can move only along edges of triangle in either of direction, let’s say one is
represented by 1 and another by 0, since there are 3 sides eight combinations are
possible, when all ants are going in same direction they won’t collide that is 111 or
000 so probability of not collision is 2/8=1/4 or collision probability is 6/8=3/4

Ethernet Interview Questions

o Question 18. How To Write Fsm Is Verilog?
Answer :
there r mainly 4 ways 2 write fsm code
o using 1 process where all input decoder, present state, and output
decoder r combine in one process.
o using 2 process where all comb ckt and sequential ckt separated in
different process
o using 2 process where input decoder and persent state r combine and
output decoder seperated in other process
o using 3 process where all three, input decoder, present state and output
decoder r separated in 3 process. 
Shell Scripting Interview Questions
o Question 19. What Is Difference Between Freeze Deposit And Force?
Answer :
 $deposit(variable, value);
This system task sets a Verilog register or net to the specified value. variable is the
register or net to be changed; value is the new value for the register or net. The value
remains until there is a subsequent driver transaction or another $deposit task for
the same register or net. This system task operates identically to the ModelSim force
-deposit command.
The force command has -freeze, -drive, and -deposit options. When none of these is
specified, then -freeze is assumed for unresolved signals and -drive is assumed for
resolved signals. This is designed to provide compatibility with force files. But if you
prefer -freeze as the default for both resolved and unresolved signals. 
o Question 20. Will Case Infer Priority Register If Yes How Give An
Example?
Answer :
yes case can infer priority register depending on coding style
reg r; 
// Priority encoded mux, 
always @ (a or b or c or select2) 
begin 
r = c; 
case (select2) 
2'b00: r = a; 
2'b01: r = b; 
endcase 
end 
Advanced C++ Interview Questions
o Question 21. Given The Following Verilog Code, What Value Of "a" Is
Displayed?
Answer :
always @(clk) begin
a = 0;
a <= 1;
$display(a);
end
This is a tricky one! Verilog scheduling semantics basically imply a four-level deep
queue for the current simulation time:
o Active Events (blocking statements)
o Inactive Events (#0 delays, etc)
o Non-Blocking Assign Updates (non-blocking statements)
 o Monitor Events ($display, $monitor, etc).
Since the "a = 0" is an active event, it is scheduled into the 1st "queue".
The "a <= 1" is a non-blocking event, so it's placed into the 3rd queue.
Finally, the display statement is placed into the 4th queue. Only events in the active
queue are completed this sim cycle, so the "a = 0" happens, and then the display
shows a = 0. If we were to look at the value of a in the next sim cycle, it would show
1. 
o Question 22. What Is The Difference Between The Following Two Lines
Of Verilog Code?
Answer :
#5 a = b;
a = #5 b;
#5 a = b;
Wait five time units before doing the action for "a = b;". 
a = #5 b; The value of b is calculated and stored in an internal temp register,After five
time units, assign this stored value to a. 
o Question 23. What Does `timescale 1 Ns/ 1 Ps Signify In A Verilog
Code?
Answer :
'timescale directive is a compiler directive.It is used to measure simulation time or
delay time. Usage :`timescale / reference_time_unit : Specifies the unit of
measurement for times and delays. time_precision: specifies the precision to which
the delays are rounded off. 

Basic C Interview Questions

o Question 24. What Is The Difference Between === And == ?
Answer :
output of "==" can be 1, 0 or X.
output of "===" can only be 0 or 1.
When you are comparing 2 nos using "==" and if one/both the numbers have one or
more bits as "x" then the output would be "X" . But if use "===" outpout would be 0 or
1.
e.g A = 3'b1x0
B = 3'b10x
A == B will give X as output.
A === B will give 0 as output.
"==" is used for comparison of only 1's and 0's .It can't compare Xs. If any bit of the
input is X output will be X
 "===" is used for comparison of X also.
o Question 25. How To Generate Sine Wav Using Verilog Coding Style?
Answer :
The easiest and efficient way to generate sine wave is using CORDIC Algorithm. 
o Question 26. What Is The Difference Between Wire And Reg?
Answer :
(wire,tri)Physical connection between structural elements. Value assigned by a
continuous assignment or a gate output. Register type: (reg, integer, time, real, real
time) represents abstract data storage element. Assigned values only within an
always statement or an initial statement. The main difference between wire and reg
is wire cannot hold (store) the value when there no connection between a and b like
a->b, if there is no connection in a and b, wire loose value. But reg can hold the value
even if there in no connection. Default values:wire is Z,reg is x. 
o Question 27. How Do You Implement The Bi-directional Ports In Verilog
Hdl?
Answer :
module bidirec (oe, clk, inp, outp, bidir);
// Port Declaration
input oe;
input clk;
input [7:0] inp;
output [7:0] outp;
inout [7:0] bidir; 
reg [7:0] a;
reg [7:0] b;
assign bidir = oe ? a : 8'bZ ;
assign outp = b;
// Always Construct
always @ (posedge clk)
begin
b <= bidir;
a <= inp;
end
endmodule

o Question 28. What Is Verilog Case (1) ?

Answer :
wire [3:0] x;
always @(...) begin
 case (1'b1)
x[0]: SOMETHING1;
x[1]: SOMETHING2;
x[2]: SOMETHING3;
x[3]: SOMETHING4;
endcase
end
The case statement walks down the list of cases and executes the first one that
matches. So here, if the lowest 1-bit of x is bit 2, then something3 is the statement
that will get executed (or selected by the logic). 
o Question 29. Why Is It That "if (2'b01 & 2'b10)..." Doesn't Run The True
Case?
Answer :
This is a popular coding error. You used the bit wise AND operator (&) where you
meant to use the logical AND operator (&&). 

o Question 30. What Are Different Types Of Verilog Simulators ?

Answer :
There are mainly two types of simulators available. 
o Event Driven 
o Cycle Based 
Event-based Simulator: 
This Digital Logic Simulation method sacrifices performance for rich functionality:
every active signal is calculated for every device it propagates through during a clock
cycle. Full Event-based simulators support 4-28 states; simulation of Behavioral HDL,
RTL HDL, gate, and transistor representations; full timing calculations for all devices;
and the full HDL standard. Event-based simulators are like a Swiss Army knife with
many different features but none are particularly fast. 
Cycle Based Simulator: 
This is a Digital Logic Simulation method that eliminates unnecessary calculations to
achieve huge performance gains in verifying Boolean logic: 
o Results are only examined at the end of every clock cycle; and 
o The digital logic is the only part of the design simulated (no timing
calculations). By limiting the calculations, Cycle based Simulators can
provide huge increases in performance over conventional Event-based
simulators. 
Cycle based simulators are more like a high speed electric carving knife in
comparison because they focus on a subset of the biggest problem: logic
verification. 
 Cycle based simulators are almost invariably used along with Static Timing verifier to
compensate for the lost timing information coverage. 

Q1. What Is Difference Between Verilog Full Case And Parallel Case?
A “full” case statement is a case statement in which all possible case-expression binary
patterns can be matched to a case item or to a case default. If a case statement does not
include a case default and if it is possible to find a binary case expression that does not
match any of the defined case items, the case statement is not “full.”
A “parallel” case statement is a case statement in which it is only possible to match a case
expression to one and only one case item. If it is possible to find a case expression that
would match more than one case item, the matching case items are called “overlapping”
case items and the case statement is not “parallel.”
Q2. What Is Pli?why Is It Used?
Programming Language Interface (PLI) of Verilog HDL is a mechanism to interface Verilog
programs with programs written in C language. It also provides mechanism to access
internal databases of the simulator from the C program.
PLI is used for implementing system calls which would have been hard to do otherwise (or
impossible) using Verilog syntax. Or, in other words, you can take advantage of both the
paradigms – parallel and hardware related features of Verilog and sequential flow of C –
using PLI.
Q3. Difference Between $monitor,$display & $strobe?
These commands have the same syntax, and display text on the screen during simulation.
They are much less convenient than waveform display tools like cwaves?. $display and
$strobe display once every time they are executed, whereas $monitor displays every time
one of its parameters changes.
The difference between $display and $strobe is that $strobe displays the parameters at the
very end of the current simulation time unit rather than exactly where it is executed. The
format string is like that in C/C++, and may contain format characters. Format characters
include %d (decimal), %h (hexadecimal), %b (binary), %c (character), %s (string) and %t
(time), %m (hierarchy level). %5d, %5b etc. would give exactly 5 spaces for the number
instead of the space needed. Append b, h, o to the task name to change default format to
binary, octal or hexadecimal.
Q4. Variable And Signal Which Will Be Updated First?
Signals
Q5. What Is Sensitivity List?
The sensitivity list indicates that when a change occurs to any one of elements in the list
change, begin…end statement inside that always block will get executed.
Q6. In A Pure Combinational Circuit Is It Necessary To Mention All The Inputs In Sensitivity
Disk? If Yes, Why?
Yes in a pure combinational circuit is it necessary to mention all the inputs in sensitivity disk
other wise it will result in pre and post synthesis mismatch.
 Q7. Write A Verilog Code To Swap Contents Of Two Registers With And Without A
Temporary Register?
With temp reg ;
always @ (posedge clock)
begin
temp=b;
b=a;
a=temp;
end
Without temp reg;
always @ (posedge clock)
begin
a <= b;
b <= a;
end
Q8. Difference Between Task And Function?
Function: 
 A function is unable to enable a task however functions can enable other functions.

 A function will carry out its required duty in zero simulation time. ( The program time will not be
incremented during the function routine)

 Within a function, no event, delay or timing control statements are permitted

 In the invocation of a function their must be at least one argument to be passed.

 Functions will only return a single value and can not use either output or inout statements.
Tasks: 
 Tasks are capable of enabling a function as well as enabling other versions of a Task

 Tasks also run with a zero simulation however they can if required be executed in a non zero
simulation time.

 Tasks are allowed to contain any of these statements.

 A task is allowed to use zero or more arguments which are of type output, input or inout.

 A Task is unable to return a value but has the facility to pass multiple values via the output and inout
statements .
Q9. Difference Between Inter Statement And Intra Statement Delay?
//define register variables
reg a, b, c;
//intra assignment delays
initial
begin
a = 0; c = 0;
b = #5 a + c; //Take value of a and c at the time=0, evaluate
//a + c and then wait 5 time units to assign value
//to b.
end
//Equivalent method with temporary variables and regular delay control
initial
begin
a = 0; c = 0;
temp_ac = a + c;
#5 b = temp_ac; //Take value of a + c at the current time and
//store it in a temporary variable. Even though a and c
//might change between 0 and 5,
//the value assigned to b at time 5 is unaffected.
end
Syntax:

$display (“format_string”, par_1, par_2, … );

$strobe (“format_string”, par_1, par_2, … );
$monitor (“format_string”, par_1, par_2, … );
Q10. What Is Difference Between Freeze Deposit And Force?
$deposit(variable, value);
This system task sets a Verilog register or net to the specified value. variable is the register
or net to be changed; value is the new value for the register or net. The value remains until
there is a subsequent driver transaction or another $deposit task for the same register or
net. This system task operates identically to the ModelSim force -deposit command.

The force command has -freeze, -drive, and -deposit options. When none of these is
specified, then -freeze is assumed for unresolved signals and -drive is assumed for
resolved signals. This is designed to provide compatibility with force files. But if you prefer
-freeze as the default for both resolved and unresolved signals.

Q11. What Is Meant By Inferring Latches,how To Avoid It?

Consider the following :
always @(s1 or s0 or i0 or i1 or i2 or i3)
case ({s1, s0})
2’d0 : out = i0;
2’d1 : out = i1;
2’d2 : out = i2;
endcase
in a case statement if all the possible combinations are not compared and default is also not
specified like in example above a latch will be inferred ,a latch is inferred because to
reproduce the previous value when unknown branch is specified.
For example in above case if {s1,s0}=3 , the previous stored value is reproduced for this
storing a latch is inferred.
The same may be observed in IF statement in case an ELSE IF is not specified.
To avoid inferring latches make sure that all the cases are mentioned if not default condition
is provided.
Q12. Tell Me How Blocking And Non Blocking Statements Get Executed?
Execution of blocking assignments can be viewed as a one-step process:
1. Evaluate the RHS (right-hand side equation) and update the LHS (left-hand side
expression) of the blocking assignment without interruption from any other Verilog
statement. A blocking assignment “blocks” trailing assignments in the same always block
from occurring until after the current assignment has been completed

1. Execution of nonblocking assignments can be viewed as a two-step process:

1. Evaluate the RHS of nonblocking statements at the beginning of the time step.

2. Update the LHS of nonblocking statements at the end of the time step.
 

Q13. Tell Me Structure Of Verilog Code You Follow?

A good template for your Verilog file is shown below.
// timescale directive tells the simulator the base units and precision of the simulation
`timescale 1 ns / 10 ps
module name (input and outputs);
// parameter declarations
parameter parameter_name = parameter value;
// Input output declarations
input in1;
input in2; // single bit inputs
output [msb:lsb] out; // a bus output
// internal signal register type declaration – register types (only assigned within always
statements). reg register
variable 1;
reg [msb:lsb] register variable 2;
// internal signal. net type declaration – (only assigned outside always statements) wire net
variable 1;
// hierarchy – instantiating another module
reference name instance name (
.pin1 (net1),
.pin2 (net2),
.
.pinn (netn)
);
// synchronous procedures
always @ (posedge clock)
begin
.
end
// combinatinal procedures
always @ (signal1 or signal2 or signal3)
begin
.
end
assign net variable = combinational logic;
endmodule
Q14. Difference Between Verilog And Vhdl?
Compilation
VHDL. Multiple design-units (entity/architecture pairs), that reside in the same system file,
may be separately compiled if so desired. However, it is good design practice to keep each
design unit in it’s own system file in which case separate compilation should not be an
issue.
Verilog. The Verilog language is still rooted in it’s native interpretative mode. Compilation is
a means of speeding up simulation, but has not changed the original nature of the
language. As a result care must be taken with both the compilation order of code written in
a single file and the compilation order of multiple files. Simulation results can change by
simply changing the order of compilation.

Data types 
VHDL. A multitude of language or user defined data types can be used. This may mean
dedicated conversion functions are needed to convert objects from one type to another. The
choice of which data types to use should be considered wisely, especially enumerated
(abstract) data types. This will make models easier to write, clearer to read and avoid
unnecessary conversion functions that can clutter the code. VHDL may be preferred
because it allows a multitude of language or user defined data types to be used.
Verilog. Compared to VHDL, Verilog data types a re very simple, easy to use and very
much geared towards modeling hardware structure as opposed to abstract hardware
modeling. Unlike VHDL, all data types used in a Verilog model are defined by the Verilog
language and not by the user. There are net data types, for example wire, and a register
data type called reg. A model with a signal whose type is one of the net data types has a
corresponding electrical wire in the implied modeled circuit. Objects, that is signals, of type
reg hold their value over simulation delta cycles and should not be confused with the
modeling of a hardware register. Verilog may be preferred because of it’s simplicity.

Design reusability 
VHDL. Procedures and functions may be placed in a package so that they are avail able to
any design-unit that wishes to use them.

Verilog. There is no concept of packages in Verilog. Functions and procedures used within
a model must be defined in the module. To make functions and procedures generally
accessible from different module statements the functions and procedures must be placed
in a separate system file and included using the `include compiler directive.

Q15. Can You List Out Some Of Enhancements In Verilog 2001?

In earlier version of Verilog ,we use ‘or’ to specify more than one element in sensitivity list .
In Verilog 2001, we can use comma as shown in the example below.
// Verilog 2k example for usage of comma
always @ (i1,i2,i3,i4)
Verilog 2001 allows us to use star in sensitive list instead of listing all the variables in RHS
of combo logics . This removes typo mistakes and thus avoids simulation and synthesis
mismatches,  Verilog 2001 allows port direction and data type in the port list of modules as
shown in the example below

module memory (
input r,
input wr,
input [7:0] data_in,
input [3:0] addr,
output [7:0] data_out
);
Q16. How To Write Fsm Is Verilog?
there r mainly 4 ways 2 write fsm code
1. using 1 process where all input decoder, present state, and output decoder r combine in one process.

2. using 2 process where all comb ckt and sequential ckt separated in different process

3. using 2 process where input decoder and persent state r combine and output decoder seperated in other
process

4. using 3 process where all three, input decoder, present state and output decoder r separated in 3
process.
Q17. Write A Verilog Code For Synchronous And Asynchronous Reset?
Synchronous reset, synchronous means clock dependent so reset must not be present in
sensitivity disk
eg: always @ (posedge clk )

begin if (reset)
. . . end
Asynchronous means clock independent so reset must be present in sensitivity list.

Eg: Always @(posedge clock or posedge reset)

begin
if (reset)
. . . end
Q18. There Is A Triangle And On It There Are 3 Ants One On Each Corner And Are Free To
Move Along Sides Of Triangle What Is Probability That They Will Collide?
Ants can move only along edges of triangle in either of direction, let’s say one is
represented by 1 and another by 0, since there are 3 sides eight combinations are possible,
when all ants are going in same direction they won’t collide that is 111 or 000 so probability
of not collision is 2/8=1/4 or collision probability is 6/8=3/4
Q19. What Does `timescale 1 Ns/ 1 Ps Signify In A Verilog Code?
‘timescale directive is a compiler directive.It is used to measure simulation time or delay
time. Usage :`timescale / reference_time_unit : Specifies the unit of measurement for times
and delays. time_precision: specifies the precision to which the delays are rounded off.
Q20. What Is The Difference Between === And == ?
output of “==” can be 1, 0 or X.
output of “===” can only be 0 or 1.
When you are comparing 2 nos using “==” and if one/both the numbers have one or more
bits as “x” then the output would be “X” . But if use “===” outpout would be 0 or 1.

e.g A = 3’b1x0
B = 3’b10x
A == B will give X as output.
A === B will give 0 as output.
 “==” is used for comparison of only 1’s and 0’s .It can’t compare Xs. If any bit of the input is
X output will be X

“===” is used for comparison of X also.

Q21. Will Case Infer Priority Register If Yes How Give An Example?
yes case can infer priority register depending on coding style
reg r;
// Priority encoded mux,
always @ (a or b or c or select2)
begin
r = c;
case (select2)
2’b00: r = a;
2’b01: r = b;
endcase
end
Q22. Given The Following Verilog Code, What Value Of “a” Is Displayed?
always @(clk) begin
a = 0;
a <= 1;
$display(a);
end
This is a tricky one! Verilog scheduling semantics basically imply a four-level deep queue
for the current simulation time:

1. Active Events (blocking statements)

2. Inactive Events (#0 delays, etc)

3. Non-Blocking Assign Updates (non-blocking statements)

4. Monitor Events ($display, $monitor, etc).

Since the “a = 0” is an active event, it is scheduled into the 1st “queue”.

The “a <= 1” is a non-blocking event, so it’s placed into the 3rd queue.

Finally, the display statement is placed into the 4th queue. Only events in the active queue
are completed this sim cycle, so the “a = 0” happens, and then the display shows a = 0. If
we were to look at the value of a in the next sim cycle, it would show 1.

Q23. Why Is It That “if (2’b01 & 2’b10)…” Doesn’t Run The True Case?
This is a popular coding error. You used the bit wise AND operator (&) where you meant to
use the logical AND operator (&&).
Q24. What Are Different Types Of Verilog Simulators ?
There are mainly two types of simulators available.
 Event Driven

 Cycle Based
Q25. What Is The Difference Between The Following Two Lines Of Verilog Code?
#5 a = b;
a = #5 b;
#5 a = b;
Wait five time units before doing the action for “a = b;”.

a = #5 b; The value of b is calculated and stored in an internal temp register,After five time
units, assign this stored value to a.

Q26. How To Generate Sine Wav Using Verilog Coding Style?

The easiest and efficient way to generate sine wave is using CORDIC Algorithm.
Q27. What Is The Difference Between Wire And Reg?
(wire,tri)Physical connection between structural elements. Value assigned by a continuous
assignment or a gate output. Register type: (reg, integer, time, real, real time) represents
abstract data storage element. Assigned values only within an always statement or an initial
statement. The main difference between wire and reg is wire cannot hold (store) the value
when there no connection between a and b like a->b, if there is no connection in a and b,
wire loose value. But reg can hold the value even if there in no connection. Default
values:wire is Z,reg is x

1. When would you use blocking vs non-blocking assignments when coding sequential
logic?

2. A lot of designers like to use a #1 when coding flip-flops (sequential logic). What
purpose does it serve? Why should you use #1 or not?

3. What is the difference between at task and a function? When would use one vs the
other?

4. Can you develop a flip flop model using Verilog's specify statements? When would
you use Verilog's specify statement? What advantage does it have?

5. How does one handle tri-state logic? What Verilog primitives support it? How does
one model various levels of drive strength?

6. When would you use a casex vs a casez statement?

7. When using one of the case, casex, casez, variation, when would you use a // synopsys
parallel_case full_case directive? What does it do?

8. Should your Verilog case statement always include a "default" case? If yes, why? If
not, why not?

9. Suppose a part of your logic has 50 instances of a module. Do you cut and paste it or
generate the logic? If you are going to generate it, what tools do you use?
10. When running gate-level simulation, the output of a block is generating an "X". How
do you debug it? What could be causing the "X"?

 Execution of blocking and non-blocking assignments in Verilog ?

Explain it by examples,
 What is the race condition in verilog ? when it will occur ? and how do you
solve it ?
 What are the inter and intra delays in Verilog ?
 How do you swap two numbers with reduced register in Verilog ?
 How do you generate clock in verilog ?
 Difference between “==” and “===” operator in Verilog ?
 What is continuous assign statement in Verilog ? and when do you use ?
 What is fork-join in Verilog ?
 What is tasks & functions in Verilog ?
 What you will do, when you have to instantiate the module for multiple
times in Verilog ?
 In which condition, the latch will get inferred in Verilog ?