MP2825GQKT

MPS Confidential - For Quanta Use Only
MP2825
3 Rails, 8 Phases
SVI3 Controller for AMD Core
PRELIMINARY SPECIFICATIONS SUBJECT TO CHANGE
DESCRIPTION FEATURES
The MP2825 is a 3-rail, digital, multi-phase  Up to 8-Phase, 3-Output, Digital Controller
controller that provides power for SVI3 AMD for AMD SVI3 Vcore Power
core power. The MP2825 can work with MPS’s  I2CBus Communication Interface
Intelli-Phase products to complete the  SVI3 Interface
multiphase voltage regulator (VR) solution with  Rail3 SVI3 Type 2 Supporting
minimum external components. The MP2825  Built-In NVM to Store Configurations
rail/phase combination can be configured  Switching Frequency 200kHz to 2MHz
flexibly.  Automatic Loop Compensation
The MP2825 provides an on-chip NVM to store  Flexible Phase Assignment for 3 Rails
and restore device configurations. Device  Auto-Phase Shedding to Improve Overall
configurations and fault parameters can be Efficiency
easily programmed or monitored via the  Phase-to-Phase Active Current Balancing
I2CBus/I2C interface. The MP2825 can monitor with Programmable Offsets for Thermal
and report output current by sensing the CS Balance
output of Intelli-Phase devices.  Input and Output Voltage, Current and
Power Monitoring
The MP2825 is based on a unique, digital,
 Separate EN/PG/TEMP Sense
multi-phase, nonlinear control to provide a fast
transient response to the load transient with  VIN UVLO, Output OVP/UVP, OCP, OTP
minimum value of output capacitors. With only with No Action, or Latch-off
one power-loop control method for both steady  Per Phase OCL and UCL
state and load transient, the power loop  Digital Load-Line Regulation
compensation is very easy to configure.  RoHS Compliant Super Small TQFN-52
(6mmx6mm) Package
The MP2825 also provides active current
balancing and auto-phase shedding for better APPLICATIONS
thermal and efficiency performance. MP2825  AMD SVI3 Vcore Power
includes input and output voltage, output  Telecom and Networking Systems
current (IMON), temperature monitoring with All MPS parts are lead-free, halogen-free, and adhere to the RoHS directive.
selectable protection functions, and For MPS green status, please visit the MPS website under Quality
Assurance. “MPS”, the MPS logo, and “Simple, Easy Solutions” are
programmable load line for each rail. trademarks of Monolithic Power Systems, Inc. or its subsidiaries.
MP2825 Rev. 0.8 MonolithicPower.com 1

11/17/2023 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
Preliminary Specifications Subject to Change © 2023 MPS. All Rights Reserved.
MP2825 – DIGITAL AMD SVI3 CONTROLLER WITH I2C
TYPICAL APPLICATION
+3.3V VIN
VDRV
+3.3V AGND
VDD33
VIN GND
VINSEN
EN1
+3.3V VIN
EN2 VDRV
EN3
AGND
VDDIO
SVTI
SVTO
SVD
SVI3
SVC
OCP_L
RESET_L
+3.3V VIN
PGD1
VDRV
PGD2
AGND
PGD3
I2CBus SCL
SDA
VDD18
ADDR
PSYS/ISYS

ORDERING INFORMATION
Part Number* Package Top Marking MSL Rating
MP2825GQKT-003C** TQFN-52 (6mmx6mm) See Below 3
* For Tape & Reel, add suffix -Z (e.g.: MP2825GQKT-003C-Z).
** “003C” is the configuration code identifier for the register settings stored in the MTP. To create a unique value
for this code, please contact an MPS FAE.
TOP MARKING
MPS: MPS prefix

YY: Year code
WW: Week code
MP2825: Part number
LLLLLLLLL: Lot number
PACKAGE REFERENCE
TOP VIEW
PSYS/ISYS
VOSEN3
VORTN3
VOSEN2
VORTN2
VINSEN
TEMP1
TEMP2
TEMP3
VDD18
VDD33
PWM8
CS8
52 51 40
PWM7 1 39 CS7
PWM6 2 38 CS6
PWM5 3 37 CS5
PWM4 4 36 CS4
PWM3 5 35 CS3
PWM2
PWM1
6
7
PAD 34
33
CS2
CS1
OCP_L 8 AGND 32 VORTN1
SDA 9 31 VOSEN1
SCL 10 30 EN1
ADDR 11 29 SVTI
EN3 12 28 SVTO
PGD3 13 27 SVC
14 15 16 17 18 19 20 21 22 23 24 25 26
VDDIO
NC
NC
NC
NC
SVD
EN2
PGD2
STB1
STB2
STB3
RESET_L
PGD1
TQFN-52 (6mmx6mm)

PIN FUNCTIONS
Package
Name Type Description
Pin #
Phase 7 PWM outputs. Each output is connected to the PWM input of the
1 PWM7 D [O]
Intelli-Phase. Float PWM pin of the unused phase.
2 PWM6 D [O]
3 PWM5 D [O]
4 PWM4 D [O]
5 PWM3 D [O]
6 PWM2 D [O]
7 PWM1 D [O]
Open-drain OCP_L output. OCP_L is the voltage regulator’s over-current
8 OCP_L D [O]
warning indicator. Active low.
9 SDA D [I/O] I2C interface Data line.
10 SCL D [I] I2C interface Clock line.
I2C slave address programming pin. Connect ADDR_P pin to VDD18 pin
11 ADDR A [I]
through a resistor divider.
12 EN3 D [I] Enable signal input of Rail 3.
13 PGD3 D [O] Power-Good signal output of Rail 3. Open-drain output.
14 EN2 D [I] Enable signal input of Rail 2.
D/A Pins for vendor’s preferred use. Expected use: Capacitor or resistor to
16-19 NC
[I/O] ground.
20 STB1 D [O] Standby signal output of Rail 1.
Reset input of the SVI3 interface. Reset all SVI3 state machines and SVI3-
23 RESET_L D [I]
defined registers to default states. Active low.
Input power of SVI3 interface. Serve as the reference for SVC, SVD, SVTI
24 VDDIO A [I]
and SVTO. Bypass this pin with 1uF MLCC.
26 SVD D [I] Command data input of SVI3 interface.
27 SVC D [I] Clock input of SVI3 interface.
28 SVTO D [O] Telemetry data output of SVI3 interface.
29 SVTI D [I] Telemetry data input of SVI3 interface.
30 EN1 D [I] Enable signal input for Rail 1.
Positive remote voltage sense input of Rail 1. VOSEN1 is connected directly
31 VOSEN1 A [I] to the VR output voltage at the load and should be routed differentially with
VORTN1.
Remote voltage sensing return input of Rail 1. VORTN1 is connected
32 VORTN1 A [I]
directly to ground at the load and should be routed differentially with VOSEN1.

PIN FUNCTIONS (continued)
Package
Name Type Description
Pin #
33 CS1 A [I]
Phase 1 current sensing input. Float CS pin of the unused phase.
34 CS2 A [I]
35 CS3 A [I]
36 CS4 A [I]
37 CS5 A [I]
38 CS6 A [I]
39 CS7 A [I]
40 CS8 A [I]
41 VORTN2 A [I]
VORTN2.
43 VORTN3 A [I]
VORTN3.
45 TEMP3 A [I] Temperature sensing input of Rail 3.
48 PSYS/ISYS A [I] System power or input current sensing input.
49 VINSEN A [I] Input Voltage Sensing input.
3.3V power supply input. Connect a 4.7µF bypass capacitor from VDD33 to
50 VDD33 A [I]
AGND.
1.8V LDO output for internal digital power supply. Connect a 1µF bypass
51 VDD18 A [I/O]
capacitor to AGND.
52 PWM8 D [O]
Pad AGND A [I/O] Analog ground.

ABSOLUTE MAXIMUM RATINGS (1) Thermal Resistance (4) θJA θJC
VDD33 .........................................-0.3V to +4.0V TQFN-52 (6mmx6mm) ..........23.7 ... 16.5 . °C/W
VDD18, VDDIO ............................-0.3V to +2.2V
Notes:
VORTN1/2/3............................... -0.3V to +0.3V 1) Exceeding these ratings may damage the device.
CS1/2/3/4/5/6/7/8, PWM1/2/3/4/5/6/7/8, 2) The maximum allowable power dissipation is a function of the
maximum junction temperature TJ (MAX), the junction-to-
TEMP1/2/3, STB1/2/3, VOSEN1/2/3, EN1/2/3, ambient thermal resistance θJA, and the ambient temperature
SCL, SDA, PGD1/2/3, OCP_L, RESET_L TA. The maximum allowable continuous power dissipation at
....................................................-0.3V to +4.0V any ambient temperature is calculated by PD (MAX) = (TJ
(MAX)-TA)/θJA. Exceeding the maximum allowable power
VINSEN, SVD, SVC, SVTI, SVTO, VDDIO, dissipation produces an excessive die temperature, causing
PSYS/ISYS, NC ...........................-0.3V to +2.2V the regulator to go into thermal shutdown. Internal thermal
Junction temperature ................................150°C shutdown circuitry protects the device from permanent
damage.
Lead temperature .....................................260°C 3) The device is not guaranteed to function outside of its
Continuous power dissipation (2) ................. 4.22W operating conditions.
4) Measured on JESD51-7, 4-layer PCB.
ESD Ratings
Human body model (HBM)...................Class 1C
Charged device model (CDM)........... Class C2B
Recommended Operating Conditions (3)
Supply voltage (VDD33) ............... +3.1V to 3.5V
Operating junction temp. (TJ) ... -40°C to +125°C

ELECTRICAL CHARACTERISTICS
VDD33 = 3.3V, EN = 3.3V, VDDIO =1.8V, current going into the pin is positive. Typical values are
TA = 25°C, min/max values are at TJ = -40°C to +125°C, unless otherwise noted.
Parameter Symbol Condition Min Typ Max Units
Remote Sense Amplifier (Rail 1/2/3)
Bandwidth(5) GBW(RSA) 20 MHz
IRTN1/2/3 EN = 3.3V, VOSEN 1/2/3 =

VORTN 1,2,3 current -100 -40 μA
3V, VORTN 1/2/3 = 0V
IVOSEN1/2/3 EN = 3.3V, VOSEN 1/2/3 =

VOSEN 1,2,3 current 40 100 μA
3V, VORTN 1/2/3 = 0V
Oscillator
Frequency fOSC 1.56 MHz
System Interface Control Inputs
EN 1/2/3
Input Low Voltage VIL(EN) 0.65 V
Input High Voltage VIH(EN) 1.15 V
Enable High Leakage IIH(EN) EN = 3.3V 6 µA
st
Enable Delay (normal mode) EN Hi to 1 PWM Hi 10 us
Enable Delay (low power
EN Hi to 1st PWM Hi 100 us
mode)
PGD 1/2/3
Output low voltage at IOL =
Power Good VOL_DC 0 0.2 V
4mA
VDD33 = 3.3V, PGD
Power Good leakage current IPGDLKG 3 µA
pin=3.3V
UVP, OVP Comparator (Rail 1/2/3, UV, OV Protection) register programmable
VID digital-to-analog
converter (VID-DAC)
805 mV
Relative Under-voltage reference voltage at 1000mV,
threshold (VVID_UV) delta voltage = -200mV
Resolution/L
3 bit register 50(5) mV
SB
VID-DAC reference voltage at
1000mV, delta voltage = 1205 mV
Relative Over-voltage 200mV
threshold (VVID_OV)
Resolution/L
3 bit register 50(5) mV
SB
TEMP Fault Comparator (Rail 1/2/3, OT Protection)
TEMP fault threshold VTH_VTEMP FLT 2 2.2 V
PWM Outputs
Output low voltage VOL (PWM) IPWM(SINK) = 400µA 10 200 mV

ELECTRICAL CHARACTERISTICS (continued)
VDD33 = 3.3V, EN = 3.3V, VDDIO = 1.8V, current going into the pin is positive. Typical values are
VDD33
Output high voltage VOH (PWM) IPWM(SOURCE) = -400µA 3.15 V
- 0.02
Rise and fall time(5) C = 10pF 10 ns
PWM leakage PWM = 3.3V, EN = 0V -1 1 µA
VDD33 Supply
EN = 1, Vout = 0V,
Programmed as non-low 14.7 mA
Supply current IVDD33 power mode
Low power mode 136 µA
UVLO threshold voltage VCC_Rising VDD33 is rising, TA = 25°C 2.87 3 V
UVLO threshold voltage VCC_Falling VDD33 is falling, TA = 25°C 2.6 2.74 V
1.8V LDO
1.8V regulator output
VDD18 IVDD18 = 0mA, TA = 25°C 1.782 1.8 1.818 V
voltage
1.8V regulator load
IVDD18 VOL = VDD18 - 40mV 30 mA
capability
SVI3 Interface
SVI3 bus
VDDIO 1.08 1.98 V
voltage
VIL 0.35*
Input low voltage SVC, SVD,SVTI,VDDIO=1.8V V
VDDIO
VIH 0.65*
Input high voltage SVC, SVD,SVTI,VDDIO=1.8V V
VDDIO
Hysteresis (5) VHYST SVC, SVD,SVTI,VDDIO=1.8V 100 mV
SVC, SVD,SVTO output low
@8mA,VDDIO=1.8V, TA = 0.45 V
25°C
Output low voltage VOL
SVC, SVD,SVTO output low
@4mA,VDDIO=1.8V, TA = 0.22 V
25°C
SVC, SVD,SVTO output high VDDIO-
V
@8mA,VDDIO=1.8V 0.45
Output high voltage VOH
SVC, SVD,SVTO output high VDDIO-
V
@4mA,VDDIO=1.8V 0.22
Reset_L Input low voltage VIL_RESET_L 0.63 V
Reset_L Input high voltage VIL_RESET_H 1.17 V

Input leakage current SVC, SVD,SVTI, connect to
IOL -10 10 µA
connect high VDDIO

Input pin capacitance(5) CPIN SVC, SVD 2 pF
ADC
ADC resolution(5) 10 bit

ADC reference voltage TA=25°C 1.595 1.600 1.605 V
Sample rate(5) 780 kHz
VID DAC (Reference
Voltage for Rail 1/2/3)
Range 1.6 V
(5)
Resolution 10 bit
VOUT DC Loop DAC (VOUT Calibration for Rail 1/2/3)
Range 240 mV
Resolution (5) ∆DAC 8 bit
OCP-Phase DAC (Rail 1/2/3,OCP-Phase Protection)
Range Adjustable via the I2CBus 2.56 V
Resolution/LSB(5) 6 bit DAC 20 mV
IMON 1/2/3
IMON current sense gain Gain (IMON#/I_CSSUM)=1/8,
-1.2% 1.2%
accuracy TA = 25°C
I2CBus DC Characteristics(SDA, SCL)
Input high voltage VIH SCL, SDA 1.35 V
Input low voltage VIL SCL, SDA 0.6 V
Input leakage current SCL, SDA -10 10 μA
VOL SDA sinks 2mA (about 90

Output low voltage(5) 400 mV
ohm when NMOS on)
VMAX Transient voltage including

Maximum voltage(5) -0.3 3.3 3.6 V
ringing
Pin capacitance(5) CPIN 10 pF
(5)
I2CBus Timing Characteristics
Operating frequency range 10 1000 kHz
Between stop and start
Bus free time 0.5 μs
condition
Holding time 0.26 μs

Repeated start condition
0.26 μs
set-up time
Stop condition set-up time 0.26 μs
Data hold time 0 ns
Data set-up time 50 ns
Clock low time-out 25 35 ms
Clock low period 0.5 μs
Clock high period 0.26 50 μs
Clock/data fall time 120 ns
Clock/data rise time 120 ns
Note:
5) Guaranteed by design or characterization data, not tested in production.

BLOCK DIAGRAM
PSYS/
RESET_L OCP_L VDDIO SVTO SVTI SVD SVC ADDR VINSEN TEMP1/2/3 SDA SCL
ISYS
ADC INPUT MUX

SVI3
DIGITAL SYSTEM
CONTROL CONFIGIRE
REGISTERS
UVLO
EN1/2/3
BIAS
PGD1/2/3
CONTROL
Rail 1 PWM1
VREF1/2/3
VTRIM1/2/3 DAC PWM GEN
PWM2
VRAMP1/2/3
... Rail 2 PWM3
PWMSET1/2/3 SYSTEM
VDD33 PWM GEN PWM PWM4
CONTROL MUX PWM5
FAULT1/2/3
Rail 3
LDO PWM6
VDD18 PGD1/2/3 PWM GEN
BANGGAP PWM7
REF CONTROL PWM8
AGND STB1/2/3
COMMON BLOCK
IDROOP1/2/3
FAULT1/2/3 PGD-1/2/3 MUX CMD

VTRIM1/2/3
-
Comp PWMSET1/2/3 AUTO PHASE
+ ADC
SHEDDING
VRAMP
VREF1/2/3
Rdroop 1/2/3 TEMP1/2/3 OT DROOP IMON1/2/3
1/2/3 1/2/3
PG CURRENT SENSE BALANCE AND
OVP1/2/3 - OVP
&
UC
MODULATION
ADC CS1~8
- + FAULT
VORTN1/2/3 VDIFF1/2/3 OV OC
+ X CSSUM1/2/3
VOSEN1/2/3
80mV/160mV
- UVP RVP
-
Gain Control UVP1/2/3
+ UV RV
+
VDIFF1/2/3 RAIL 1/2/3
Figure 1: Functional Block Diagram

OPERATION
The MP2825 is a three-output, digital, multi- System Configuration
phase VR controller for AMD SVI3 platform. The MP2825 provides differential output voltage
MP2825 offers separate EN, PG, STB, TEMP sense and input voltage sense. The MP2825
Sense, Current Sense, differential remote can work with the Intelli-Phase to sense the
sense for each rail. phase current, total load current, and the
The MP2825 can implement adaptive phase maximum temperature among the Intelli-Phase
shedding and phase adding according to the with a minimum number of external
load current to improve overall VR efficiency. components. The PWM of the MP2825 outputs
The MP2825 has built-in DAC and ADC, high-Z signals before outputting power to the
differential remote voltage sense amplifier, fast load to achieve the pre-bias function.
comparators, current sense amplifiers, internal The I2CBus slave address can be set up by
slope compensation, digital load-line setting, ADDR or by the register via the I2CBus.
PGD monitor, temperature monitor, I2CBus and
SVI3 interface, and NVM to store custom Phase Configuration
configuration. The MP2825 can configure phases to different
output rails with great flexibility. The phase
Fault protection features include OCP (over-
configuration can be achieved by the
current protection), OC WARN, cycle-by-cycle
combination of register setting and PWM pin
phase-current O/UCL (over/under-current limit),
configuration. In MP2825, the phase number of
OVP (over-voltage protection), UVP (under-
each rail can be independently configured by
voltage protection), and OTP (over-temperature
I2C register (i.e. Page0. 69H. bit[3:0] for Rail1,
protection), OT WARN, VIN_UVLO (Input
bit[5:4] for Rail2, and bit[7:6] for Rail3). The
under-voltage lockout), VIN_OV (Input over-
MAX supported phase number of Rail1/2/3 is
voltage protection) and RVP (reverse-voltage
8/3/2. After phase number is determined, the
protection).
phase assignment for Rail1 is with the highest
PWM Control and Switching Period priority and the phase assignment for Rail3 is
The MP2825 applies the MPS unique digital with the second priority. Table 1 shows
PWM control to provide the fast load transient common phase configuration.
response and easy loop compensation. The For Rail1, the first phase of Rail1 is always PH1,
switching period is programmable through and phase is assigned in positive order (from
I2CBus command for each rail. small to large) based on the Rail1’s phase
The PWM On-Time of each phase updates in number. For example, if Rail1’s phase number
real-time according to the input voltage, output is 4, PH1~4 are assigned to Rail1.
voltage and switching period, as Equation (1). For Rail3, the first phase is always PH8, and
VOUT phase is assigned in negative order (from large
Ton   TS to small) based on the Rail3’s phase number.
VIN For example, if Rail3’s phase number is 2, PH8
(1) and PH7 are assigned to Rail3.
1
Fsw 
TS For Rail2 with lowest phase assignment priority,
phase is assigned in negative order and the first
Where phase of Rail2 is based on the Rail3’s phase
number. For example, if Rail2’s phase number
VOUT is the real time output voltage. VIN is the
is 2 and Rail3’s phase number is 1, PH7 and
input voltage. TS is the switching period, which
PH6 are assigned to Rail2, and the first phase
is set by I2C register MFR_SW_PRD_SET (63h.
is PH7.
bit[9:0]) of each Page. Fsw is the switching
frequency. On top of the register setting options, the
MP2825 real operation phase configuration can
be further extended by PWM pin configuration

(a pull-up 1K resistor pulling to 3.3V is usually Example 2:
recommended). A few examples are shown as
Select the 6+0+2 option by register setting, and
below.
pull PWM7 to 3.3V to achieve the 6+0+1
Example 1: configuration.
Select the 5+2+1 option by register setting, and Any unused PWM enters Hi-Z state. The active
pull PWM5 to 3.3V to achieve the 4+2+1 phase is interleaved automatically. Please float
configuration. the unused PWM pins.
Table 1: Common Phase Configuration
Phase Configuration PH1 PH2 PH3 PH4 PH5 PH6 PH7 PH8
8+0+0 Rail1
7+0+1 Rail1 Rail3
6+0+2 Rail1 Rail3
6+1+1 Rail1 Rail2 Rail3
5+3+0 Rail1 Rail2
Power On and Start-up Sequence 3. EN of the MP2825’s certain is pulled to high.

The MP2825 is supplied by a +3.3V voltage. Each rail of MP2825 has separated EN, and
The internal LDO produces a +1.8V voltage for is independent with each other.
the digital circuit. The system is reset by the 4. After EN delay time, the VR ramps to the
internal power-on reset signal (POR). default (boot) voltage. EN delay time is
The MP2825 can be enabled through EN in programmable via I2C register EN_DELAY
junction with the I2CBus operation command (65h. bit[5:0], Page0/1/2).
(01h). Normally, the operation command is on 5. The output voltage ramps with default slew
by default (01h = 0x80), so the MP2825 begins rate and finally reaches the default voltage.
working when VCC exceeds UVLO. And the corresponding PWRGD is asserted
The start-up sequence is listed below: within 5μs after the output voltage is within
tolerance and start-up ramping is complete.
1. The MP2825 VDD33 supply rises above its
UVLO threshold. The internal LDO
generates a 1.8V power supply for the
digital circuit.
2. IC initialization, the configuration in the NVM
begins transferring to the operating registers,
and copying the default (boot) voltage and
the default (boot) slew rate to the target VID
and slew rate registers respectively, all
those will be finished within 1ms.
Accordingly, the TVCC-EN is recommended to Figure 2: Start-up Sequence
be larger than 1ms.
Default Voltage and Default Slew Rate rate is determined by SVI3 register
The Default Voltage and Default Slew Rate are DOWN_SLEW_RATE (20h. bit[4]) and
used as the MP2825’s initial VID value and UP_SLEW_RATE (20h. bit[3:0]). The PGD
initial slew rate. At first VCC power-on, MP2825 of the corresponding rail will be de-asserted.
will ramps to the default voltage with default 2. The VR would also shut down upon
slew rate. receiving PSI6 command from the SVI3
The default slew rate can be set via I2C register master. MP2825 provides 2 methods for
BOOT_SR (78h. bit[4:3], Page0/1/2). The output voltage falling down to 0V, decay
default voltage is also programmable, and can down and slew down. Per SVI3 spec, If the
be set via I2C register SVI3_BOOT (61h. SVI3 register DECAY_CONDITIONS (20h.
bit[3:0], Page0/1/2). bit[5]) is 1, VR enters Hi-Z shutdown. If the
Table 2: Default VID SVI3 register DECAY_CONDITIONS (20h.
Value Default Voltage (V) bit[5]) is 0, VR will slew down to 0V before
entering Hi-Z. The PGD of the
0h Off (Wait for SV3 cmd.)
corresponding rail will remain asserted for
1h 0.500 PSI6 shutdown.
2h 0.600
3. The I2C operation command (01h) is
3h 0.700
immediate off (01h=0x00). PWM enters a
4h 0.800 Hi-Z state to turn off the high-side and low-
5h 0.900 side MOSFETs.
6h 1.000
4. UVP, VIN_UVLO, VIN_OVP, OCP, OTP
7h 1.100 turn off all phases immediately by forcing
8h 1.200 PWM into Hi-Z state.
9h 1.300
5. OVP forces PWM low to turn off all high-
Ah 1.400 side MOSFETs and turn on all low-side
Bh 1.500 MOSFETs to discharge the output capacitor
Ch 1.800 until the output voltage falls below the
Dh 2.000 reverse-voltage protection (RVP) level
Eh 2.500 (80mV/160mV).
Fh 2.800 Voltage Reference
Table 3: Default Slew Rate
The MP2825 has individual VID DAC for each
output to provide the reference voltage (VREF)
Value Default Slew Rate (mV/µs) for output closed-loop control. VREF is in VID
00b 2.5 format with 5mV per step and ranges from 0 to
01b 10 2.8V and could be set via SVI3 command. The
10b 20 VID Table is shown in Table 9.
11b 40 Output Voltage Setting and Sensing
Shut Down The output voltage is sensed with differential
voltage sense amplifier for each rail. This type
The MP2825 enters the shutdown state through
of sensing provides better load regulation. The
the following ways:
sensed output voltages are used for loop
1. EN pulls low. MP2825 provides 2 methods compensation, output voltage protections and
for EN shut down, decay down and slew output voltage monitoring via I2CBus interface
down. If the SVI3 register and SVI3 interface. There are two remote
DECAY_CONDITIONS (20h. bit[5]) is 1, VR sense gain value in differential voltage sense
enters Hi-Z shutdown. If the SVI3 register amplifier for different voltage range and it can
DECAY_CONDITIONS (20h. bit[5]) is 0, VR be programmed via I2C register VDIFF_GAIN
will slew down to 0V before entering Hi-Z. (7Ch. bit[11]) for each rail, see Figure 3.
When the rail is set to slew down, the slew
Figure 6). Therefore, ISUM is proportional to
the output current for each rail. CS_SUM is a
VORTN - 1.24V constant voltage and can sink or source
X1 or X0.5 VDIFF current to provide voltage shifts that meet the
+ operating voltage range of CS. Moreover, the
VOSEN unused CS pins should be floating.
Gain Control
7CH. bit[11]
Different Intelli-Phase products have different
operating voltage range of CS, VCS_MIN and
Figure 3: Vout Sense and VDIFF Gain VCS_MAX. Refer to each Intelli-Phase’s datasheet
Table 4 shows the VID range and the to determine minimum and maximum operating
recommended remote sense gain options. voltage range. Use equation (2) to determine a
proper RCS value,
Table 4: VID and Remote Sense Gain
Vout VID Remote Sense Gain VCS _ MIN  ICSRCS  1.24V  VCS _ MAX
(2)
0~1.56V 0x000~0x0FF 1 ICS  IL  Kcs
>1.56V >0x0FF 0.5 Where “Kcs” is the current sense gain of Intelli-
Input Voltage Sensing Phase. By pairing with Intelli-Phase, MP2825
doesn’t need temperature compensation and
The input power supply voltage is sampled at impedance matching to achieve accurate
VINSEN and used for the output voltage current sense.
regulation as the feed-forward control,
VIN_UVLO, VIN_OVP fault protection, and +3.3V VIN
input voltage monitoring.
VDD
A resistor divider network outside the chip is

BST
connected to VINSEN (see Figure 4). The CS1

CS1 CS
MO SFE SW
recommended values are Rin1 = 2MΩ and Rin2 =

Dr iver
CS2
CS2
133kΩ. A filtering capacitor 1nF or above is

AGND PGND
MP2825
recommend at VINSEN. +3.3V VIN
VDD
BST
CS SW
MO S FE
Driver
AGND PGND
Intelli-Phase
Figure 5: Phase Current Sense with 2-phase
Figure 4: VIN Sense Network Configuration
Current Sensing IMON and IDROOP
The MP2825 works together with MPS Intelli- Figure 6 shows the MP2825 IMON sense, and
Phase to accurately sense per-phase inductor IDROOP block diagram, where x, y are
current (see Figure 5). The cycle-by-cycle selectable via I2C register. The x is IMON
current information is used for phase current current mirror gain, which is proportion of IMON
balancing, over current protection, phase to ISUM and can be selected by 1/4, 1/8, 1/32 or
current limitation, and load line setting. 1/64 via I2C register IMON_GAIN_SET (7Ch.
MPS Intelli-Phase has the built-in current sense bit[6:7]) for each output rail. The IMON voltage,
function. The CS pin of Intelli-Phase outputs a which is proportional to the output current, is
current source signal which is proportional to generated by IMON flowing through a resistor
inductor current. All the Intelli-Phase CS pins of RIMON inside MP2825. The RIMON value can be
the same output rail are connected to CS_SUM selected by 4k, 8k, 32k or 64k via I2C register
with resistors RCS inside the MP2825 (see IMON_RES_SET (7Ch. bit[9:8]) of per rail. The

IMON voltage is sampled and converted by the droop resistor RDROOP, which is also referred
ADC and then stored for SVI3 telemetry and as initial load line slope. RDROOP is set by I2C
I2C reporting purposes. register RDROOP_SET (73h. bit[6:0], Page0/1/
CS1
iCS1 2).
CS2 The Load-Line adjustment via SVI3 command
iCS2
can select the IDROOP gain from 0(OFF) to
Rcs 200% with adjust increment around 10%, which
IDROOP : IMON : ISUM = y:x:1
means there are 20 steps based on a selected
RDROOP resister, as shown in figure 7.
IDROOP IMON ISUM CS_SUM
LL_Adjust
Table 6: DC Load Line Range
Parameter Min Typ. Max Unit
Buffer Vbias = 1.24V Load-Line Slope
Digital 0 10 mΩ
Rdroop
RIMON Capability
SVI3 Load-Line 0
VDIFF 200 %
Gain Adjustment (Off)
Figure 6: Current Sense IMON/ IDROOP SVI3 Load-Line
10 %
Output current telemetry consists of a 10-bit Gain Adj. Increment
encoding that is mapped to eight user-
selectable scales. IOUT scale can be set via IDROOP
I2C register I_OUT_SCALE (78h. bit[2:0], Page LL_Adjust
0/1/2). Table 5 shows the recommend RIMON (SVI3, 21h [4:0])
FB
and IMON current mirror gain based on the Comp
different Iout scale and “Kcs” (current sense Vref
gain of Intelli-Phase).
Table 5: Recommend RIMON and IMON current Digital LL
RDROOP
mirror gain Value (I2C, 73h[6:0])
Kcs = 5μA/A Kcs = 10μA/A

Iout IMON IMON
VOSEN
Scale current current
RIMON RIMON VDIFF
mirror mirror
VORTN
gain gain
Custom 32kΩ 1/4 32kΩ 1/4 Figure 7: Digital LL Implementation
32A 32kΩ 1/4 32kΩ 1/8 System Power and Input Current Sensing
64A 32kΩ 1/8 16kΩ 1/8
System power (PSYS) or Input current (ISYS) is
128A 16kΩ 1/8 8kΩ 1/8 sampled in MP2825 PSYS/ISYS pin and used
256A 8kΩ 1/8 4kΩ 1/8 for system power or input current telemetry.
512A 16kΩ 1/32 8kΩ 1/32 System power telemetry consists of a 10-bit
1024A 8kΩ 1/32 4kΩ 1/32 encoding that is mapped to eight user-
2048A 8kΩ 1/64 4kΩ 1/64
selectable scales (i.e. Custom, 32W, 64W,
128W, 256W, 512W, 1024W, 2048W). System
In Figure 6, the y is droop current mirror gain, power scale can be selected via I2C register
which is selected by 1/16, 1/8, 1/4, 1/2 via I2C PSYS_SCALE (78h. bit[7:5], Page1).
register IDROOP_1ST_CM_SET (73h. bit[9:8]) Input current telemetry consists of a 10-bit
of per rail. encoding that is mapped to eight user-
Digital Load-Line selectable scales (i.e. Custom, 4A, 8A, 16A,
The Load-Line of all rails are programmable by 32A, 64A, 128A, 256A). Input current scale can
registers through I2C and SVI3 command to be selected via I2C register SCALE_IIN (7Ah.
achieve the range shown in table 6. There are bit[15:13], Page0).
two parameters can be adjusted to achieve the
desired load line, droop current mirror gain and
System power or input current is converted into VTEMP of the Intelli-Phase is a voltage output
a small current signal by power or current proportional to the junction temperature. For
sense device of system power monitor. The example of MP86901C, the VTEMP voltage can
conversion ratio from system power or input be calculated with below Equation:
current to current signal is named as “KPSYS/ISYS”.
V  100mV
A resistor (RPSYS/ISYS) is required and connected TJUNCTION  TEMP (4)
from PSYS/ISYS pin to GND, which is shown in 10mV/ o
C
Figure 8. The PSYS/ISYS pin voltage, which is for TJUNCTION > 10°C.
formed by current signal flowing through
+3.3V VIN
RPSYS/ISYS and is proportional to system power
or input current, is measured by the PSYS/ISYS VDD
ADC inside MP2825. Moreover, a proper MP2825

BST
RPSYS/ISYS value is determined by equation (3) or

(4).
VTEMP
TEMP1 M OSF ET
Dr iv er
SW
C R
System power sample: AGND PGND
1.2 (3) Intelli-Phase

RPSYS/ISYS 
(PSYS_SCALE* K PSYS ) +3.3V VIN
Input current sample: VDD

BST
1.2 (4)
RISYS/ISYS 
(ISYS_SCALE* K ISYS ) VTEMP
M OSF E T
Dr iv er
SW
Where “1.2” refers to the MAX PSYS/ISYS pin AGND PGND
voltage 1.2V; PSYS_SCALE is the selected

Intelli-Phase
system power scale and is in W; ISYS_SCALE
is the selected input current scale and is in A; Figure 9: External Temperature Sense
KPSYS is in A/W and KISYS is in A/A. Voltage-On-The-Fly (VOTF)
The MP2825 supports dynamic output voltage
MP2825 transitions by changing the VID code with SVI3
PSYS* KPSYS or
PSYS/ISYS
ISYS* KISYS interface or I2C interface. It is selectable via I2C
register (5Fh. bit[9], Page 0/1/2).
RPSY S/ISYS When the MP2825 works in SVI3 VID mode.
Once VDDIO is ready and RESET_L is high,
the MP2825 detects 8 cycles of SVC toggling
Figure 8: PSYS Pin Configuration and begins monitoring SVC and SVD for SVI3
Temperature Sensing commands. The MP2825 decodes the
MP2825 TEMP pin is used to sense the instruction and acknowledges the VID code. For
temperature of VR power system. The sensed VID codes higher than the current VID level, the
temperature is used for temperature reporting, MP2825 begins stepping the commanded VR
temperature telemetry and over-temperature outputs to the new VID target with a slew rate
fault protection. MP2825 measures the external which is programmed by the SVI3 register
temperature by connecting all Intelli-Phase’s (of UP_SLEW_RATE (20h. bit[3:0]). The MAX slew
the related Rail) VTEMP pins together (see rate is 40mV/μs.
Figure 9). The voltage of TEMP pin of the VID Ramp Upwards/Downwards
MP2825 is the highest voltage among the The MP2825 applies an advanced digital
Intelli-Phase devices, which indicates the control method to improve the output voltage
highest temperature of the VR power system. performance during VID ramping up and down.
Normally, a 49.9kΩ resistor in parallel with a
1µF capacitor from TEMP to GND is needed. When the output voltage is ramping upwards,
the inductor current becomes higher to charge

the output capacitors. This current results in an commanded. The activation criteria of decay
extra droop voltage and lowers the output mode is configured by SVI3 command.
voltage. When VREF ramping ends, the output
Power State Change
voltage may be smaller than the minimum
regulation tolerance budget (TOB) of the target The MP2825 applies 2 modes to control the VR
voltage. The MP2825 is able to ramp up more to enter to different power states to achieve
VID steps automatically than the target VID and high efficiency at different load conditions, SVI3
falls back to fasten the output voltage to rise mode and I2C mode. The power state control
into the regulation tolerance budget. mode can be select via I2C register
SVI3_I2C_PSI_SET (5Fh. bit[3], on each Page).
When the output voltage is ramping downwards, The VR is expected to optimize its power loss
the inductor current becomes smaller to to flatten the efficiency curve over the operating
discharge the output capacitors. The output current range with the power state commands
capacitors continue to discharge when ramping issued by the processor.
ends and may lead to an output voltage
undershoot. The MP2825 applies a low-pass In PSI0 mode, all active phases are running in
filter for VID_DAC to smooth out the reference continuous conduction mode (CCM).
voltage when the output voltage is ramping In PSI1 mode, active phase number set in SVI3
downwards. register PHASE_SHED_1 (2Dh. bit[7:4]) runs in
CCM Mode. Default is one phase CCM.
In PSI2 mode, active phase number set in SVI3
register PHASE_SHED_2 (2Dh. bit[3:0]) runs in
CCM Mode. Default is one phase CCM.
In PSI3 mode, only one phase is running with
synchronous switching while the other phases
are in HiZ state. When load decrease, this
phase will be running in the active diode
emulation mode, and the switching frequency
falls down automatically due to the light-load
condition.
Figure 10: VID Ramping Downwards 
PSI4 is not supported.
VID Ramping Upwards
PSI5 is reserved per SVI3 specification.
Figure 10 shows the output voltage when VID
ramps upward after the previous VID finishes In PSI6 mode, the power regulation is disabled
ramping downward. and VR power down to 0V. The corresponding
PGD remains asserted. All non-essential
VID Decay Mode
systems are shutdown. In PSI6, VR still passes
At SVI3 VID mode, when the VID codes are through telementry and adds its header packet
lower than the current VID level, the MP2825 and possible register read back as long as the
checks the state of the DECAY_CONDITIONS SVI3 interface is enabled.
bit in the SVI3 register (20h. bit[7:5]). If the
power state bit are not active, the controller In PSI7 mode, the MP2825 enters auto-phase
begins stepping the regulator output to the new shedding mode.
VID target with slew rate controlled by SVI3 When the dynamic VID up transition is issued
register DOWN_SLEW_RATE (20h. bit[4]). If by a voltage-on-the-fly command, the power
the power state bit is active, the MP2825 allows state of the related rail changes to full-phase
the output voltage to decay and slowly step mode. After the output is regulated to the new
DAC down with the natural decay of the output target voltage, the power state gets back to the
voltage. This allows the controller to recover power state issued by the processor PSI
quickly and move to a high VID code if command.

If the dynamic VID down transition happened The total current report is used to determine
while decay condition is disabled, it operates whether to add phase or shed phase to flatten
the same way with VID up. the overall efficiency over the operating current
range.
While if dynamic VID down transition happened
while decay condition is enabled, VR will The MP2825 provides an auto-phase shedding
operate with decay down. Table 7 below shows (APS) function to improve the efficiency when it
a summary of the power states. is in PSI7. As shown in Figure 11, taking 2-
Table 7: Power States and active Phases
phase operation as an example, the VR works
at 2-phase CCM at heavy load, and 1-phase
PSI Action
CCM at light load to optimize the efficiency, and
0 Full phase count (default)
enters 1-phase DCM at extreme light load
Phase count 1st level (phase count ditacted
1
by 4-bit register in SVI3 Command) reduce the switching loss further.
Phase count 2nd level (phase count
2
ditacted by 4-bit register in SVI3 Command)
Single phase operation + active diode
3 emulation (low-side actively driven when
I_ind is positive)
4 Not support
5 Reserved
Power down to 0V (voltage regulation Figure 12: Phase Shedding Threshold and
6 disabled). The corresponding PWRGD pin Hysteresis setting
remains asserted
Automated phase shedding and diode
The APS function is implemented by comparing
7 the sensed load current with each power state
emulation
current threshold. The MP2825 provides two
Auto-Phase Shedding (APS) types of parameters to configure the auto-
The auto-phase shedding (APS) function is phase shedding function: Phase Shedding
required by SVI3 spec. If SVI3 master sends a Threshold (DCM shedding threshold: I2C
command of entering PSI7 to the MP2825, the register 71h. bit [7:0], CCM shedding threshold:
MP2825 would enter APS mode. However, if I2C register 71h. bit[15:8], on each Page) and
APS is not enabled or required from the SVI3 Hysteresis (I2C register 72h. bit[7:0], on each
command, platform designer still has the option Page). DCM Shedding Threshold is the
to enable APS via the I2CBus. Selecting PSI threshold of 1 phase CCM shedding to DCM.
control mode to I2C and set I2C register CCM Shedding Threshold is the threshold of
I2C_PSI_SET (5Fh. bit[2:0], on each Page) to CCM each phase shedding. Hysteresis is the
3b’111. hysteresis from phase shedding level to adding
level. For example, shown in Figure 12, DCM
Shedding Threshold is set to 5A, CCM
Shedding Threshold is set to 10A, and
Hysteresis is set to 3A.
Besides the sensed output current comparison,
the MP2825 provides three conditions to exit
APS immediately and run with full phase CCM
operation so as to accelerate the load transient
response and reduce the output voltage
undershoot.
1. DVID process makes the controller runs
with full phase CCM (PSI0). After the output
voltage is settled to the target value, new
power state is determined by the load
Figure 11: APS Function Diagram at 2-Phase current.
Mode
2. Load step up cause High frequency is timeout and I2C register LOW_PWR_SEL
detection tripping (set by NVM) will trigger _SVC_TIMEOUT (Page0. 7Bh. bit[8]) sets 1.
full phase CCM running to reduce output
In low power mode, the I2C and SVI3
voltage undershoot.
communication is disabled, and the quiescent
3. Phase current exceeds per phase over current is reduced to 136µA (typical value). In
current limit, the MP2825 runs with full regular-power mode, the I2C communication is
phase CCM (PSI0). available and the MTP is alive.
Phase Current Balancing/Thermal Balancing Standby Mode for Intelli-Phase
The phase current is sensed and calculated STB signal can control the power mode for
with the current reference in the current loop. Intelli-Phase. In active mode, the controller STB
Each phase’s PWM on time is adjusted pin would be high to enable the Intelli-Phase to
individually to balance the currents accordingly. output power to the load. During shutdown (EN
low) or PSI6, the STB pin would be in Hi-Z or
The MP2825 applies Σ-Δ modulation and delay
low state (can be selected by I2C register
line-loop technology in the current balance
MFR_STB_CONFIG, 7Ch. bit[15], Page2) to
modulation to increase the resolution of the
make the Intelli-Phase work in standby Mode to
current balance modulation and reduce the jitter
save power. Users can program the delay time
of PWM greatly. The time resolution of the
from exiting standby to PWM start pulsing
digital system is 10ns. By applying the Σ-Δ
through NVM setting.
modulation and DLL technology, the digital
PWM resolution can be increased to 1.25ns. Figure 13 shows the connection between the
MP2825 STB pin and the Intelli-Phase’s SYNC
Each current balance loop can also include the
pin. Each rail shares the similar connection
programmable phase current offset to achieve
structure.
thermal balance among the phases. The phase
has a greater cooling capability due to better +3.3V VIN
proximity to the airflow, which allows it to take
more phase current by increasing the phase MP2825
VDD
BST
current reference with the offset to keep the

phase thermal more balanced. The bandwidth
SW
SYNC
STB1 M OSF E T
Driv er
of the current proportional-integral (PI) loop is AGND PGND
relatively lower than the output voltage

feedback loop, so it barely impacts the output Intelli-Phase
voltage. +3.3V VIN
.
SVI3 Type 2 Supporting
VDD
In addition to being used as SVI3 Type 1 device, BST
MP2825 also can support SVI3 Type 2 device SW

SYNC
application. Rail3 in MP2825 can be configured M OSF E T
Driv er
individually as Type 2 device by setting I2C AGND PGND
register SLAVE_TYPE (7Ch. bit[1], Page2).

Intelli-Phase
Low Power Mode
The MP2825 can be programmed to low power Figure 13: STB Connection between MP2825 and
mode (LPM) or regular-power mode. The low MPS Intelli-Phase
power mode function can be configured enable Fault Monitoring and Protections
or disable by I2C register LOW_PWR_EN (7Bh. The MP2825 supports several fault monitoring
bit[7], Page0). and protections with two protection mode, no-
With LPM function enabled, two condition must action mode and latch-off mode chosen by I2C
be satisfied that the VR will enter LPM. The first register. In no-action mode, the MP2825
condition is Rail1/2/3 EN off or enter PSI6; the ignores the fault on both power action and I2C
second condition is that VDDIO is low, or SVC fault reporting. In latch-off mode, an external

intervention is required to clear the latch before
the VR can restart again. The external
intervention can be the enable signal toggle,
controller power supply recycle.
The fault/warning status (OVP, UVP, OCP,
OTP, OC WARNING, VRHOT) is recorded in
SVI3 register FAULT_STATUS (10h). Once
triggered, the fault register reports Figure 14: OVP and RVP Trigger Threshold
corresponding fault, even if the fault condition
no longer exists. FAULT_STATUS (10h) After OVP being triggered and the low-side
register can be cleared by SVI3 issuing the MOSFET is turned on to discharge the output
Write Register command to FAULT_STATUS voltage. If Vout drops lower than RVP (Reverse
(10h) with data 0. Voltage Protections) threshold, RVP occurs and
the low-side MOSFET is turned off to prevent
The protections are listed as below. Vout from becoming negative. The RVP
VIN UVLO threshold can be set 80mV/160mV by I2C
register (7Ch. bit[10], Page0/1/2).
This is shared for all Rails. When VIN triggers
UVLO, VR can select latch-off or hiccup mode Figure 15 shows the OVP waveforms together
based on I2C register VIN_UVLO_LATCH (6Ch. with RVP of the MP2825.
bit[9], Page0). In latch-off or hiccup mode, VR
shuts off immediately if the sensed VIN is below
VIN_OFF (I2C register, 36h. bit[7:0], Page0).
Only in hiccup mode, VR will restart when the
sensed VIN is above VIN_ON (I2C register, 35h.
bit[7:0], Page0).
VIN OV
Applied for all Rails, if the input voltage is above
VIN OV, VR can select latch-off or hiccup mode
based on I2C register VIN_OVP_LATCH (6Ch.
bit[8], Page0). In latch-off or hiccup mode, VR
shuts off immediately if the sensed VIN is over
VIN_OV (I2C register, 55h. bit[15:8], Page0). Figure 15: OVP Waveform
Only in hiccup mode, VR will restart when the The OVP signals are blanked during the soft-
sensed VIN is below VIN_OV. start and down processes to avoid a false
Over-Voltage Protection (OVP) trigger by a pre-bias condition. The OVP signals
Each Rail have separated OVP protection, and are also blanked in decay mode.
is independent with each other. Reverse-Voltage Protection (RVP)
If the delta voltage exceeds SVI3 register A large reverse inductor current may cause
OVP_DELTA (2Ch bit[6:4]) for OVP delay time, negative output voltages that can harm the
OVP triggers, the OVP threshold is combined processor and other output components. The
by the VID target or VID_MAX (select via SVI3 MP2825 provides RVP with no additional
register 2Ch bit[7]), OVP Delta and Vout offset system cost.
as shown in Figure 14, all those parameters When OVP occurs, all LS-FETs are forced on
can be set through SVI3 command and default to discharge the voltage of the output
settings are in NVM. capacitors quickly. The inductor current
becomes very negative, which can discharge
the voltage of the output capacitors negative
enough to destroy the load without RVP.

OCP_WARN
With the RVP function, when the VOSEN
voltage falls below 80mV or 160mV after OVP,
the MP2825 triggers RVP by latching all PWM Iout
outputs to HiZ state. The reverse inductor
current can quickly reset to 0A by dissipating Vout
the energy in the inductor to the input DC
voltage source through the forward-biased body
PWM
diode of the HS-FETs. The RVP function after
OVP is shown in Figure 15.
PGD MIN_PULSE
Over-Current Protection (OCP)
The MP2825 supports 2-level over-current OCP_L
protection for each rail, WARNING and FAULT.
The first level is OCP Warning. The OCP Figure 16: OCP Warning
Warning function uses a programmable For per-phase OCL, if the present phase
threshold OCP_WARN_THRESH (28h. bit[7:0], current is higher than the setting valley point,
SVI3 register) with a programmable period of then the PWM on signal of this phase is
time OCP_WARN_MIN_PULSE (29h. bit[7:3], blocked and will not turn on until its current falls
SVI3 register) to set the minimum pulse to below the setting level. If the present phase
trigger the assertion of OCP_L and the sticky PWM on signal is blocked for more than 80ns,
OCP_WARN bit in the TEMP1/WARN SVI3 the PWM on signal is skipped for this cycle and
telemetry packet and SVI3 register next phase is turned on directly to regulate the
FAULT_STATUS (10h. bit[4]). In this period, the output voltage. The valley point over-current
system takes no action on PWM operation. level can be programmed via the I2C register
The second level is OCP Fault. When the PER_PHASE_OC_LEVEL (54h. bit[5:0], on
measured current exceeds the OCP_THRESH each page).
(27h. bit[7:0], SVI3 register) continuously with a OCP_Delay
OCP_Fault
period of time OCP_FAULT_DELAY (29h.
bit[2:0], SVI3 register), OCP triggers. The Iout
controller will assert SVI3 register
FAULT_STATUS (10h. bit[0]).
Vout
All those parameters can be programmed
through SVI3 command and default settings are
in NVM. PWM
Besides the dual OC mechanism described
above, the MP2825 utilizes an extra valley point PGD
current limit method to limit each phase
over/under current cycle-by-cycle (per-phase Figure 17: OC Fault Protection
OCL/UCL).
For per-phase UCL, if the negative phase
current reaches the under-current level, the
PWM on signal of this phase will be triggered to
limit the negative current. The under-current
level (I2C register PER_PHASE_OC_LEVEL,
54h. bit[11:6], on each page) and the width of
PWM on signal (I2C register UCP_ONTIME,
72h.bit[4:0], on each page) can be programmed
via the I2CBus, respectively.

Under-Voltage Protection (UVP) The second level is OTP, which is triggered
Each rail of MP2825 have separated UVP when the sensed power stage temperature
protection, and is independent with each other. exceeds OTP_THRESHOLD (SVI3 register,
2Bh. bit[7:0]) and OTP is enabled by SVI3
If the delta voltage exceeds UVP_DELTA (2Ch. command. MP2825 will immediately shut down
bit[2:0], SVI3 register) for an UVP delay time, and assert FAULT_STATUS (SVI3 register, 10h.
UVP is triggered, the UVP threshold is bit[3]).
combined with the VID or VID_MIN (select via
SVI3 register 2Ch. bit[3]), UVP Delta and Vout NVM Fault
offset as shown in Figure 18. If the data from NVM is checked as invalid by
the cyclic redundancy check (CRC) during the
VID or VID_MIN
system initialization process, the system enters
‐ΔV an NVM fault state without outputting power
and waits for the error clear command, and the
UV_Delay UV
VOUT_OFFSET COMP
configuration from the NVM is ignored.
VDIFF
There are two steps to clear the NVM fault and
Figure 18: Under-Voltage Protection start-up again with the default value in the
All those parameters can be set through SVI3 register:
command and default settings are in NVM. 1. Store the configuration into the NVM with
Normally, UVP will be triggered when the per- I2C command (15h).
phase over-current limit is triggered. When the 2. Restart with a VDD33 power recycle.
per-phase OC limit is triggered, MP2825 will
block PWM signals to prevent phase current to I2CBus and SVI3 Communication
become higher and output voltage will be lower. The MP2825 supports real-time monitoring for
(See Figure 19). the VR operation parameters and fault status
with both I2CBus and SVI3 interface. Table 8
lists the monitored parameters.
Table 8: I2C Monitored Parameters
Parameter I2CBus SVI3
Output voltage  
Output current  
Temperature  
Input voltage  
Phase current 
OVP  
UVP  
Figure 19: UVP Triggered when Per-Phase OCP  
Current is limited by OCP-PHASE UCP 
Over-Temperature Protection (OTP) OTP  
VIN_UVLO 
Each rail of MP2825 have separated OTP
VIN_OV 
protection, and is independent with each other.
MP2825 supports two levels of over I2CBus Address Configuration
temperature mechanism. The first level is To support multiple VR devices using the same
VRHOT indication, which is triggered when the I2CBus interface, MP2825 provides a
temperature exceeds VRHOT_THRESHOLD configurable I2CBus address via the ADDR pin
(SVI3 register, 2Ah. bit[7:0]) and VRHOT is or I2C register. The address is a 7-bit code and
enabled by SVI3 to assert the VRHOT bit in the the configuration mode of I2CBus address can
TEMP1/WARN SVI3 telemetry packet and be selected by setting I2C register
FAULT_STAUTS (SVI3 register, 10h. bit[5]). MFR_ADDR_SET (62h. bit[7], Page0).

When MFR_ADDR_SET = 1, I2CBus address
is determined by I2C register MFR_ADDR_I2C
(62h. bit[6:0], Page0).
When MFR_ADDR_SET = 0, I2CBus address
is determined by ADDR pin voltage and I2C
register 62h. bit[6:4] of Page0. The ADDR pin
voltage can be configured by a resistor divider
from VDD18 to AGND, and the midpoint of the
divider is connected to ADDR. The relation of
I2CBus address, I2C register 62h and ADDR
pin voltage is listed in Table 9.
Table 9: Relation of I2CBus address, I2C register
62h and ADDR pin voltage
I2CBus Address ADDR pin voltage
X0H 0V
X1H 0.3V
X2H 0.5V
X3H 0.7V
X4H 0.9V
X5H 1.1V
X6H 1.3V
X7H 1.5V
“X” is set by I2C register 62H. bit[6:4] of Page0.

Table-10 SVI3 SERIAL VID CODES (Part1)
SVID[8:0] Voltage SVID[8:0] Voltage SVID[8:0] Voltage SVID[8:0] Voltage
BIN HEX (V) BIN HEX (V) BIN HEX (V) BIN HEX (V)
000000000 0 OFF 000100000 20 0.405 001000000 40 0.565 001100000 60 0.725
000000001 1 0.250 000100001 21 0.410 001000001 41 0.570 001100001 61 0.730
000000010 2 0.255 000100010 22 0.415 001000010 42 0.575 001100010 62 0.735
000000011 3 0.260 000100011 23 0.420 001000011 43 0.580 001100011 63 0.740
000000100 4 0.265 000100100 24 0.425 001000100 44 0.585 001100100 64 0.745
000000101 5 0.270 000100101 25 0.430 001000101 45 0.590 001100101 65 0.750
000000110 6 0.275 000100110 26 0.435 001000110 46 0.595 001100110 66 0.755
000000111 7 0.280 000100111 27 0.440 001000111 47 0.600 001100111 67 0.760
000001000 8 0.285 000101000 28 0.445 001001000 48 0.605 001101000 68 0.765
000001001 9 0.290 000101001 29 0.450 001001001 49 0.610 001101001 69 0.770
000001010 A 0.295 000101010 2A 0.455 001001010 4A 0.615 001101010 6A 0.775
000001011 B 0.300 000101011 2B 0.460 001001011 4B 0.620 001101011 6B 0.780
000001100 C 0.305 000101100 2C 0.465 001001100 4C 0.625 001101100 6C 0.785
000001101 D 0.310 000101101 2D 0.470 001001101 4D 0.630 001101101 6D 0.790
000001110 E 0.315 000101110 2E 0.475 001001110 4E 0.635 001101110 6E 0.795
000001111 F 0.320 000101111 2F 0.480 001001111 4F 0.640 001101111 6F 0.800
000010000 10 0.325 000110000 30 0.485 001010000 50 0.645 001110000 70 0.805
000010001 11 0.330 000110001 31 0.490 001010001 51 0.650 001110001 71 0.810
000010010 12 0.335 000110010 32 0.495 001010010 52 0.655 001110010 72 0.815
000010011 13 0.340 000110011 33 0.500 001010011 53 0.660 001110011 73 0.820
000010100 14 0.345 000110100 34 0.505 001010100 54 0.665 001110100 74 0.825
000010101 15 0.350 000110101 35 0.510 001010101 55 0.670 001110101 75 0.830
000010110 16 0.355 000110110 36 0.515 001010110 56 0.675 001110110 76 0.835
000010111 17 0.360 000110111 37 0.520 001010111 57 0.680 001110111 77 0.840
000011000 18 0.365 000111000 38 0.525 001011000 58 0.685 001111000 78 0.845
000011001 19 0.370 000111001 39 0.530 001011001 59 0.690 001111001 79 0.850
000011010 1A 0.375 000111010 3A 0.535 001011010 5A 0.695 001111010 7A 0.855
000011011 1B 0.380 000111011 3B 0.540 001011011 5B 0.700 001111011 7B 0.860
000011100 1C 0.385 000111100 3C 0.545 001011100 5C 0.705 001111100 7C 0.865
000011101 1D 0.390 000111101 3D 0.550 001011101 5D 0.710 001111101 7D 0.870
000011110 1E 0.395 000111110 3E 0.555 001011110 5E 0.715 001111110 7E 0.875
000011111 1F 0.400 000111111 3F 0.560 001011111 5F 0.720 001111111 7F 0.880

010000000 80 0.885 010100000 A0 1.045 011000000 C0 1.205 011100000 E0 1.365
010000001 81 0.890 010100001 A1 1.050 011000001 C1 1.210 011100001 E1 1.370
010000010 82 0.895 010100010 A2 1.055 011000010 C2 1.215 011100010 E2 1.375
010000011 83 0.900 010100011 A3 1.060 011000011 C3 1.220 011100011 E3 1.380
010000100 84 0.905 010100100 A4 1.065 011000100 C4 1.225 011100100 E4 1.385
010000101 85 0.910 010100101 A5 1.070 011000101 C5 1.230 011100101 E5 1.390
010000110 86 0.915 010100110 A6 1.075 011000110 C6 1.235 011100110 E6 1.395
010000111 87 0.920 010100111 A7 1.080 011000111 C7 1.240 011100111 E7 1.400
010001000 88 0.925 010101000 A8 1.085 011001000 C8 1.245 011101000 E8 1.405
010001001 89 0.930 010101001 A9 1.090 011001001 C9 1.250 011101001 E9 1.410
010001010 8A 0.935 010101010 AA 1.095 011001010 CA 1.255 011101010 EA 1.415
010001011 8B 0.940 010101011 AB 1.100 011001011 CB 1.260 011101011 EB 1.420
010001100 8C 0.945 010101100 AC 1.105 011001100 CC 1.265 011101100 EC 1.425
010001101 8D 0.950 010101101 AD 1.110 011001101 CD 1.270 011101101 ED 1.430
010001110 8E 0.955 010101110 AE 1.115 011001110 CE 1.275 011101110 EE 1.435
010001111 8F 0.960 010101111 AF 1.120 011000111 C7 1.280 011101111 EF 1.440
010010000 90 0.965 010110000 B0 1.125 011010000 D0 1.285 011110000 F0 1.445
010010001 91 0.970 010110001 B1 1.130 011010001 D1 1.290 011110001 F1 1.450
010010010 92 0.975 010110010 B2 1.135 011010010 D2 1.295 011110010 F2 1.455
010010011 93 0.980 010110011 B3 1.140 011010011 D3 1.300 011110011 F3 1.460
010010100 94 0.985 010110100 B4 1.145 011010100 D4 1.305 011110100 F4 1.465
010010101 95 0.990 010110101 B5 1.150 011010101 D5 1.310 011110101 F5 1.470
010010110 96 0.995 010110110 B6 1.155 011010110 D6 1.315 011110110 F6 1.475
010010111 97 1.000 010110111 B7 1.160 011010111 D7 1.320 011110111 F7 1.480
010011000 98 1.005 010111000 B8 1.165 011011000 D8 1.325 011111000 F8 1.485
010011001 99 1.010 010111001 B9 1.170 011011001 D9 1.330 011111001 F9 1.490
010011010 9A 1.015 010111010 BA 1.175 011011010 DA 1.335 011111010 FA 1.495
010011011 9B 1.020 010111011 BB 1.180 011011011 DB 1.340 011111011 FB 1.500
010011100 9C 1.025 010111100 BC 1.185 011011100 DC 1.345 011111100 FC 1.505
010011101 9D 1.030 010111101 BD 1.190 011011101 DD 1.350 011111101 FD 1.510
010011110 9E 1.035 010111110 BE 1.195 011011110 DE 1.355 011111110 FE 1.515
010011111 9F 1.040 010111111 BF 1.200 011011111 DF 1.360 011111111 FF 1.520

100000000 100 1.525 100100000 120 1.685 101000000 140 1.845 101100000 160 2.005
100000001 101 1.530 100100001 121 1.690 101000001 141 1.850 101100001 161 2.010
100000010 102 1.535 100100010 122 1.695 101000010 142 1.855 101100010 162 2.015
100000011 103 1.540 100100011 123 1.700 101000011 143 1.860 101100011 163 2.020
100000100 104 1.545 100100100 124 1.705 101000100 144 1.865 101100100 164 2.025
100000101 105 1.550 100100101 125 1.710 101000101 145 1.870 101100101 165 2.030
100000110 106 1.555 100100110 126 1.715 101000110 146 1.875 101100110 166 2.035
100000111 107 1.560 100100111 127 1.720 101000111 147 1.880 101100111 167 2.040
100001000 108 1.565 100101000 128 1.725 101001000 148 1.885 101101000 168 2.045
100001001 109 1.570 100101001 129 1.730 101001001 149 1.890 101101001 169 2.050
100001010 10A 1.575 100101010 12A 1.735 101001010 14A 1.895 101101010 16A 2.055
100001011 10B 1.580 100101011 12B 1.740 101001011 14B 1.900 101101011 16B 2.060
100001100 10C 1.585 100101100 12C 1.745 101001100 14C 1.905 101101100 16C 2.065
100001101 10D 1.590 100101101 12D 1.750 101001101 14D 1.910 101101101 16D 2.070
100001110 10E 1.595 100101110 12E 1.755 101001110 14E 1.915 101101110 16E 2.075
100001111 10F 1.600 100101111 12F 1.760 101000111 147 1.920 101101111 16F 2.080
100010000 110 1.605 100110000 130 1.765 101010000 150 1.925 101110000 170 2.085
100010001 111 1.610 100110001 131 1.770 101010001 151 1.930 101110001 171 2.090
100010010 112 1.615 100110010 132 1.775 101010010 152 1.935 101110010 172 2.095
100010011 113 1.620 100110011 133 1.780 101010011 153 1.940 101110011 173 2.100
100010100 114 1.625 100110100 134 1.785 101010100 154 1.945 101110100 174 2.105
100010101 115 1.630 100110101 135 1.790 101010101 155 1.950 101110101 175 2.110
100010110 116 1.635 100110110 136 1.795 101010110 156 1.955 101110110 176 2.115
100010111 117 1.640 100110111 137 1.800 101010111 157 1.960 101110111 177 2.120
100011000 118 1.645 100111000 138 1.805 101011000 158 1.965 101111000 178 2.125
100011001 119 1.650 100111001 139 1.810 101011001 159 1.970 101111001 179 2.130
100011010 11A 1.655 100111010 13A 1.815 101011010 15A 1.975 101111010 17A 2.135
100011011 11B 1.660 100111011 13B 1.820 101011011 15B 1.980 101111011 17B 2.140
100011100 11C 1.665 100111100 13C 1.825 101011100 15C 1.985 101111100 17C 2.145
100011101 11D 1.670 100111101 13D 1.830 101011101 15D 1.990 101111101 17D 2.150
100011110 11E 1.675 100111110 13E 1.835 101011110 15E 1.995 101111110 17E 2.155
100011111 11F 1.680 100111111 13F 1.840 101011111 15F 2.000 101111111 17F 2.160

110000000 180 2.165 110100000 1A0 2.325 111000000 1C0 2.485 111100000 1E0 2.645
110000001 181 2.170 110100001 1A1 2.330 111000001 1C1 2.490 111100001 1E1 2.650
110000010 182 2.175 110100010 1A2 2.335 111000010 1C2 2.495 111100010 1E2 2.655
110000011 183 2.180 110100011 1A3 2.340 111000011 1C3 2.500 111100011 1E3 2.660
110000100 184 2.185 110100100 1A4 2.345 111000100 1C4 2.505 111100100 1E4 2.665
110000101 185 2.190 110100101 1A5 2.350 111000101 1C5 2.510 111100101 1E5 2.670
110000110 186 2.195 110100110 1A6 2.355 111000110 1C6 2.515 111100110 1E6 2.675
110000111 187 2.200 110100111 1A7 2.360 111000111 1C7 2.520 111100111 1E7 2.680
110001000 188 2.205 110101000 1A8 2.365 111001000 1C8 2.525 111101000 1E8 2.685
110001001 189 2.210 110101001 1A9 2.370 111001001 1C9 2.530 111101001 1E9 2.690
110001010 18A 2.215 110101010 1AA 2.375 111001010 1CA 2.535 111101010 1EA 2.695
110001011 18B 2.220 110101011 1AB 2.380 111001011 1CB 2.540 111101011 1EB 2.700
110001100 18C 2.225 110101100 1AC 2.385 111001100 1CC 2.545 111101100 1EC 2.705
110001101 18D 2.230 110101101 1AD 2.390 111001101 1CD 2.550 111101101 1ED 2.710
110001110 18E 2.235 110101110 1AE 2.395 111001110 1CE 2.555 111101110 1EE 2.715
110001111 18F 2.240 110101111 1AF 2.400 111000111 1C7 2.560 111101111 1EF 2.720
110010000 190 2.245 110110000 1B0 2.405 111010000 1D0 2.565 111110000 1F0 2.725
110010001 191 2.250 110110001 1B1 2.410 111010001 1D1 2.570 111110001 1F1 2.730
110010010 192 2.255 110110010 1B2 2.415 111010010 1D2 2.575 111110010 1F2 2.735
110010011 193 2.260 110110011 1B3 2.420 111010011 1D3 2.580 111110011 1F3 2.740
110010100 194 2.265 110110100 1B4 2.425 111010100 1D4 2.585 111110100 1F4 2.745
110010101 195 2.270 110110101 1B5 2.430 111010101 1D5 2.590 111110101 1F5 2.750
110010110 196 2.275 110110110 1B6 2.435 111010110 1D6 2.595 111110110 1F6 2.755
110010111 197 2.280 110110111 1B7 2.440 111010111 1D7 2.600 111110111 1F7 2.760
110011000 198 2.285 110111000 1B8 2.445 111011000 1D8 2.605 111111000 1F8 2.765
110011001 199 2.290 110111001 1B9 2.450 111011001 1D9 2.610 111111001 1F9 2.770
110011010 19A 2.295 110111010 1BA 2.455 111011010 1DA 2.615 111111010 1FA 2.775
110011011 19B 2.300 110111011 1BB 2.460 111011011 1DB 2.620 111111011 1FB 2.780
110011100 19C 2.305 110111100 1BC 2.465 111011100 1DC 2.625 111111100 1FC 2.785
110011101 19D 2.310 110111101 1BD 2.470 111011101 1DD 2.630 111111101 1FD 2.790
110011110 19E 2.315 110111110 1BE 2.475 111011110 1DE 2.635 111111110 1FE 2.795
110011111 19F 2.320 110111111 1BF 2.480 111011111 1DF 2.640 111111111 1FF 2.800

SVI3 Registers
Table 14 shows the data and configuration registers for the SVI3 protocol
Addr
Bit Register Name Default Value Note
(Hex)
1 [7:0] SVI3_VERSION 01h
[7:5] TYPE_ID 000b
2
[4:0] MFG_ID 02h
3 [7:0] MODEL_ID 25h
4 [7:0] TEN_BIT_TEL_AVAIL 77h
5 [7:0] SIXTEEN_BIT_TEL_AVAIL 00h
[7:7] CRC_ENABLED 1b Enabled
6 [4:2] PSI 000b PSI0
[0:0] VID[8] Default VID copied from
Platform
7 [7:0] VID[7:0] VID_DEFAULT_VOLTAGE
[5:4] DEFAULT_SLEW_RATE Platform NVM configurable, based on platform
8
[3:0] VID_DEFAULT_VOLTAGE Platform NVM configurable, based on platform
[7:6] V_IN_SCALE 10b 0.3125V/LSB
9 [5:3] I_OUT_SCALE Platform NVM configurable, based on platform
[2:0] I_IN_SCALE Platform NVM configurable, based on platform
0A [7:0] MAX_VOUT_SUPPORTED Platform NVM configurable, based on platform
0B [7:0] MIN_VOUT_SUPPORTED Platform NVM configurable, based on platform
10 [7:0] FAULT_STATUS 00h
11 [7:0] NACK_STATUS 00h
[7:5] DECAY_CONDITIONS 000b NVM configurable
20 [4:4] DOWN_SLEW_RATE 0b NVM configurable
[3:0] UP_SLEW_RATE Platform Copied from DEFAULT_SLEW_RATE
21 [4:0] LL_ADJUST 01010b 100%
22 [7:0] VOUT_OFFSET 00h NVM configurable
23 [7:0] VID_MAX 00h Disabled
24 [7:0] VID_MIN 00h Disabled
25 [7:0] TEN_BIT_TEL_EN 00h
26 [7:0] SIXTEEN_BIT_TEL_EN 00h
27 [7:0] OCP_THRESH Platform NVM configurable, based on platform
28 [7:0] OCP_WARN_THRESH Platform NVM configurable, based on platform
[7:3] OCP_WARN_MIN_PULSE Platform NVM configurable, based on platform
29
[2:0] OCP_FAULT_DELAY Platform NVM configurable, based on platform
2A [7:0] VRHOT_THRESH 8Ch 100°C
2B [7:0] OTP_THRESH A5h 125°C, NVM configurable
[7:7] OVP_REF 0b VID, NVM configurable
[6:4] OVP_DELTA 110b 350mV, NVM configurable
2C
[3:3] UVP_REF 0b VID, NVM configurable
[2:0] UVP_DELTA 110b 350mV, NVM configurable
[7:4] PHASE_SHED_1 0001b 1 phase
2D
[3:0] PHASE_SHED_2 0001b 1 phase

40 [7:0] DEBUG_ENABLED 00h
41 [7:0] DEBUG_TEMP1_OVERRIDE 00h
42 [7:0] DEBUG_VOUT_OVERRIDE 00h
43 [1:0] DEBUG_VOUT_OVERRIDE 00b
44 [7:0] DEBUG_IOUT_OVERRIDE 00h
45 [1:0] DEBUG_IOUT_OVERRIDE 00b
46 [2:0] DEBUG_OUTPUT_OVERRIDE 000b
50 [7:0] GEN_PURPOSE_0 00h

I2CBUS COMMANDS/REGISTERS RAIL 1/2/3 (PAGE 0/1/2)
Command Code Command Name Type Bytes Page 0 Page 1 Page 2
00h PAGE RW 1 √ √ √
01h OPERATION RW 1 √ √ √
03h CLEAR_FAULTS Send 0 √ - -
15h STORE_USER_ALL Send 0 √ - -
16h RESTORE_USER_ALL Send 0 √ - -
21h VOUT_COMMAND RW 2 √ √ √
22h MFR_VOUT_TRIM RW 2 √ √ √
24h VOUT_MAX RW 2 √ √ √
2Bh VOUT_MIN RW 2 √ √ √
35h VIN_ON RW 2 √ - -
36h VIN_OFF RW 2 √ - -
38h MFR_CUR_GAIN_OFFSET_PH1 RW 2 √ - -
39h MFR_CUR_GAIN_OFFSET_PH2 RW 2 √ - -
3Ah MFR_CUR_GAIN_OFFSET_PH3 RW 2 √ - -
3Bh MFR_CUR_GAIN_OFFSET_PH4 RW 2 √ - -
3Ch MFR_CUR_GAIN_OFFSET_PH5 RW 2 √ - -
3Dh MFR_CUR_GAIN_OFFSET_PH6 RW 2 √ - -
3Eh MFR_CUR_GAIN_OFFSET_PH7 RW 2 √ - -
3Fh MFR_CUR_GAIN_OFFSET_PH8 RW 2 √ - -
40h MFR_SLOPE_SET_1PHS RW 2 √ √ √
41h MFR_SLOPE_SET_2PHS RW 2 √ √ √
42h MFR_SLOPE_SET_3PHS RW 2 √ √ -
43h MFR_SLOPE_SET_4PHS RW 2 √ - -
48h MFR_SLOPE_SET_DCM RW 2 √ √ √
49h MFR_SLOPE_SET_EXT RW 2 √ √ √
4Ah MFR_SLOPE_SET_EXT_DCM RW 2 √ - -
54h OCP_UCP_SET RW 2 √ √ √
55h VIN_OV_UV_SET RW 2 √ - -
56h IOUT_CAL_OFFSET_GAIN RW 2 √ √ √
57h MFR_CB_SATU_PI RW 2 √ √ √
58h MFR_VCAL_PI RW 2 √ √ √
59h OCP_CAL_GAIN_OFFSET RW 2 √ √ √
5Ah MFR_CS_OFFSET32 RW 2 √ - -
5Bh MFR_CS_OFFSET54 RW 2 √ - -
5Ch MFR_CS_OFFSET76 RW 2 √ - -
5Ch MFR_VIN_HYS RW 2 - √ -
5Ch MFR_IOUT3_OFFSET1_DCM RW 2 - - √
5Dh MFR_CS_OFFSET8_CS_RES RW 2 √ - -

I2CBUS COMMANDS/REGISTERS RAIL 1/2/3 (PAGE 0/1/2) (continued)
5Dh PSYS_CAL_OFFSET_GAIN RW 2 - √ -
5Dh MFR_IOUT1/2_OFFSET_DCM RW 2 - - √
5Eh MFR_TEMP_GAIN_OFFSET RW 2 √ √ √
5Fh MFR_RAIL_CTRL1 RW 2 √ √ √
60h MFR_RAIL_CTRL2 RW 2 √ √ √
61h MFR_VR_BOOT RW 2 √ √ √
62h MFR_FAST_ADC_ADDR RW 2 √ - -
63h MFR_SW_PRD_SET RW 2 √ √ √
64h MFR_FREQ_DET RW 2 √ √ √
65h MFR_PWR_DLY RW 2 √ √ √
66h MFR_PWM_MINTIME_SET RW 2 √ - -
67h MFR_MINOFF_TIME RW 2 √ √ √
68h MFR_VO_COMP_MAX RW 2 √ √ √
69h MFR_PHS_CFG RW 2 √ - -
6Ah MFR_PSI_TRIM_1 RW 2 √ - -
6Ah MFR_PSI_TRIM RW 2 - √ √
6Bh MFR_PSI_TRIM_2 RW 2 √ - -
6Ch MFR_PROTECT_CFG RW 2 √ √ √
6Dh MFR_DOWN_PLATFORM RW 2 √ √ √
6Eh MFR_DYNAMIC_CTRL RW 2 √ √ √
6Fh MFR_UVP_OVP_DELAY RW 2 √ √ √
70h MFR_APS_HYS RW 2 √ √ √
71h MFR_APS_THRESHOLD RW 2 √ √ √
72h MFR_PLATFORM_SET RW 2 √ √ √
73h MFR_DROOP_SET RW 2 √ √ √
74h MFR_APS_DECAY_TIME RW 2 √ √ √
75h OVUV_OCWARN_THRESHOLD RW 2 √ √ √
76h TOTAL_OCP_SET RW 2 √ √ √
77h MFR_SVI3_VERSION_ID RW 2 √ - -
78h MFR_SVI3_PSYS_SR_IOUT RW 2 √ - -
78h MFR_SVI3_SR_IOUT RW 2 - √ √
MFR_SVI3_VOUT_OFFSET_OTP_TH
79h RW 2 √ √ √
D
7Ah MFR_SVI3_DECAY_CONFIG RW 2 √ √ √
7Bh SVI3_CONFIG RW 2 √ - -
7Ch MFR_DEBUG RW 2 √ √ √
7Dh DIFFERENTIAL_FUNCTION RW 2 √ √ √
7Eh MFR_CTL_CFG1 RW 2 √ - -
7Fh MFR_CTL_CFG2 RW 2 √ - -
80h PROTECTION_STATUS1 R 2 √ - -
81h PROTECTION_STATUS2 R 2 √ - -
82h MFR_I2C_PASSWORD RW 2 √ - -
83h MFR_DEBUG_CFG RW 2 √ - -

I2CBUS COMMANDS/REGISTERS RAIL 1/2/3 (PAGE 0/1/2) (continued)
84h MFR_TRANS_CFG RW 2 √ √ √
85h PRODUCT_DATA_CODE RW 2 √ - -
85h CODE_REV RW 2 - √ -
85h KCS_IOUT_CUSTOM RW 2 - - √
A0h I2CBUS_ADDR R 2 √ √ √
A7h READ_VIN R 2 √ - -
A8h READ_VOUT R 2 √ √ √
A9h READ_IOUT R 2 √ √ √
AAh READ_TEMP R 2 √ √ √
AEh READ_CRC R 2 √ - -

PAGE 0 REGISTER MAP
PAGE (00h)
Format: Unsigned binary
This command provides the ability to configure, control and monitor through only one physical address
for 3 rails and the test mode.
Bits Access Bit Name Description
7:3 R/W Reserved Unused. X indicates writes are ignored and reads are always 0.
It provides the ability to configure, control and monitor through only one
physical address for 3 rails and the test mode.
3’b000: Rail 1
2:0 R/W PAGE 3’b001: Rail 2
3’b010: Rail 3
3’b011: Trim Page
3’b100: Debug page
OPERATION (01h)
OPERATION is a paged register. The OPERATION command is used to turn the device output on/off in
conjunction with input from the EN pins. The unit stays in the commanded operating mode until a
subsequent OPERATION command or a change in the state of the EN pins instructs the device to
change to another mode.
It is used to turn on/off when EN is on.
7 R/W OPERATION 1'b0: Immediate off
1'b1: Power on
CLEAR_FAULTS (03h)
The CLEAR_FAULTS command is used to clear fault bits that have been set. This command clears all
bits in all status registers simultaneously. This command is written only. There is no data byte for this
command.
STORE_USER_ALL (15h)
The STORE_USER_ALL command instructs the I2C device to copy the Page 0~Page 3 values in the
operating memory to the matching locations in the MTP. Any items in the operating memory that do not
have matching locations in the MTP are ignored. This command can be used while the device is
outputting power. This command is write only. There is no data byte for this command.
RESTORE_USER_ALL (16h)
The RESTORE_USER_ALL command instructs the I2C device to copy the Page 0~Page 3 value of the
MTP to the matching locations in the operating memory. The values in the operating memory are
overwritten by the value retrieved from the MTP. Any items in the MTP that do not have matching
locations in the operating memory are ignored. Do not use this command while the device is outputting
power or the command will be ignored. This command is write only. There is no data byte for this
command.
VOUT_COMMAND (21h)
This command is used to set the I2C mode VID command of Rail 1.

9:0 R/W VOUT_COMMAND It is used to set VID at I2C mode, 5mV/LSB.
MFR_VOUT_TRIM (22h)
This command is used to set the VOUT trim value for Rail 1.
It is used to set VOUT trim value for 3~8-phase CCM mode.
15:12 R/W 3~8-PHASE CCM 1.5625mV/LSB @VDIFF GAIN = 1
3.125mV/LSB @VDIFF GAIN = 0.5
It is used to set VOUT trim value for 2-phase CCM mode.
11:8 R/W 2-PHASE CCM 1.5625mV/LSB @VDIFF GAIN = 1
It is used to set VOUT trim value for 1-phase DCM mode.
3:0 R/W 1-PHASE DCM 1.5625mV/LSB @VDIFF GAIN = 1
VOUT_MAX (24h)
This command is used to set max Vout supported for Rail 1.
It is used to set Max Vout Supported.
7:0 R/W MAX_VOUT
Max Vout = Reg[7:0] * 20 mV
VOUT_MIN (2Bh)
This command is used to set min Vout supported for Rail 1.
It is used to set Min Vout Supported.
7:0 R/W MIN_VOUT
Min Vout = Reg[7:0] * 5 mV
VIN_ON (35h)
This command is used to set VIN on threshold.
7:0 R/W VIN_ON It is used to set Vin on threshold voltage value. 0.125V/LSB
VIN_OFF (36h)
This command is used to set VIN off threshold.

7:0 R/W VIN_OFF It is used to set Vin off threshold voltage value. 0.125V/LSB
MFR_CUR_GAIN_OFFSET_PH1 (38h)
This command is used to set single phase current report gain and offset value for Phase1.
PHASE_CURRENT_ It is used to set single phase current report gain.
15:8 R/W
GAIN Phase Current report = Ix_ADC * 103 / GAIN / 2 - OFFSET
PHASE_CURRENT_ It is used to set single phase current report offset.
7:0 R/W
OFFSET Phase Current report = Ix_ADC * 103 / GAIN / 2 - OFFSET
MFR_CUR_GAIN_OFFSET_PH2 (39h)
15:8 R/W
7:0 R/W
MFR_CUR_GAIN_OFFSET_PH3 (3Ah)
15:8 R/W
7:0 R/W
MFR_CUR_GAIN_OFFSET_PH4 (3Bh)
15:8 R/W
7:0 R/W
MFR_CUR_GAIN_OFFSET_PH5 (3Ch)
15:8 R/W
7:0 R/W

MFR_CUR_GAIN_OFFSET_PH6 (3Dh)
15:8 R/W
7:0 R/W
MFR_CUR_GAIN_OFFSET_PH7 (3Eh)
15:8 R/W
7:0 R/W
MFR_CUR_GAIN_OFFSET_PH8 (3Fh)
15:8 R/W
7:0 R/W
MFR_SLOPE_SET_1PHS (40h)
This command is used to set the slew rate and saturate time of slope compensation during 1 phase
CCM operation for Rail 1. Slope compensation provides enough noise immunity for PWM generation to
make the PWM switches stable. Slope compensation is generated by an I2C-configurable current
source and capacitor.
It is used to set cap number.
The cap number = 16 – {49h[1:0], 40h[15:14]}, 1.9pF per cap.
15:14 R/W 16 – CAP
For example, if the EXTEND_BIT_1PH (49h[1:0]) is 2'b01, 40h[15:14] is
2'b01, the capacitor number is 16 - 4'b0101 = 11.
13:8 R/W CURRENT_SOURCE It is used to set charge current source of slope compensation. 0.25μA/LSB.
7:0 R/W SATURATE_TIME It is used to set charge saturate time of slope compensation. 20ns/LSB.
CCM operation for Rail 1.
15:14 R/W 16 – CAP

15:14 R/W 16 – CAP
15:14 R/W 16 – CAP
15:14 R/W 16 – CAP
15:14 R/W 16 – CAP
15:14 R/W 16 – CAP
15:14 R/W 16 – CAP
MFR_SLOPE_SET_DCM (48h)
DCM operation for Rail 1.
15:14 R/W 16 – CAP
The cap number = 16 – {4Ah[1:0], 48h[15:14]}, 1.9pF per cap.
MFR_SLOPE_SET_EXT (49h)
This command is used as extend bit of cap numbers for 1~8 phase CCM slope compensation of Rail 1.
15:14 R/W EXTEND_BIT_8PH It is used as extend bit of cap numbers for 8 phase CCM.
MFR_SLOPE_SET_EXT_DCM (4Ah)
This command is used as extend bit of cap numbers of 1 phase DCM slope compensation and Initial
slope of Rail 1.

MFR_SLOPE_SR_INI
7:2 R/W Initial slope for start-up.5mV/LSB
TI
EXTEND_BIT_1PH_D
1:0 R/W It is used as extend bit of cap numbers for 1 phase DCM.
CM
OCP_UCP_SET (54h)
This command is used to set phase current limit level and min off time of pulse triggered by UCP for
Rail 1.
15 R/W Reserved Unused. X indicates writes are ignored and reads are always 0.
14:12 R/W UCP_BLANK_TIME The min off time of pulse triggered by UCP, 40ns/LSB.
PER_PHASE_UC_LE
11:6 R/W It is used to set phase under-current limit level. With 1.24V bias, 20mV/LSB.
VEL
PER_PHASE_OC_LE
5:0 R/W It is used to set phase over-current limit level. With 1.24V bias, 20mV/LSB.
VEL
VIN_OV_UV_SET (55h)
This command is used to set VIN OV and UV warning threshold.
15:8 R/W VIN_OV It is used to set Vin OV threshold voltage value. 0.125V/LSB
7:0 R/W VIN_UV_WARN It is used to set Vin UV warning threshold voltage value. 0.125V/LSB
IOUT_CAL_OFFSET_GAIN (56h)
This command is used to set IOUT report gain and offset for Rail 1.
It is used to set IOUT report offset.
15:9 R/W IOUT_OFFSET
IOUT report = IMON_ADC * 256 / GAIN + OFFSET
It is used to set IOUT report gain.
Note:
Select Custom=8A or 16A
8:0 R/W IOUT_GAIN
Custom=8A:
Kcs=5μA/A, Iout Report Gain=51; Kcs=10μA/A, Iout Report Gain=102
Custom=16A:
MFR_CB_SATU_PI (57h)
This command is used to set current balance gain and saturation value for Rail 1.
15:12 R/W TUNE_NSATU It is used to set the negative saturation value. 10ns/LSB
11:8 R/W TUNE_PSATU It is used to set the positive saturation value. 10ns/LSB
7:0 R/W MFR_CB_PI It is used to set PI parameter for current balance loop of Rail 1.
MFR_VCAL_PI (58h)
This command is used to set frequency loop's and DC loop's PI value for Rail 1.

15:8 R/W MFR_FS_LOOP_PI It is used to set PI parameter for FS calibration loop of Rail 1.
6:0 R/W MFR_VCAL_PI It is used to set PI parameter for DC calibration loop of Rail 1.
OCP_CAL_GAIN_OFFSET (59h)
This command is used to set OCP/OCP WARNING threshold gain and offset value for Rail 1.
It is used to set OCP/OCP WARNING Gain.
15:8 R/W OCP_GAIN
OCP_ANA = THRESHOLD * GAIN / 128 - OFFSET
7:4 R/W OCP_OFFSET It is used to set OCP threshold offset.
OCP_WARN_OFFSE
3:0 R/W It is used to set OCP WARNING threshold offset.
T
MFR_CS_OFFSET32 (5Ah)
This command is used to set phase offset during current balance calculation for phase 2 and phase 3.
15:8 R/W MFR_CS_OFFSET2 It is used to set phase offset during current balance calculation for phase 2.
MFR_CS_OFFSET54 (5Bh)
MFR_CS_OFFSET76 (5Ch)
MFR_CS_OFFSET8_CS_RES (5Dh)
This command is used to set phase offset during current balance calculation for phase 8 and
phase1~8's Rcs (internal resistor from CS pin to CS_SUM).
It is used to select phase 8's Rcs.
15 R/W RCS_SEL_PH8 1'b0: 0.75kohm
1'b1: 1.5kohm
14 R/W RCS_SEL_PH7
1'b0: 0.75kohm

1'b1: 1.5kohm
1'b1: 1.5kohm
1'b1: 1.5kohm
1'b1: 1.5kohm
1'b1: 1.5kohm
1'b1: 1.5kohm
1'b1: 1.5kohm
MFR_TEMP_GAIN_OFFSET (5Eh)
This command is used to set temperature report gain and offset for Rail 1.
It is used to set temp report offset.
15:8 R/W TEMP_OFFSET
Temp report = TEMP_ADC * GAIN / 128 + OFFSET
It is used to set temp report gain.
7:0 R/W TEMP_GAIN
MFR_RAIL_CTRL1 (5Fh)
This command is used to set enable bits for some functions of Rail 1.
It's used to enable digital filter of VID DAC when decay down.
15 R/W DIGTAL_FILTER_EN 1’b0: Enable digital filter when decay down
1’b1: Disable
Mode selection bit to exit APS and enter full-phase operation once phase
current limit trigger.
14 R/W OC_EXIT_APS_SEL
1'b0: 1phase DCM or CCM
1'b1: All state
Enable bit to latch frequency loop for a certain time when transient events
occur.
13 R/W MFR_FS_LATCH_EN
1'b0: Disable
1'b1: Enable
Enable bit of frequency loop.
12 R/W MFR_FS_LOOP_EN
1'b0: Disable

1'b1: Enable
It's used to enable VID analog filter only at VID slew down.
MFR_VID_FILTER_E
11 R/W 1'b0: Disable
N
1'b1: Enable
Enable bit of VID analog filter, which is used in the condition when VID is
ramping down and interrupted by a VID up command.
10 R/W MFR_DAC_CMP_EN
1'b0: Disable
1'b1: Enable
It is used to select the VID control mode.
9 R/W VID_MODE_SEL 1'b0: SVI3 Mode
1'b1: I2C Mode
Enable bit to reduce PWM on time when the rail works in DCM (Discontinuous
Conduction Mode). The function is used to reduce the output ripple in DCM.
8 R/W DCM_TON_REDUCE
1'b0: Disable
1'b1: Enable
Enable bit to exit APS and enter full-phase operation once phase current limit
trigger.
7 R/W OC_EXIT_APS_EN
1'b0: Disable
1'b1: Enable
DC calibration loop in DCM mode enable bit.
MFR_VCAL_DCM_E
6 R/W 1'b0: Disable
N
1'b1: Enable
DC calibration loop enable bit.
5 R/W MFR_VCAL_EN 1'b0: Disable
1'b1: Enable
Current balance function enable bit.
4 R/W MFR_CB_EN 1'b0: Disable
1'b1: Enable
It is used to set PSI control mode.
3 R/W SVI3_I2C_PSI_SET 1'b0: Rail's power state controlled by SVI3 command
1'b1: Rail's power state controlled by I2C register 5Fh[2:0]
It is used to set PSI state by I2C.
3'b000: PSI0
3'b001: PSI1
3'b002: PSI2
2:0 R/W I2C_PSI_SET 3'b003: PSI3
3'b004: PSI4 (Not support)
3'b007: PSI7
MFR_RAIL_CTRL2 (60h)
This command is used to set enable bits for some function of Rail 1.
It is used to select the feedback for DC Loop.
15 R/W DCL_FB_SEL 1'b0: VFB
1'b1: VOUT
14 R/W MFR_APS_FORCE It is used to force VR into APS without considering the PSI state.
1'b0: Disable
1'b1: Enable
It is used to enable VID analog filter at DVID (VID UP and VID slew down).
13 R/W DVID_FILTER_EN 1'b0: Disable
1'b1: Enable
It is used to select the PWM behavior when detect the high frequency to force
into full phases in PSI7 state.
12 R/W FSW_HIGH_PWM
1'b0: HIZ-LOW
1'b1: HIZ-HIGH
It is used to force VR into full phases when detect the high frequency in PSI7
HIGH_FSW_EXIT_AP state.
11 R/W
S 1'b0: Disable
1'b1: Enable
It is used to enable phase current limit during soft-start.
10 R/W SS_OC_EN 1'b0: Disable
1'b1: Enable
It is used to set VID filter time constant for Rail 1, which is the VID output
analog filter for VID slew down transitions.
9:8 R/W VID_FILTER_SEL 2'b00: 2.35us

2'b01: 4.7us
2'b10: 7.05us
2'b11: 9.4us
7:4 R/W VID_DATA_UPDATE It is used to set time for each VID update, VID update time = ([7:4] +1)*100ns.
3:0 R/W SHUTDOWN_LEVEL It is used to set VID shutdown level. 20mV/LSB
MFR_VR_BOOT (61h)
This command is used to set the I2C mode and SVI3 mode boot voltage of Rail 1.
7:4 R/W I2C_VBOOT It is used to set the I2C mode default voltage, default voltage=[7:0]*10mV
It is used to set the default voltage.
1h = 0.500 V
2h = 0.600 V
3h = 0.700 V
4h = 0.800 V
5h = 0.900 V
6h = 1.000 V
7h = 1.100 V
3:0 R/W SVI3_VBOOT 8h = 1.200 V
9h = 1.300 V
Ah = 1.400 V
Bh = 1.500 V
Ch = 1.800 V
Dh = 2.000 V
Eh = 2.500 V
Fh = 2.800 V
0h = 0V
MFR_FAST_ADC_ADDR (62h)

This command is used to set the I2C ADDR and fast ADC configuration for IC.
It is used to enable fast ADC clock in other PSI states except PSI7.
FAST_ADC_GATE_C
15 R/W 1’b0: Disable fast ADC clock
LK
1’b1: Enable fast ADC clock
It is used to enable fast ADC power in other PSI states except PSI7.
FAST_ADC_POWER
14 R/W 1’b0: Disable fast ADC power
_EN
1’b1: Enable fast ADC power.
It is used to enable fast APS of rail1.
13 R/W MFR_FAST_APS_EN 1’b0: Disable fast APS
1’b1: Enable fast APS
It is used to jump the ADC sample of the rail with EN low.
12 R/W ADC_JUMP_EN 1’b0: Disable jump function
1’b1: Enable jump function
It is used to set fast ADC wake delay time when fast ADC enable and ADC
power enable. (Default set 4 – 5μs)
4’b0000: 0us
4’b0001: 0 – 1μs
4’b0010: 1 – 2μs
4’b0011: 2 – 3μs
4’b0100: 3 – 4μs
4’b0101: 4 – 5μs
11:8 R/W ADC_WAKE_DELAY 4’b0110: 5 – 6μs
4’b0111: 6 – 7μs
4’b1000: 7 – 8μs
4’b1001: 8 – 9μs
4’b1010: 9 – 10μs
4’b1011: 10 – 11μs
4’b1100: 11 – 12μs
4’b1101: 12 – 13μs
4’b1110: 13 – 14μs
4’b1111: 14 – 15μs
It is used to select setting I2C address by register or ADDR pin.
7 R/W MFR_ADDR_SET 1'b0: Pin set
1'b1: Register set
6:0 R/W MFR_ADDR_I2CBUS It is used to set I2CBus address by register.
MFR_SW_PRD_SET (63h)
This command is used to set the PWM period for Rail 1.
9:0 R/W MFR_SW_PRD_SET It is used to set period for Rail 1. 10ns/LSB
MFR_FREQ_DET (64h)
This command is used to set the frequency detection threshold for Rail 1.
HIGH_FREQ_DET_E Enable bit of high frequency detection.
15 R/W
N 1'b0: Disable
1'b1: Enable
HIGH_FREQ_DET_S
14:8 R/W It is used to set high frequency detection value. 20ns/LSB
ET
Enable bit of low frequency detection.
LOW_FREQ_DET_E
7 R/W 1'b0: Disable
N
1'b1: Enable
LOW_FREQ_DET_S
6:0 R/W It is used to set low frequency detection value. 80ns/LSB
ET
MFR_PWR_DLY (65h)
This command is used to set the delay time for Rail 1.
When Intelli-Phase PFO is enabled (Page0/1/2. 74H. bit[13]=0), it is used to
set STB pull high or low during decay down entering PSI6.
15 R/W PS6_LOW_EN
1’b0: STB pull high
1’b1: STB pull low
14:13 R/W PG_DELAY_TIME It is used to set PGD assertion delay time for all rails, 4μs/LSB.
12:9 R/W INITIAL_DELAY It is to set initial delay time for initialization (for all rails). 100μs/LSB
8:6 R/W PS6_EXIT_DLY It is used to set PS6 EXIT delay time. 20μs/LSB
5:0 R/W EN_DELAY It is used to set EN delay time. 20μs/LSB
MFR_PWM_MINTIME_SET (66h)
This command is used to set the PWM relative time for Rail 1.
14:10 R/W MFR_MINTON It is used to set minimum on time. 5ns/LSB
TMIN_LOW_EXIT_HI
9:5 R/W It is used to set minimum low time from HIZ to HIGH; 10ns/LSB
Z
4:0 R/W TRI_STATE_DELAY It is used to set minimum low time from high to HIZ; 10ns/LSB
MFR_MINOFF_TIME (67h)
It is used to enable anti slope leakage function.
ANTI_SLOPE_LEAKA
GE
1'b1: Enable
SLOPE_DIS_TIME_C
14:12 R/W It is used to set slope discharge time in CCM. 10ns/LSB.
CM
11:7 R/W MFR_BLANK_TIME It is used to set PWM blank time. 10ns/LSB
6:0 R/W MFR_MINOFF_TIME It is used to set PWM minimum off time. 10ns/LSB
MFR_VO_COMP_MAX (68h)
This command is used to set the VO_COMP max value for Rail 1.

For internal debug.
15 R/W INTERNAL_DEBUG
Please set to 0 for normal usage.
For internal debug.
It is used to enable PWM pull up self-check.
13 R/W MFR_PWM_CHK 1’b0: Disable
1’b1: Enable
12:8 R/W ADC_HOLD_TIME It is used to set ADC hold time for two ADC sample. 100ns/LSB
7:0 R/W VO_COMP_MAX It is used to set the VO_COMP max value. 0.3125mV/LSB
MFR_PHS_CFG (69h)
This command is used to set the phase number for each rail.
For internal debug.
For internal debug.
For internal debug.
It is used to enable Rail2 and Rail3 with no phase setting.
12 R/W PHASE_R2_R3_EN 1'b0: Disable, turn off Rail2 and Rail3 with no phase setting
1'b1: Enable Rail2 and Rail3 even if no phase setting
It is used to enable Rail1 with no phase setting.
11 R/W PHASE_R1_EN 1'b0: Disable, turn off Rail1 with no phase setting
1'b1: Enable Rail1 even if no phase setting
It is used to enable if Rail3 can be as SVI3 target or not with no phase setting.
10 R/W PHASE_R3_SVI3_EN 1'b0: Disable
1'b1: Enable, Rail3 can be as SVI3 target
It is used to enable if Rail2 can be as SVI3 target or not with no phase setting.
9 R/W PHASE_R2_SVI3_EN 1'b0: Disable
1'b1: Enable, Rail2 can be as SVI3 target
Enable bit for only Rail3 POL with SVI3.
8 R/W POL_EN 1'b0: Disable
1'b1: Enable
It is used to set phase number of rail3.
2'b00: no phase
7:6 R/W PHASE_NUM_R3 2'b01: 1 phase (phase number rail1 <8)
2'b10: 2 phase (phase number rail1 <7)
2'b11: 2 phase (phase number rail1 <7)
2'b00: no phase
5:4 R/W PHASE_NUM_R2 2'b01: 1 phase (phase number rail1 + rail3 <8)
2'b10: 2 phase (phase number rail1 + rail3 <7)
2'b11: 3 phase (phase number rail1 + rail3 <6)
3:0 R/W PHASE_NUM_R1
4'b0000: no phase

4'b0001: 1 phase
4'b0010: 2 phase
4'b0011: 3 phase
4'b0100: 4 phase
4'b0101: 5 phase
4'b0110: 6 phase
4'b0111: 7 phase
4'b1000: 8 phase
Others: 8 phase
MFR_PSI_TRIM_1 (6Ah)
This command is used to set the VO_COMP initial value for Rail 1.
15:12 R/W 3-PHASE CCM It is used to set VO_COMP initial value for 3-phase CCM mode. 2.5mV/LSB
3:0 R/W 1-PHASE DCM It is used to set VO_COMP initial value for 1-phase DCM mode. 2.5mV/LSB
MFR_PSI_TRIM_2 (6Bh)
MFR_PROTECT_CFG (6Ch)
This command is used to set the protection mode for Rail 1.
For internal debug.
Enable bit for VIN UV/OV Protection.
VIN_PROTECTION_E
N
1'b1: Enable
Enable bit for VIN UVLO latch-off mode.
9 R/W VIN_UVLO_LATCH 1'b0: Hiccup mode
1'b1: Latch-off mode
Enable bit for VIN OVP latch-off mode.
8 R/W VIN_OVP_LATCH 1'b0: Hiccup mode
1'b1: Latch-off mode
It is used to enable enter full phase when phase current limit is triggered in
PS1/3_OC_ENTER_F PSI1/3.
7 R/W
ULLPHASE 1'b0: Disable
1'b1: Enable
Enable bit for shedding to target phase number directly.
SHEDDING_PHASE_
6 R/W 1'b0: Disable
FAST
1'b1: Enable
Enable bit for Over Temperature Protection.
3 R/W OTP_EN 1'b0: Disable
1'b1: Enable
Enable bit for Under Voltage Protection.
2 R/W UVP_EN 1'b0: Disable
1'b1: Enable
Enable bit for Over Current Protection.
1 R/W OCP_EN 1'b0: Disable
1'b1: Enable
Enable bit for Over Voltage Protection.
0 R/W OVP_EN 1'b0: Disable
1'b1: Enable
MFR_DOWN_PLATFORM (6Dh)
This command is used to set VID down platform and PSI3 DVID behavior for Rail 1.
SLOPE_DIS_TIME_D
15:12 R/W It is used to set slope discharge time in DCM. 10ns/LSB
CM
It is used to Enable VID down platform.
11 R/W DOWN_PLAT_EN 1'b0: Disable
1'b1: Enable
10:8 R/W LEVEL_DELAY_TIME It is used to set down platform time, 20μs/LSB.
VID_ZERO_DOWN_P
7:2 R/W It is used to set down platform voltage, 5mV/LSB.
LATFROM
It is used to select special DVID behavior in PSI3.
1 R/W PSI3_UP_PSI1_EN 1’b0: DVID up with entering PSI0 state, DVID down with entering PSI1 state
1’b1: DVID up and down with entering PSI1 state
It is used to Enable special DVID behavior in PSI3.
0 R/W PSI3_UP_EN 1’b0: Disable, DVID with entering PSI0 state
1’b1: Enable, DVID behavior in PSI3 depends on 6Ch. bit[1]
MFR_DYNAMIC_CTRL (6Eh)
This command is used to set dynamic operation control for Rail 1.
APS_RECOVERY_H It is used to set hold time for recovery APS.
15:11 R/W
OLDTIME 1 ADC sampling period/LSB
DC_CB_HOLDTIME_ It is used to set hold time for DC calibration loop/current balance loop.
10:6 R/W
SET 1 ADC sampling period/LSB
It is used to determine to immediately recovery APS once DVID or PSI
change is finished.
5 R/W DVID_PSI_DIS_APS
1'b0: Enable, immediately recovery APS
1'b1: Disable, first hold full phase and then recovery APS (Hold time of full

phase is set by 6E. bit[15:11])
It is used to determine to immediately recovery APS once the behavior, that
phase1 OC limit triggers entering full phase, is finished.
4 R/W OC1_DIS_APS 1'b0: Enable, immediately recovery APS
high frequency detection triggers entering full phase, is finished.
HIGH_LOW_FS_DIS_
3 R/W 1'b0: Enable, immediately recovery APS
APS
It is used to set if disable DC calibration loop and current balance loop for a
certain time or not when phase1 OC limit happens.
2 R/W OC1_DC_CB
1'b0: Keep DC and CB loop Enable
1'b1: Disable
DVID_PSI_DIS_DC_ certain time or not when VID or PSI change happens.
1 R/W
CB 1'b0: Keep DC and CB loop Enable
1'b1: Disable
HIGH_LOW_FS_DIS_ certain time or not when high or low frequency is detected.
0 R/W
DC_CB 1'b0: Keep DC and CB loop Enable
1'b1: Disable
MFR_UVP_OVP_DELAY (6Fh)
This command is used to set UVP and OVP delay time for Rail 1.
11:6 R/W UVP_DELAY It is used to set UVP delay time. 20μs/LSB
5:0 R/W OVP_DELAY It is used to set OVP delay time. 200ns/LSB
MFR_APS_HYS (70h)
This command is used to set APS phase adding hysteresis for Rail 1.
7:0 R/W MFR_APS_HYS It is used to set phase adding hysteresis. 1.5625mV/LSB
MFR_APS_THRESHOLD (71h)
This command is used to set APS threshold for Rail 1.
15:8 R/W APS_CCM_TH It is used to set threshold for CCM. 1.5625mV/LSB
7:0 R/W APS_DCM_TH It is used to set threshold for 1DCM to 1CCM. 1.5625mV/LSB
MFR_PLATFORM_SET (72h)
This command is used to set phase under-current limit function and VID ramping up platform
parameters for Rail 1.
It is used to set UCP function enable.
14 R/W UCP_EN 1'b0: Disable
1'b1: Enable
13:8 R/W UCP_ONTIME It is used to set PWM on time when UCP happened. 10ns/LSB
PLATFORM_VOLTA It is used to set the excess platform voltage over the target VID when VID
7:5 R/W
GE ramps up. 5mV/LSB
4:0 R/W PLATFORM_TIME It is used to set platform time. 1μs/LSB
MFR_DROOP_SET (73h)
This command is used to set droop parameter for Rail 1.
It is used to select power mode of droop current block for Rail 1.
CUR_SNS_BLOCK_S
14 R/W 1'b0: Low power mode
EL
1'b1: High power mode
It is used to select AC or DC droop.
AC_DC_DROOP_SE
13 R/W 1'b0: DC droop
L
1'b1: AC droop
It is used to reduce biasing current (reduce AC droop bandwidth).
12 R/W BIAS_CUR_REDUCE 1'b0: Enable
1'b1: Disable
It is used to increase compensation cap (reduce AC droop bandwidth).
COMP_CAP_INCREA
11 R/W 1'b0: Enable
SE
1'b1: Disable
It is used to set current mirror ratio of Transient Droop.
DIFFERENTIAL_CM_
10 R/W 1'b0: 1*IDROOP CM gain
SET
1'b1: (1/2)*IDROOP CM gain
It is used to set 1st current mirror ratio of IDROOP.
IDROOP_1ST_CM_S 2'b00: 1/16

9:8 R/W 2'b01: 1/8
ET
2'b10: 1/4
2'b11: 1/2
It is used to short the first half resistors.
HALF_RES_SHORT_
7 R/W 1'b0: Disable
EN
1'b1: Enable
6:0 R/W RDROOP_SET It is used to set DC droop resistor value. 15.625Ω/LSB
MFR_APS_DECAY_TIME (74h)
This command is used to set APS delay time, decay blank time and PFO function for Rail 1.

For internal debug.
For internal debug.
It is used to enable Intelli-Phase PFO function.
INTELLI-
13 R/W 1’b0: Enable
PHASE_PFO_EN
1’b1: Disable
It is used to set blank time of comp signal when decay down.
3’b000, 3’b001: no delay time
3’b010: 200ns
DECAY_BLANK_TIM 3’b011: 300ns
12:10 R/W
E 3’b100: 400ns
3’b101: 500ns
3’b110: 600ns
3’b111: 700ns
It is used to set APS delay time to drop 1phase.
9:0 R/W APS_DELAY_TIME
1 ADC sample cycle/LSB
OVUV_OCWARN_THRESHOLD (75h)
This command is used to set UV/OV/OCWARN threshold for Rail 1.
It is used to set over current warning threshold level.
OCWARN_THRESHO 00h = Disabled
15:8 R/W
LD OCWARN Threshold = 2* MAX_CURRENT* (Reg[15:8]/ 256) A
Note: MAX_CURRENT = 3FFh of selected current scale.
It is used to reference of over-voltage protection threshold.
7 R/W OVP_REF
0b = VID, 1b = VID_MAX
It is used to set delta value of over-voltage protection threshold.
6:4 R/W OVP_DELTA 000b = Disabled
OVP Delta = Reg[6:4] * 50 + 50 mV
It is used to reference of under-voltage protection threshold.
3 R/W UVP_REF
0b = VID, 1b = VID_MIN
It is used to set delta value of under-voltage protection threshold.
2:0 R/W UVP_DELTA 000b = Disabled
UVP Delta = Reg[2:0] * 50 + 50 mV
TOTAL_OCP_SET (76h)
This command is used to set OCP threshold and delay time for Rail 1.
It is used to set over current protection threshold level.
00h = Disabled (no OCP protection)
15:8 R/W OCP_THRESHOLD
OCP Threshold = 2* MAX_CURRENT* (Reg[15:8]/ 256) A
Note: MAX_CURRENT = 3FFh of selected current scale
OCP_WARN_MIN_P It is used to set minimum asserted pulse width of OCP_WARN signal.
7:3 R/W
ULSE Minimum pulse = Reg[7:3] * 500ns
It is used to set continuous time that current must exceed OCP_THRESH
before triggering fault.
2:0 R/W OCP_FAULT_DELAY
000b = Instantaneous fault
Fault delay = Reg[2:0] * 5μs

MFR_SVI3_VERSION_ID (77h)
This command is used to set SVI3 related parameters for Rail 1.
It is used to set the version of SVI3 for which the slave is compliant. Equal to
15:8 R/W MFR_SVI3_VERSION
x in Rev. x.yy of Spec.
Indicates the type of the target.
7:5 R/W TYPE_ID
000b = Type 1: Multi-Phase Step-Down.
Indicates the manufacturer of the slave/controller.
4:0 R/W MFG_ID 00h = AMD (Eval Platform)
02h = Monolithic Power Systems
MFR_SVI3_PSYS_SR_IOUT (78h)
15:8 R/W MODEL_ID It is used to set unique model code defined by manufacturer.
Psys scale, programmed at platform level (NVM, resistor strap, etc.)
000b = Custom Scale / Reserved
001b = 32W (0.03125W/LSB)
010b = 64W (0.0625W/LSB)
7:5 R/W PSYS_SCALE 011b = 128W (0.125W/LSB)
100b = 256W (0.25W/LSB)
101b = 512W (0.5W/LSB)
110b = 1024W (1W/LSB)
111b = 2048W (2W/LSB)
It is used to set default slew rate programmed at platform level (NVM, resistor
strap, etc.)
00b = 2.5 mV/μs
4:3 R/W BOOT_SR
01b = 10 mV/μs
10b = 20 mV/μs
11b = 40 mV/μs
Output current scale, programmed at platform level (NVM, resistor strap, etc.)
001b = 32A (0.03125A/LSB)
010b = 64A (0.0625A/LSB)
2:0 R/W I_OUT_SCALE 011b = 128A (0.125A/LSB)
100b = 256A (0.25A/LSB)
101b = 512A (0.5A/LSB)
110b = 1024A (1A/LSB)
111b = 2048A (2A/LSB)
MFR_SVI3_VOUT_OFFSET_OTP_THD (79h)
It is used to set default output voltage offset.
15:8 R/W MFR_VOUT_OFFSET 00h = Disabled
Others = Reg[7:0]*5 – 250mV
It is used to set default over temperature protection threshold.
7:0 R/W MFR_OTP_THRESH 00h = Disabled
Others = Reg[7:0] - 40°C

MFR_SVI3_DECAY_CONFIG (7Ah)
IIN scale, programmed at platform level (NVM, resistor strap, etc.)
001b = 4A (0.00390625A/LSB)
010b = 8A (0.0078125A/LSB)
15:13 R/W SCALE_IIN 011b = 16A (0.015625A/LSB)
100b = 32A (0.03125A/LSB)
101b = 64A (0.0625A /LSB)
110b = 128A (0.125A/LSB)
111b = 256A (0.25A/LSB)
For internal debug.
For internal debug.
For internal debug.
For internal debug.
For internal debug.
For internal debug.
It is used to set default decay condition in PSI0, PSI1 and PSI2 (or equivalent
MFR_DECAY_MODE states when in PSI7).
3 R/W
_PSI0/1/2 1’b0: Disable
1’b1: Enable decay
It is used to set default decay condition in PSI3 (or equivalent states when in
MFR_DECAY_MODE PSI7).
2 R/W
_PSI3 1’b0: Disable
It is used to set default decay condition in PSI6 or when PWR_ENABLE is de-
MFR_DECAY_MODE asserted.
1 R/W
_PSI6/ENOFF 1’b0: Disable
It is used to set default down slew rate.
MFR_DOWN_SLEWR
0 R/W 1’b0: Down slew rate = Up slew rate
ATE
1’b1: Down slew rate = 1/4 Up slew rate
SVI3_CONFIG (7Bh)
This command is used to set SVI3 related parameters.
If VR detection SVTI every time VDDIO power on or only the first time VDDIO
TERMINAL_CHK_SE power on.
15 R/W
L
1’b0: Every time VDDIO recycling.

1’b1: Only detection one time.
If TELEMETRY should be acked if TELEM_REQ command is sent before
TELEM_PROCESS_S previous telemetry finish.
14 R/W
EL 1’b0: NACK
1’b1: ACK
For internal debug.
For internal debug.
Please always set to 0 for normal usage.
For internal debug.
For internal debug.
It is an enable bit to determine if VR enter low power mode when low power
mode main enable bit (7BH. bit[7]) is 1 and Reset_L pulling low happens at
LOW_PWR_SEL_RE PSI6 state or EN low state.
9 R/W
SET_L
1'b0: Disable
1'b1: Enable
It is an enable bit to determine if VR enter low power mode when low power
mode main enable bit (7BH. bit[7]) is 1 and SVC timeout happens at PSI6
LOW_PWR_SEL_SV state or EN low state.
8 R/W
C_TIMEOUT
1'b0: Disable
1'b1: Enable
It is the main enable bit to determine if VR is able to enter low power mode
when conditions meet.
7 R/W LOW_PWR_EN
1'b0: Disable
1'b1: Enable
It is used to debug terminal slave and this bit only active when 7Bh.bit[5] is 1.
6 R/W TERMINAL_DEBUG 1’b0: No terminal on this controller
1'b1: Last rail is forced as terminal slave
It is used to debug terminal slave.
5 R/W TERMINAL_EN_I2C 1’b0: Terminal slave is determined by external connection
1'b1: Terminal slave is determined by 7Bh.bit[6]
It is used to set if VR support PSYS telemetry or not.
4 R/W PSYS_TELEM_SUP 1’b0: VR doesn’t support PSYS telemetry
1’b1: VR supports PSYS telemetry
It is used to set if VR support IIN telemetry or not.
3 R/W IIN_TELEM_SUP 1’b0: VR doesn’t support IIN telemetry
1’b1: VR supports IIN telemetry
It is used to set if VR support VIN telemetry or not.
2 R/W VIN_TELEM_SUP 1’b0: VR doesn’t support VIN telemetry
1’b1: VR supports VIN telemetry
If the second ACK is produced before the first ACK packet finished
transmitting.
1 R/W ACK_LIVE_MODE Special mode, please set to 1'b0 for normal case.
1'b0: Not override
1'b1: The previous ACK packet will be overridden by the later ACK.
0 R/W SVI3_CRC_IGNORE Enable bit of ignoring CRC error.

Special mode, please set to 1'b0 for normal case

1'b0: Disable
1'b1: Enable
MFR_DEBUG (7Ch)
This command is used to set IMON related parameters and some other functions for Rail 1.
It is used to enable DLL calculation module.
MFR_SDM_FRAC_E
N
1'b1: Enable
It is used to select first fast ADC result or second fast ADC result after fast
FAST_ADC_RESULT ADC power up in APS.
14 R/W
_SEL 1'b0: Use first ADC result for APS
1'b1: Remove first ADC result and use second ADC result for APS
It is used to set DCM slope to CCM slope updated time.
MFR_VID_UP_UPDA
13 R/W 1'b0: Update immediately but affect with next PWM
TE_SLOPE
1'b1: After next PWM
It is used to set APS phase adding behavior for Rail 1.
APS_ADD_PHASE_B
12 R/W 1'b0: HIZ-LOW to add one phase
EHAVIOR
1'b1: HIZ-HIGH to add one phase
It is used to set Vdiff gain for Rail 1.
11 R/W VDIFF_GAIN_R1 1'b0: 1
1'b1: 0.5
It is used to set RVP level for Rail 1.
10 R/W RVP_SET_RAIL1 1'b0: 160mV
1'b1: 80mV
It is used to set IMON resistor for Rail 1.
2'b00: 4k
9:8 R/W IMON_RES_SET_R1 2'b01: 8k
2'b10: 16k
2'b11: 32k
It is used to set IMON current mirror gain and IMON_OCP current mirror gain
for Rail 1.
7:6 R/W IMON_GAIN_SET_R1 2'b00: 1/4 IMON current mirror gain 1/8 IMON_OCP current mirror gain
2'b01: 1/8 IMON current mirror gain 1/16 IMON_OCP current mirror gain
It is used to set OCP resistor for Rail 1.
2'b00: 5k
5:4 R/W IMON_OC_RES_SET 2'b01: 10k
2'b10: 20k
2'b11: 40k
For internal debug.
1It is used to select IMON trim data for Rail 1.
3'b000: 1/4 32k trim data
2:0 R/W IMON_TRIM_SET_R1 3'b001: 1/8 32k trim data

3’b100: 1/8 4k trim data
3’b101: 1/32 8k trim data
Others: 1/4 32k trim data
DIFFERENTIAL_FUNCTION (7Dh)
This command is used to set Transient Droop function for Rail 1.
It is used to enable Transient Droop.
12 R/W FUNCTION_EN 1'b0: Enable
1'b1: Disable
Set the resistor value of Transient Droop, which is used to adjust the voltage
11:8 R/W SET_RESISTOR
added to N and P-input side. 100Ω/LSB
It is used to select the filter type for N-input side (VFB).
7 R/W SELECT_N_FILTER 1'b0: Fast
1'b1: Slow
It is used to set the filter time for N-input side (VFB).
6:4 R/W N_FILTER_TIME when bit[7] =1, filter time = 4us*(7-bit[6:4]);
when bit[7] =0, filter time = 20ns*(7-bit[6:4]);
It is used to select the filter type for P-input side (VREF).
3 R/W SELECT_P_FILTER 1'b0: Fast
1'b1: Slow
It is used to set the filter time for P-input side (VREF).
2:0 R/W P_FILTER_TIME when bit[3] =1, filter time = 4us*(7-bit[2:0]);
MFR_CTL_CFG1 (7Eh)
This command is used to set control configuration for IC.
15:14 R/W MFR_DEBUG2 It is used for internal debug.
It is used to add 0.5 divider on sensed Temp pin for all rails.
TEMP_SENSE_DIVID
13 R/W 1'b0: Without 0.5 divider
ER
1'b1: With 0.5 divider
It is used to set OV/UV Vdiff gain for Rail 3.
VDIFF_GAIN_OVUV_
12 R/W 1'b0: 1
R3
1'b1: 0.5
VDIFF_GAIN_OVUV_
11 R/W 1'b0: 1
R2
1'b1: 0.5
VDIFF_GAIN_OVUV_
10 R/W 1'b0: 1
R1
1'b1: 0.5
It is used select BG chop frequency.
MFR_BG_CHOP_MO
9:8 R/W 2b'00: Disable
DE 2b'01: 125kHz
2b'10: 250kHz

2b'11: 500kHz
It is used to enable MTP fault record function. The function is to record fault
MFR_FAULT_RECO information in MTP when fault happens.
7 R/W
RD_EN 1'b0: Disable
1'b1: Enable
It is used to clear last fault information in MTP.
CLEAR_LAST_FAUL
6 R/W 1'b0: Disable
T_EN
1'b1: Enable
It is used to enable Delay-line function module in PSI3 state.
5 R/W MFR_DLL_EN_PSI3 1'b0: Enable
1'b1: Disable
It is used to enable Delay-line function.
4 R/W MFR_DLL_EN 1'b0: Disable
1'b1: Enable
It is used to enable storing trimming registers.
MFR_STORE_TRIM_
3 R/W 1'b0: Disable
REG_EN
1'b1: Enable
It is used to enable copy MTP to register when enable on.
MFR_MTP_COPY_E
2 R/W 1'b0: Disable
N
1'b1: Enable
It is used to enable ignoring temperature fault while start-up.
INGORE_TEMP_FAU
1 R/W 1'b0: Disable
LT_START
1'b1: Enable
It is used to enable ignoring VIN fault while start-up.
INGORE_VIN_FAULT
0 R/W 1'b0: Disable
_START
1'b1: Enable
MFR_CTL_CFG2 (7Fh)
This command is used to set control configuration for IC.
It is used to enable OVP block delay time after DVID finish.
OVP_DELAY_EN_DV
15 R/W 1'b0: No delay
ID
1'b1: After first PWM rising edge
It is used to enable AC load line when LL_adjust setting zero.
14 R/W AC_LL_ENABLE_BIT 1'b0: Disable
1'b1: Enable
It is used to set PG pin state with enable pin low.
13 R/W PG_LOW_OPTION 1'b0: Enable pin low, PG low
1'b1: Enable pin low, PG keep state
It is used to select protection for rail.
12 R/W PROTECT_SELECT 1'b0: Each rail protection for each rail
1'b1: All rail protection for each rail
It is used to select PSI6 or low power mode to set STB HIZ.
STB_DEPEND_LOW
11 R/W 1'b0: PSI6
PWR
1'b1: Low power mode
10 R/W INTERNAL_DEBUG For internal debug.
It is used to disable OVP and UVP when VID_DAC is lower than 100mV.
VID_DAC_100mV_DI
9 R/W 1b'0: Disable OVP and UVP when VID_DAC is lower than 100mV
S
1b'1: Enable OVP and UVP when VID_DAC is lower than 100mV
It is used to enable I2C timeout.
8 R/W I2C_TIMEOUT_EN 1'b0: Disable
1'b1: Enable
It is used to add extra delay time on SDA signal of I2C interface.
I2C_SDA_DEALY_SE 2'b00: 5ns

7:6 R/W 2'b01: 10ns
T
2'b10: 20ns
2'b11: 45ns
It is used to enable Intelli-Phase parallel mode for Rail 3.
INTELLI-PHASE
5 R/W 1'b0: Disable
_PARALLEL_EN_R3
1'b1: Enable
It is used to enable Intelli-Phase parallel mode for Rail 2.
INTELLI-PHASE
4 R/W 1'b0: Disable
_PARALLEL_EN_R2
1'b1: Enable
It is used to enable Intelli-Phase parallel mode for Rail1.
INTELLI-PHASE
3 R/W 1'b0: Disable
_PARALLEL_EN_R1
1'b1: Enable
It is used to enable OV and UV protection when protection level changes.
(Include OVP and UVP reference changes, OVP and UVP delta level enable
to disable or disable to enable, Vout max and min enable to disable or disable
2 R/W OVUV_CHANGE_EN to enable, OCP Warning and fault enable to disable or disable to enable).
1'b0: Enable
1'b1: Disable
It is used to enable SVTI signal buffer when LPM.
1 R/W SVTI_BUF_EN 1'b0: Enable
1'b1: Disable
It is used to enable SVC/SVD signal buffer when LPM.
0 R/W SVC_SVD_BUF_EN 1'b0: Enable
1'b1: Disable
PROTECTION_STATUS1 (80h)
This command is used to show protection status for IC.
15:9 R Reserved Unused. X indicates writes are ignored and reads are always 0.
Indicate under voltage protection status of Rail 1.
8 R RAIL1_UVP 1'b0: Not trigger
1'b1: Trigger
Indicate over voltage protection status of Rail 1.
7 R RAIL1_OVP 1'b0: Not trigger
1'b1: Trigger
Indicate over current protection status of Rail 1.
6 R RAIL1_OCP
1'b0: Not trigger

1'b1: Trigger
1'b1: Trigger
1'b1: Trigger
3 R RAIL2_OCP 1'b0: Not trigger
1'b1: Trigger
1'b1: Trigger
1'b1: Trigger
0 R RAIL3_OCP 1'b0: Not trigger
1'b1: Trigger
PROTECTION_STATUS2 (81h)
This command is used to show protection status for IC.
Indicate Vin over voltage protection status.
7 R VIN_OVP 1'b0: Not trigger
1'b1: Trigger
Indicate VIN UVLO status.
6 R VIN_UVLO 1'b0: Not trigger
1'b1: Trigger
Indicate TEMP fault status of Rail 3.
RAIL3_FAULT_OT_F
5 R 1'b0: Not trigger
LAG
1'b1: Trigger
Indicate over temperature protection status of Rail 3.
4 R RAIL3_OTP_FLAG 1'b0: Not trigger
1'b1: Trigger
RAIL2_FAULT_OT_F
LAG
1'b1: Trigger
1'b1: Trigger
RAIL1_FAULT_OT_F
LAG
1'b1: Trigger

1'b1: Trigger
MFR_I2C_PASSWORD (82h)
This command is used to set I2C communication password for IC. D0h is password input register.
Enable bit of I2C communication password for IC.
15 R/W PW_EN 1'b0: Disable
1'b1: Enable
14:0 R/W PW_SET It is used to set I2C communication password for IC.
MFR_DEBUG_CFG (83h)
This command is used to set GATE CLK for IC.
It is used to close fast ADC clock when rail VOUT equal to zero.
15 R/W MFR_APS_ZERO_EN 1'b0: Disable
1'b1: Enable
It is used to enable byte read function from MTP.
MFR_SINGLE_RD_E
N
1'b1: Enable
It is used to reduce calculation time when not full three rails work.
13 R/W MFR_CAL_JUMP_EN 1'b0: Disable(No reduce)
1'b1: Enable(Reduce)
It is used to hold per phase current balance loop when this phase PWM is Min
Ton.
12 R/W MFR_CB_LIMIT_EN
1'b0: Disable(No hold)
1'b1: Enable(Hold)
It is used to step by step or direct down to zero when VOUT down to zero with
MFR_FAST_DECAY_ decay enable.
11 R/W
DOWN 1'b0: Step by step
1'b1: Direct shutdown
It is used to improve the Vout telemetry accuracy.
VOUT_TEL_IMPROV
E
1'b1: Enable, Vout telemetry accuracy is improved to 2.5mV.
For internal debug.
For internal debug.
For internal debug.
For internal debug.
5 R/W INTERNAL_DEBUG For internal debug.

For internal debug.
For internal debug.
For internal debug.
It is used to set last fault protect record into MTP to block power up.
LAST_FAULT_BLOC
1 R/W 1'b0: No Block
K_POWER_UP_EN
1'b1: Block
It is used to clear last fault protect data record into MTP.
LAST_FAULT_CLEA
0 R/W 1'b0: Write 80 and 81h(Page0) data in MTP
R_EN
1'b1: Write 80 and 81h(Page0) 0x0000 in MTP
MFR_TRANS_CFG (84h)
This command is used to set I2C VID step and step delay time, and decay down step number, and
VOTF slew rate tuning for rail 1.
If VR works in SVI3 mode, it is used to fine tune the VOTF slew rate.
3’b000: VOTF slew rate *32/32
SVI3_SLEWRATE_T 3’b010: VOTF slew rate *32/30
12:10 R/W 3’b011: VOTF slew rate *32/29
UNE
MFR_TRANS_DECA It is used to set step number for decay down (Per step is 5mV).
9:8 R/W
Y_VIDSTEP Step number=[9:8]+1
It is used to set step number for every time VID changes when rail1 works in
MFR_TRANS_FAST_
7:6 R/W I2C mode (1 Step= 5mV).
VIDSTEP
Step number=[7:6]+1
I2C_STEP_DELAYTI If rail1 works in I2C mode, it is used to set delay time for one step change.
5:0 R/W
ME 100ns/LSB
PRODUCT_DATA_CODE (85h)
This command is used to set the unique four-digit hex code identifier for different customers or different
projects.
PRODUCT_DATA_C It is used to set the unique four-digit hex code identifier for different customers
15:0 R/W
ODE or different projects of the VR controller.
I2CBUS_ADDR (A0h)
This command is used to show I2CBus address for IC.

7:0 R I2CBUS_ADDR It is used to show I2Cbus address.
READ_VIN (A7h)
This command is used to report VIN value for IC.
9:0 R READ_VIN It is used to report VIN value for IC. 0.03125V/LSB
READ_VOUT (A8h)
This command is used to report output voltage for Rail 1.
9:0 R READ_VOUT It is used to report output voltage for IC. 5mV/LSB
READ_IOUT (A9h)
This command is used to report output current for Rail A.
It is used to report output current for IC.
9:0 R READ_IOUT
Follow 78h register setting.
READ_TEMP (AAh)
This command is used to report temperature for Rail 1.
It is used to report temperature.
8:0 R READ_TEMP
1°C/LSB, -256~255°C, bit[8] is the sign bit.
READ_CRC (AEh)
This command is used to report MTP CRC for IC.
15:0 R CRC It is used to report MTP CRC.

PAGE 1 REGISTER MAP
PAGE (00h)
The page command provides the ability to configure, control and monitor through only one physical
address for 3 rails and the test mode.
3’b000: Rail 1
3’b010: Rail 3
3’b011: Trim Page
OPERATION (01h)
conjunction with input from the EN pins. It is also used to set the output voltage to the upper or lower
MARGIN voltages. The unit stays in the commanded operating mode until a subsequent OPERATION
command or a change in the state of the EN pins instructs the device to change to another mode.
1'b1: Power on
VOUT_COMMAND (21h)
9:0 R/W VOUT_COMMAND It is used to set VID at I2C mode. 5mV/LSB.
MFR_VOUT_TRIM (22h)
3:0 R/W 1-PHASE DCM It is used to set VOUT trim value for 1-phase DCM mode.

1.5625mV/LSB @VDIFF GAIN = 1
VOUT_MAX (24h)
7:0 R/W MAX_VOUT
Max Vout = Reg[7:0] * 20 mV
VOUT_MIN (2Bh)
7:0 R/W MIN_VOUT
15:14 R/W 16 – CAP
15:14 R/W 16 – CAP
15:14 R/W 16 – CAP

15:14 R/W 16 – CAP
This command is used as extend bit of cap numbers for 1/2/3 phase CCM and 1 phase DCM slope
compensation, and Initial slope of Rail 2.
MFR_SLOPE_SR_INI
13:8 R/W Initial slope for start-up. 5mV/LSB
TI
Extended
Bit_1PH_DCM
5:4 R/W Extended Bit_3PH It is used as extend bit of cap numbers for 3 phase CCM.
OCP_UCP_SET (54h)
Rail 2.
PER_PHASE_UC_LE
VEL
PER_PHASE_OC_LE
VEL
8:0 R/W IOUT_GAIN IOUT report = IMON_ADC * 256 / GAIN + OFFSET
Note:
Custom=8A:
Custom=16A:
MFR_VCAL_PI (58h)
6:0 R/W MFR_VCAL_PI It is used to set DC loop PI value of Rail 2.
15:8 R/W OCP_GAIN
OCP_WARN_OFFSE
T
MFR_VIN_HYS (5Ch)
This command is used to set VIN hysteresis for IC.
3:0 R/W MFR_VIN_HYS It is used to set Vin hysteresis. 100mV/LSB.
PSYS_CAL_OFFSET_GAIN (5Dh)
This command is used to set the PSYS report offset and gain.
It is used to set Psys report offset.
14:8 R/W PSYS_OFFSET
Psys report = PSYS_ADC * GAIN / 128 + OFFSET
It is used to set Psys report gain.
7:0 R/W PSYS_GAIN
Psys report = PSYS_ADC * GAIN / 128 + OFFSET
This command is used to set temp report gain and offset for Rail 2.
7:0 R/W TEMP_GAIN
15 R/W DIGTAL_FILTER_EN 1’b0: Enable digital filter when decay down
1’b1: Disable
1'b1: All state
occur.
1'b0: Disable
1'b1: Enable
12 R/W MFR_FS_LOOP_EN 1'b0: Disable
1'b1: Enable
MFR_VID_FILTER_E
N
1'b1: Enable
1'b0: Disable
1'b1: Enable
1'b1: I2C Mode
1'b0: Disable
1'b1: Enable
trigger.
1'b0: Disable
1'b1: Enable
MFR_VCAL_DCM_E
6 R/W 1'b0: Disable
N
1'b1: Enable

DC calibration loop enable bit.
5 R/W MFR_VCAL_EN 1'b0: Disable
1'b1: Enable
1'b1: Enable
3'b000: PSI0
3'b001: PSI1
3'b002: PSI2
3'b007: PSI7
1'b1: VOUT
It is used to force VR into APS without considering the PSI state.
14 R/W MFR_APS_FORCE 1'b0: Disable
1'b1: Enable
It is used to enable VID analog filter at DVID.
1'b1: Enable
12 R/W FSW_HIGH_PWM
1'b0: HIZ-LOW
1'b1: HIZ-HIGH
11 R/W
S 1'b0: Disable
1'b1: Enable
1'b1: Enable
It is used to set VID filter time constant for Rail 1, which is the VID analog filter
for VID slew down transitions.

2'b01: 4.7us
2'b10: 7.05us
2'b11: 9.4us

MFR_VR_BOOT (61h)
1h = 0.500 V
2h = 0.600 V
3h = 0.700 V
4h = 0.800 V
5h = 0.900 V
6h = 1.000 V
7h = 1.100 V
3:0 R/W SVI3_VBOOT 8h = 1.200 V
9h = 1.300 V
Ah = 1.400 V
Bh = 1.500 V
Ch = 1.800 V
Dh = 2.000 V
Eh = 2.500 V
Fh = 2.800 V
0h = 0V
MFR_FREQ_DET (64h)
Enable bit of high frequency detection.
HIGH_FREQ_DET_E
N
1'b1: Enable
HIGH_FREQ_DET_S
ET
LOW_FREQ_DET_E
7 R/W 1'b0: Disable
N
1'b1: Enable
LOW_FREQ_DET_S
ET
MFR_PWR_DLY (65h)

ANTI_SLOPE_LEAKA
GE
1'b1: Enable
SLOPE_DIS_TIME_C
CM
For internal debug.
For internal debug.
MFR_PSI_TRIM (6Ah)
15:12 R/W 3-PHASE CCM It is used to set VO_COMP initial value for 3-phase CCM mode. 2.5mV/LSB.
For internal debug.

For internal debug.
For internal debug.
For internal debug.
It is used to enable fast APS of rail2.
8 R/W MFR_FAST_APS_EN 1’b0: Disable fast APS
1’b1: Enable fast APS
7 R/W
1'b1: Enable
SHEDDING_PHASE_
6 R/W 1'b0: Disable
FAST
1'b1: Enable
1'b1: Enable
1'b1: Enable
1'b1: Enable
1'b1: Enable
SLOPE_DIS_TIME_D
CM
1'b1: Enable
VID_ZERO_DOWN_P
LATFROM
0 R/W PSI3_UP_EN
1’b0: Disable, DVID with entering PSI0 state

APS_RECOVERY_H It is used to set hold time for recovery APS.

15:11 R/W
OLDTIME 1 ADC sampling period/LSB
10:6 R/W
change is finished.
5 R/W DVID_PSI_DIS_APS 1'b0: Enable, immediately recovery APS
HIGH_LOW_FS_DIS_
APS
2 R/W OC1_DC_CB
1'b1: Disable
1 R/W
1'b1: Disable
0 R/W
1'b1: Disable
MFR_APS_HYS (70h)

1'b1: Enable
7:5 R/W
MFR_DROOP_SET (73h)
CUR_SNS_BLOCK_S
EL
AC_DC_DROOP_SE
L
1'b1: AC droop
1'b1: Disable
COMP_CAP_INCREA
11 R/W 1'b0: Enable
SE
1'b1: Disable
DIFFERENTIAL_CM_ It is used to set current mirror ratio of Transient Droop.
10 R/W
SET
1'b0: 1*IDROOP CM gain


9:8 R/W 2'b01: 1/8
ET
2'b10: 1/4
2'b11: 1/2
HALF_RES_SHORT_
7 R/W 1'b0: Disable
EN
1'b1: Enable
For internal debug.
For internal debug.
INTELLI-PHASE
_PFO_EN
1’b1: Disable
3’b010: 200ns
12:10 R/W
E 3’b100: 400ns
3’b101: 500ns
3’b110: 600ns
3’b111: 700ns
15:8 R/W
7 R/W OVP_REF
6:4 R/W OVP_DELTA 000b = Disabled
OVP Delta = Reg[6:4] * 50 + 50 mV
3 R/W UVP_REF
2:0 R/W UVP_DELTA It is used to set delta value of under-voltage protection threshold.
000b = Disabled

UVP Delta = Reg[2:0] * 50 + 50 mV
TOTAL_OCP_SET (76h)
It is used to set over current protection threshold level
15:8 R/W OCP_THRESHOLD
7:3 R/W
ULSE Minimum pulse = Reg[7:3] * 500 ns
MFR_SVI3_SR_IOUT (78h)
strap, etc.)
4:3 R/W BOOT_SR 00b = 2.5 mV/μs

01b = 10 mV/μs
10b = 20 mV/μs
11b = 40 mV/μs
Output current scale, programmed at platform level (NVM, resistor strap, etc.)
001b = 32A (0.03125A/LSB)
010b = 64A (0.0625A/LSB)
100b = 256A (0.25A/LSB)
101b = 512A (0.5A/LSB)
110b = 1024A (1A/LSB)
111b = 2048A (2A/LSB)
It is used to set default decay condition in PSI0, PSI1and PSI2 (or equivalent
MFR_DECAY_MODE states when in PSI7).
3 R/W
_PSI0/1/2 1’b0: Disable
2 R/W
1 R/W
MFR_DOWN_SLEWR
ATE
MFR_DEBUG (7Ch)
For internal debug.
15:12 R/W INTERNAL_DEBUG
Please set to 4’b0011 for normal usage.
APS_ADD_PHASE_B
EHAVIOR
1'b1: 0.5
1'b1: 80mV
2'b00: 4k
2'b10: 16k
2'b11: 32k
for Rail 2.
4:3 R/W IMON_OC_RES_SET
2'b00: 5k
2'b01: 10k
2'b10: 20k
2'b11: 40k
For internal debug.
1:0 R/W IMON_TRIM_SET_R2 2'b01: 1/8 16k trim data
1'b1: Disable
1'b1: Slow
6:4 R/W N_FILTER_TIME when bit[7] =1, filter time = 4us*(7-bit[6:4]);
1'b1: Slow
MFR_TRANS_CFG (84h)
VOTF slew rate tuning for Rail 2.
SVI3_SLEWRATE_T 3’b010: VOTF slew rate *32/30
12:10 R/W 3’b011: VOTF slew rate *32/29
UNE

9:8 R/W
MFR_TRANS_FAST_
7:6 R/W I2C mode (Per step is 5mV).
VIDSTEP
Step number=[7:6]+1
5:0 R/W
ME 100ns/LSB
CODE_REV (85h)
The CODE_REV command on Page 1 identifies the VR product and the code revision.
It is used to provide the unique identification assigned by the VR vendor for
15:8 R/W PRODUCT_ID_VR
the VR product.
7:0 R/W CODE_REV It is used to identify the code revision.
I2CBUS_ADDR (A0h)
7:0 R I2CBUS_ADDR It is used to show I2CBus address.
READ_VOUT (A8h)
9:0 R READ_VOUT It is used to report output voltage for IC. 5mV/LSB
READ_IOUT (A9h)
This command is used to report output current for Rail 2.
9:0 R READ_IOUT It is used to report output current for IC. Follow 78h register setting
READ_TEMP (AAh)
8:0 R READ_TEMP

PAGE 2 REGISTER MAP
PAGE (00h)
The page command provides the ability to configure, control and monitor through only one physical
address for 3 rails and the test mode.
3’b000: Rail 1
3’b010: Rail 3
3’b011: Trim Page
OPERATION (01h)
conjunction with input from the EN pins. It is also used to set the output voltage to the upper or lower
MARGIN voltages. The unit stays in the commanded operating mode until a subsequent OPERATION
command or a change in the state of the EN pins instructs the device to change to another mode.
1'b1: Power on
VOUT_COMMAND (21h)
It is used to set VID at I2C mode.
9:0 R/W VOUT_COMMAND 5mV/LSB for Type1
10mV/LSB for Type2
MFR_VOUT_TRIM (22h)
3:0 R/W 1-PHASE DCM It is used to set VOUT trim value for 1-phase DCM mode.

1.5625mV/LSB @VDIFF GAIN = 1
VOUT_MAX (24h)
7:0 R/W MAX_VOUT Max Vout = Reg[7:0] * 20 mV for Type1
Max Vout = Reg[7:0] * 40 mV for Type2
VOUT_MIN (2Bh)
7:0 R/W MIN_VOUT
15:14 R/W 16 – CAP
15:14 R/W 16 – CAP
15:14 R/W 16 – CAP It is used to set cap number.

This command is used as extend bit of cap numbers for 1/2 phase CCM and 1 phase DCM slope
compensation, and Initial slope of Rail 3.
MFR_SLOPE_SR_INI
13:8 R/W Initial slope for start-up. 5mV/LSB
TI
Extended
Bit_1PH_DCM
OCP_UCP_SET (54h)
Rail 3.
PER_PHASE_UC_LE
VEL
PER_PHASE_OC_LE
VEL
Note:
8:0 R/W IOUT_GAIN
Custom=8A:
Custom=16A:

MFR_VCAL_PI (58h)
6:0 R/W MFR_VCAL_PI It is used to set DC loop PI value of Rail 3.
15:8 R/W OCP_GAIN
OCP_WARN_OFFSE
T
MFR_IOUT3_OFFSET1_DCM (5Ch)
This command is used to set the IOUT report offset in DCM for Rail 3.
Selection bit for Rail B Iout report offset when rail works in DCM.
7 R/W IOUT3_OFFSET_SEL 1’b0: Select P2.56H[15:9] as Rail 3 IOUT report offset in DCM.
1’b1: Select P2.5CH[6:0] as Rail 3 IOUT report offset in DCM.
IOUT3_OFFSET_DC It is used to set Rail 3 IOUT report offset when rail works in DCM.
6:0 R/W
M IOUT3 report = IMON_ADC * 256 / GAIN + OFFSET
MFR_IOUT1/2_OFFSET_DCM (5Dh)
This command is used to set the IOUT report offset in DCM for Rail 1 & Rail 2.
Selection bit for Rail 2 Iout report offset when rail works in DCM.
15 R/W IOUT2_OFFSET_SEL 1’b0: select P1.56H[15:9] as Rail 2 IOUT offset in DCM.
1’b1: select P2.5DH[14:8] as Rail 2 IOUT offset in DCM.
14:8 R/W
Selection bit for Rail 1 Iout report offset when rail works in DCM.
7 R/W IOUT1_OFFSET_SEL 1’b0: select P0.56H[15:9] as Rail 1 IOUT offset in DCM.
1’b1: select P2.5DH[6:0] as Rail 1 IOUT offset in DCM.
6:0 R/W

This command is used to set temp report gain and offset for Rail 3.
7:0 R/W TEMP_GAIN
15 R/W DIGITAL_FILTER_EN 1’b0: Enable digital filter when decay down
1’b1: Disable
1'b1: All state
occur.
1'b0: Disable
1'b1: Enable
12 R/W MFR_FS_LOOP_EN 1'b0: Disable
1'b1: Enable
MFR_VID_FILTER_E
N
1'b1: Enable
1'b0: Disable
1'b1: Enable
1'b1: I2C Mode
1'b0: Disable
1'b1: Enable
trigger.
1'b0: Disable
1'b1: Enable
MFR_VCAL_DCM_E
6 R/W 1'b0: Disable
N
1'b1: Enable
5 R/W MFR_VCAL_EN DC calibration loop enable bit.

1'b0: Disable
1'b1: Enable
1'b1: Enable
3'b000: PSI0
3'b001: PSI1
3'b002: PSI2
3'b007: PSI7
1'b1: VOUT
It is used to force VR into APS without considering the PSI state.
14 R/W MFR_APS_FORCE 1'b0: Disable
1'b1: Enable
It is used to enable VID analog filter at DVID.
1'b1: Enable
12 R/W FSW_HIGH_PWM
1'b0: HIZ-LOW
1'b1: HIZ-HIGH
11 R/W
S 1'b0: Disable
1'b1: Enable
1'b1: Enable
It is used to set VID filter time constant for Rail 1, which is the VID_DAC
output filter for VID slew down transitions.

2'b01: 4.7us
2'b10: 7.05us
2'b11: 9.4us

MFR_VR_BOOT (61h)
0h = Off (wait for SVI3 VID command)
1h = 0.500 V
2h = 0.600 V
3h = 0.700 V
4h = 0.800 V
5h = 0.900 V
6h = 1.000 V
3:0 R/W SVI3_VBOOT 7h = 1.100 V
8h = 1.200 V
9h = 1.300 V
Ah = 1.400 V
Bh = 1.500 V
Ch = 1.800 V
Dh = 2.000 V(Type1)/2.500V (Type2)
Eh = 2.500 V(Type1)/3.300V (Type2)
Fh = 2.800 V(Type1)/5.000V(Type2)
MFR_FREQ_DET (64h)
Enable bit of high frequency detection.
HIGH_FREQ_DET_E
N
1'b1: Enable
HIGH_FREQ_DET_S
ET
LOW_FREQ_DET_E
7 R/W 1'b0: Disable
N
1'b1: Enable
LOW_FREQ_DET_S
ET
MFR_PWR_DLY (65h)

ANTI_SLOPE_LEAKA
GE
1'b1: Enable
SLOPE_DIS_TIME_C
CM
For internal debug.
For internal debug.
MFR_PSI_TRIM (6Ah)
For Internal debug.

For Internal debug.
7 R/W
1'b1: Enable
SHEDDING_PHASE_
6 R/W 1'b0: Disable
FAST
1'b1: Enable
1'b1: Enable
1'b1: Enable
1'b1: Enable
1'b1: Enable
SLOPE_DIS_TIME_D
CM
1'b1: Enable
VID_ZERO_DOWN_P
LATFROM
0 R/W PSI3_UP_EN 1’b0: Disable, DVID with entering PSI0 state
APS_RECOVERY_H
15:11 R/W It is used to set hold time for recovery APS.
OLDTIME

1 ADC sampling period/LSB
10:6 R/W
change is finished.
5 R/W DVID_PSI_DIS_APS 1'b0: Enable, immediately recovery APS
HIGH_LOW_FS_DIS_
APS
2 R/W OC1_DC_CB
1'b1: Disable
1 R/W
1'b1: Disable
0 R/W
1'b1: Disable
MFR_APS_HYS (70h)
1'b1: Enable
7:5 R/W
MFR_DROOP_SET (73h)
CUR_SNS_BLOCK_S
EL
AC_DC_DROOP_SE
L
1'b1: AC droop
1'b1: Disable
COMP_CAP_INCREA
11 R/W 1'b0: Enable
SE
1'b1: Disable
It is used to set current mirror ratio of Transient Droop.
DIFFERENTIAL_CM_
10 R/W 1'b0: 1*IDROOP CM gain
SET

9:8 R/W 2'b01: 1/8
ET
2'b10: 1/4
2'b11: 1/2
HALF_RES_SHORT_
7 R/W 1'b0: Disable
EN
1'b1: Enable

For internal debug.
For internal debug.
INTELLI-PHASE
_PFO_EN
1’b1: Disable
3’b010: 200ns
12:10 R/W
E 3’b100: 400ns
3’b101: 500ns
3’b110: 600ns
3’b111: 700ns
15:8 R/W
7 R/W OVP_REF
000b = Disabled
6:4 R/W OVP_DELTA
For Type1: OVP Delta = Reg[6:4] * 50 + 50 mV
For Type2: OVP Delta = Reg[6:4] * 100 + 100 mV
3 R/W UVP_REF
It is used to set delta value of under-voltage protection threshold.
000b = Disabled
2:0 R/W UVP_DELTA
For Type1: UVP Delta = Reg[2:0] * 50 + 50 mV
For Type2: UVP Delta = Reg[2:0] * 100 + 100 mV
TOTAL_OCP_SET (76h)
15:8 R/W OCP_THRESHOLD It is used to set over current protection threshold level

Note: MAX_CURRENT = 3FFh of selected current scale
7:3 R/W
ULSE Minimum pulse = Reg[7:3] * 500ns
MFR_SVI3_SR_IOUT (78h)
This command is used to SVI3 related parameters for Rail 3.
strap, etc.).
4:3 R/W BOOT_SR 00b = 2.5 mV/μs

01b = 10 mV/μs
10b = 20 mV/μs
11b = 40 mV/μs
Output current scale, programmed at platform level (NVM, resistor strap, etc.).
001b = 32A (0.03125A/LSB)
010b = 64A (0.0625A/LSB)
100b = 256A (0.25A/LSB)
101b = 512A (0.5A/LSB)
110b = 1024A (1A/LSB)
111b = 2048A (2A/LSB)
MFR_DECAY_MODE It is used to set default decay condition in PSI0, PSI1 and PSI2 (or equivalent
3 R/W
_PSI0/1/2 states when in PSI7).

1’b0: Disable
2 R/W
1 R/W
MFR_DOWN_SLEWR
ATE
MFR_DEBUG (7Ch)
It is used to set STB disable mode.
15 R/W MFR_STB_CONFIG 1'b0: STB HIZ as disable signal
1'b1: STB LOW as disable signal
For internal debug.
It is used to enable the function that reduces LPM exit time with STB.
MFR_LPM_EXIT_FA
ST
1'b1: Enable
APS_ADD_PHASE_B
EHAVIOR
1'b1: 0.5
1'b1: 80mV
2'b00: 4k
2'b10: 16k
2'b11: 32k
for Rail 3.
5:4 R/W IMON_OC_RES_SET
2'b00: 5k

2'b01: 10k
2'b10: 20k
2'b11: 40k
For internal debug.
It is used to set remote sense gain in TYPE2 for Rail 3.
2 R/W MFR_USER_GAIN 1'b0: 1
1’b1: 0.5
It is used to select SVI3 TYPE for Rail 3.
1 R/W SLAVE_TYPE 1'b0: TYPE1
1’b1: TYPE2
0 R/W IMON_TRIM_SET_R3 3'b0: 1/4 32k trim data
1'b1: Disable
1'b1: Slow
6:4 R/W N_FILTER_TIME when bit[7] =1, filter time = 4us*(7-bit[6:4])
when bit[7] =0, filter time = 20ns*(7-bit[6:4])
1'b1: Slow
MFR_TRANS_CFG (84h)
VOTF slew rate tuning for Rail 3.
SVI3_SLEWRATE_T
12:10 R/W
UNE 3’b000: VOTF slew rate *32/32

9:8 R/W
MFR_TRANS_FAST_
7:6 R/W I2C mode (Per step is 5mV).
VIDSTEP
Step number=[7:6]+1
5:0 R/W
ME 100ns/LSB
KCS_IOUT_CUSTOM (85h)
This command is used to select Iout custom scale and Intelli-Phase's current sense gain for Rail1/2/3.
It's used to select Custom Scale of rail3.
5 R/W CUSTOM_IOUT_R3 1'b0: 8A (0.0078125A/LSB)
1'b1: 16A (0.015625A/LSB)
1'b1: 16A (0.015625A/LSB)
1'b1: 16A (0.015625A/LSB)
It's used to select Intelli-Phase's current sense gain of rail1.
2 R/W KCS_3 1'b0: 10μA/A
1'b1: 5μA/A
It's used to select Intelli-Phase’s current sense gain of rail1.
1 R/W KCS_2 1'b0: 10μA/A
1'b1: 5μA/A
It's used to select Intelli-Phase’s current sense gain of rail1.
0 R/W KCS_1 1'b0: 10μA/A
1'b1: 5μA/A
I2CBus_ADDR (A0h)
7:0 R I2CBus_ADDR It is used to show I2CBus address.
READ_VOUT (A8h)

It is used to report Rail3 output voltage. 5mV/LSB in Type1, 10mV/LSB in
9:0 R READ_VOUT
Type2.
READ_IOUT (A9h)
This command is used to report output current for Rail 3.
9:0 R READ_IOUT It is used to report output current for IC. Follow 78h register setting
READ_TEMP (AAh)
8:0 R READ_TEMP

PACKAGE INFORMATION
TQFN-52 (6mmx6mm)
0.18X45° REF PIN 1 ID

PIN 1 ID 0.30X45° TYP
MARKING
PIN 1 ID
INDEX AREA
TOP VIEW BOTTOM VIEW
SIDE VIEW
NOTE:
1) ALL DIMENSIONS ARE IN MILLIMETERS.

2) EXPOSED PADDLE SIZE DOES NOT INCLUDE MOLD FLASH.
3) LEAD COPLANARITY SHALL BE 0.08 MILLIMETERS MAX.
4) JEDEC REFERENCE IS MO-303.
RECOMMENDED LAND PATTERN 5) DRAWING IS NOT TO SCALE.

CARRIER INFORMATION
Pin1 1 1 1 1
ABCD ABCD ABCD ABCD
Feed Direction
Carrier Carrier
Package Quantity/ Quantity/ Quantity/ Reel
Part Number Tape Tape
Description Reel Tube Tray Diameter
Width Pitch
MP2825GQKT- TQFN-52
5000 N/A N/A 13 in. 12 mm 8 mm
003C-Z (6mmx6mm)
Notice: The information in this document is subject to change without notice. Please contact MPS for current specifications.
Users should warrant and guarantee that third-party Intellectual Property rights are not infringed upon when integrating MPS
products into any application. MPS will not assume any legal responsibility for any said applications.
MARKING LAYOUT EXAMPLE
TOP MARKING EXAMPLE 1:
Company Initial Year & Week Code

Lead & Halogen Free ID
M P S Y Y WW Part Number
P P P P P P P P Lot Number
Pin 1 ID
L L L L L L L L
Year & Week Code

Pin 1 ID
Lead & Halogen Free ID
M P Y W
Part Number Prefix Part Number
P P P P
Lot Number
O L L L
Optional Special Mark
6 5 4
Part Number Code
Lead & Halogen Free ID Year and Week Code
P P Y W
1 2 3
YEAR, WEEK AND COUNTRY CODE DEFINATION
SINGLE DIGIT YEAR SINGLE DIGIT WORK WEEK

(Y) DEFINITION (W) DEFINITION
0 2000 A 1-2
1 2001 B 3-4
2 2002 C 5-6
3 2003 D 7-8
4 2004 E 9-10
5 2005 F 11-12
6 2006 G 13-14
7 2007 H 15-16
8 2008 J 17-18
9 2009 K 19-20
A 2010 L 21-22
B 2011 M 23-24
C 2012 N 25-26
D 2013 P 27-28
E 2014 Q 29-30
F 2015 R 31-32
G 2016 S 33-34
H 2017 T 35-36
J 2018 U 37-38
K 2019 V 39-40
M 2020 X 41-42
N 2021 Y 43-44
P 2022 Z 45-46
R 2023 3 47-48
S 2024 6 49-50
T 2025 9 51-54
V 2026
W 2027
X 2028
Y 2029
Z 2030

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MPS Confidential - For Quanta Use Only

MP2825 Rev. 0.8 MonolithicPower.com 1

MP2825 Rev. 0.8 MonolithicPower.com 2

MPS: MPS prefix

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IRTN1/2/3 EN = 3.3V, VOSEN 1/2/3 =

IVOSEN1/2/3 EN = 3.3V, VOSEN 1/2/3 =

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Reset_L Input high voltage VIL_RESET_H 1.17 V

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ADC resolution(5) 10 bit

VOL SDA sinks 2mA (about 90

VMAX Transient voltage including

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ADC INPUT MUX

FAULT1/2/3 PGD-1/2/3 MUX CMD

Figure 1: Functional Block Diagram

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7+0+1 Rail1 Rail3

6+0+2 Rail1 Rail3

6+1+1 Rail1 Rail2 Rail3

5+1+2 Rail1 Rail2 Rail3

5+2+1 Rail1 Rail2 Rail3

5+3+0 Rail1 Rail2

4+2+2 Rail1 Rail2 Rail3

4+3+1 Rail1 Rail2 Rail3

3+3+2 Rail1 Rail2 Rail3

Power On and Start-up Sequence 3. EN of the MP2825’s certain is pulled to high.

A resistor divider network outside the chip is

connected to VINSEN (see Figure 4). The CS1

recommended values are Rin1 = 2MΩ and Rin2 =

133kΩ. A filtering capacitor 1nF or above is

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Kcs = 5μA/A Kcs = 10μA/A

ADC inside MP2825. Moreover, a proper MP2825

RPSYS/ISYS value is determined by equation (3) or

1.2 (3) Intelli-Phase

Input current sample: VDD

Where “1.2” refers to the MAX PSYS/ISYS pin AGND PGND

voltage 1.2V; PSYS_SCALE is the selected

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current reference with the offset to keep the

of the current proportional-integral (PI) loop is AGND PGND

relatively lower than the output voltage

In addition to being used as SVI3 Type 1 device, BST

MP2825 also can support SVI3 Type 2 device SW

individually as Type 2 device by setting I2C AGND PGND

register SLAVE_TYPE (7Ch. bit[1], Page2).

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