ARM INSTRUCTION SET

Instructions
Instructions process data held in registers
and access memory with load and store
registers
Classes of instructions:
o Data processing
o Branch instructions
o Load-store instructions
o Software interrupt instructions
o Program status register instructions
 ARM Data types
Word is 32 bits long
Word can be divided into four bytes
ARM addresses can be 32 bit long
Address refers to byte
o Address 4 starts at byte 4
Can be configured at power up as little
endian or big endian mode
 Data Processing
Manipulate data within registers
o MOVE instructions
o Arithmetic instructions
• Multiply instructions
o Logical instructions
o Comparison instructions
Suffix S on data processing instructions
updates flags in CPSR
 Data processing instructions
• Operands are 32 bit wide; comes from
registers or specified as literal in the
instruction itself
• Second operand send to ALU via barrel
shifter
• 32-bit result placed in register; long
multiply instruction produces 64 bit result
 Move instruction
MOV Rd, N
o Rd: Destination register
o N: can be an immediate value or source
register
o Example: mov r7, r5

o MVN Rd, N
o Move into Rd not of the 32-bit value from
source
 Using Barrel Shifter
Enables shifting 32 bit operand in one of
the source registers left or right by a
specific no. of positions within the cycle
time of instructions
Basic barrel shifter operations
o Shift left, shift right, rotate right
Facilitates fast multiply, division and
increases code density
Example : mov r7, r5, LSL #2
 Arithmetic instructions
 Implements 32 bit addition and subtraction
 3 operand form
 Examples
SUB r0, r1, r2
Subtract value stored in r2 from that of
r1 and store in r0
SUBS r1, r1, #1
Subtract 1 from r1 and store result in r1
and update Z and C flags
 With Barrel shifter
Use of barrel shifter with arithmetic and
logical instructions increases the set of
possible available operations
Example
o ADD r0, r1, r1 LSL #1
o Register r1 is shifted to the left by 1, then it is
added with r1 and the result (3 times of r1) is
stored in r0.
 Multiply instructions
• Multiply contents of a pair of registers
Long multiply generates 64 bit result
Examples
MUL r0, r1, r2
UMULL r0, r1, r2, r3
Number of cycles taken for execution of
multiply instruction depends upon
processor implementation
 Logical instructions
Bit wise logical operations on the two
source registers
o AND, OR , Ex-OR, bit clear
o Example : BIC r0, r1, r2
o r2 contains a binary pattern where every binary 1
in r2 clears a corresponding bit location in register
r1
o Useful in manipulating status flags and interrupt
masks
 Compare instructions
• Enables comparison of 32 bit values
– Updates CPSR flags but do not affect other
registers
– Examples
• CMP r0, r9
– Flags set as a result of r0 - r9
• TEQ r0, r9
– Flags set as a result of r0 ex-or r9
• TST r0, r9
– Flags set as a result of r0 & r9
LOAD/STORE INSTRUCTIONS
 Transfers data between memory and processor
registers
• Single register transfer
• Data types supported are signed and unsigned
• words(32 bits), half-words and bytes
• Multiple-register transfer
• Transfers multiple registers between memory and the
processor in a single instruction
• Swap
• Swap content of a memory location with the contents of the
register
 Single Transfer instructions
 Load and Store data on a boundary alignment
• LDR, LDRH, LDRB;
• Load (word, half-word, byte)
• STR, STRH, STRB;
• Store (word, half-word, byte)
• Supports different addressing modes:
• Register indirect: LDR r0, [r1]
• Immediate: LDR r0, [r1, #4]
• 12 bit offset added to the base register
• Register operation: LDR r0, [r1, -r2]
• Address calculated using base register and another register
 More addressing modes
• Scaled
o Address is calculated using the base address
register and a barrel shift operation
• Pre and Post indexing
o Pre-index with write back: LDR r0, [r1, #4]!
• Updates the address base register with new
address
o Post index: LDR r0, [r1], #4
• Updates the address register after address is used
 Example
Pre-indexing with write back
LDR r0, [r1, #4]!
o Before instruction execution
• r0 = 0x00000000 r1 = 0x00009000
• Mem32[0x00009000] = 0x01010101
• Mem32[0x00009004] = 0x02020202
o After instruction execution
• r0 = 0x02020202
• r1 = 0x00009004
 Multiple Register Transfer
 Load-store multiple instructions transfer multiple
register contents between memory and the
processor in a single instruction
 More efficient – for moving blocks of memory,
saving and restoring context and stack
 These instructions can increase interrupt latency
o Usually instruction executions are not interrupted by
ARM
 Multiple Byte Load-Store
• Any subset of current bank of registers
can be transferred to memory or fetched
from memory
LDM{cond}address-mode Rn{!},reg-list{^}
– LDM
{r0,r1,r4-r6,pc}
– STM
• The base register Rn determines source
or destination address
 Stack Processing
• ARM architecture uses the load store multiple
instructions to carry out stack operations
• Ascending –stack grows towards higher memory
address
• Descending –stack grows towards lower
memory address
• Full – sp points to the last item on the stack
• Empty - sp points after the last item on the stack
 Modes of Stack Operation
• ARM Multiple register transfer instructions
support
– Full ascending: grows up, SP points to the
highest address containing a valid item
– Empty ascending: grows up, SP points to the
first empty location above stack
– Full descending: grows down, SP points to
the lowest address containing a valid data
– Empty descending: grows down, SP points to
the first location below stack
Addressing Methods for Stack
Operations
 SWAP INSTRUCTION
• Special case of load store instruction
• Swap instructions
– SWP: swap a word between memory and
register
– SWPB: swap a byte between memory and
register
 Control Flow instructions
• Branch instructions
• Conditional branches
• Conditional execution
• Branch and link instructions
• Subroutine return instructions
 Branch instruction
• Branch instruction: B label
– Example: B forward
– Address label is stored in the instruction as a
signed pc-relative offset
• Conditional Branch: B <cond> label
– Example: BNE loop
– Branch has a condition associated with it and
executed if condition codes have the correct
value
 Conditional Execution
• An unusual feature of ARM instruction set
is that conditional execution applies not
only to branches but to all ARM
instructions
• Example: ADDEQ r0, r1, r2
– Instruction will only be executed when the
zero flag is set to 1
 Advantages of conditional
execution
• Reduces the number of branches
– Reduces the number of pipeline flushes
– Improves performance of the code
• Increases code density
• Whenever the conditional sequence is 3
instructions or fewer (smaller and faster) to
exploit conditional execution than to use a
branch
 Branch and Link
• Perform a branch, save the address following
the branch in the link register, r14
– Example: BL subroutine
 Subroutine return instructions
• No specific instructions
• Example:
sub …..
MOV PC, r14
Software Interrupt Instruction(SWI)
• A software interrupt instruction causes a
software interrupt exception, which provides a
mechanism for moving the processor to move
from application routine to OS routines
• Instruction: SWI {<cond>} SWI_number
• When the processor executes an SWI
instruction, it sets the program counter to the
offset 0x08 in the vector table
• Instruction also forces the processor mode to
SVC, which allows an operating system routine
to execute
 SWI
• SWI is typically executed in user mode
• Instruction forces processor mode to supervisor
(SVC) – this allows an OS routine to be
executed in privileged mode
• Each SWI has an associated SWI number which
is used to represent a particular function call or
feature
• Parameter passing – through registers; Return
value is also passed using registers
 Example
• PRE: cpsr = nzcvqift_USER
• pc = 0x00008000
• lr = 0x003fffff (lr = r14)
• r0 = 0x12
• 0x00008000 SWR 0X123456
• POST: cpsr = nzcvqift_SVC
• Spsr = nzcvqift_USER
• pc = 0x00008004
• lr = 0x00008004 (lr = r14_SVC)
• r0 = 0x12
 Program Status Register
Instructions
• Two instructions to control PSR directly
• MRS – transfers register contents of either
cpsr or spsr into a register
• MSR – transfers contents of register to
cpsr or spsr
 Example
Enabling IRQ interrupt
o PRE cpsr = nzcvqIFt_SVC
MRS r1, CPSR
BIC r1, r1, #0x80
MSR cpsr, r1
o POST cpsr = nzcvqiFt_SVC
o Instructions in SVC mode
 Coprocessor Instructions
• Used to extend the instruction set
– Used by cores with a coprocessor
– Coprocessor specific operations
• Syntax: Coprocessor data processing
– CDP{<cond>} cp, opcode1, Cd, Cn, Cm, {,opcode2}
• Cp represents coprocessor number between p0 to p15
• Opcode fields describes coprocessor operation
• Cd, Cn, Cm coprocessor registers
• Also coprocessor register transfer and memory
transfer instructions