Module 2

ARM Cortex M3 instruction

sets and Programing

Dr. Suchitra M
Professor
Dept. of ECE, VVCE, Mysuru

07/10/2021 1
Instruction sets

• An instruction is a binary
pattern designed inside a
processor to perform a
specific function.
• Machine instructions are
represented by 0s and 1s
• We use mnemonics such as
mov, dec, branch, add etc
• A complete set of mnemonics
and rules constitute Assembly
language
• Assembler
Assembly language (source
program) to machine
instructions (object
program)
ARM has multiple instruction sets

ARM instruction (32 bit)

Thumb instruction (16 bit)

Thumb2 instruction ( Mixed 32 bit and 16 bit)

ARM instruction (32 bit)

• All instructions are 32 bits

• Three address data processing instructions

• Most instructions are executed conditionally

• Provides more coding flexibility

• Disadvantage is its coding density

• Performance is high
Thumb instruction (16 bit)

• 16 bit instruction set

• Two registers instead of three registers

• Only low 8 registers (R0 to R7)

• No condition execution (except for branches)

SUBNE

• Limited immediate values

• High code density is less memory required thereby reducing

the cost and power consumption
Contd.
To get the best of both, many applications have mixed ARM
and Thumb codes.
Execution Program status register

T=1, executing thumb instructions

T=0, executing ARM instructions

BX reg and BLX reg instructions change the state of processor

from thumb to Arm
or from ARM to thumb
There is overhead to switch between the states, and

ARM and Thumb codes might need to be compiled separately

in different files.

This increases the complexity of software development and

reduces maximum efficiency of the CPU core
Thumb-2 instruction (16 bit and 32 bit)

• Mix of 16 bit and 32 bit instructions

• Mode switching is not required

• Extension of thumb instruction set

• Conditional execution via IT instruction

• Higher performance than thumb

Contd.
Thumb-2 instruction set is a superset of the previous 16-bit
Thumb instruction set
Provides – A large set of 16-bit instructions, enabling 2
instructions per memory fetch
A small set of 32-bit instructions to support more complex
operations
Contd.

• In thumb state ARM processor only reads half aligned

words
• Thumb-2 encoding

Cortex-M3, is always in Thumb state and does not support ARM state
Unified Assembler Language (UAL)

• To support and get the best out of the Thumb®-2

instruction set, the Unified Assembler Language (UAL) was
developed to allow selection of 16-bit and 32-bit
instructions and to make it easier to port applications
between ARM code and Thumb code by using the same
syntax for both.

• ADD R0, R1 ; R0 = R0 + R1, using Traditional Thumb

syntax

• ADD R0, R0, R1 ; Equivalent instruction using UAL syntax

Contd.
• Whether the instruction changes the flag depends on the S
suffix.
• ANDS R0, R0, R1 ;

• With UAL, we can specify which instruction is required by

adding suffixes

• ADDS.N R0, #1 ; Use 16-bit Thumb instruction (N=Narrow)

ADDS.W R0, #1 ; Use 32-bit Thumb-2 instruction (W=wide)

• The .W (wide) suffix specifies a 32-bit instruction.

• Use the .N (narrow) suffix to specify a 16-bit Thumb
instruction.
• If no suffix is given, the assembler tool can choose either
instruction but usually defaults to 16-bit Thumb code to get a
smaller size.
Some insight into the instruction set in the
Cortex™-M3

Department of ECE, VVCE 14

Data transfer instructions

One of the most basic functions in a processor is transfer of

data.

In the Cortex-M3, data transfers can be of one of the

following types:

• Moving data between register and register

• Moving data between memory and register

• Moving data between special register and register

• Moving an immediate data value into a register

Moving data between register and register

MOV R5, R3
The MOV instruction copies the value of R3 into R5

Prior
R5=0x98765431
R3= 0x AABBCCDD

After
R5=0x AABBCCDD
R3= 0x AABBCCDD
Contd.

MVN R0, R2

The MVN instruction takes the value of R2, performs

a bitwise logical NOT operation on the value,
and places the result into R0.

Prior
R2=0xFFFFFFF0
R0= 0x AABBcd09

After
R2=0xFFFFFFF0
R0=0x0000000F
Moving data between special register and register

MSR and MRS: Move to special register from general-purpose register and move
special register to general-purpose register
Moving an immediate data value into a register

MOVS R0, #0x12 ; Set R0 to 0x12

For a larger value (over 8 bits),

MOVW Rd, #imm16 Move 16-bit constant

MOVT Rd, #imm16 Move To Top

Or if the value is 32-bit, two instructions to set the

upper and lower halves:

MOVW.W R0,#0x789A ; Set R0 lower half to 0x789A

MOVT.W R0,#0x3456 ; Set R0 upper half to 0x3456.

Now ; R0=0x3456789A
Contd.
Alternate, LDR (a pseudo-instruction provided in ARM
assembler).
For example, LDR R0, =0x3456789A

This is not a real assembler command, but the ARM

assembler will convert it into a PC relative load instruction to
produce the required data.

Instead the assembler translates this pseudo-instruction into

one or more real instructions

To generate 32-bit immediate data, using LDR is

recommended rather than the MOVW.W and MOVT.W
combination because it gives better readability and the
assembler might be able to reduce the memory being used if
the same immediate data are reused in several places of the
same program.
Contd.

• LDR R0, =address1 ; R0 set to address1 ;

• address1 MOV R0, R1 ; contains program code ...
• address here is 0x4000
• the assembler will automatically set the LSB to 1
• The LDR instruction will put 0x4001 into R1;
• The LSB is set to 1 to indicate that it is Thumb code.

• If address1 is a data address, LSB will not be changed.

• For example, LDR R0, =address1 ;
• address1 DCD 0x0 ;
• address1 contains data ...
• R0 set to 0x4000 ... address1 ;
Contd.
 Contd.

For ADR, you can load the address value of a program code into
a register without setting the LSB automatically.

For example, ADR R0, address1 (address here is 0x4000)

address1 MOV R0, R1 ; contains program code ...

We will get 0x4000 in the ADR instruction.

 Comparison
LDR, is more versatile and can load immediate 32 bit number
loads memory address identified by label in to register

There equal sign (=) in the LDR statement

Set the LSB bit of register based on address is containing code

or data

ADR, loads memory address identified by label in to register

It has a short range

There is no equal sign (=) in the ADR statement

Does not set the LSB bit

Moving data between memory and register
• The basic instructions for accessing memory are Load and
Store.

• Load (LDR) transfers data from memory to registers

• Store transfers data from registers to memory.

• The transfers can be in different data sizes (byte, half

word, word, and double word
Example : LDR R5, [R1]

After execution
STR R3,[R1]

After execution
Contd.
LDRD loads a 64-bit value from memory to register
R2=0x00001000 0x00001004 AADDCCEE
0x00001000 44567832
LDRD.W R0, R1, [R2] ;

This will gives R0 = memory[0x1000] ;

R1 = memory[0x1004]

STRD stores a 64-bit value from register to memory.

R2=0x00001020, R0=0x0000AABB, R1=0x0000CCDD;

0x00001024 0000CCDD
STRD.W R0, R1, [R2] ;
0x00001020 0000AABB

This will gives memory[0x1020] = R0, ;

memory[0x1024] = R1
Contd.
Contd.
Cortex M processors supports three addressing modes

• Pre index

• Pre index with update

• Post index
Pre index
Pre index with
write back
Post index
Contd.

• Multiple Load and Store operations can be combined into

single instructions called LDM (Load Multiple) and STM
(Store Multiple).

• LDMxx Rd{!}, {reg list}

• STMxx Rd{!}, {reg list}

• The exclamation mark (!) in the instruction specifies

whether the register Rd should be updated after the
instruction is completed.

• xx specifies the addressing mode

Addressing modes for LDM and STM
Without updating R0

Address Data
0x10001020 50

R0=0x10001010 0x1000101C 40

0x10001018 30
R1=10
R2=20
0x10001014 20
R3=30
0x10001010 10
R0=0x10001010
------------
With updating R0

Address Data
R0=0x10001010
0x10001020 50
R1=10
0x1000101C 40
R2=20
R3=30 0x10001018 30

R0=0x1000101C 0x10001014 20

0x10001010 10

------------
Example of four different memory address
modes for LDM
Example of four different memory address
modes for STM
STMDB same as PUSH operation

LDMIA same as POP operation

07/10/2021 41
Data processing instructions

The Cortex-M3 provides many different instructions for data

processing

Many data operation instructions can have multiple instruction

formats

For example, an ADD instruction can operate between two

registers or between one register and an immediate data
value:

ADD R0, R0, R1 ; R0 = R0 + R1

ADDS R0, R0, #0x12 ; R0 = R0 + 0x12

ADD.W R0, R1, R2 ; R0 = R1 + R2

SDIV and UDIV

The syntax for signed and unsigned divide instructions is as

follows:

SDIV.W/UDIV.W Rd, Rn, Rm

The result is Rd = Rn/Rm.

For example,

LDR R0,=300 ;Decimal 300

MOV R1,#5

UDIV.W R2, R0, R1

This will give you an R2 result of 60 (0x3C)

32 bit Multiply instructions

UMULL R0, R4, R5, R6 ;

Unsigned (R4,R0) = R5 × R6

UMLAL R4, R5, R3, R8 ;

UnSigned (R5,R4) = (R5,R4) + R3 × R8
Logical operation instructions
Bit field processing and manipulation instructions

Bit field clear (BFC)

BFC Rd, #LSB, #width ; Bit field clear, Rd[(width+LSB-1):LSB] 0

LDR R0,=0x1234FFFF
BFC.W R0, #4, #8 ;

31 - - - 13 12 11 10 9 8 7 6 5 44 3 2 1 0
0 00 1 0 0 1 0 0 0 1 1 01 001 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

31 - - 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 00 1 0 0 1 0 0 0 1 1 01 001 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1

This will give R0 = 0x1234F00F 8+4-1 4

Bit field processing and manipulation instructions

Bit field clear (BFC)

BFC Rd, #LSB, #width ; Bit field clear, Rd[(width+LSB-1):LSB] 0

LDR R0,=0x1234FFFF
BFC.W R0, #8, #8 ;

31 - 15 14 1 12 11 10 9 8 7 6 5 4 3 2 1 0
3
0 00 1 0 01 0 0011 0100 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

31 1 14 1 12 11 10 9 8 7 6 5 4 3 2 1 0
5 3
0 00 1 0 010 0 011 0 10 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

8+8-1 8
This will give R0 = 0x123400FF
Bit field insert (BFI): Insert bit field to a register

BFI Rd, Rn, #LSB, #width ;

Rd[(width+LSB-1):LSB] Rn [(width-1):0]

LDR R0,=0x12345678,LDR R1,=0x3355AACC

BFI.W R1, R0, #8, #16 ;

R0
31 - 15 14 1 12 11 10 9 8 7 6 5 4 3 2 1 0
3
0 00 10 0 1 0 00 1 1 0 100 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0

31 23 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 1 1 0 0 1 1 00 11 00 1 0 1 10 10 01 10 1 10 1 0 10 00 1 1 0 0 1 1 0 0

R1
16+8-1 8

This will give R1 = 0x335678CC

Bit field insert (BFI): Insert bit field to a register

BFI R0, R4, #16, #6

LDR R4,=0x12333378,
LDR R0,=0x3355AACC

R4
31 - 15 14 1 12 11 10 9 8 7 6 5 4 3 2 1 0
3
0 00 10 0 1 0 00 1 1 0 011 0 0 1 1 0 0 1 1 0 1 1 1 1 0 0 0

31 23 2 2 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
21 6
0 0 1 1 0 0 1 1 0 1 10 11 10 01 0 01 1 0 1 0 1 0 1 0 1 1 0 0 1 1 0 0

R0
16+6-1 16 This will give R0 = 0x3338AACC
Bit field extract (BFX) Extract from Rn and
write in Rd

UBFX.W ,Rd , Rn,<#lsb>, <#width>

SBFX.W ,Rd , Rn, <#lsb>, <#width>
 LDR R0,=0x5678ABCD
UBFX.W R1, R0, #4, #8

R0

31 - 15 14 1 12 11 10 9 8 7 6 5 4 3 2 1 0
3
0 10 10 1 1 0 01 1 1 1 000 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1
1 0 1 1 1 1 0 0
R1

31 23 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
00 00 10 10 00 00 10 10 00 10 00 10 0 10 0 10 10 0 10 0 10 0 10 01 10 1 1 0 10 1 11 00 00

This will give R1 = 0x000000BC

LDR R0,=0x5678ABCD
SBFX.W R1, R0, #4, #8;

R0

31 - 15 14 1 12 11 10 9 8 7 6 5 4 3 2 1 0
3
0 10 10 1 1 0 01 1 1 1 000 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1
1 0 1 1 1 1 0 0
R1

31 23 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
10 10 1 1 01 01 1 1 01 1 01 1 01 1 01 1 1 01 1 01 1 01 1 01 10 1 1 0 10 1 11 00 00

This will give R1 = 0xFFFFFFBC.

 UBFX R1, R11, #9, #10 ; Extract bit 9 to bit 18 (10 bits) from
R11 and zero ; extend to 32 bits and
then write the result to R8

R11

31 - 15 14 1 12 11 10 9 8 7 6 5 4 3 2 1 0
3
0 10 10 1 1 0 01 1 1 1 000 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1
0 00 1 0 1 0 1 0 1

R1

31 23 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 01 10 011 0 10 10 101 1 0 1 0 1 0 1 0 1 1 0 0 1 1 0 0

0 0 0 00 000 0 00 00 000 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1

This will give R1 = 0x00000055

 SBFX R8, R11, #9, #7 ;

R11

31 - 15 14 1 12 11 10 9 8 7 6 5 4 3 2 1 0
3
0 10 10 1 1 0 01 1 1 1 000 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1

R8
31 23 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 01 10 011 0 10 10 101 1 0 1 0 1 0 1 0 1 1 0 0 1 1 0 0

1 11 11 111 1 11 11 111 1 1 1 1 1 1 1 1 1 1 0 1 0 1 0 1

This will give R8 = 0xFFFFFFD5

Reversing the order of bits and bytes write i
RBIT

The RBIT instruction reverses the bit order in a data word.

This instruction is very useful for processing serial bit

streams in data communications.

For example,
if R1 is 0xB4E10C23

1011_0100_1110_0001_0000_1100_0010_0011

RBIT.W R0, R1
1100_0100_0011_0000_1000_0111_0010_1101

R0 = 0xC430872D
REV
Reverses the byte order in a data word
For example,
if R0 is 0x12345678
REV R2, R0
R0
31 - 15 14 1 12 11 10 9 8 7 6 5 4 3 2 1 0
3
0 00 10 0 1 0 00 1 1 0 100 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0
0 00 10 0 1 000 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0

0 1 1 1 1 0 000 1 0 1 0 1 1 0 00 1 1 0 1 0 0 0 00 10 0 1 0

R2= 0x 78563412
REVH
Reverses the byte order inside a half word.
For example,
if R0 is 0x12345678
REVH R2, R0

31 - 15 14 1 12 11 10 9 8 7 6 5 4 3 2 1 0
3
0 00 10 0 1 0 00 11 0 100 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0
0 00 10 0 1 0 00 1 1 0 100 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0
0 00 10 0 1 000 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 00

00 1 1 0 1 0 00 00 10 0 1 0 0 1 1 1 1 0 0 0 0 1 0 1 0 1 1 0

R2= 0x34127856
REVSH
Processes the lower half word, and then it sign extends the
result word.
For example,
if R0 is 0x33448899,
REVSH R1, R0
R0
31 - 15 14 1 12 11 10 9 8 7 6 5 4 3 2 1 0
0 01 10 0 1 1 01 00 0 100 1 0 03 0 1 0 0 0 1 0 0 1 1 0 0 1
0 01 10 0 1 1 01 0 0 0 100 1 0 0 0 1 0 0 0 1 0 0 1 1 0 0 1
1 0 0 0 1 0 0 0 1 0 0 1 1 0 01

1 11 11 1 1 1 11 11 1 111 1 0 0 1 1 0 0 1 1 0 0 0 1 0 0 0

R1= 0xFFFF9988
SXTB, SXTH, UXTB, and UXTH
The four instructions are used to extend a byte or half word data into a word.

SXTB R1, R0;

if R0 is 0x55AA8765
31 - 15 14 1 12 11 10 9 8 7 6 5 4 3 2 1 0
3

00 01 00 01 00 01 00 01 01 00 01 00 01 00 01 00 01 00 00 00 00 01 01 01 00 11 11 00 00 11 00 11

R1 = 0x00000065

SXTH R1, R0;

31 - 15 14 1 12 11 10 9 8 7 6 5 4 3 2 1 0
3

10 11 10 11 10 11 10 11 11 10 11 10 11 10 11 10 11 00 00 00 00 11 11 11 00 11 11 00 00 11 00 11

R1 = 0xFFFF8765
Contd.
UXTB R1, R0
if R0 is 0x55AA8765
31 - 15 14 1 12 11 10 9 8 7 6 5 4 3 2 1 0
3
0 10 10 1 0 1 10 1 0 1 010 1 0 0 0 0 1 1 1 0 1 1 0 0 1 0 1
0 00 00 0 0 0 00 0 0 0 000 0 0 0 0 0 0 0 0 0 1 1 0 0 1 0 1

R1 = 0x00000065
UXTH R1, R0;
31 - 15 14 1 12 11 10 9 8 7 6 5 4 3 2 1 0
3

00 01 00 01 00 01 00 01 01 00 01 00 01 00 01 00 11 00 00 00 00 11 11 11 00 11 11 00 00 11 00 11

R1 = 0x00008765
Shift and Rotate Instructions
Logical shift left

Logical shift right

Arithmetic shift right
 LSL R1,R0, #0x2

0 1 1 1 1 0 0 0 1 1 1 1 1 1 0 0 0 0 1 1 1 0 0 0 1 1 1 1 0 1 0 1 1

1 1 1 1 0 0 0 1 1 1 1 1 1 0 0 0 0 1 1 1 0 0 0 1 1 1 1 0 1 0 1 1 0

1 1 1 0 0 0 1 1 1 1 1 1 0 0 0 0 1 1 1 0 0 0 1 1 1 1 0 1 0 1 1 0 0
 ASR R1, R0, #0x3

1 1 1 1 0 0 0 1 1 1 1 1 1 0 0 0 0 1 1 1 0 0 0 1 1 1 1 0 1 0 1 1 0

1 1 1 1 1 0 0 0 1 1 1 1 1 1 0 0 0 0 1 1 1 0 0 0 1 1 1 1 0 1 0 1 1

1 1 1 1 1 1 0 0 0 1 1 1 1 1 1 0 0 0 0 1 1 1 0 0 0 1 1 1 1 0 1 0 1

1 1 1 1 1 1 1 0 0 0 1 1 1 1 1 1 0 0 0 0 1 1 1 0 0 0 1 1 1 1 0 1 0
 ASR R1, R0, #0x3

0 1 1 1 0 0 0 1 1 1 1 1 1 0 0 0 0 1 1 1 0 0 0 1 1 1 1 0 1 0 1 1 0

0 0 1 1 1 0 0 0 1 1 1 1 1 1 0 0 0 0 1 1 1 0 0 0 1 1 1 1 0 1 0 1 1

0 0 0 1 1 1 0 0 0 1 1 1 1 1 1 0 0 0 0 1 1 1 0 0 0 1 1 1 1 0 1 0 1

0 0 0 0 1 1 1 0 0 0 1 1 1 1 1 1 0 0 0 0 1 1 1 0 0 0 1 1 1 1 0 1 0
Rotate right without carry

Rotate right with carry

 R0R R1, R0, #0x3

1 1 1 1 0 0 0 1 1 1 1 1 1 0 0 0 0 1 1 1 0 0 0 1 1 1 1 0 1 0 1 1 0

1 1 1 1 1 0 0 0 1 1 1 1 1 1 0 0 0 0 1 1 1 0 0 0 1 1 1 1 0 1 0 1 1

1 1 1 1 1 1 0 0 0 1 1 1 1 1 1 0 0 0 0 1 1 1 0 0 0 1 1 1 1 0 1 0 1

0 1 1 1 1 1 1 0 0 0 1 1 1 1 1 1 0 0 0 0 1 1 1 0 0 0 1 1 1 1 0 1 0
 RRX R1, R0, #0x2

1 1 1 1 0 0 0 1 1 1 1 1 1 0 0 0 0 1 1 1 0 0 0 1 1 1 1 0 1 0 1 1 0

0 1 1 1 1 0 0 0 1 1 1 1 1 1 0 0 0 0 1 1 1 0 0 0 1 1 1 1 0 1 0 1 1

1 0 1 1 1 1 0 0 0 1 1 1 1 1 1 0 0 0 0 1 1 1 0 0 0 1 1 1 1 0 1 0 1
 HAPPY LEARNING


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