MPMC
MPMC
MPMC
6
Definition of a Microprocessor.
The microprocessor is a
programmable device that takes in numbers,
performs on them arithmetic or logical
operations according to the program stored in
memory and then produces other numbers as
a result.
7
Microprocessor ?
A microprocessor is multi
programmable clock driven
register based semiconductor
device that is used to fetch ,
process & execute a data
within fraction of seconds.
8
Applications
• Calculators
• Accounting system
• Games machine
• Instrumentation
• Traffic light Control
• Multi user, multi-function environments
• Military applications
• Communication systems
9
MICROPROCESSOR HISTORY
10
DIFFERENT PROCESSORS AVAILABLE
Socket
Pinless
Processor
Processor Slot
Processor
ProcessorSl
ot
11
Development of Intel Microprocessors
• 8086 - 1979
• 286 - 1982
• 386 - 1985
• 486 - 1989
• Pentium - 1993
• Pentium Pro - 1995
• Pentium MMX -1997
• Pentium II - 1997
• Pentium II Celeron - 1998
• Pentium II Zeon - 1998
• Pentium III - 1999
• Pentium III Zeon - 1999
• Pentium IV - 2000
• Pentium IV Zeon - 2001
12
GENERATION OF PROCESSORS
Processor Bits Speed
8080 8 2 MHz
8086 16 4.5 – 10
MHz
8088 16 4.5 – 10
MHz
80286 16 10 – 20
MHz
80386 32 20 – 40
MHz
80486 32 40 – 133
MHz
13
GENERATION OF PROCESSORS
Pentium 32 60 – 233
MHz
Pentium 32 150 – 200
Pro MHz
Pentium II, 32 233 – 450
Celeron , MHz
Xeon
Pentium 32 450 MHz –
III, Celeron 1.4 GHz
, Xeon
Pentium IV, 32 1.3 GHz –
Celeron , 3.8 GHz
Xeon
Itanium 64 800 MHz –
3.0 GHz
14
Intel 4004
Introduced in 1971.
15
Intel 4040
Introduced in 1971.
It was also 4-bit µP.
16
8-bit Microprocessors
17
Intel 8008
Introduced in 1972.
It was first 8-bit µP.
Its clock speed was
500 KHz.
Could execute
50,000 instructions
per second.
18
Intel 8080
Introduced in 1974.
It was also 8-bit µP.
Its clock speed was
2 MHz.
It had 6,000
transistors.
19
Intel 8085 Introduced in 1976.
It was also 8-bit µP.
Its clock speed was 3 MHz.
Its data bus is 8-bit and
address bus is 16-bit.
It had 6,500 transistors.
Could execute 7,69,230
instructions per second.
It could access 64 KB of
memory.
It had 246 instructions.
20
16-bit Microprocessors
21
Introduced in 1978.
It was created as a
cheaper version of
Intel’s 8086.
24
INTEL 80286
Introduced in 1982.
It was 16-bit µP.
Its clock speed was 8
MHz.
Its data bus is 16-bit
and address bus is 24-
bit.
It could address 16 MB
of memory.
It had 1,34,000 25
transistors.
32-BIT MICROPROCESSORS
26
Introduced in 1986.
28
Introduced in 1993.
INTEL PENTIUM
It was also 32-bit µP.
29
INTEL PENTIUM PRO
Introduced in 1995.
It was also 32-bit µP.
It had 21 million
transistors.
Cache memory:
8 KB for instructions.
8 KB for data.
30
INTEL PENTIUM II
Introduced in 1997.
It was also 32-bit µP.
Its clock speed was 233
MHz to 500 MHz.
Could execute 333
million instructions per
second.
31
INTEL PENTIUM II XEON
Introduced in 1998.
32
INTEL PENTIUM III
Introduced in 1999.
It was also 32-bit µP.
Its clock speed varied
from 500 MHz to 1.4
GHz.
It had 9.5 million
transistors.
33
INTEL PENTIUM IV
Introduced in 2000.
It had 42 million
transistors.
34
Introduced in 2006.
INTEL DUAL CORE
It is 32-bit or 64-bit µP.
35
36
64-BIT MICROPROCESSORS
37
Intel Core 2 Intel Core i3
38
INTEL CORE I5 INTEL CORE I7
39
Basic Terms
• Bit: A digit of the binary number { 0 or 1 }
• Nibble: 4 bit Byte: 8 bit word: 16 bit
• Double word: 32 bit
• Data: binary number/code operated by an
instruction
• Address: Identification number for memory
locations
• Clock: square wave used to synchronize various
devices in µP
• Memory Capacity = 2^n ,
n->no. of address lines
40
BUS CONCEPT
• BUS: Group of conducting lines that carries data ,
address & control signals.
CLASSIFICATION OF BUSES:
1.DATA BUS: group of conducting lines that carries
data.
2. ADDRESS BUS: group of conducting lines that
carries address.
3.CONTROL BUS: group of conducting lines that
carries control signals {RD, WR etc}
CPU BUS: group of conducting lines that directly
connected to µP
SYSTEM BUS: group of conducting lines that carries
data , address & control signals in a µP system
41
TRISTATE LOGIC
3 logic levels are:
• High State (logic 1)
• Low state (logic 0)
• High Impedance state
High Impedance: output is not being driven to any defined logic level
by the output circuit.
42
Basic Microprocessors System
Central Processing Unit
Arithmetic-
Control
Logic
Unit
ProcessingUnit
Input Data into Output
Devices Information
Primary Storage Devices
Unit
Keyboard, Monitor
Mouse Printer
etc
1
THE 8086 MICROPROCESSOR
44
UNIT 1 Syllabus
• Introduction to 8086
• Microprocessor architecture
• Addressing modes
• Instruction set
• Assembler directives
• Assembly language programming
• Modular Programming
1.Linking and Relocation
2.Stacks , Procedures , Macros
• Interrupts and interrupt service routines
• Byte & String Manipulation. 45
8086 Microprocessor-introduction
INTEL launched 8086 in 1978
8086 is a 16-bit microprocessor with
• 16-bit Data Bus {D0-D15}
• 20-bit Address Bus {A0-A19} [can access upto
2^20= 1 MB memory locations] .
It has multiplexed address and data bus
AD0-AD15 and A16–A19.
It can support upto 64K I/O ports
46
8086 Microprocessor
It provides 14, 16-bit registers.
8086 requires one phase clock with a 33%
duty cycle to provide optimized internal
timing.
– Range of clock:
• 5 MHz for 8086
• 8Mhz for 8086-2
• 10Mhz for 8086-1
47
8086 Internal Architecture
8086 employs parallel processing
8086 CPU has two parts which operate at the
same time
• Bus Interface Unit 8086 CPU
• Execution Unit
CPU functions Bus Interface
Unit (BIU)
1. Fetch
48
Bus Interface Unit
Sends out addresses for memory locations
Fetches Instructions from memory
Reads/Writes data to memory
Sends out addresses for I/O ports
Reads/Writes data to Input/Output ports
49
Execution Unit
Tells BIU (addresses) where to fetch
instructions or data
Decodes & Executes instructions
50
Architecture Diagram of 8086
51
∑
Memory
Interface
Instruction
Decoder
AH AL
BH BL ARITHMETIC
CH CL LOGIC UNIT
CONTROL
DH DL
SYSTEM
STACK POINTER (SP)
BASE POINTER (BP) OPERANDS
FLAGS
SOURCE INDEX (SI)
DESTINATION INDEX (DI)
EU 52
Execution Unit
Main components are
• Instruction Decoder
• Control System
• Arithmetic Logic Unit
• General Purpose Registers
• Flag Register
• Pointer & Index registers
53
Instruction Decoder
Translates instructions fetched from memory
into a series of actions which EU carries out
Control System
Generates timing and control signals to
perform the internal operations of the
microprocessor
56
Flag Register
U U U U OF DF IF TF SF ZF U AF U PF U CF
1. CF CARRY FLAG
Conditional Flags
2. PF PARITY FLAG
(Compatible with 8085,
3. AF AUXILIARY CARRY
except OF)
4. ZF ZERO FLAG
5. SF SIGN FLAG
6. OF OVERFLOW FLAG
7. TF TRAP FLAG
Control Flags
8. IF INTERRUPT FLAG
9. DF DIRECTION FLAG
57
Flag Register
Auxiliary Carry Flag
Carry Flag
This is set, if there is a carry from the
lowest nibble, during addition, or This flag is set, when there is
borrow during subtraction. a carry out of MSB in case of
addition or a borrow in case
of subtraction.
This flag is set, when the This flag is set, when the This flag is set to 1, if the lower
result of any computation accumulator result is zero byte of the result contains even
is negative number of 1’s ; for odd number
of 1’s set to zero.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OF DF IF TF SF ZF AF PF CF
Trap Flag
Over flow Flag This flag is set, if an If this flag is set, the processor
overflow occurs, i.e, if the result is out of range enters the single step execution
mode by generating internal
interrupts after the execution of
each instruction
Direction Flag Interrupt Flag
This is used by string manipulation instructions. If this flag bit
is ‘0’, the string is processed beginning from the lowest Causes the 8086 to recognize
address to the highest address, i.e., auto incrementing mode. external mask interrupts; clearing IF
Otherwise, the string is processed from the highest address disables these interrupts.
towards the lowest address, i.e., auto incrementing mode. 58
Registers, Flag
8086 registers
categorized 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
into 4 groups OF DF IF TF SF ZF AF PF CF
61
Instruction Queue
8086 employs parallel processing
When EU is busy decoding or executing
current instruction, the buses of 8086 may
not be in use.
At that time, BIU can use buses to fetch upto
six instruction bytes for the following
instructions
BIU stores these pre-fetched bytes in a FIFO
register called Instruction Queue
When EU is ready for its next instruction, it
simply reads the instruction from the queue
in BIU
62
Pipelining
EU of 8086 does not have to wait in
between for BIU to fetch next
instruction byte from memory
So the presence of a queue in 8086
speeds up the processing
Fetching the next instruction while the
current instruction executes is called
pipelining
63
Memory Segmentation
8086 has a 20-bit address bus
So it can address a maximum of 1MB of
memory
8086 can work with only four 64KB segments
at a time within this 1MB range
These four memory segments are called
• Code segment
• Stack segment
• Data segment
• Extra segment
64
Memory
64KB Memory 1 00000H
Segment 2
3
4
4
5
Only 4 such segments can be 6
addressed at a time 7
8
1MB
9
Address
10 Range
11
12
13
14
15
16 FFFFFH
65
Code Segment
That part of memory from where BIU is
currently fetching instruction code bytes
Stack Segment
A section of memory set aside to store
addresses and data while a subprogram
executes
66
Memory
Code Segment 1 00000H
2
4
Data & Extra 5
Segments 6
8
1MB
9 Address
10 Range
11
12
13
14
15
68
Memory
1 00000H
CS 1000 0H Code Segment
3
Starting Addresses
8
1MB
9
of Segments Address
10
Range
11
12
13
14
15
71
Physical Address Calculation Memory
Start of Code Segment
1 00000H
348A0H Data
Segment
IP = 4214H 3
4
Code Byte 38AB4H MOV AL, BL
Code
Segment
Extra
Segment
7 1MB
8 Address
9 Range
CS 348A0 H 10
11
IP + 4214 H 12
Physical Address 38AB4 H 13
14
15
Stack
72
Segment FFFFFH
Stack Segment (SS) Register
Stack Pointer (SP) Register
Upper 16-bits of the starting address of
stack segment is stored in SS register
It is located in BIU
SP register holds a 16-bit offset from the
start of stack segment to the top of the
stack
It is located in EU
73
Other Pointer & Index Registers
Base Pointer (BP) register
Source Index (SI) register
Destination Index (DI) register
Can be used for temporary storage of data
Main use is to hold a 16-bit offset of a data
word in one of the segments
74
ADDRESSING
MODES OF
8086
75
Various Addressing Modes
1. Immediate Addressing Mode
2. Register Addressing Mode
3. Direct Addressing Mode
4. Register Indirect Addressing Mode
5. Indexed Addressing Mode
6. Register Relative Addressing Mode
7. Based Indexed Addressing Mode
8. Relative Based Indexed Addressing
Mode
9. Strings Addressing Mode
76
1. IMMEDIATE ADDRESSING MODE
• The instruction will specify the name
of the register which holds the data
to be operated by the instruction.
AL=20H, AH=10H
77
2.REGISTER ADDRESSING MODE
• In immediate addressing mode, an
8-bit or 16-bit data is specified as
part of the instruction
OR
78
3. DIRECT ADDRESSING MODE
79
4. REGISTER INDIRECT ADDRESSING MODE
80
5.Indexed Addressing Mode
offset of the operand is stored in one of the index registers.
81
6. REGISTER RELATIVE ADDRESSING MODE
Eg: MOV AX, 50H [BX]
82
7.BASED INDEXED ADDRESSING MODES
83
8. RELATIVE BASED INDEXED ADDRESSING
MODE
MOV AX, 50H [BX] [SI]
84
INSTRUCTION
SET of 8086
86
Instruction set basics
• Instruction:- An instruction is a binary pattern designed
inside a microprocessor to perform a specific function.
88
Types of instruction set of 8086
microprocessor
(1). Data Copy/Transfer instructions.
BEFORE AFTER
EXECUTION EXECUTION
A AL A AL
H H
B BL MOV CL,M B BL
H H
40 40
C CL C CL 40
H H
D DL D DL
H H 91
Stack Pointer
It is a 16-bit register, contains the address of the data
item currently on top of the stack.
92
(2). Push Source
Source can be register, segment register or
memory.
This instruction pushes the contents of specified
source on to the stack.
In this stack pointer is decremented by 2.
The higher byte data is pushed first (SP-1).
Then lower byte data is pushed (SP-2).
E.g.:
(1). PUSH AX;
(2). PUSH DS;
(3). PUSH [5000H];
93
INITIAL POSITION
(1) STACK
POINTER
DECREMENTS SP & STORES HIGHER
BYTE
94
BEFORE EXECUTION
SP 2002H
2000H
BH BL
2001H
CH 10 CL 50
DH DL 2002H
PUSH CX
AFTER EXECUTION
2000H 50
SP 2000H
BH BL
2001H 10
CH 10 CL 50
DH DL 2002H
95
(3) POP Destination
Destination can be register, segment register or
memory.
This instruction pops (takes) the contents of
specified destination.
In this stack pointer is incremented by 2.
The lower byte data is popped first (SP+1).
Then higher byte data is popped (SP+2).
E.g.
(1). POP AX;
(2). POP DS;
(3). POP [5000H];
96
INITIAL POSITION AND READS LOWER
(1) STACK BYTE
POINTER LOWER BYTE
INCREMENTS SP
LOWER BYTE
HIGHER BYTE
(3) STACK
POINTER
97
BEFORE EXECUTION
2000H 30
SP 2000H
2001H 50
BH BL
2002H
POP BX
AFTER EXECUTION
2000H 30
SP 2002H 2001H 50
BH 5 BL 30 2002H
0 98
(4). XCHG Destination, source;
•E.g.
(1). XCHG BX, AX;
(2). XCHG [5000H],AX;
99
BEFORE EXECUTION AFTER EXECUTION
AH 20 AL 40 AH 70 AL 80
BH 70 BL 80 BH 20 BL 40
XCHG AX,BX
100
(5)IN AL/AX, 8-bit/16-bit port address
PORT 10 AL
80H
IN AL,80H
AFTER EXECUTION
PORT 10 AL 10
80H
102
OUT 8-bit/16-bit port address, AL/AX
PORT 10 AL 40
50H
OUT 50H,AL
AFTER EXECUTION
PORT 40 AL 40
50H
104
(7) XLAT
Also known as translate instruction.
It is used to find out codes in case of code conversion.
i.e. it translates code of the key pressed to the
corresponding 7-segment code.
After execution this instruction contents of AL register
always gets replaced.
E.g. XLAT;
105
8.LEA 16-bit register (source), address (dest.)
E.g.
(1). LEA BX,Address;
(2). LEA SI,Address[BX];
106
(9). LDS 16-bit register (source), address (dest.);
(10). LES 16-bit register (source), address (dest.);
E.g.
(1). LDS BX,5000H;
(2). LES BX,5000H;
107
(1). LDS BX,5000H;
(2). LES BX,5000H;
15 0 7 0
BX 20 10 10 5000H
20
5001H
30 5002H
DS/ES 40 30
40 5003H
108
(11). LAHF:- This instruction loads the AH register
from the contents of lower byte of the flag register.
This command is used to observe the status of the
all conditional flags of flag register.
E.g. LAHF;
109
PUSH & POP
(13). PUSH F:- This instruction decrements the
stack pointer by 2.
It copies contents of flag register to the memory
location pointed by stack pointer.
E.g. PUSH F;
Addition,
Subtraction,
Increment,
Decrement.
111
(2). Arithmetic Instructions
(1). ADD destination, source;
This instruction adds the contents of source operand with
the contents of destination operand.
The source may be immediate data, memory location or
register.
The destination may be memory location or register.
The result is stored in destination operand.
AX is the default destination register.
112
AFTER EXECUTION
BEFORE EXECUTION
AH 30 AL 30
AH 10 AL 10 ADD AX,2020H
1010
+2020
3030
AH 10 AL 10 AH 30 AL 30
ADD AX,BX
BH 20 BL 20 BH 20 BL 20
113
ADC destination, source
This instruction adds the contents of source
operand with the contents of destination operand
with carry flag bit.
The source may be immediate data, memory
location or register.
The destination may be memory location or
register.
The result is stored in destination operand.
AX is the default destination register.
114
(3) INC source
This instruction increases the contents of source
operand by 1.
The source may be memory location or register.
The source can not be immediate data.
The result is stored in the same place.
115
BEFORE EXECUTION AFTER EXECUTION
AH 10 AL 11 INC AX AH 10 AL 12
116
4. DEC source
This instruction decreases the contents of
source operand by 1.
The source may be memory location or register.
The source can not be immediate data.
The result is stored in the same place.
117
BEFORE EXECUTION AFTER EXECUTION
AH 10 AL 11 DEC AX AH 10 AL 10
118
(5) SUB destination, source;
This instruction subtracts the contents of source
operand from contents of destination.
The source may be immediate data, memory
location or register.
The destination may be memory location or
register.
The result is stored in the destination place.
AH 20 AL 00 SUB AX,1000H AH 10 AL 00
2000
-1000
=1000
AH 20 AL 00 AH 10 AL 00
SUB AX,BX
BH 10 BL 00 BH 10 BL 00
120
(6). SBB destination, source;
Also known as Subtract with Borrow.
This instruction subtracts the contents of source
operand & borrow from contents of destination
operand.
The source may be immediate data, memory
location or register.
The destination may be memory location or
register.
The result is stored in the destination place.
B 1 SBB AX,1000H
AH 20 AL 20 AH 10 AL 19
2020
- 1000
1020-
BEFORE EXECUTION 1=1019 AFTER EXECUTION
B 1
AH 20 AL 20 AH 10 AL 19
SBB AX,BX
BH 10 BL 10 BH 10 BL 10
2050
122
(7). CMP destination, source
Also known as Compare.
This instruction compares the contents of source
operand with the contents of destination operands.
The source may be immediate data, memory
location or register.
The destination may be memory location or
register.
Then resulting carry & zero flag will be set or reset.
AH 10 AL 00
BH 10 BL 00
CMP AX,BX CY 0 Z 1
124
AAA (ASCII Adjust after Addition):
The data entered from the terminal is in ASCII format.
In ASCII, 0 – 9 are represented by 30H – 39H.
This instruction allows us to add the ASCII codes.
This instruction does not have any operand.
126
MUL operand
Unsigned Multiplication.
Operand contents are positively signed.
Operand may be general purpose register or memory
location.
If operand is of 8-bit then multiply it with contents of AL.
If operand is of 16-bit then multiply it with contents of AX.
Result is stored in accumulator (AX).
127
IMUL operand
Signed Multiplication.
Operand contents are negatively signed.
Operand may be general purpose register, memory location
or index register.
If operand is of 8-bit then multiply it with contents of AL.
If operand is of 16-bit then multiply it with contents of AX.
Result is stored in accumulator (AX).
128
DIV operand
Unsigned Division.
Operand may be register or memory.
Operand contents are positively signed.
Operand may be general purpose register or
memory location.
AL=AX/Operand (8-bit/16-bit) & AH=Remainder.
130
Multiplication and Division Examples
131
BEFORE EXECUTION
AH 00 AL 05
BH 00 BL 03
CH CL
AH 00 AL 0F
BH BL
CH CL
DH 00 DL 00
132
BEFORE EXECUTION
AH 00 AL 0F
BH 00 BL 02
CH CL AX=Quotient {0007}
DX=Reminder {0001}
DIV BX 000F =7 1
AFTER EXECUTION 0002 2
AH 00 AL 07
BH BL
CH CL
DH 00 DL 01
133
134
135
136
LOGICAL (or) Bit Manipulation
Instructions
These instructions are used at the bit level.
137
Bit Manipulation Instructions(LOGICAL Instructions)
• AND
– Especially used in clearing certain bits (masking)
xxxx xxxx AND 0000 1111 = 0000 xxxx
(clear the first four bits)
– Examples: AND BL, 0FH
• OR
– Used in setting certain bits
xxxx xxxx OR 0000 1111 = xxxx 1111
(Set the upper four bits)
138
XOR
– Used in Inverting bits
139
AFTER EXECUTION
BEFORE EXECUTION
AH FF AL FF AH 11 AL 11
AND AX,BXH
BH 11 BL 11 BH 11 BL 11
140
AFTER EXECUTION
BEFORE EXECUTION
AH FF AL FF AH FF AL FF
OR AX,BXH
BH 11 BL 11 BH 11 BL 11
141
AFTER EXECUTION
BEFORE EXECUTION
AH FF AL FF AH EE AL EE
XOR AX,BXH
BH 11 BL 11 BH 11 BL 11
142
AFTER EXECUTION
BEFORE EXECUTION
AH FF AL FF AH 00 AL 00
NOT AXH
143
SHL Instruction
The SHL (shift left) instruction performs a logical left shift
on the destination operand, filling the lowest bit with 0.
0
CF
mov dl,5d
shl dl,1
144
SHR Instruction
The SHR (shift right) instruction performs a logical right shift
on the destination operand. The highest bit position is filled
with a zero.
0
CF
MOV DL,80d
SHR DL,1 ; DL = 40
SHR DL,2 ; DL = 10
145
SAR Instruction
SAR (shift arithmetic right) performs a right
arithmetic shift on the destination operand.
CF
MOV DL,-80
SAR DL,1 ; DL = -40
SAR DL,2 ; DL = -10
146
Shifting left n bits multiplies the operand by 2n
For example, 5 * 22 = 20
For example, 80 / 23 = 10
147
ROL Instruction
ROL (rotate) shifts each bit to the left
The highest bit is copied into both the Carry flag
and into the lowest bit
No bits are lost
CF
MOV Al,11110000b
ROL Al,1 ; AL = 11100001b
MOV Dl,3Fh
ROL Dl,4 ; DL = F3h
148
ROR Instruction
ROR (rotate right) shifts each bit to the right
The lowest bit is copied into both the Carry flag and
into the highest bit
No bits are lost
CF
MOV AL,11110000b
ROR AL,1 ; AL = 01111000b
MOV DL,3Fh
ROR DL,4 ; DL = F3h
149
RCL Instruction
RCL (rotate carry left) shifts each bit to the left
Copies the Carry flag to the least significant bit
Copies the most significant bit to the Carry flag
CF
CLC ; CF = 0
MOV BL,88H ; CF,BL = 0 10001000b
RCL BL,1 ; CF,BL = 1 00010000b
RCL BL,1 ; CF,BL = 0 00100001b
150
RCR Instruction
RCR (rotate carry right) shifts each bit to the right
Copies the Carry flag to the most significant bit
Copies the least significant bit to the Carry flag
CF
STC ; CF = 1
MOV AH,10H ; CF,AH = 00010000 1
RCR AH,1 ; CF,AH = 10001000 0
151
SHL Instruction
The SHL (shift left) instruction performs a logical left
shift on the destination operand, filling the lowest bit
with 0.
0
CF
BEFORE
EXECUTION
0 0 0 0 0 1 0 1 =05H
CF
=0AH
AFTER 0 0 0 0 0 1 0 1 0
EXECUTION
152
SHR Instruction
0
CF
BEFORE
EXECUTION
0 0 0 0 0 1 0 1 =05H
CF
AFTER 0 0 0 0 0 0 1 0
EXECUTION
1
=02H
153
ROL Instruction
CF
BEFORE
EXECUTION 0 0 0 0 0 1 0 1 =05H
CF
AFTER 0 0 0 0 0 1 0 1 0 =0AH
EXECUTION
154
ROR Instruction
CF
BEFORE 0 0 0 0 0 1 0 1 =05H
EXECUTION
CF
AFTER 1 0 0 0 0 0 1 0 1 =82H
EXECUTION
155
Branching Instructions (or)
Program Execution Transfer
Instructions
These instructions cause change in the sequence of the execution
of instruction.
This change can be through a condition or sometimes
unconditional.
The conditions are represented by flags.
156
CALL Des:
RET:
157
SUBROUTINE & SUBROUTINE HANDILING INSTRUCTIONS
Main program
Subroutine A
First Instruction
Call subroutine A
Next instruction
Return
Call subroutine A
Next instruction
158
JMP Des:
159
Conditional Jump Table
Mnemonic Meaning
JA Jump if Above
JAE Jump if Above or Equal
JB Jump if Below
JBE Jump if Below or Equal
JC Jump if Carry
JE Jump if Equal
JNC Jump if Not Carry
JNE Jump if Not Equal
JNZ Jump if Not Zero
JPE Jump if Parity Even
JPO Jump if Parity Odd
JZ Jump if Zero
160
Loop Des:
161
String Instructions
String in assembly language is just a sequentially stored bytes or
words.
There are very strong set of string instructions in 8086.
162
CMPS Des, Src:
SCAS String:
It scans a string.
163
MOVS / MOVSB / MOVSW:
164
1. Copying a string (MOV SB)
MOV CX,0003 copy 3 memory locations
MOV SI,1000
MOV DI,2000
L1 CLD
MOV SB
DEC CX decrement CX
JNZ L1
HLT
165
2. Find & Replace
166
REP (Repeat):
167
Processor Control Instructions
These instructions control the processor itself.
168
STC
It sets the carry flag to 1.
CLC
CMC
It complements the carry flag.
169
STD:
It sets the direction flag to 1.
CLD:
It clears the direction flag to 0.
170
HLT instruction – HALT processing
The HLT instruction will cause the 8086 to stop fetching and
executing instructions.
NOP instruction
this instruction simply takes up three clock cycles and does no
processing.
LOCK instruction
this is a prefix to an instruction. This prefix makes sure that during
execution of the instruction, control of system bus is not taken by other
microprocessor.
WAIT instruction
this instruction takes 8086 to an idle condition. The CPU
will not do any processing during this.
171
INSTRUCTION SET-summary
1.DATA TRANSFER INSTRUCTIONS
Mnemonic Meaning Format Operation
ADC Add with carry ADC D,S (S)+(D)+(CF) (D) carry (CF)
174
Shift & Rotate Instructions
Mnemonic Meaning Format
SAL/SHL Shift arithmetic Left/ SAL/SHL D, Count
Shift Logical left
176
5. STRING INSTRUCTIONS
• CMPS Des, Src - compares the string bytes
• SCAS String - scans a string
• MOVS / MOVSB / MOVSW - moving of byte or
word
• REP (Repeat) - repetition of the instruction
177
6. PROCESSOR CONTROL INSTRUCTIONS
• STC – set the carry flag (CF=1)
• CLC – clear the carry flag (CF=0)
• STD – set the direction flag (DF=1)
• CLD – clear the direction flag (DF=0)
• HLT – stop fetching & execution
• NOP – no operation(no processing)
• LOCK - control of system bus is not taken by other µP
• WAIT - CPU will not do any processing
• ESC - µP does NOP or access a data from memory for coprocessor
178
Assembler
Directives
ASSUME,END,ENDP,EQU,EVEN,DD – 8 mark
179
Directives Expansion
180
• ASSUME Directive - The ASSUME directive is
used to tell the assembler that the name of
the logical segment should be used for a
specified segment.
• DB(define byte) - DB directive is used to
declare a byte type variable or to store a byte
in memory location.
• DW(define word) - The DW directive is used
to define a variable of type word or to reserve
storage location of type word in memory.
181
• DD(define double word) :This directive is used
to declare a variable of type double word or
restore memory locations which can be
accessed as type double word.
• DQ (define quadword) :This directive is used
to tell the assembler to declare a variable 4
words in length or to reserve 4 words of
storage in memory .
• DT (define ten bytes):It is used to inform the
assembler to define a variable which is 10
bytes in length or to reserve 10 bytes of
storage in memory.
182
• END- End program .This directive indicates the
assembler that this is the end of the program
module. The assembler ignores any
statements after an END directive.
• ENDP- End procedure: It indicates the end of
the procedure (subroutine) to the assembler.
• ENDS-End Segment: This directive is used with
the name of the segment to indicate the end
of that logical segment.
• EQU - This EQU directive is used to give a
name to some value or to a symbol.
183
• PROC - The PROC directive is used to identify
the start of a procedure.
• PTR -This PTR operator is used to assign a
specific type of a variable or to a label.
• ORG -Originate : The ORG statement
changes the starting offset address of the
data.
184
Directives examples
• ASSUME CS:CODE cs=> code segment
• ORG 3000
• NAME DB ‘THOMAS’
• POINTER DD 12341234H
• FACTOR EQU 03H
185
Assembly Language
Programming(ALP)
8086
186
Program 1: Increment an 8-bit number
187
Program 3: Decrement an 8-bit number
188
Program 5: 1’s complement of an 8-bit number.
189
Program 7: 2’s complement of an 8-bit number.
• MOV AL, 05H Move 8-bit data to AL.
• NOT AL Complement AL.
• INC AL Increment AL
After Execution AX = FAH + 1 = FB
Program 8: 2’s complement of a 16-bit
number.
• MOV AX, 0005H Move 16-bit data to AX.
• NOT AX Complement AX.
• INC AX Increment AX
After Execution AX = FFFAH + 1 = FFFB
190
Program 9: Add two 8-bit numbers
MOV AL, 05H Move 1st 8-bit number to AL.
MOV BL, 03H Move 2nd 8-bit number to BL.
ADD AL, BL Add BL with AL.
After Execution AL = 08H
191
Program 11: subtract two 8-bit numbers
MOV AL, 05H Move 1st 8-bit number to AL.
MOV BL, 03H Move 2nd 8-bit number to BL.
SUB AL, BL subtract BL from AL.
After Execution AL = 02H
193
Program 15: Multiply two 16-bit unsigned
numbers.
MOV AX, 0004H Move 1st 16-bit number to AL.
MOV BX, 0002H Move 2nd 16-bit number to BL.
MUL BX Multiply BX with AX and the result will
be in DX:AX {4*2=0008=> 08=> AX , 00=> DX}
194
Detailed coding
16 BIT ADDITION
195
Detailed coding
16 BIT SUBTRACTION
196
16 BIT MULTIPLICATION
197
16 BIT DIVISION
198
SUM of N numbers
MOV AX,0000
MOV SI,1100
MOV DI,1200
MOV CX,0005 5 NUMBERS TO BE TAKEN SUM
MOV DX,0000
L1: ADD AX,[SI]
INC SI
INC DX
CMP CX,DX
JNZ L1
MOV [1200],AX
HLT 199
Average of N numbers
MOV AX,0000
MOV SI,1100
MOV DI,1200
MOV CX,0005 5 NUMBERS TO BE TAKEN AVERAGE
MOV DX,0000
L1: ADD AX,[SI]
INC SI
INC DX
CMP CX,DX
JNZ L1
DIV CX AX=AX/5(AVERAGE OF 5 NUMBERS)
MOV [1200],AX
HLT 200
FACTORIAL of N
MOV CX,0005 5 Factorial=5*4*3*2*1=120
MOV DX,0000
MOV AX,0001
L1: MUL CX
DEC DX
CMP CX,DX
JNZ L1
MOV [1200],AX
HLT
201
ASCENDING ORDER
202
203
DECENDING ORDER
205
LARGEST NUMBER
206
SMALLEST NUMBER
207
Modular
Programming
208
• Generally , industry-programming projects consist
of thousands of lines of instructions or operation
code.
• The size of the modules are reduced to a humanly
comprehensible and manageable level.
• Program is composed from several smaller
modules. Modules could be developed by
separate teams concurrently.OBJ modules
(Object modules).
• The .OBJ modules so produced are combined
using a LINK program.
• Modular programming techniques simplify the
software development process
209
CHARACTERISTICS of module:
1. Each module is independent of other modules.
2. Each module has one input and one output.
3. A module is small in size.
4. Programming a single function per module is a goal
Advantages of Modular Programming:
• It is easy to write, test and debug a module.
• Code can be reused.
• The programmer can divide tasks.
• Re-usable Modules can be re-used within a program
DRAWBACKS:
Modular programming requires extra time and memory
210
MODULAR PROGRAMMING:
1.LINKING & RELOCATION
2.STACKS
3.Procedures
4.Interrupts & Interrupt Routines
5.Macros
211
LINKING &
RELOCATION
212
LINKER
• A linker is a program used to join together several
object files into one large object file.
• The linker produces a link file which contains the
binary codes for all the combined modules.
213
• The loader is a part of the operating system
and places codes into the memory after
reading the ‘.exe’ file
• A program called locator reallocates the
linked file and creates a file for permanent
location of codes in a standard format.
214
Creation and execution of a program
215
Loader
->Loader is a utility program which takes object code as
input prepares it for execution and loads the
executable code into the memory .
->Loader is actually responsible for initializing the
process of execution.
Functions of loaders:
1.It allocates the space for program in the memory(Allocation)
2.It resolves the code between the object modules(Linking)
3. some address dependent locations in the program, address constants
must be adjusted according to allocated space(Relocation)
4. It also places all the machine instructions and data of corresponding
programs and subroutines into the memory .(Loading)
216
Relocating loader (BSS Loader)
• When a single subroutine is changed then all
the subroutine needs to be reassembled.
• The binary symbolic subroutine (BSS) loader
used in IBM 7094 machine is relocating loader.
• In BSS loader there are many procedure
segments
• The assembler reads one sourced program
and assembles each procedure segment
independently
217
• The output of the relocating loader is the object program
• The assembler takes the source program as input; this source
program may call some external routines.
SEGMENT COMBINATION:
ASM-86 assembler regulating the way segments with the
same name are concatenated & sometimes they are overlaid.
Form of segment directive:
Segment name SEGEMENT Combine-type
Possible combine-type are:
• PUBLIC
• COMMON
• STACK
• AT
• MEMORY
218
Procedures
CALL & RET instruction
219
• Procedure is a part of code that can be called from
your program in order to make some specific task.
Procedures make program more structural and
easier to understand.
• syntax for procedure declaration:
name PROC
…………. ; here goes the code
…………. ; of the procedure ...
RET
name ENDP
here PROC is the procedure name.(used in top & bottom)
RET - used to return from OS. CALL-call a procedure
PROC & ENDP – complier directives
CALL & RET - instructions 220
EXAMPLE 1 (call a procedure)
ORG 100h
CALL m1
MOV AX, 2
RET ; return to operating system.
m1 PROC
MOV BX, 5
RET ; return to caller.
m1 ENDP
END
• The above example calls procedure m1, does MOV BX, 5 &
returns to the next instruction after CALL: MOV AX, 2.
221
Example 2 : several ways to pass
parameters to procedure
ORG 100h
MOV AL, 1
MOV BL, 2
CALL m2
CALL m2
CALL m2
CALL m2
RET ; return to operating system.
m2 PROC
MUL BL ; AX = AL * BL.
RET ; return to caller.
m2 ENDP
value of AL register is update every time the
END procedure is called.
final result in AX register is 16 (or 10h)
PUSH & POP instruction
223
• Stack is an area of memory for keeping
temporary data.
• STACK is used by CALL & RET instructions.
PUSH -stores 16 bit value in the stack.
POP -gets 16 bit value from the stack.
• PUSH and POP instruction are especially useful
because we don't have too much registers to operate
1. Store original value of the register in stack (using
PUSH).
2. Use the register for any purpose.
3. Restore the original value of the register from stack
(using POP).
224
Example-1 (store value in STACK using
PUSH & POP)
ORG 100h
MOV AX, 1234h
PUSH AX ; store value of AX in stack.
MOV AX, 5678h ; modify the AX value.
POP AX ; restore the original value of AX.
RET
END
225
Example 2: use of the stack is for
exchanging the values
ORG 100h
MOV AX, 1212h ; store 1212h in AX.
MOV BX, 3434h ; store 3434h in BX
PUSH AX ; store value of AX in stack.
PUSH BX ; store value of BX in stack.
POP AX ; set AX to original value of BX.
POP BX ; set BX to original value of AX.
RET
END
push 1212h and then 3434h, on pop we will
first get 3434h and only after it 1212h 226
MACROS
How to pass parameters using macros-6/8 Mark
227
• Macros are just like procedures, but not really.
• Macros exist only until your code is compiled
• After compilation all macros are replaced with
real instructions
• several macros to make coding easier(Reduce
large & complex programs)
Example (Macro definition)
name MACRO [parameters,...]
<instructions>
ENDM
228
Example1 : Macro Definitions
SAVE MACRO definition of MACRO name SAVE
PUSH AX
PUSH BX
PUSH CX
ENDM
229
230
MACROS with Parameters
Example:
COPY MACRO x, y ; macro named COPY with
2 parameters{x, y}
PUSH AX
MOV AX, x
MOV y, AX
POP AX
ENDM
231
INTERRUPTS
&
INTERRUPT SERVICE
ROUTINE(ISR)
232
INTERRUPT & ISR ?
• ‘Interrupts’ is to break the sequence of
operation.
• While the CPU is executing a program, on
‘interrupt’ breaks the normal sequence of
execution of instructions, diverts its execution
to some other program called Interrupt
Service Routine (ISR)
233
234
235
236
• Maskable Interrupt: An Interrupt that can be
disabled or ignored by the instructions of CPU
are called as Maskable Interrupt.
• Non- Maskable Interrupt: An interrupt that
cannot be disabled or ignored by the instructions
of CPU are called as Non- Maskable Interrupt.
• Software interrupts are machine instructions
that amount to a call to the designated interrupt
subroutine, usually identified by interrupt
number. Ex: INT0 - INT255
237
238
239
240
241
242
INTERRUPT VECTOR TABLE
NMI(INT2)
INTR
245
Byte &
String
Manipulation
246
Move, compare, store, load, scan
247
Byte Manipulation
Example 3:
Example 1:
MOV AX,[1000]
MOV AX,[1000]
MOV BX,[1002]
MOV BX,[1002]
AND AX,BX XOR AX,BX
MOV [2000],AX MOV [2000],AX
HLT HLT
Example 2: Example 4:
MOV AX,[1000]
MOV AX,[1000]
MOV BX,[1002]
OR AX,BX
NOT AX
MOV [2000],AX MOV [2000],AX
HLT HLT
248
STRING MANIPULATION
1. Copying a string (MOV SB)
MOV CX,0003 copy 3 memory locations
MOV SI,1000
MOV DI,2000
L1 CLD
MOV SB
DEC CX decrement CX
JNZ L1
HLT
249
2. Find & Replace
250
UNIT-2
8086 SYSTEM BUS
STRUCTURE
DEPARTMENTS: CSE,IT {semester 04}
ECE {semester 05}
Regulation : 2013
251
UNIT 2 Syllabus
252
8086 signals or
Pin Diagram
253
INTEL 8086-Pin Diagram/Signal Description
254
INTEL 8086 - Pin Details
Power Supply
5V ± 10%
Ground
Reset
Registers, seg
regs, flags
CS: FFFFH, IP:
0000H
If high for
minimum 4
Clock clks
Duty cycle: 33%
255
INTEL 8086 - Pin Details
Address/Data Bus:
Contains address Address Latch Enable:
bits A15-A0 when ALE
is 1 & data bits D15 – When high,
D0 when ALE is 0. multiplexed
address/data bus
contains address
information.
256
INTEL 8086 - Pin Details
INTERRUPT
Non - maskable
interrupt
Interrupt
acknowledge
Interrupt request
257
INTEL 8086 - Pin Details
Direct
Memory
Access
Hold
Hold
acknowledge
258
INTEL 8086 - Pin Details
Address/Status Bus
Address bits A19 –
A16 & Status bits S6
– S3
259
INTEL 8086 - Pin Details
1,1: No selection
260
INTEL 8086 - Pin Details
Min/Max mode
Minimum Mode: +5V
Maximum Mode: 0V
Maximum Mode
Pins
261
Minimum Mode- Pin Details
Read Signal
Write Signal
Memory or I/0
Data
Transmit/Receive
S2 S1 S0
000: INTA
001: read I/O port
010: write I/O port
011: halt
100: code access Status Signal
101: read memory
110: write memory Inputs to 8288 to
111: none -passive generate eliminated
signals due to max
mode.
263
Maximum Mode - Pin Details
Lock Output
Used to lock peripherals
off the system
DMA
Activated by using the Request/Grant
LOCK: prefix on any
instruction
Lock Output
264
Maximum Mode - Pin Details
QS1 QS0
00: Queue is idle
01: First byte of opcode
10: Queue is empty
11: Subsequent byte of
opcode
Queue Status
Used by numeric
coprocessor (8087)
265
Minmode operation
signals (MN/MX=1) Time-
0V=“0”, GND 1 40 Vcc multiplexed
AD14 AD15 5V±10%
reference Address Bus
for all AD13 A16/S3 /Status signals
voltages AD12 A17/S4 Maxmode operation (outputs)
AD11 A18/S5 signals (MN/MX=0)
AD10 A19/S6
___
AD9 BHE/S7
___ (HIGH) Control Operation Mode,
AD8 MN/MX
___ Bus (input):
Time-multiplexed AD7 INTEL RD ___ ____ (in,out) 1 = minmode
Address / Data Bus AD6 8086 HOLD (RQ/GT0)
___ ____ (8088 generates all
(bidirectional) AD5 HLDA
___ (RQ/GT1)
______ the needed control
AD4 WR__ (LOCK)
__ signals for a small
AD3 IO/M
__ (S2)
__ Status system),
Hardware AD2 DT/R
____ (S1)
__ signals
interrupt AD1 DEN (S0) (outputs) 0 = maxmode
requests (inputs) AD0 ALE
_____ (QS0)
(8288 Bus
NMI INTA
_____ (QS1)
Controller expands
2...5MHz, INTR TEST Interrupt the status signals
1/3 duty cycle CLK READY acknowledge to generate more
(input) GND 20 21 RESET (output) control signals)
266
Timing
Diagram
Basics
only for understanding
System Timing Diagrams
T-State:
— One clock period is referred to as a T-State
T-State
T1 T2 T3 T4
269
Signal Transition
occurs when the clock
signal is HIGH
Signal Transition
occurs when the clock
signal is LOW
Signal Transition
occurs from HIGH to
LOW on RISING EDGE
AD0-AD15
SYSTEM BUS
TIMING
276
Memory Read Timing Diagrams
• Dump address on address bus.
• Issue a read ( RD ) and set M/ IO to 1.
• Wait for memory access cycle.
277
Memory Write Timing Diagrams
• Dump address on address bus.
• Dump data on data bus.
• Issue a write ( WR ) and set M/ IO to 1.
278
Bus Timing
During T 1 :
• The address is placed on the Address/Data bus.
• Control signals M/ IO , ALE and DT/ R specify memory or I/O, latch the address
onto the address bus and set the direction of data transfer on data bus.
During T 2 :
• 8086 issues the RD or WR signal, DEN , and, for a write, the data.
• DEN enables the memory or I/O device to receive the data for writes and the 8086 to
receive the data for reads.
During T 3 :
• This cycle is provided to allow memory to access data.
• READY is sampled at the end of T 2 .
• If low, T 3 becomes a wait state.
• Otherwise, the data bus is sampled at the end of T 3 .
During T 4 :
• All bus signals are deactivated, in preparation for next bus cycle.
• Data is sampled for reads, writes occur for writes.
279
Setup & Hold Time
Setup time – The time before the rising edge of the clock, while the data
must be valid and constant
Hold time – The time after the rising edge of the clock during which the data
must remain valid and constant
280
WAIT State
Tw
1 2 3 4
Clock
READY
283
1.Minimum
Mode
configuration
Minimum Mode 8086 System
• 8086 is operated in minimum mode by
MN/MX pin to logic 1 ( Vcc ).
• In this mode, all the control signals are given
out by the microprocessor chip itself.
287
288
Memory READ in Minimum Mode
Memory WRITE in Minimum Mode
2.Maximum
Mode
configuration
NOTE: Explain Maximum mode signals also {refer pin diagram}
MAXIMUM MODE SIGNALS
292
8288 – BUS CONTROLLER
293
MAXIMUM MODE
294
295
296
MULTIPROCESSOR
CONFIGURATIONS
297
Coprocessor 8087
Multiprocessor
configuration
298
Multiprocessor configuration
• Multiprocessor Systems refer to the use of multiple
processors that executes instructions simultaneously
and communicate with each other using mail boxes and
Semaphores.
300
Co-processor – Intel 8087
8086 and 8087 reads
instruction bytes and puts
8087 instructions them in the respective queues
are inserted in
the 8086 NOP
program
8087 instructions have 11011
as the MSB of their first code
byte
301
Coprocessor / Closely Coupled
Configuration
302
TEST pin of 8086
• Used in conjunction with the WAIT instruction in
multiprocessing environments.
303
1.Coprocessor Execution Example
Coprocessor cannot take control of the bus, it does everything through the CPU
304
2.Closely Coupled Execution Example
• Closely Coupled
processor may take
control of the bus
independently.
305
3.Loosely Coupled Configuration
• has shared system bus, system memory, and system
I/O.
1. Daisy Chaining:
- Need a bus controller to monitor bus busy and bus request
signals
- Sends a bus grant to a Master >> each Master either keeps the
service or passes it on
- Controller synchronizes the clocks
- Master releases the Bus Busy signal when finished
Daisy Chaining:
Independent
Advantages of Multiprocessor
Configuration
1. High system throughput can be achieved by having more than
one CPU.
2. The system can be expanded in modular form.
Each bus master module is an independent unit and normally resides on
a separate PC board. One can be added or removed without affecting the
others in the system.
3. A failure in one module normally does not affect the breakdown
of the entire system and the faulty module can be easily
detected and replaced
4. Each bus master has its own local bus to access dedicated
memory or IO devices. So a greater degree of parallel processing
can be achieved.
313
INTRODUCTION
TO ADVANCED
PROCESSORS
314
Intel family of microprocessor, bus and memory sizes
80286 16 24 16M
80386 DX 32 32 4G
80486 32 32 4G
Pentium 4 & 64 40 1T
core 2
315
80186
316
80286
317
80386
318
UNIT-3
319
I/O
INTERFACING
DEPARTMENTS: CSE,IT {semester 04}
ECE {semester 05}
Regulation : 2013
UNIT 3 Syllabus
• Memory Interfacing & I/O interfacing
• Parallel communication interface {8255 PPI}
• Serial communication interface {8251 USART}
• D/A and A/D Interface {ADC 0800/0809,DAC 0800}
• Timer {or counter} – {8253/8254 Timer}
• Keyboard /display controller {8279}
• Interrupt controller {8259}
• DMA controller {8237/8257}
• Programming and applications Case studies
1.Traffic Light control
2.LED display 3.LCD display
4.Keyboard display interface 5.Alarm Controller
320
321
Data Transfers
Synchronous ----- Usually occur when
peripherals are located within the same
computer as the CPU. Close proximity
allows all state bits change at same
time on a common clock.
Asynchronous ----- Do not require that
the source and destination use the
same system clock.
322
Parallel communication
interface
INTEL 8255
327
8255 PPI
• The 8255 chip is also called as Programmable
Peripheral Interface.
• The Intel’s 8255 is designed for use with Intel’s
8-bit, 16-bit and higher capability
microprocessors
• The 8255 is a 40 pin integrated circuit (IC),
designed to perform a variety of interface
functions in a computer environment.
• It is flexible and economical.
328
Signals of 8085
8255 PIO/PPI
330
Control Logic
CS signal is the master Chip Select
A0 and A1 specify one of the two I/O Ports
CS A1 A0 Selected
0 0 0 Port A
0 0 1 Port B
0 1 0 Port C
0 1 1 Control
Register
1 X X 8255 is not
selected
Block Diagram of 8255A 334
335
CS , RD , WR , RESET , A1 , A0
338
interrupt capability
345
346
Solution:
1 0 1 0 1 1 1 0 = AEH
349
Solution:
1 0 0 0 0 0 0 0 = 80H
Solution:
1 0 0 1 1 0 1 1 = 9BH
- A parallel-in, serial-out
shift register
- A serial-in, parallel-out
shift register.
-
351
TRANSMITTER 352
Receiver
Serial communication
353
interface
INTEL 8251 USART
UNIVERSAL SYNCHRONOUS 354
ASYNCHRONOUS RECEIVER
TRANSMITTER (USART)
Programmable chip designed for
synchronous and asynchronous serial data
transmission
28 pin DIP
Coverts the parallel data into a serial stream
of bits suitable for serial transmission.
Receives a serial stream of bits and convert
it into parallel data bytes to be read by a
microprocessor.
355
BLOCK DIAGRAM 356
357
Five Sections
– Read/Write Control Logic
• Interfaces the chip with MPU
– Transmitter
• Converts parallel word received from MPU into serial bits
– Receiver
• Receives serial bits from peripheral
telephone line
358
Input Signals
CS – Chip Select
When this signal goes low, 8251 is selected by
MPU for communication
C/D – Control/Data
When this signal is high, the control register
or status register is addressed
When it is low, the data buffer is addressed
Control and Status register is differentiated by
WR and RD signals, respectively
359
• WR – Write
– writes in the control register or sends outputs to the
data buffer.
– This connected to IOW or MEMW
• RD – Read
– Either reads a status from status register or accepts
data from the data buffer
– This is connected to either IOR or MEMR
• RESET - Reset
• CLK - Clock
– Connected to system clock
– Necessary for communication with microprocessor.
360
CS C/D RD WR Function
0 1 1 0 MPU writes instruction in the
control register
0 1 0 1 MPU reads status from the status
register
0 0 1 0 MPU outputs the data to the Data
Buffer
0 0 0 1 MPU accepts data from the Data
Buffer
1 X X X USART is not Selected
361
• Control Register
– 16-bit register
– This register can be accessed an output port
when the C/D pin is high
• Status Register
– Checks ready status of a peripheral
• Data Buffer
362
Transmitter Section
Section
• TxD – Transmit Data
– Serial bits are transmitted on this line
register is empty
364
Receiver Section
Section
RxD – Receive Data
Bits are received serially on this line and
converted into parallel byte in the receiver input
RxC – Receiver Clock
RxRDY – Receiver Ready
It goes high when the USART has a character in
the buffer register and is ready to transfer it to
the MPU
Signals Associated with Modem 366
Control
• DSR- Data Set Ready
– Normally used to check if the Data Set is ready when
communicating with a modem
• DTR – Data Terminal Ready
– device is ready to accept data when the 8251 is
communicating with a modem.
• RTS – Request to send Data
– the receiver is ready to receive a data byte from
modem
• CTS – Clear to Send
367
Control words
368
369
370
371
372
Interfacing of 8255(PPI) with 8085 processor:
373
11-
374
Programming 8251
8251 mode register
7 6 5 4 3 2 1 0 Mode register
TIMER/COUNTER
390
RD: read signal 391
11-394
8254 Modes
Gate is low the
count will be Mode 0: An events counter enabled with G.
paused
Gate is high
Will continue
counting
Gate is
High output
will be high
395
Mode 2: Counter generates a series of pulses 1 clock
pulse wide
397
398
Keyboard/Display
Controller
INTEL 8279
399
Keyboard section
Display section
Scan section
a) Keyboard Display Mode Set : The format of the command word to select different
modes of operation of 8279 is given below with its bit definitions.
D7 D6 D5 D4 D3 D2 D1 D0
0 0 0 D D K K K
413
SENSOR MATRIX
SENSOR MATRIX
414
B) Programmable clock :
0 0 1 P P P P P
c) Read FIFO / Sensor RAM : The format of this command is given 415
below.
D7 D6 D5 D4 D3 D2 D1 D0
0 1 0 AI X A A A
D7 D6 D5 D4 D3 D2 D1 D0
0 1 1 AI A A A A
D7 D6 D5 D4 D3 D2 D1 D0
1 0 0 AI A A A A
D7 D6 D5 D4 D3 D2 D1 D0
1 0 1 X IW IW BL BL
E- Error mode
X- don’t care
INTERRUPT
CONTROLLER
8259 Programmable Interrupt Controller (PIC)
1. This IC is designed to simplify the implementation of the interrupt interface in the 8088
and 8086 based microcomputer systems.
2. This device is known as a ‘Programmable Interrupt Controller’ or PIC.
3. It is manufactured using the NMOS technology and It is available in 28-pin DIP.
4. The operation of the PIC is programmable under software control (Programmable)and it
can be configured for a wide variety of applications.
5. 8259A is treated as peripheral in a microcomputer system.
6. 8259A PIC adds eight vectored priority encoded interrupts to the microprocessor.
7. This controller can be expanded without additional hardware to accept up to 64
interrupt request inputs. This expansion required a master 8259A and eight 8259A
slaves.
8. Some of its programmable features are:
· The ability to accept level-triggered or edge-triggered inputs.
· The ability to be easily cascaded to expand from 8 to 64 interrupt-inputs.
· Its ability to be configured to implement a wide variety of priority schemes.
8259A PIC- PIN DIGRAM
8
2
5
9
ASSINGMENT OF SIGNALS FOR 8259:
1. D7- D0 is connected to microprocessor data bus D7-D0 (AD7-AD0).
2. IR7- IR0, Interrupt Request inputs are used to request an interrupt and to connect to a slave
in a system with multiple 8259As.
3. WR - the write input connects to write strobe signal of microprocessor.
4. RD - the read input connects to the IORC signal.
5. INT - the interrupt output connects to the INTR pin on the microprocessor from the master,
and is connected to a master IR pin on a slave.
6. INTA - the interrupt acknowledge is an input that connects to the INTA signal on the system.
In a system with a master and slaves, only the master INTA signal is connected.
7. A0 - this address input selects different command words within the 8259A.
8. CS - chip select enables the 8259A for programming and control.
9. SP/EN - Slave Program/Enable Buffer is a dual-function pin.
When the 8259A is in buffered mode, this pin is an
output that controls the data bus transceivers in a
large microprocessor-based system.
When the 8259A is not in buffered mode, this pin
programs the device as a master (1) or a slave (0).
CAS2-CAS0, the cascade lines are used as outputs from
the master to the slaves for cascading multiple
8259As in a system.
8259A PIC- BLOCK DIAGRAM
Programming the 8259A: -
The 82C59A accepts two types of command words generated by the
CPU:
1. Initialization Command Words (ICWs):
Before normal operation can begin, each 82C59A in the
system must be brought to a starting point - by a sequence of 2 to
4 bytes timed by WR pulses.
2. Operational Command Words (OCWs):
These are the command words which command the 82C59A
to operate in various interrupt modes. Among these modes are:
a. Fully nested mode.
b. Rotating priority mode.
c. Special mask mode.
d. Polled mode.
The OCWs can be written into the 82C59A anytime after
initialization.
ICW1:
Selects the vector number used with the interrupt request inputs.
For example, if we decide to program the 8259A so that it functions at vector
locations 08H-0FH, we place a 08H into this command word.
Likewise, if we decide to program the 8259A for vectors 70H-77H, we place a
70H in this ICW.
ICW3:
Is used only when ICW1 indicates that the system is operated in cascade mode.
This ICW indicates where the slave is connected to the master.
For example, if we connected a slave to IR2, then to program ICW3 for this
connection, in both master and slave, we place a 04H in ICW3.
Suppose we have two slaves connected to a master using IR0 and IR1. The
master is programmed with an ICW3 of 03H; one slave is programmed with an
ICW3 of 01H and the other with an ICW3 of 02H.
ICW4:
Is programmed only when the AEOI mod is not selected for the 8259A.
In this case, this OCW selects how the 8259A responds to an interrupt.
The modes are listed as follows in next slide:
OCW3:
Selects the register to be read, the operation of the special mask register, and
the poll command.
If polling is selected, the P-bit must be set and then output to the 8259A. The
next read operation would read the poll word. The rightmost three bits of the
poll word indicate the active interrupt request with the highest priority.
The leftmost bit indicates whether there is an interrupt, and must be checked
to determine whether the rightmost three bits contain valid information.
8237DMA CONTROLLER
453
Introduction:
Direct Memory Access (DMA) is a method of allowing data
to be moved from one location to another in a computer
without intervention from the central processor (CPU).
It is also a fast way of transferring data within (and
sometimes between) computer.
The DMA I/O technique provides direct access to the
memory while the microprocessor is temporarily disabled.
The DMA controller temporarily borrows the address bus,
data bus and control bus from the microprocessor and
transfers the data directly from the external devices to a
series of memory locations (and vice versa).
454
The 8237 DMA controller
• Supplies memory and I/O with control signals and addresses during DMA
transfer
• 4-channels (expandable)
– 0: DRAM refresh
– 1: Free
– 2: Floppy disk controller
– 3: Free
• 1.6MByte/sec transfer rate
• 64 KByte section of memory address capability with single programming
• “fly-by” controller (data does not pass through the DMA-only memory to I/O
transfer capability)
• Initialization involves writing into each channel:
• i) The address of the first byte of the block of data that must be transferred (called
the base address).
• ii) The number of bytes to be transferred (called the word count).
455
8237 pins
• CLK: System clock
• CS΄: Chip select (decoder output)
• RESET: Clears registers, sets mask register
• READY: 0 for inserting wait states
• HLDA: Signals that the μp has relinquished buses
• DREQ3 – DREQ0: DMA request input for each channel
• DB7-DB0: Data bus pins
• IOR΄: Bidirectional pin used during programming
and during a DMA write cycle
• IOW΄: Bidirectional pin used during programming
and during a DMA read cycle
• EOP΄: End of process is a bidirectional signal used as input to terminate a DMA process or
as output to signal the end of the DMA transfer
• A3-A0: Address pins for selecting internal registers
• A7-A4: Outputs that provide part of the DMA transfer address
• HRQ: DMA request output
• DACK3-DACK0: DMA acknowledge for each channel.
• AEN: Address enable signal
• ADSTB: Address strobe
• MEMR΄: Memory read output used in DMA read cycle
• MEMW΄: Memory write output used in DMA write cycle
456
8237 block diagram
457
Block Diagram Description
461
Programming and
applications Case
studies
1.Traffic Light control
2.LED display
3.LCD display
4.Keyboard display interface
462 5.Alarm Controller
1. TRAFFIC
LIGHT
CONTROL
463
Traffic lights, which may also be known as stoplights, traffic
lamps, traffic signals, signal lights, robots or semaphore, are
signaling devices positioned at road intersections, pedestrian
crossings and other locations to control competing flows of
traffic.
INTERFACING TRAFFIC LIGHT WITH 8086
The Traffic light controller section consists of 12 Nos.
point led’s arranged by 4Lanes in Traffic light interface card.
Each lane has Go(Green), Listen(Yellow) and Stop(Red) LED
is being placed.
464
LAN Direction 8086 LINES MODULES
465
CIRCUIT DIAGRAM TO INTERFACE TRAFFIC LIGHT WITH 8086
466
8086 ALP:
1100: START: MOV BX, 1200H
MOV CX, 0008H
MOV AL,[BX]
MOV DX, CONTROL PORT
OUT DX, AL
INC BX
NEXT: MOV AL,[BX]
MOV DX, PORT A
OUT DX,AL
CALL DELAY
INC BX
LOOP NEXT
JMP START
DELAY: PUSH CX
MOV CX,0005H
REPEAT: MOV DX,0FFFFH
LOOP2: DEC DX
JNZ LOOP2
LOOP REPEAT
POP CX
RET
467
Lookup Table
1200 80H
1201 21H,09H,10H,00H (SOUTH WAY)
1205 0CH,09H,80H,00H (EAST WAY)
1209 64H,08H,00H,04H (NOURTH WAY)
120D 24H,03H,02H,00H (WEST WAY)
1211 END
468
2. LED DISPLAY
469
Light Emitting Diodes (LED) is the most commonly
used components, usually for displaying pins digital states.
Typical uses of LEDs include alarm devices, timers and
confirmation of user input such as a mouse click or keystroke.
INTERFACING LED
Anode is connected through a resistor to GND & the
Cathode is connected to the Microprocessor pin. So when the
Port Pin is HIGH the LED is OFF & when the Port Pin is LOW
the LED is turned ON.
470
PIN ASSIGNMENT WITH 8086
471
INTERFACE LED WITH 8255
472
8086 ALP LED interface
1100: START: MOV AL, 80
MOV DX, FF36
OUT DX, AL
BEGIN: MOV AL, 00
MOV DX, FF30
OUT DX, AL
CALL DELAY
MOV AL, FF
OUT DX, AL
CALL DELAY
JMP BEGIN
DELAY: MOV CX, FFFF
PO: DEC CX
JNE PO
RET
473
3. LCD DISPLAY
474
475
HARDWARE CONFIGURATION OF LCD
WITH 8051/8086/8085
476
LCD INTERFACING WITH 8086
TRAINER KIT
GPIO- I (8255) J1 Connector
PORTS ADDRESS
Control port FF26
PORT A FF20
PORT B FF22
PORT C FF24
477
478
Used in UNIT 5 also
479
480
4. Keyboard display interface
481
HARDWARE DESCRIPTION OF 8279 INTERFACE CARD
Keyboard and display is configured in the encoded mode.
In the encoded mode, a binary count sequence is put on the scan
lines SL0-SL3.These lines must be externally decoded to provide
the scan lines for keyboard and display. A 3 to 8 decoder
74LS138 is provided for this purpose. The S0-S1 output lines of
this decoder are connected to the two rows of the keyboard.
And QA0 to QA7 is connected to 7 Segment Display
482
483
5. ALARM
CONTROLLER
Relevant
Material
Not exact
488
489
GPIO- I J1 Connecter
PORTS ADDRESS
Control port FF26
PORT A FF20
PORT B FF22
PORT C FF24
GPIO- II J1 Connecter
PORTS ADDRESS
Control port FF36
PORT A FF30
PORT B FF32
PORT C FF34
490
Basics
Microprocessor &
Microcontroller
491
What is Microcontroller?
Micro Controller
A smaller computer
On-chip RAM, ROM, I/O ports...
Example: Motorola’s 6811, Intel’s 8051, Zilog’s
Z8 and PIC
494
495
Microprocessor Microcontroller
Not Expansive
Expansive
Single-purpose
General-purpose
496
Home
Appliances, intercom, telephones, security systems, garage door
openers, answering machines, fax machines, home computers,
TVs, cable TV tuner, VCR, camcorder, remote controls, video
games, cellular phones, musical instruments, sewing machines,
lighting control, paging, camera, pinball machines, toys, exercise
equipment etc.
Office
Telephones, computers, security systems, fax machines,
microwave, copier, laser printer, color printer, paging etc.
Auto
Trip computer, engine control, air bag, ABS, instrumentation,
security system, transmission control, entertainment, climate
control, cellular phone, keyless entry
497
498
499
500
External Interrupts
8bit
CPU
Bus Serial
OSC 4 I/O Ports
Control Port
TXD RXD
P0 P1 P2 P3
504
8 bit CPU
On-chip clock oscillator
4K bytes of on-chip Program Memory-ROM
128 bytes of on-chip Data RAM
64KB Program Memory address space
64KB Data Memory address space
32 bidirectional I/0 lines (Port 0,1,2,3)
Port 0 { P0.0-P0.7 } – 8 pins
Port 1 { P1.0-P1.7 } – 8 pins
Port 2 { P2.0-P2.7 } – 8 pins
Port 3 { P3.0-P3.7 } – 8 pins
505
Two 16-bit timer/counters(Timer 1,Timer 0)
One serial port
UART(Universal Asynchronous Receiver Transmitter)
6-source interrupt structure
1. External interrupt INT0
2. Timer interrupt T0
3. External interrupt INT1
4. Timer interrupt T1
5. Serial communication interrupt
6. Timer Interrupt T2
4 Register Banks (Bank 0, Bank 1, Bank 2, Bank 3)
each bank has R0-R7 registers
506
Pin Description
of the 8051
or
IO Port structure
507
EA/VPP
• EA, “external access’’
508
I/O Port Pins
• The four 8-bit I/O ports
509
Port 3
• Port 3 can be used as input or output.
510
Pin Description Summary
PIN TYPE NAME AND FUNCTION
Vss I Ground: 0 V reference.
Vcc I Power Supply + 5V.
512
Architecture of
8051
microcontroller
513
514
515
516
External
External
60K
64K 64K
SFR
Bank 3 R0 R1 R2 R3 R4 R5 R6 R7
Bank 2 R0 R1 R2 R3 R4 R5 R6 R7
Bank 1 R0 R1 R2 R3 R4 R5 R6 R7
Bank 0 R0 R1 R2 R3 R4 R5 R6 R7
522
Program Status Word [PSW]
C AC F0 RS1 RS0 OV F1 P
Carry Parity
Auxiliary Carry User Flag 1
00-Bank 0
01-Bank 1
10-Bank 2
11-Bank 3
523
Data Pointer Register (DPTR)
It consists of two separate registers:
DPH (Data Pointer High) &
DPL (Data Pointer Low).
524
Stack Pointer (SP) Register
8 bit
8 bit
8 bit
8 bit
525
INSTRUCTION
SET OF
8051
526
8051 Instruction Set
• The instructions are grouped into 5 groups
– Arithmetic
– Logic
– Data Transfer
– Boolean
– Branching
527
1. Arithmetic Instructions
• ADD A, source
A ← A + <operand>.
• ADDC A, source
A ← A + <operand> + CY.
• SUBB A, source
A ← A - <operand> - CY{borrow}.
528
• INC
– Increment the operand by one. Ex: INC DPTR
• DEC
– Decrement the operand by one. Ex: DEC B
• MUL AB
Multiplication Result
8 byte * 8 byte A*B A=low byte,
B=high byte
• DIV AB
Division Quotient Remainder
8 byte /8 byte A/B A B
529
Multiplication of Numbers
MUL AB ; A × B, place 16-bit result in B and A
A=07 , B=02
MUL AB ;07 * 02 = 000E where B = 00 and A = 0E
Division of Numbers
DIV AB ; A / B , 8-bit Quotient result in A &
8-bit Remainder result in B
A=07 , B=02
DIV AB ;07 / 02 = Quotient 03(A) Remainder 01 (B)
530
2. Logical
instructions
531
• ANL D,S
-Performs logical AND of destination & source
- Eg: ANL A,#0FH ANL A,R5
• ORL D,S
-Performs logical OR of destination & source
- Eg: ORL A,#28H ORL A,@R0
•XRL D,S
-Performs logical XOR of destination & source
- Eg: XRL A,#28H XRL A,@R0
532
• CPL A
-Compliment accumulator
-gives 1’s compliment of accumulator data
• RL A
-Rotate data of accumulator towards left without carry
• RLC A
- Rotate data of accumulator towards left with carry
• RR A
-Rotate data of accumulator towards right without carry
• RRC A
- Rotate data of accumulator towards right with carry
533
3. Data Transfer
Instructions
534
MOV Instruction
• MOV destination, source ; copy source to destination.
535
• MOVX
– Data transfer between the accumulator and
a byte from external data memory.
•MOVX A, @DPTR
•MOVX @DPTR, A
536
• PUSH / POP
– Push and Pop a data byte onto the stack.
•PUSH DPL
•POP 40H
537
• XCH
– Exchange accumulator and a byte variable
•XCH A, Rn
•XCH A, direct
•XCH A, @Ri
538
4.Boolean variable
instructions
539
CLR:
• The operation clears the specified bit indicated in
the instruction
• Ex: CLR C clear the carry
SETB:
• The operation sets the specified bit to 1.
CPL:
• The operation complements the specified bit
indicated in the instruction
540
• ANL C,<Source-bit>
• ORL C,<Source-bit>
541
• XORL C,<Source-bit>
•MOV P2.3,C
•MOV C,P3.3
•MOV P2.0,C
542
5. Branching
instructions
543
Jump Instructions
• LJMP (long jump):
– Original 8051 has only 4KB on-chip ROM
544
Call Instructions
• LCALL (long call):
– Target address within 64K-byte range
545
• 2 forms for the return instruction:
– Return from subroutine – RET
– Return from ISR – RETI
546
547
8051
Addressing
Modes
8051 Addressing Modes
• The CPU can access data in various ways, which are
called addressing modes
1. Immediate
2. Register
3. Direct
4. Indirect
5. Relative
6. Absolute
7. Long
8. Indexed
549
1. Immediate Addressing Mode
• The immediate data sign, “#”
• Data is provided as a part of instruction.
550
2. Register Addressing Mode
• In the Register Addressing mode, the instruction involves
transfer of information between registers.
551
3. Direct Addressing Mode
• This mode allows you to specify the operand by giving its
actual memory address
552
4. Indirect Addressing Mode
• A register is used as a pointer to the data.
• Only register R0 and R1 are used for this purpose.
• R2 – R7 cannot be used to hold the address of an
operand located in RAM.
• When R0 and R1 hold the addresses of RAM locations,
they must be preceded by the “@” sign.
MOVX A,@DPTR
553
5. Relative Addressing
• This mode of addressing is used with some type of jump
instructions, like SJMP (short jump) and conditional
jumps like JNZ
554
6. Absolute Addressing
• In Absolute Addressing mode, the absolute
address, to which the control is transferred, is
specified by a label.
• Two instructions associated with this mode
of addressing are ACALL and AJMP
instructions.
• These are 2-byte instructions
555
7. Long Addressing
• This mode of addressing is used with the
LCALL and LJMP instructions.
• It is a 3-byte instruction
• It allows use of the full 64K code space.
556
8. Indexed Addressing
• The Indexed addressing is useful when there is a
need to retrieve data from a look-up table (LUT).
557
8051
Assembly
Language
Programming(ALP)
558
ADDITION OF TWO 8 bit Numbers
ADDRESS LABEL MNEMONICS
9100: CLR C
MOV A,#05
MOV B,#03
SUBB A,B
MOV DPTR,#9200
MOVX @DPTR,A
HERE SJMP HERE
After execution: A=02 560
MULTIPLICATION OF TWO DIVISION OF TWO 8 bit
8 bit Numbers Numbers
Address Label Mnemonics Address Label Mnemonics
MUL AB DIV AB
564
8051
TIMERS
565
8051 Timer Modes
8051 TIMERS
Timer 0 Timer 1
Mode 0 Mode 0
Mode 1 Mode 1
Mode 2 Mode 2
Mode 3
566
TMOD Register
GATE:
When set, timer/counter x is enabled, if INTx pin is high
and TRx is set.
When cleared, timer/counter x is enabled, if TRx bit set.
C/T*:
When set(1), counter operation (input from Tx input pin).
When clear(0), timer operation (input from internal clock).
567
TMOD Register
00- MODE 0
01- MODE 1
10- MODE 2
11- MODE 3
568
TCON Register
OSC ÷12
C /T = 0 TLx THx TFx
(8 Bit) (8 Bit) (1 Bit)
C /T =1
T PIN
INTERRUPT
TR
Gate
INT PIN
570
TIMER 0
OSC ÷12
C /T = 0
TL0 TH0 TF0
C /T =1
T 0 PIN
INTERRUPT
TR0
Gate
INT 0 PIN
571
TIMER 0 – Mode 0
13 Bit Timer / Counter
OSC ÷12
TL0 TH0 INTERRUPT
TF0
C /T = 0
T 0 PIN
C /T =1
(5 Bit) (8 Bit)
TR 0
Gate
INT 0 PIN
OSC ÷12
TL0 TH0 INTERRUPT
TF0
C /T = 0
T 0 PIN
C /T =1
(8 Bit) (8 Bit)
TR 0
Gate
INT 0 PIN
OSC ÷12
TL0 TH0
TF0 INTERRUPT
C /T = 0
T 0 PIN
C /T =1
(8 Bit) (8 Bit)
TR 0
Gate Reload
INT 0 PIN
TH0
(8 Bit)
OSC ÷12
TL0 INTERRUPT
TF0
C /T = 0
T 0 PIN
C /T =1
(8 Bit)
TR 0
Gate
INT 0 PIN
TR1
575
TIMER 1
OSC ÷12
C /T = 0
TL1 TH1 TF1
C /T =1
T 1PIN
INTERRUPT
TR1
Gate
INT 1 PIN
576
TIMER 1 – Mode 0
13 Bit Timer / Counter
OSC ÷12
TL1 TH1 INTERRUPT
TF1
C /T = 0
T 1PIN
C /T =1
(5 Bit) (8 Bit)
TR1
Gate
INT 1 PIN
OSC ÷12
TL1 TH1 INTERRUPT
TF1
C /T = 0
T 1PIN
C /T =1
(8 Bit) (8 Bit)
TR1
Gate
INT 1 PIN
OSC ÷12
TL1 TH1
TF1 INTERRUPT
C /T = 0
T 1PIN
C /T =1
(8 Bit) (8 Bit)
TR1
Gate Reload
INT 1 PIN
TH1
(8 Bit)
(MSB) (LSB)
TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0
Timer 1 Timer0 for Interrupt
TCON Register (2/2)
• TF (timer flag, control flag)
– TF0 for timer/counter 0; TF1 for timer/counter 1.
– TF is like a carry. Originally, TF=0. When TH-TL roll
over to 0000 from FFFFH, the TF is set to 1.
• TF=0 : not reach
• TF=1: reach
• If we enable interrupt, TF=1 will trigger ISR.
(MSB) (LSB)
TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0
Timer 1 Timer0 for Interrupt
Equivalent Instructions for the Timer Control
Register
For timer 0
SETB TR0 = SETB TCON.4
CLR TR0 = CLR TCON.4
• The timer works with the internal system clock. In other words,
the timer counts up each machine cycle.
TF = 0 TF = 0 TF = 0 TF = 0 TF = 1
XTAL
oscillator ÷ 12
C/T = 0
Timer
overflow
flag
TH TL TF
TR
TF goes high when FFFF 0
Timer Delay Calculation for XTAL = 11.0592 MHz
(a) in hex
• (FFFF – YYXX + 1) × 1.085 µs
• where YYXX are TH, TL initial values respectively.
• Notice that values YYXX are in hex.
(b) in decimal
• Convert YYXX values of the TH, TL register to
decimal to get a NNNNN decimal number
• then (65536 – NNNNN) × 1.085 µs
Example 1 (1/3)
• square wave of 50% duty on P1.5
• Timer 0 is used
whole clock
Example 1 (2/3)
;generate delay using timer 0
DELAY:
SETB TR0 ;start the timer 0
AGAIN:JNB TF0,AGAIN
CLR TR0 ;stop timer 0
CLR TF0 ;clear timer 0 flag
RET
Solution:
FFFFH – 7634H + 1 = 89CCH = 35276 clock
count
Half period = 35276 × 1.085 µs = 38.274 ms
Whole period = 2 × 38.274 ms = 76.548 ms
Frequency = 1/ 76.548 ms = 13.064 Hz.
Note
Mode 1 is not auto reload then the program must reload
the TH1, TL1 register every timer overflow if we want to
have a continuous wave.
Find Timer Values
Solution:
1. The period of the square wave = 1 / 50 Hz = 20 ms.
2. The high or low portion of the square wave = 10 ms.
3. 10 ms / 1.085 µs = 9216
4. 65536 – 9216 = 56320 in decimal = DC00H in hex.
5. TL1 = 00H and TH1 = DCH.
Example 3 (2/2)
MODE 1 Programming
{16 bit mode}
MODE 2 Programming
{8 bit mode}
Auto Reload Mode
8051
Serial
Port
611
612
Basics of Serial Communication
• Serial data communication uses two methods
– Synchronous method transfers a block of data at a time
613
614
615
Asynchronous – Start & Stop Bit
• Asynchronous serial data communication is widely used
for character-oriented transmissions
616
Asynchronous – Start & Stop Bit
617
Data Transfer Rate
• The rate of data transfer in serial data communication is
stated in bps (bits per second).
618
8051 Serial Port
• Synchronous and Asynchronous
• SCON Register is used to Control
• Data Transfer through TXd & RXd pins
• Some time - Clock through TXd Pin
• Four Modes of Operation:
619
Registers related to Serial
Communication
1. SBUF Register
2. SCON Register
3. PCON Register
620
SBUF Register
• SBUF is an 8-bit register used solely for serial communication.
• For a byte data to be transferred via the TxD line, it must be
placed in the SBUF register.
• SBUF holds the byte of data when it is received by 8051 RxD
line.
621
SBUF Register
• Sample Program:
622
SCON Register
623
8051 Serial Port – Mode 0
The Serial Port in Mode-0 has the following features:
624
8051 Serial Port – Mode 1
The Serial Port in Mode-1 has the following features:
625
8051 Serial Port – Mode 2
The Serial Port in Mode-2 has the following features:
626
8051 Serial Port – Mode 3
The Serial Port in Mode-3 has the following features:
627
Programs in 8051 serial port
636
Interrupt
– Upon receiving an interrupt signal, the
microcontroller interrupts whatever it is doing
and serves the device.
– The program which is associated with the
interrupt is called the interrupt service routine
(ISR) .
637
Interrupt Vs Polling
1. Interrupts
Whenever any device needs its service, the device notifies the
microcontroller by sending it an interrupt signal.
Upon receiving an interrupt signal, the microcontroller interrupts
whatever it is doing and serves the device.
The program which is associated with the interrupt is called the
interrupt service routine (ISR) or interrupt handler.
2. Polling
The microcontroller continuously monitors the status of a given
device.
When the conditions met, it performs the service.
After that, it moves on to monitor the next device until every one
is serviced.
Steps in Executing an Interrupt
1. It finishes the instruction it is executing and saves the address of
the next instruction (PC) on the stack.
2. It also saves the current status of all the interrupts internally (i.e:
not on the stack).
3. It jumps to a fixed location in memory, called the interrupt
vector table, that holds the address of the ISR.
4. The microcontroller gets the address of the ISR from the
interrupt vector table and jumps to it.
5. It starts to execute the interrupt service subroutine until it
reaches the last instruction of the subroutine which is RETI
(return from interrupt).
6. Upon executing the RETI instruction, the microcontroller returns
to the place where it was interrupted.
639
Steps in executing an interrupt
• Finish current instruction and saves the PC on stack.
642
8051 Interrupt related Registers
• The various registers associated with the use of
interrupts are:
– IE - interrupt Enable
– IP - Interrupts priority
643
Enabling and Disabling an Interrupt
• The register called IE (interrupt enable) that is
responsible for enabling (unmasking) and disabling
(masking) the interrupts.
644
Interrupt Enable (IE) Register
--
• EA : Global enable/disable.
• --- : Reserved for additional interrupt hardware.
646
Interrupt Priority (IP) Register
Serial Port
Timer 1 Pin INT 0 Pin
KEYBOARD
INTERFACING
KEYBOARD INTERFACING
• Keyboards are organized in a matrix of rows
and columns
The CPU accesses both rows and columns
through ports .
•Therefore, with two 8-bit ports, an 8 x 8
matrix of keys can be connected to a
microprocessor
When a key is pressed, a row and a
column make a contact
650
• Otherwise, there is no connection
between rows and columns
•A 4x4 matrix connected to two ports
The rows are connected to an
output port and the columns are
connected to an input port
651
4x4 matrix
652
653
Connection with keyboard matrix
Final Circuit
Stepper Motor
Interfacing
656
Stepper Motor Interfacing
• Stepper motor is used in applications such as;
dot matrix printer, robotics etc
657
658
659
Full step
660
Step angle:
• Step angle is defined as the minimum degree of rotation
with a single step.
• No of steps per revolution = 360° / step angle
• Steps per second = (rpm x steps per revolution) / 60
• Example: step angle = 2°
• No of steps per revolution = 180
661
A switch is connected to pin P2.7. Write an ALP to
monitor the status of the SW.
If SW = 0, motor moves clockwise and
If SW = 1, motor moves anticlockwise
SETB P2.7
MOV A, #66H
MOV P1,A
TURN: JNB P2.7, CW
RL A
ACALL DELAY
MOV P1,A DELAY: MOV R1,#20
SJMP TURN L2: MOV R2,#50
L1:DJNZ R2,L2
CW: RR A
DJNZ R2,L1
ACALL DELAY
RET
MOV P1,A
662 SJMP TURN
LCD Interfacing
using 8051
{before discussed in Unit 3 LCD
interfacing using 8086}
663
664
Pin Connections of LCD:
665
666
A/D Interfacing
using 8051
{before discussed in Unit 3 A/D
interfacing using 8086}
Refer book Mohammad Ali
Explanation is not sufficient
667
Interfacing ADC to 8051
ADC0804 is an 8 bit successive approximation analogue to digital
converter from National semiconductors. The features of ADC0804
are differential analogue voltage inputs, 0-5V input voltage range, no zero
adjustment, built in clock generator, reference voltage can be externally
adjusted to convert smaller analogue voltage span to 8 bit resolution etc.
668
ADC Interfacing:
669
D/A Interfacing
using 8051
{before discussed in Unit 3 D/A
interfacing using 8086}
Refer book Mohammad Ali
Explanation is not sufficient
670
8051 Connection to DAC808
671
program to send data to the DAC to
generate a stair-step ramp
672
SENSOR
INTERFACING
take temperature sensor for example
Shunt voltage
diodes
675
EXTERNAL
MEMORY
INTERFACING
Refer book Mohammad Ali
Explanation is not sufficient
676
Access to External Memory
• Port 0 acts as a multiplexed address/data bus. Sending
the low byte of the program counter (PCL) as an
address.
• Port 2 sends the program counter high byte (PCH)
directly to the external memory.
• The signal ALE operates as in the 8051 to allow an
external latch to store the PCL byte while the multiplexed
bus is made ready to receive the code byte from the
external memory.
• Port 0 then switches function and becomes the data bus
receiving the byte from memory.
677
678
Documents References
• 8086 SYSTEM BUS STRUCTURE by Prof.L.PETER STANLEY
BEBINGTON ( PROFESSOR AND
DEAN(ACADEMIC),VCET,Erode)
• I/O Interfacing by Prof.P.JAYACHANDAR , ASSOCIATE
PROFESSOR and DEAN(SA),VCET,Erode
• 8086 Microprocessor by Dr. M. Gopikrishna ,Assistant Professor of
Physics,Maharajas College ,Ernakulam
• 8086 architecture By Er. Swapnil Kaware
• 8086 presentations by Gursharan Singh Tatla (Eazynotes.com)
• Microprocessor - Ramesh Gaonkar
• 8086 micro processor prasadpawaskar
• 8086 class notes-Y.N.M by MURTHY Y.N
• Introduction to 8086 Microprocessor by Rajvir Singh
• 8086 micro processor by Poojith Chowdhary
• 8086 ASSEMBLY LANGUAGE PROGRAMMING Cutajar & Cutajar
• Intel microprocessor history by Ramzi_Alqrainy
679
Website References
• http://80864beginner.com/
• www.eazynotes.com
• www.slideshare.net
• www.scribd.com
• www.docstoc.com
• www.slideworld.com
• www.nptel.ac.in
• http://opencourses.emu.edu.tr/
• http://engineeringppt.blogspot.in/
• http://www.pptsearchengine.net/
• www.4shared.com
• http://8085projects.info/
680