Issued Date: Aug. 02, 2007 Model No.

: V400H1 - L01

Approval

TFT LCD Approval Specification

MODEL NO.: V400H1

- L01

Customer: Approved by: Note:

Approved By

TVHD LY Chen QRA Dept. Tomy Chen Product Development Div. WT Lin

Reviewed By

Prepared By

LCD TV Marketing and Product Management Div. Denise Shieh Gina Tsou

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- CONTENTS REVISION HISTORY 1. GENERAL DESCRIPTION

1.1 OVERVIEW 1.2 FEATURES 1.3 APPLICATION 1.4 GENERAL SPECIFICATIONS 1.5 MECHANICAL SPECIFICATIONS 2.1 ABSOLUTE RATINGS OF ENVIRONMENT 2.2 PACKAGE STORAGE 2.3 ELECTRICAL ABSOLUTE RATINGS 2.3.1 TFT LCD MODULE 2.3.2 BACKLIGHT UNIT -------------------------------------------------------------------------------------------------------------

3 4

2. ABSOLUTE MAXIMUM RATINGS

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3. ELECTRICAL CHARACTERISTICS

------------------------------------------------------3.1 TFT LCD MODULE 3.2 BACKLIGHT UNIT 3.2.1 CCFL(Cold Cathode Fluorescent Lamp) CHARACTERISTICS 3.2.2 BALANCE BOARD CHARACTERISTICS 4.1 TFT LCD MODULE -------------------------------------------------------------------------------------------------------------

4. BLOCK DIAGRAM

11 12

5. INTERFACE PIN CONNECTION

5.1 TFT LCD MODULE 5.2 BACKLIGHT UNIT 5.3 BALANCE BOARD UNIT 5.4 BLOCK DIAGRAM OF INTERFACE 5.5 LVDS INTERFACE 5.6 COLOR DATA INPUT ASSIGNMENT 6.1 INPUT SIGNAL TIMING SPECIFICATIONS 6.2 POWER ON/OFF SEQUENCE 7.1 TEST CONDITIONS 7.2 OPTICAL SPECIFICATIONS

6. INTERFACE TIMING

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7. OPTICAL CHARACTERISTICS

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8. DEFINITION OF LABELS
8.1 CMO MODULE LABEL

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9. PACKAGING

9.1 PACKING SPECIFICATIONS 9.2 PACKING METHOD

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10. PRECAUTIONS

10.1 ASSEMBLY AND HANDLING PRECAUTIONS 10.2 SAFETY PRECAUTIONS 10.3 SAFETY STANDARDS

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11. MECHANICAL CHARACTERISTICS

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REVISION HISTORY
Version Ver 2.0 Date Aug. 02,07 Page Section Description (New) All All Approval Specification was first issued.

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1. GENERAL DESCRIPTION
1.1 OVERVIEW
V400H1- L01 is a 40 TFT Liquid Crystal Display module with 20-CCFL Backlight unit and 2ch-LVDS interface. This module supports 1920 x 1080 FHD format and can display true 16.7M colors (8-bit colors). The inverter module for backlight is built-in.

1.2 FEATURES
- High brightness (550 nits) - Ultra-high contrast ratio (1800:1) - Faster response time (Gray to gray average 6.5ms) - High color saturation NTSC 72% - Ultra wide viewing angle : 176(H)/176(V) (CR>20) with Super MVA technology - DE (Data Enable) only mode - LVDS (Low Voltage Differential Signaling) interface - Color reproduction (nature color) - Optimized response time for both 50/60 Hz Frame rate - Low color shift function - RoHS compliance

1.3 APPLICATION
- TFT LCD TVs - Multi-Media Display

1.4 GENERAL SPECIFICATI0NS

Item Active Area Bezel Opening Area Driver Element Pixel Number Pixel Pitch (Sub Pixel) Pixel Arrangement Display Colors Display Operation Mode Surface Treatment

Specification 885.6(H) x 498.15 (V) (40 diagonal) 891.7 (H) x 504.2 (V) a-si TFT active matrix 1920 x R.G.B. x 1080 0.1730 (H) x 0.5190 (V) RGB vertical stripe 16.7M Transmissive mode / Normally black Anti-Glare coating (Haze 25%),Hard coating (3H)

Unit mm mm pixel mm color -

Note (1)

1.5 MECHANICAL SPECIFICATIONS

Item Horizontal(H) Vertical(V) Module Size Depth(D) Depth(D) Weight Min. 951 550 45.6 52.2 Typ. 952 551 46.6 53.2 10350 Max. 953 552 47.6 54.2 Unit mm mm mm mm g Note (1) (1) To PCB cover To inverter cover

Note (1) Please refer to the attached drawings for more information of front and back outline dimensions.

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2. ABSOLUTE MAXIMUM RATINGS

2.1 ABSOLUTE RATINGS OF ENVIRONMENT
Item Storage Temperature Operating Ambient Temperature Shock (Non-Operating) Vibration (Non-Operating) (a) 90 %RH Max. (Ta (c) No condensation. Note (2) The maximum operating temperature is based on the test condition that the surface temperature of display area is less than or equal to 60 C with LCD module alone in a temperature controlled chamber. Thermal management should be considered in final product design to prevent the surface temperature of display area from being over 60 C. The range of operating temperature may degrade in case of improper thermal management in final product design. Note (3) 11 ms, half sine wave, 1 time for X, Y, Z. Note (4) 10 ~ 200 Hz, 10 min, 1 time each X, Y, Z. Note (5) At testing Vibration and Shock, the fixture in holding the module has to be hard and rigid enough so that the module would not be twisted or bent by the fixture. 40 C). Symbol TST TOP SNOP VNOP Min. -20 0 Value Max. +60 +50 50 1.0 Unit C C G G Note (1) (1), (2) (3), (5) (4), (5)

Note (1) Temperature and relative humidity range is shown in the figure below. (b) Wet-bulb temperature should be 39 C Max. (Ta > 40 C).

Relative Humidity (%RH)

100 90 80

60

Operating Range

40

20 10 -40 -20 0

Storage Range
20 40 60 80

Temperature (C)

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2.2 PACKAGE STORAGE

When storing modules as spares for a long time, the following precaution is necessary. (a) Do not leave the module in high temperature, and high humidity for a long time. It is highly recommended to store the module with temperature from 0 to 35 at normal humidity without condensation. (b) The module shall be stored in dark place. Do not store the TFT-LCD module in direct sunlight or fluorescent light.

2.3 ELECTRICAL ABSOLUTE RATINGS 2.3.1 TFT LCD MODULE

Item Power Supply Voltage Input Signal Voltage Symbol Vcc VIN Min. -0.3 -0.3 Value Max. 13.5 3.6 Unit V V Note (1)

2.3.2 BACKLIGHT UNIT

Item Lamp Voltage Symbol VW Value Min. Max. 3000 Unit VRMS Note

Note (1) No moisture condensation or freezing.

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3. ELECTRICAL CHARACTERISTICS
3.1 TFT LCD MODULE
Parameter Power Supply Voltage Power Supply Ripple Voltage Rush Current White Power Supply Current Black Vertical Stripe Differential Input High Threshold Voltage LVDS Differential Input Low Interface Threshold Voltage Common Input Voltage Terminating Resistor CMOS Input High Threshold Voltage interface Input Low Threshold Voltage Note (2) Measurement Conditions:
+12.0V Q1 2SK1475 Vcc FUSE R1 47K C3 1uF (LCD Module Input)

Ta = 25 2 C Symbol VCC VRP IRUSH ICC VLVTH VLVTL VLVC RT VIH VIL Min. 10.8 -100 1.125 2.7 0 Value Typ. 12.0 1.2 0.6 1.0 1.25 100 Max. 13.2 350 4.5 1.5 0.7 1.2 +100 1.375 3.3 0.7 Unit V mV A A A A mV mV V ohm V V Note (1) (2) (3)

Note (1) The module should be always operated within above ranges.

(High to Low) (Control Signal) R2 SW 1K +15V 47K

Q2 2SK1470

VR1 C1

C2

0.01uF

1uF

Vcc rising time is 470us

+12V
0.9Vcc 0.1Vcc

GND 470us

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Note (3) The specified power supply current is under the conditions at Vcc = 12 V, Ta = 25 2 C, f v = 60 Hz, whereas a power dissipation check pattern below is displayed. a. White Pattern b. Black Pattern

Active Area

Active Area

c. Vertical Stripe Pattern

R G B R G B B R G B R G B R B R G B R G B R R G B R G B
Active Area

3.2 BACKLIGHT UNIT 3.2.1 CCFL (Cold Cathode Fluorescent Lamp) CHARACTERISTICS (Ta = 25 2 C)
Parameter Lamp Voltage Lamp Current Lamp Starting Voltage Operating Frequency Lamp Life Time Symbol VW IL VS FO LBL Min. 7.7 40 50,000 Value Typ. 1400 8.0 Max. 8.3 2290 2060 70 Unit VRMS mARMS VRMS VRMS KHz Hrs Note Ih = 8.0mA (1) (2), Ta = 0 C (2), Ta = 25 C (3) (4)

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3.2.2 BALANCE BOARD CHARACTERISTICS (Ta = 25 2 C)

Parameter
Input High Voltage

Symbol
V(HV1/HV2

Min. 41 7.7 5 150 -

Input Current Oscillating Frequency

Individual Lamp Current

IBL(HV) FW
IL

Value Typ. 1400 175 44 8.0

Max. 47 8.3 1.5 170 -

Unit V mArms kHz mA V V Hz %

Note (2) No Dimming H.V Normal Operation Lamp Connector Open

Lamp Detection

High (LD)

LD LD FB DMIN

Low (LD) Dimming frequency Minimum Duty Ratio

160 15

Note (1) Lamp current is measured by utilizing high frequency current meters as shown below: Note (2) Input High Voltage Hv based on spec. +-7% tolerance. Note (3) Asymmetric ratio must be from 90% to 110% (0.9<Ip/ Irms@T/2X
2

<1.1)

T Ip

I-p

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A A A A A A A A Balance Board A A A A A A A A A A A A

1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2

H V (Blue +) H V (W hite -) H V (Blue +) H V (W hite -) H V (Blue +) H V (W hite -) H V (Blue +) H V (W hite -) H V (Blue +) H V (W hite -) H V (Blue +) H V (W hite -) H V (Blue +) H V (W hite -) H V (Blue +) H V(W hite -)

LC D M odule

H V (Blue +) 1 H V (W hite -) 2 H V (Blue +) 1 H V (W hite -) 2

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4. BLOCK DIAGRAM
4.1 TFT LCD MODULE
ERX0(+/-) ERX1(+/-) ERX2(+/-) ERX3(+/-) ECLK(+/-)

FRAME BUFFER

SCAN DRIVER IC

INPUT CONNECTOR

SELLVDS REF ODSEL

TFT LCD PANEL (1920x3x1080)

(FI-RE51S-HF )

TIMING CONTROLLER
DC/DC CONVERTER & REFERENCE VOLTAGE
CN1

ORX0(+/-) ORX1(+/-) ORX2(+/-) ORX3(+/-) OCLK(+/-)

DATA DRIVER IC

Vcc GND CN103: KN30-5P-1.25H (Hirose)

BACKLIGHT IP Board BALANCE BOARD UNIT

CN201 - CN210 : SM02-BDAS-3-TB(JST) +/- HV CN101: SM02-BDAS-3-TB (JST)

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5. INTERFACE PIN CONNECTION

5.1 TFT LCD MODULE
CNF1 Connector Pin Assignment Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 Name VCC VCC VCC VCC VCC GND GND GND GND ORX0ORX0+ ORX1ORX1+ ORX2ORX2+ GND OCLKOCLK+ GND ORX3ORX3+ N.C. N.C. GND ERX0ERX0+ ERX1ERX1+ ERX2ERX2+ GND ECLKECLK+ +12V power supply +12V power supply +12V power supply +12V power supply +12V power supply Ground Ground Ground Ground Odd pixel, Negative LVDS differential data input. Channel 0 Odd pixel, Positive LVDS differential data input. Channel 0 Odd pixel, Negative LVDS differential data input. Channel 1 Odd pixel, Positive LVDS differential data input. Channel 1 Odd pixel, Negative LVDS differential data input. Channel 2 Odd pixel, Positive LVDS differential data input. Channel 2 Ground Odd pixel, Negative LVDS differential clock input Odd pixel, Positive LVDS differential clock input. Ground Odd pixel, Negative LVDS differential data input. Channel 3 Odd pixel, Positive LVDS differential data input. Channel 3 No Connection No Connection Ground Even pixel Negative LVDS differential data input. Channel 0 Even pixel Positive LVDS differential data input. Channel 0 Even pixel Negative LVDS differential data input. Channel 1 Even pixel Positive LVDS differential data input. Channel 1 Even pixel Negative LVDS differential data input. Channel 2 Even pixel Positive LVDS differential data input. Channel 2 Ground Even pixel Negative LVDS differential clock input. Even pixel Positive LVDS differential clock input. 12 (1) Description Note

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34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51

GND ERX3ERX3+ N.C. N.C. GND ODSEL N.C. N.C. N.C. N.C. SELLVDS N.C. N.C. N.C. N.C. N.C. N.C.

Ground Even pixel Negative LVDS differential data input. Channel 3 Even pixel Positive LVDS differential data input. Channel 3 No Connection No Connection Ground Overdrive Lookup Table Selection No Connection No Connection No Connection No Connection LVDS Data Format Selection No Connection No Connection No Connection No Connection No Connection No Connection (1) (1) (3) (1) (1) (1) (1) (2) (1)

Note (1) Reserved for internal use. Please leave it open. Note (2) Low : JEIDA LVDS Format (default), High : VESA Format. Note (3) Overdrive lookup table selection. The overdrive lookup table should be selected in accordance to the frame rate to optimize image quality. ODSEL L H Note Lookup table was optimized for 60 Hz frame rate. Lookup table was optimized for 50 Hz frame rate.

Note (4) Low =Open or Connect to GND, High = Connect to +3.3V

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5.2 BACKLIGHT UNIT

The pin configuration for the housing and leader wire is shown in the table below.

Pin No.
1 2

CN201-CN210 (Housing): BDAMR-02VAS-3 (JST) Symbol Description

HV HV High Voltage High Voltage

Wire Color Blue White

Note (1) The backlight interface housing for high voltage side is a model BDAMR-02VAS-3 (JST), manufactured by JST. The mating header on inverter part number is SM02-BDAS-3-TB (JST).

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5.3 BALANCE BOARD UNIT

CN101 (Header): SM02-BADAS-3-TB (JST) Pin No. Symbol 1 CCFL high voltage HV2 CCFL high voltage HV+ CN201-CN210 (Header): SM02-BADAS-3-TB(JST) Pin No. Symbol 1 CCFL high voltage HV+ 2 CCFL high voltage HVDescription

Description

CN103 (Header): KN30-5P-1.25H (Hirose). Pin No. Symbol Description Power Supply for Protection Circuit 1 VCC Lamp Current Detected Voltage 2 FBK Signal Ground 3 GND No Connect 4 NC CCFL Connector Open & Non-lighting signal 5 LD

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5.4 BLOCK DIAGRAM OF INTERFACE

CNF1

ERx0+ ER0-ER7 EG0-EG7 EB0-EB7 DE OR0-OR7 OG0-OG7 OB0-OB7 DCLK Host Graphics Controller ORx0+ ORx0ORx1+ ORx1ORx2+ ORx2ORx3+ ORx3OCLK+ PLL OCLKPLL TxIN ERx0ERx1+ ERx1-

51
100pF

RxOUT

51 51
100pF

ER0-ER7 EG0-EG7 EB0-EB7

100pF

51

ERx2+ ERx2ERx3+ ERx3ECLK+ ECLK-

51 51 51
100pF

DE OR0-OR7 OG0-OG7 OB0-OB7

51 51
100pF

51

PLL

DCLK

Timing
51
100pF

Controller

51 51
100pF

51
100pF

51 51
100pF

51 51
100pF

51

PLL

LVDS Transmitter THC63LVDM83A (LVDF83A)

LVDS Receiver

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ER0~ER7 : Even pixel R data EG0~EG7 : Even pixel G data EB0~EB7 : Even pixel B data OR0~OR7 : Odd pixel R data OG0~OG7: Odd pixel G data OB0~OB7 : Odd pixel B data DE DCLK : Data enable signal : Data clock signal

Note (1) The system must have the transmitter to drive the module. Note (2) LVDS cable impedance shall be 50 ohms per signal line or about 100 ohms per twist-pair line when it is used differentially. Note (3) Two pixel data send into the module for every clock cycle. The first pixel of the frame is even pixel and the second pixel is odd pixel.

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5.5 LVDS INTERFACE

SIGNAL

TRANSMITTER THC63LVDM83A

INTERFACE CONNECTOR

RECEIVER THC63LVDF84A

TFT CONTROL INPUT

SELLVDS=H

SELLVDS= L or OPEN

PIN 51 52 54 55 56 3 4 6 7 11 12 14 15 19 20 22 23 24 30 50 2 8 10 16 18 25 27 28 31

INPUT TxIN0 TxIN1 TxIN2 TxIN3 TxIN4 TxIN6 TxIN7 TxIN8 TxIN9 TxIN12 TxIN13 TxIN14 TxIN15 TxIN18 TxIN19 TxIN20 TxIN21 TxIN22 TxIN26 TxIN27 TxIN5 TxIN10 TxIN11 TxIN16 TxIN17 TxIN23 TxIN24 TxIN25 TxCLK IN

Host

TFT-LCD PIN 27 29

OUTPUT Rx OUT0 Rx OUT1 Rx OUT2 Rx OUT3 Rx OUT4 Rx OUT6 Rx OUT7 Rx OUT8 Rx OUT9 Rx OUT12 Rx OUT13 Rx OUT14 Rx OUT15 Rx OUT18 Rx OUT19 Rx OUT20 Rx OUT21 Rx OUT22 Rx OUT26 Rx OUT27 Rx OUT5 Rx OUT10 Rx OUT11 Rx OUT16 Rx OUT17 Rx OUT23 Rx OUT24 Rx OUT25 RxCLK OUT

SELLVDS=H

SELLVDS= L or OPEN

R0 R1 R2 R3 R4 R5 G0 G1 G2 G3 G4 G5 B0 B1 B2 24 bit B3 B4 B5 DE R6 R7 G6 G7 B6 B7 RSVD 1 RSVD 2 RSVD 3

R2 R3 R4 R5 R6 R7 G2 G3 G4 G5 G6 G7 B2 B3 B4 B5 B6 B7 DE R0 R1 G0 G1 B0 B1 RSVD 1 RSVD 2 RSVD 3

R0 R1 R2 R3 R4 R5 G0 G1 G2 G3 G4 G5 B0 B1 B2 B3 B4 B5 DE R6 R7 G6 G7 B6 B7 NC NC NC DCLK

R2 R3 R4 R5 R6 R7 G2 G3 G4 G5 G6 G7 B2 B3 B4 B5 B6 B7 DE R0 R1 G0 G1 B0 B1 NC NC NC

TA OUT0+

Rx 0+

30 32 33

TA OUT0-

Rx 0-

35 37 38 39

TA OUT1+

Rx 1+

43 45 46

TA OUT1-

Rx 1-

47 51 53 54

TA OUT2+

Rx 2+

55 1 6

TA OUT2-

Rx 2-

7 34 41 42

TA OUT3+

Rx 3+

49 50 2

TA OUT3TxCLK OUT+ TxCLK OUT-

Rx 3RxCLK IN+ RxCLK IN-

3 5 26

DCLK

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R0~R7: Pixel R Data (7; MSB, 0; LSB) G0~G7: Pixel G Data (7; MSB, 0; LSB) B0~B7: Pixel B Data (7; MSB, 0; LSB) DE: Data enable signal Note (1) RSVD (reserved) pins on the transmitter shall be H or (L or OPEN)

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5.6 COLOR DATA INPUT ASSIGNMENT

The brightness of each primary color (red, green and blue) is based on the 8-bit gray scale data input for the color. The higher the binary input, the brighter the color. The table below provides the assignment of color versus data input. Data Signal Color Black Red Green Basic Blue Colors Cyan Magenta Yellow White Red(0) / Dark Red(1) Gray Scale Of Red Red(2) : : Red(253) Red(254) Red(255) Green(1) Gray Scale Of Green Green(2) : : Green(253) Green(254) Green(255) Blue(0) / Dark Blue(1) Gray Scale Of Blue Blue(2) : : Blue(253) Blue(254) Blue(255) 0 1 0 0 0 1 1 1 0 0 0 : : 1 1 1 0 0 : : 0 0 0 0 0 0 : : 0 0 0 0 1 0 0 0 1 1 1 0 0 0 : : 1 1 1 0 0 0 : : 0 0 0 0 0 0 : : 0 0 0 0 1 0 0 0 1 1 1 0 0 0 : : 1 1 1 0 0 0 : : 0 0 0 0 0 0 : : 0 0 0 Red 0 1 0 0 0 1 1 1 0 0 0 : : 1 1 1 0 0 0 : : 0 0 0 0 0 0 : : 0 0 0 0 1 0 0 0 1 1 1 0 0 0 : : 1 1 1 0 0 0 : : 0 0 0 0 0 0 : : 0 0 0 0 1 0 0 0 1 1 1 0 0 0 : : 1 1 1 0 0 0 : : 0 0 0 0 0 0 : : 0 0 0 0 1 0 0 0 1 1 1 0 0 1 : : 0 1 1 0 0 0 : : 0 0 0 0 0 0 : : 0 0 0 Green 0 0 0 0 0 1 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 1 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 : : : : : : : : : : 0 0 1 0 1 0 1 1 0 0 0 : : 0 0 0 0 0 0 : : 1 1 1 0 0 0 : : 0 0 0 0 0 1 0 1 0 1 1 0 0 0 : : 0 0 0 0 0 0 : : 1 1 1 0 0 0 : : 0 0 0 0 0 1 0 1 0 1 1 0 0 0 : : 0 0 0 0 0 1 : : 0 1 1 0 0 0 : : 0 0 0 0 0 1 0 1 0 1 1 0 0 0 : : 0 0 0 0 1 0 : : 1 0 1 0 0 0 : : 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 0 0 1 1 0 0 0 0 0 0 : : : : 0 0 0 1 1 1 0 1 0 0 0 : : 0 0 0 0 0 0 : : 0 0 0 0 0 0 : : 1 1 1 Blue 0 0 0 1 1 1 0 1 0 0 0 : : 0 0 0 0 0 0 : : 0 0 0 0 0 0 : : 1 1 1 0 0 0 1 1 1 0 1 0 0 0 : : 0 0 0 0 0 0 : : 0 0 0 0 0 0 : : 1 1 1 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 : : : : : :
R7 R6 R5 R4 R3 R2 R1 R0 G7 G6 G5 G4 G3 G2 G1 G0 B7 B6 B5 B4 B3 B2 B1 B0

1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 : : : : : : : : : :

0 0 0 0 0 0 0 0 0 0 0 0 : : : :

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 : : : : : :

Green(0) / Dark 0

0 1 1 1 1 0 1 1 1 1 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 : : : : : : : : : :

0 0 0 0 0 0 0 0 0 0 0 0 : : : :

0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 : : : : : :

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

1 1 1 1 1 1

1 0 1 1 1 0 1 1 1

Note (1) 0: Low Level Voltage, 1: High Level Voltage

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6. INTERFACE TIMING
6.1 INPUT SIGNAL TIMING SPECIFICATIONS
The input signal timing specifications are shown as the following table and timing diagram. Signal LVDS Receiver Clock Item Symbol Frequency 1/Tc Input cycle to Trcl cycle jitter Setup Time Hold Time Frame Rate Vertical Active Display Term Total Display Blank Total Display Blank Tlvsu Tlvhd Fr5 Fr6 Tv Tvd Tvb Th Thd Thb Min. 60 600 600 47 57 1115 1080 35 1050 960 90 Typ. 74 50 60 1125 1080 45 1100 960 140 Max. 80 200 53 63 1135 1080 55 1150 960 190 Unit MHZ ps ps ps Hz Hz Th Th Th Tc Tc Tc (1) (2) Tv=Tvd+Tvb Th=Thd+Thb Note

LVDS Receiver Data

Horizontal Active Display Term

Note (1) (ODSEL) = (H). Please refer to 5.1 for detail information. (2) (ODSEL) = (L). Please refer to 5.1 for detail information.

INPUT SIGNAL TIMING DIAGRAM

Tv Tvd Tvb

DE Th

DCLK Tc DE Thb Thd

DATA

Valid display data (960 clocks)

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LVDS RECEIVER INTERFACE TIMING DIAGRAM

Tc

RXCLK+/-

RXn+/Tlvsu Tlvhd

1T 14

3T 14

5T 14

7T 14

9T 14

11 T 14

13T 14

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6.2 POWER ON/OFF SEQUENCE

To prevent a latch-up or DC operation of LCD module, the power on/off sequence should be as the diagram below.

Power Supply VCC

0V 0.5 0 0 T1 T2 T3 10ms 50ms 50ms T4

0.9 VCC 0.1VCC

0.9 VCC 0.1Vcc

T1

T3

500ms

T2

T4

Signals
0V

VALID
Power On Power Off

Backlight (Recommended) 500ms T5 100ms T6

T5

50%

50%

T6

Power ON/OFF Sequence

Note (1) The supply voltage of the external system for the module input should follow the definition of Vcc. Note (2) Apply the lamp voltage within the LCD operation range. When the backlight turns on before the LCD operation or the LCD turns off before the backlight turns off, the display may momentarily become abnormal screen. Note (3) In case of Vcc is in off level, please keep the level of input signals on the low or high impedance. Note (4) T4 should be measured after the module has been fully discharged between power off and on period. Note (5) Interface signal shall not be kept at high impedance when the power is on.

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7. OPTICAL CHARACTERISTICS
7.1 TEST CONDITIONS
Item Ambient Temperature Ambient Humidity Supply Voltage Input Signal Lamp Current(HV) Oscillating Frequency (Inverter) Frame rate Symbol Value Unit o Ta C 252 Ha %RH 5010 VCC 12 V According to typical value in "3. ELECTRICAL CHARACTERISTICS" IL mA 8.0 0.5 FW KHz 443 60 Hz

7.2 OPTICAL SPECIFICATIONS

The relative measurement methods of optical characteristics are shown in 7.2. The following items should be measured under the test conditions described in 7.1 and stable environment shown in Note (6). Item Contrast Ratio Response Time Center Luminance of White White Variation Cross Talk Red Green Color Chromaticity Blue White Color Gamut Viewing Angle Horizontal Vertical Symbol CR Gray to gray average LC W CT Rx Ry Gx Gy Bx By Wx Wy CG x+ xY+ YCondition Min. 1200 450 Typ. 1800 6.5 550 0.650 0.330 0.264 0.612 0.148 0.063 0.280 0.290 72 88 88 88 88 Max. 12 1.3 4.0 Unit ms cd/ 2 % % Deg . Note (2) (3) (4) (7) (5)

x=0, Y =0 Viewing angle at Normal direction

Typ. 0.03

Typ. + 0.03

(6)

CR20

70 80 80 80 80

NTSC (1)

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Note (1) Definition of Viewing Angle (x, y): Viewing angles are measured by EZ-Contrast 160R (Eldim) Normal x = y = 0 yX- = 90 xy+ y+ x+ 12 oclock direction y+ = 90

6 oclock y- = 90

y-

x+

X+ = 90

Note (2) Definition of Contrast Ratio (CR): The contrast ratio can be calculated by the following expression. Contrast Ratio (CR) = L255 / L0 L255: Luminance of gray level 255 L 0: Luminance of gray level 0 CR = CR (5), where CR (X) is corresponding to the Contrast Ratio of the point X at the figure in Note (7). Note (3) Definition of Gray to Gray Switching Time :

100% 90%

Optical Response
10% 0%

Gray to gray switching time

Gray to gray switching time

Time

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The driving signal means the signal of gray level 0, 63, 127, 191, 255. Gray to gray average time means the average switching time of gray level 0 ,63,127,191,255 to each other . Note (4) Definition of Luminance of White (LC, LAVE): Measure the luminance of gray level 255 at center point and 5 points LC = L (5) LAVE = [L (1)+ L (2)+ L (3)+ L (4)+ L (5)] / 5 where L (x) is corresponding to the luminance of the point X at the figure in Note (7). Note (5) Definition of Cross Talk (CT): CT = | YB YA | / YA 100 (%) Where: YA = Luminance of measured location without gray level 0 pattern (cd/m2) YB = Luminance of measured location with gray level 0 pattern (cd/m2)
(0, 0)

Active Area
YA, U (D/2,W/8)

(0, 0) (D/4,W/4)

Active Area
YB, U (D/2,W/8)

YA, L (D/8,W/2)

Gray 128

YB, L (D/8,W/2) YA, R (7D/8,W/2) YB, D (D/2,7W/8) (D,W)

Gray 0 0 Gray
Gray 128

YB, R (7D/8,W/2) (3D/4,3W/4)

YA, D (D/2,7W/8)

(D,W)

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Note (6) Measurement Setup: The LCD module should be stabilized at given temperature for 1 hour to avoid abrupt temperature change during measuring. In order to stabilize the luminance, the measurement should be executed after lighting Backlight for 1 hour in a windless room.

LCD Module LCD Panel Center of the Screen Display Color Analyzer (Minolta CA210)

Light Shield Room (Ambient Luminance < 2 lux)

Note (7) Definition of White Variation (W): Measure the luminance of gray level 255 at 5 points W = Maximum [L (1), L (2), L (3), L (4), L (5)] / Minimum [L (1), L (2), L (3), L (4), L (5)]

Horizontal Line D
D/4 D/2 3D/4

Vertical Line

W/4

2 X

W/2

: Test Point X=1 to 5

3W/4

Active Area

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8. DEFINITION OF LABELS
8.1 CMO MODULE LABEL
The barcode nameplate is pasted on each module as illustration, and its definitions are as following explanation.

OPTOELECTRONICS

CHI

MEI

E207943
V400H1 -L01 Rev. XX
MADE IN TAIWAN

XXXXXXXYMDLNNNN

(a) Model Name: V400H1-L01 (b) Revision: Rev. XX, for example: A0, A1 B1, B2 or C1, C2etc. (c) Serial ID: X X X X X X X Y M D L N N N N Serial No. Product Line Year, Month, Date CMO Internal Use CMO Internal Use Revision CMO Internal Use Serial ID includes the information as below: (a) Manufactured Date: Year: 0~9, for 2000~2009 Month: 1~9, A~C, for Jan. ~ Dec. Day: 1~9, A~Y, for 1st to 31st, exclude I ,O, and U. (b) Revision Code: Cover all the change (c) Serial No.: Manufacturing sequence of product (d) Product Line: 1 -> Line1, 2 -> Line 2, etc.

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9. PACKAGING
9.1 PACKING SPECIFICATIONS
(1) 3 LCD TV modules / 1 Box (2) Box dimensions 1070(L) X 283 (W) X 640(H) (3) Weight approximately 36.5Kg ( 3 modules per box)

9.2 PACKING METHOD

Figures 9-1 and 9-2 are the packing method

LCD TV Module

Anti-static Bag

Figure.9-1 packing method

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Sea / Land Transportation

(L800*50mm*50mm)

(L1650*50mm*50mm)

(Pallet:L1150*W1080*H140mm)

Air Transportation

(L800*50mm*50mm)

(L1000*50mm*50mm)

(Pallet:L1150*W1080*H140mm)

Figure. 9-2 Packing method

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10. PRECAUTIONS
10.1 ASSEMBLY AND HANDLING PRECAUTIONS
(1) Do not apply rough force such as bending or twisting to the module during assembly. (2) It is recommended to assemble or to install a module into the users system in clean working areas. The dust and oil may cause electrical short or worsen the polarizer. (3) Do not apply pressure or impulse to the module to prevent the damage of LCD panel and backlight. (4) Always follow the correct power-on sequence when the LCD module is turned on. This can prevent the damage and latch-up of the CMOS LSI chips. (5) Do not plug in or pull out the I/F connector while the module is in operation. (6) Do not disassemble the module. (7) Use a soft dry cloth without chemicals for cleaning, because the surface of polarizer is very soft and easily scratched. (8) Moisture can easily penetrate into LCD module and may cause the damage during operation. (9) High temperature or humidity may deteriorate the performance of LCD module. Please store LCD modules in the specified storage conditions. (10) When ambient temperature is lower than 10C, the display quality might be reduced. For example, the response time will become slow, and the starting voltage of CCFL will be higher than that of room temperature.

10.2 SAFETY PRECAUTIONS

(1) The startup voltage of a backlight is over 1000 Volts. It may cause an electrical shock while assembling with the inverter. Do not disassemble the module or insert anything into the backlight unit. (2) If the liquid crystal material leaks from the panel, it should be kept away from the eyes or mouth. In case of contact with hands, skin or clothes, it has to be washed away thoroughly with soap. (3) After the modules end of life, it is not harmful in case of normal operation and storage.

10.3 SAFETY STANDARDS

The LCD module should be certified with safety regulations as follows: Regulatory Information Technology equipment Item UL cUL CB UL Audio/Video Apparatus cUL CB UL 60950-1: 2003 CAN/CSA C22.2 No.60950-1-03 IEC 60950-1:2001 UL 60065: 2003 CAN/CSA C22.2 No.60065-03 IEC 60065:2001 Standard

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11. MECHANICAL CHARACTERISTICS

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HIG H VOLTAGE C AU TIO N

RISK OF ELECTR C SHOCK. I D ISCON N ECT THE ELE CTRIC P OW E B EFORE SE ICI N G . R RV

33
C OLD CATH O DE FLUORESCE NT LAMP IN LCD PANEL CONTAINS A SMALL AMOUN T O F MERCURY PLEASE FOLLOW LOCAL ORDINANCES OR REGULATIONS FOR DISPOSAL.

CHI MEI

Approval

Issued Date: Aug. 02, 2007 Model No.: V400H1 - L01

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