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    Lec - 2

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    Mahidur Rahman
    VLSI Class Lectures

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    Lec - 2

    Uploaded by

    Mahidur Rahman
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    VLSI Class Lectures

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    Lec _2

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    VLSI Class Lectures

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    2 views5 pages

    Lec - 2

    Uploaded by

    Mahidur Rahman
    VLSI Class Lectures

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    of 5

    ECE-405

    Gate behavior of CMOS design Technology


    CMOS technology provides two types of transistors : an n-type transistor (nMOS) and a p-type
    transistor (pMOS). Transistor operation is controlled by electric fields so the devices are also
    called Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) or simply FETs.
    An nMOS transistor is built with a p-type body with two regions of n-type semiconductor
    adjacent to the gate called the source and the drain. For all practical purposes they are physically
    equivalent and can be used interchangeably. A pMOS transistor is built with an n-type body
    with two regions of p-type semiconductors adjacent to the gate.
    nMOS gate beviour:
    In the nMOS transistor, since the body is grounded, the p-n junctions of the source and drain to
    body are reverse-biased. If the voltage at the gate is raised, an electric field starts to build up -
    attracting free electrons to the underside of the Si-SiO2 interface. When the voltage is high
    enough, the electrons end up filling all the holes and a thin region under the gate called the
    channel gets inverted to act as an n-type semiconductor - creating a conducting path from the
    source to the drain, allowing current to flow. When the transistor is at that state, we say the
    transistor is ON. If the gate is grounded, little to no current flows through the reverse-biased
    junction. When that happens, we say the transistor is OFF.

    Fig: nMOS tranistor Fig2: pMOS transistor

    pMOS gate beviour:


    In the pMOS transistor, the behavior and setup is the complement of the nMOS transistor. The
    body is held at positive voltage. When the gate is also positive - the source and drain are reverse
    biased. When that happens, no current flows and we say the transistor is OFF.

    When the voltage at the gate is lowered, positive charges are attracted to the underside of the
    SiSiO2 interface. When the voltage gets sufficiently low the channel gets inverted - creating a
    conducting path from the source to the drain, allowing current to flow. Because the behavior of a
    pMOS transistor is the opposite of that of an nMOS transistor, the symbol for pMOS transistor is
    identical to that of nMOS with an additional bubble on the gate. That bubble is known as an
    inversion bubble.

    Fig: Transistor symbol and switch level models

    Compare between CMOS and BiCMOS VLSI circuit design technology

    CMOS Bipolar
    Low static power dissipation High static power dissipation
    High input impedance Low input impedance
    High packing density Low packing density
    High delay density to load Low delay density to load
    Low output drive current High output drive current
    High noise margin Low voltage swing logic

    CMOS: for logic


    BiCMOS: for I/O and driver circuits
    ECL: for critical high speed parts of the system
    Design a/an inverter/NAND/NOR gate using p-MOS and n-MOS device only and
    describe its principle of operation.
    Inverter:

    Fig:Inverter schematic and symbol Y= Ā

    Fig shows the schematic and symbol for a CMOS inverter or NOT gate using one
    nMOS transistor and one pMOS transistor. The bar at the top indicates VDD and
    the triangle at the bottom indicates GND. When the input A is 0, the nMOS
    transistor is OFF and the pMOS transistor is ON. Thus, the output Y is pulled up to
    1 because it is connected to VDD but not to GND. Conversely, when A is 1, the
    nMOS is ON, the pMOS is OFF, and Y is pulled down to ‘0.’ This is summarized
    in Table 1.1.
    NAND:

    A B Y
    0 0 1
    0 1 1
    1 0 1
    1 1 0

    Fig: 2 input NAND gate schematic, symbol and truth table

    Fig shows a 2-input CMOS NAND gate. It consists of two series nMOS transistors
    between Y and GND and two parallel pMOS transistors between Y and VDD. If
    either input A or B is 0, at least one of the nMOS transistors will be OFF, breaking
    the path from Y to GND. But at least one of the pMOS transistors will be ON,
    creating a path from Y to VDD. Hence, the output Y will be 1. If both inputs are 1,
    both of the nMOS transistors will be ON and both of the pMOS transistors will be
    OFF. Hence, the output will be 0. The truth table is given in Table.
    NOR :

    A 2-input NOR gate is shown in Figure 1.16. The nMOS transistors are in parallel
    to pull the output low when either input is high. The pMOS transistors are in series
    to pull the output high when both inputs are low, as indicated in Table 1.4. The
    output is never crowbarred or left floating.
    Sketch a 3-input CMOS NOR gate????

    SOLUTION: Figure 1.17 shows such a gate. If any input is high, the output is
    pulled low through the parallel nMOS transistors. If all inputs are low, the output is
    pulled high through the series pMOS transistors.

    Related question:

     Construct and verify a universal gate using CMOS circuit.


     Derrive and explain the CMOS compound gate for function

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