OPA604

OPA
604

OPA
604

SBOS019A – JANUARY 1992 – SEPTEMBER 2003

FET-Input, Low Distortion

OPERATIONAL AMPLIFIER

FEATURES APPLICATIONS
● LOW DISTORTION: 0.0003% at 1kHz ● PROFESSIONAL AUDIO EQUIPMENT
● LOW NOISE: 10nV/√Hz ● PCM DAC I/V CONVERTERS
● HIGH SLEW RATE: 25V/µs ● SPECTRAL ANALYSIS EQUIPMENT
● WIDE GAIN-BANDWIDTH: 20MHz ● ACTIVE FILTERS
● UNITY-GAIN STABLE ● TRANSDUCER AMPLIFIERS
● WIDE SUPPLY RANGE: VS = ±4.5 to ±24V ● DATA ACQUISITION
● DRIVES 600Ω LOAD
● DUAL VERSION AVAILABLE (OPA2604)
(7)
DESCRIPTION V+

The OPA604 is a FET-input operational amplifier designed

for enhanced AC performance. Very low distortion, low noise
and wide bandwidth provide superior performance in high
quality audio and other applications requiring excellent dy- (+)
namic performance. (3)
New circuit techniques and special laser trimming of dynamic (–)
Distortion
(2) Output (6)
circuit performance yield very low harmonic distortion. The Rejection
Stage(1) VO
Circuitry(1)
result is an op amp with exceptional sound quality. The low-
noise FET input of the OPA604 provides wide dynamic
range, even with high source impedance. Offset voltage is
laser-trimmed to minimize the need for interstage coupling (5)
capacitors.
The OPA604 is available in 8-pin plastic mini-DIP and SO-8 (1)
surface-mount packages, specified for the –25°C to +85°C
temperature range.
(4)
V–
NOTE: (1) Patents Granted: #5053718, 5019789

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date. Copyright © 1992-2003, Texas Instruments Incorporated
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

www.ti.com
ABSOLUTE MAXIMUM RATINGS ELECTROSTATIC
Power Supply Voltage ....................................................................... ±25V
Input Voltage ............................................................... (V–)–1V to (V+)+1V DISCHARGE SENSITIVITY
Output Short Circuit to Ground ................................................ Continuous
Operating Temperature .................................................. –40°C to +100°C Any integrated circuit can be damaged by ESD. Texas Instru-
Storage Temperature ...................................................... –40°C to +125°C ments recommends that all integrated circuits be handled with
Junction Temperature .................................................................... +150°C
appropriate precautions. Failure to observe proper handling
Lead Temperature (soldering, 10s) AP .......................................... +300°C
Lead Temperature (soldering, 3s) AU ............................................ +260°C and installation procedures can cause damage.
ESD damage can range from subtle performance degradation
PIN CONFIGURATION to complete device failure. Precision integrated circuits may be
more susceptible to damage because very small parametric
Top View DIP, SOIC changes could cause the device not to meet published speci-
fications.

Offset Trim 1 8 No Internal Connection

PACKAGE/ORDERING INFORMATION
–In 2 7 +VS For the most current package and ordering information, see
to the Package Option Addendum at the end of this data
+In 3 6 Output sheet.

–VS 4 5 Offset Trim

2
OPA604
www.ti.com SBOS019A
ELECTRICAL CHARACTERISTICS
TA = +25°C, VS = ±15V, unless otherwise noted.

OPA604AP, AU
PARAMETER CONDITION MIN TYP MAX UNITS

OFFSET VOLTAGE
Input Offset Voltage ±1 ±5 mV
Average Drift ±8 µV/°C
Power Supply Rejection VS = ±5 to ±24V 80 100 dB
INPUT BIAS CURRENT(1)
Input Bias Current VCM = 0V 50 pA
Input Offset Current VCM = 0V ±3 pA
NOISE
Input Voltage Noise
Noise Density: f = 10Hz 25 nV/√Hz
f = 100Hz 15 nV/√Hz
f = 1kHz 11 nV/√Hz
f = 10kHz 10 nV/√Hz
Voltage Noise, BW = 20Hz to 20kHz 1.5 µVPP
Input Bias Current Noise
Current Noise Density, f = 0.1Hz to 20kHz 4 fA/√Hz
INPUT VOLTAGE RANGE
Common-Mode Input Range ±12 ±13 V
Common-Mode Rejection VCM = ±12V 80 100 dB
INPUT IMPEDANCE
Differential 1012 || 8 Ω || pF
Common-Mode 1012 || 10 Ω || pF

OPEN-LOOP GAIN
Open-Loop Voltage Gain VO = ±10V, RL = 1kΩ 80 100 dB
FREQUENCY RESPONSE
Gain-Bandwidth Product G = 100 20 MHz
Slew Rate 20VPP, RL = 1kΩ 15 25 V/µs
Settling Time: 0.01% G = –1, 10V Step 1.5 µs
0.1% 1 µs
Total Harmonic Distortion + Noise (THD+N) G = 1, f = 1kHz 0.0003 %
VO = 3.5Vrms, RL = 1kΩ
OUTPUT
Voltage Output RL = 600Ω ±11 ±12 V
Current Output VO = ±12V ±35 mA
Short Circuit Current ±40 mA
Output Resistance, Open-Loop 25 Ω
POWER SUPPLY
Specified Operating Voltage ±15 V
Operating Voltage Range ±4.5 ±24 V
Current ±5.3 ±7 mA
TEMPERATURE RANGE
Specification –25 +85 °C
Storage –40 +125 °C
Thermal Resistance(2), θJA 90 °C/W

NOTES: (1) Typical performance, measured fully warmed-up. (2) Soldered to circuit board—see text.

OPA604 3
SBOS019A www.ti.com
 TYPICAL CHARACTERISTICS
TA = +25°C, VS = ±15V, unless otherwise noted.

TOTAL HARMONIC DISTORTION + NOISE TOTAL HARMONIC DISTORTION + NOISE

vs FREQUENCY vs OUTPUT VOLTAGE
1 0.1
Measurement BW = 80kHz See “Distortion Measurements”
See “Distortion Measure- for description of test method.
VO = ments” for description of VO
3.5Vrms
0.1 test method. 1kΩ
1kΩ
0.01

THD + N (%)
THD + N (%)

f = 1kHz
G = 100V/V Measurement BW = 80kHz
0.01

G = 10V/V 0.001
0.001

G = 1V/V
0.0001 0.0001
20 100 1k 10k 20k 0.1 1 10 100
Frequency (Hz) Output Voltage (VPP)

INPUT VOLTAGE AND CURRENT NOISE

OPEN-LOOP GAIN/PHASE vs FREQUENCY SPECTRAL DENSITY vs FREQUENCY
120 0 1k 1k

100
Voltage Noise (nV/ Hz)

–45

Current Noise (fA/ Hz)

Phase Shift (Degrees)
Voltage Gain (dB)

80 φ 100 Voltage Noise 100

60 –90

40
G –135 10 10
20

0 –180
Current Noise
–20 1 1
1 10 100 1k 10k 100k 1M 10M 1 10 100 1k 10k 100k 1M
Frequency (Hz) Frequency (Hz)

INPUT BIAS AND INPUT OFFSET CURRENT INPUT BIAS AND INPUT OFFSET CURRENT
vs TEMPERATURE vs INPUT COMMON-MODE VOLTAGE
100nA 10nA 10nA 1nA

10nA 1nA
Input Offset Current (pA)

Input Offset Current (pA)

Input
Input Bias Current (pA)

Input Bias Current (pA)

Bias Current Input

1nA Bias Current 100
1nA 100

100 10
100 10
Input
10 Offset Current 1 Input
Offset Current

1 0.1 10 1
–75 –50 –25 0 25 50 75 100 125 –15 –10 –5 0 5 10 15
Ambient Temperature (°C) Common-Mode Voltage (V)

4
OPA604
www.ti.com SBOS019A
TYPICAL CHARACTERISTICS (Cont.)
TA = +25°C, VS = ±15V, unless otherwise noted.

INPUT BIAS CURRENT COMMON-MODE REJECTION

vs TIME FROM POWER TURN-ON vs COMMON-MODE VOLTAGE
1nA 120

VS = ±24V

Common-Mode Rejection (dB)

Input Bias Current (pA)

110
100
VS = ±15V

100

10 VS = ±5V
90

1 80
0 1 2 3 4 5 –15 –10 –5 0 5 10 15
Time After Power Turn-On (min) Common-Mode Voltage (V)

POWER SUPPLY AND COMMON-MODE

REJECTION vs FREQUENCY AOL, PSR, AND CMR vs SUPPLY VOLTAGE
120 120 120
+PSR
Common-Mode Rejection (dB)
Power Supply Rejection (dB)

100 100
110
CMR
AOL, PSR, CMR (dB)

80 80
CMR 100
–PSR
60 60
PSR
90
40 40
AOL
80
20 20

0 0 70
10 100 1k 10k 100k 1M 10M 5 10 15 20 25
Frequency (Hz) Supply Voltage (±VS)

GAIN-BANDWIDTH AND SLEW RATE GAIN-BANDWIDTH AND SLEW RATE

vs SUPPLY VOLTAGE vs TEMPERATURE
28 33 28 30
Slew Rate
Gain-Bandwidth (MHz)
Gain-Bandwidth (MHz)

24 29 24 25
Gain-Bandwidth Slew Rate
Slew Rate (V/µs)
Slew Rate (V/µs)

G = +100

20 25 20 20

Gain-Bandwidth
G = +100
16 21 16 15

12 17 12 10
5 10 15 20 25 –75 –50 –25 0 25 50 75 100 125
Supply Voltage (±VS) Temperature (°C)

OPA604 5
SBOS019A www.ti.com
TYPICAL CHARACTERISTICS (Cont.)
TA = +25°C, VS = ±15V, unless otherwise noted.

SETTLING TIME vs CLOSED-LOOP GAIN MAXIMUM OUTPUT VOLTAGE SWING vs FREQUENCY

5 30
VO = 10V Step
RL = 1kΩ VS = ±15V
4 CL = 50pF

Output Voltage (Vp-p)

Settling Time (µs)

20
3
0.01%
2
10
0.1%
1

0 0
–1 –10 –100 –1000 10k 100k 1M 10M
Closed-Loop Gain (V/V) Frequency (Hz)

SUPPLY CURRENT vs TEMPERATURE LARGE-SIGNAL TRANSIENT RESPONSE

7

VS = ±15V +10
6
Output Voltage (V)
Supply Current (mA)

VS = ±24V

5
VS = ±5V

4 –10

3
−75 −50 −25 0 25 50 75 100 125 0 5 10
Ambient Temperature (°C)

SMALL-SIGNAL TRANSIENT RESPONSE SHORT-CIRCUIT CURRENT vs TEMPERATURE

60

ISC+ and ISC–

Short-Circuit Current (mA)

+100
50
Output Voltage (V)

40

–100 30

20
0 1 2 –75 –50 –25 0 25 50 75 100 125
Ambient Temperature (°C)

6
OPA604
www.ti.com SBOS019A
TYPICAL CHARACTERISTICS (Cont.)
TA = +25°C, VS = ±15V, unless otherwise noted.

POWER DISSIPATION vs SUPPLY VOLTAGE MAXIMUM POWER DISSIPATION vs TEMPERATURE

0.5 1.4
θJ-A = 90°C/W
0.45 Worst case sine 1.2 Soldered to

Total Power Dissipation (W)

wave RL = 600Ω Circuit Board
0.40
Power Dissipation (W)

1.0 (see text)

0.35
Typical high-level
0.30 music RL = 600Ω 0.8

0.25 0.6
0.20 Maximum
No signal 0.4 Specified Operating
0.15 or no load Temperature
0.2 85°C
0.10
0.05 0
6 8 10 12 14 16 18 20 22 24 0 25 50 75 100 125 150
Supply Voltage, ±VS (V) Ambient Temperature (°C)

APPLICATIONS INFORMATION Op amp distortion can be considered an internal error source

which can be referred to the input. Figure 2 shows a circuit
OFFSET VOLTAGE ADJUSTMENT which causes the op amp distortion to be 101 times greater
The OPA604 offset voltage is laser-trimmed and will require than normally produced by the op amp. The addition of R3 to
no further trim for most applications. As with most amplifiers, the otherwise standard noninverting amplifier configuration
externally trimming the remaining offset can change drift alters the feedback factor or noise gain of the circuit. The
performance by about 0.3µV/°C for each 100µV of adjusted closed-loop gain is unchanged, but the feedback available
offset. The OPA604 can replace many other amplifiers by for error correction is reduced by a factor of 101. This
leaving the external null circuit unconnected. extends the measurement limit, including the effects of the
signal-source purity, by a factor of 101. Note that the input
The OPA604 is unity-gain stable, making it easy to use in a
signal and load applied to the op amp are the same as with
wide range of circuitry. Applications with noisy or high imped-
conventional feedback without R3.
ance power supply lines may require decoupling capacitors
close to the device pins. In most cases, a 1µF tantalum Validity of this technique can be verified by duplicating
capacitor at each power supply pin is adequate. measurements at high gain and/or high frequency where the
distortion is within the measurement capability of the test
equipment. Measurements for this data sheet were made
+VCC with the Audio Precision System One, which greatly simpli-
fies such repetitive measurements. The measurement tech-
7
nique can, however, be performed with manual distortion
2
6
measurement instruments.
OPA604
3 1
5 ±50mV Typical CAPACITIVE LOADS
4 Trim Range
(1)
The dynamic characteristics of the OPA604 have been
optimized for commonly encountered gains, loads and oper-
NOTE: (1) 50kΩ to 1MΩ
ating conditions. The combination of low closed-loop gain
Trim Potentiometer
–VCC and capacitive load will decrease the phase margin and may
(100kΩ Recommended)
lead to gain peaking or oscillations. Load capacitance reacts
FIGURE 1. Offset Voltage Trim. with the op amp’s open-loop output resistance to form an
additional pole in the feedback loop. Figure 3 shows various
DISTORTION MEASUREMENTS circuits which preserve phase margin with capacitive load.
The distortion produced by the OPA604 is below the mea- For details of analysis techniques and applications circuits,
surement limit of virtually all commercially available equip- refer to application bulletin AB-028 (SBOA015) located at
ment. A special test circuit, however, can be used to extend www.ti.com.
the measurement capabilities.

OPA604 7
SBOS019A www.ti.com
For the unity-gain buffer, Figure 3a, stability is preserved by bipolar-input op amps react with the source impedance and
adding a phase-lead network, RC and CC. Voltage drop will dominate. At a few thousand ohms source impedance
across RC will reduce output voltage swing with heavy loads. and above, the OPA604 will generally provide lower noise.
An alternate circuit, Figure 3b, does not limit the output with
low load impedance. It provides a small amount of positive POWER DISSIPATION
feedback to reduce the net feedback factor. Input impedance
The OPA604 is capable of driving a 600Ω load with power-
of this circuit falls at high frequency as op amp gain rolloff
supply voltages up to ±24V. Internal power dissipation is
reduces the bootstrap action on the compensation network.
increased when operating at high power supply voltage. The
Figures 3c and 3d show compensation techniques for typical characteristic curve, Power Dissipation vs Power
noninverting amplifiers. Like the follower circuits, the circuit in Supply Voltage, shows quiescent dissipation (no signal or no
Figure 3d eliminates voltage drop due to load current, but at load) as well as dissipation with a worst case continuous sine
the penalty of somewhat reduced input impedance at high wave. Continuous high-level music signals typically produce
frequency. dissipation significantly less than worst-case sine waves.
Figures 3e and 3f show input lead compensation networks Copper leadframe construction used in the OPA604 im-
for inverting and difference amplifier configurations. proves heat dissipation compared to conventional plastic
packages. To achieve best heat dissipation, solder the de-
NOISE PERFORMANCE vice directly to the circuit board and use wide circuit board
Op amp noise is described by two parameters—noise volt- traces.
age and noise current. The voltage noise determines the
noise performance with low source impedance. Low noise OUTPUT CURRENT LIMIT
bipolar-input op amps such as the OPA27 and OPA37 Output current is limited by internal circuitry to approximately
provide very low voltage noise. But if source impedance is ±40mA at 25°C. The limit current decreases with increasing
greater than a few thousand ohms, the current noise of temperature as shown in the typical curves.

R1 R2

SIG. DIST.
GAIN GAIN R1 R2 R3
1 101 ∞ 5kΩ 50Ω
10 101 500Ω 5kΩ 500Ω
R3 OPA604 VO = 10Vp-p
(3.5Vrms) 100 101 50Ω 5kΩ ∞

Generator Analyzer
Output Input

Audio Precision IBM PC

RL
System One or
1kΩ
Analyzer(1) Compatible

NOTE: (1) Measurement BW = 80kHz

FIGURE 2. Distortion Test Circuit.

8
OPA604
www.ti.com SBOS019A
 (a) (b)

CC

820pF
OPA604 eo
RC
OPA604 eo
ei 750Ω CC CL
0.47µF 5000pF
CL
5000pF R2 RC
CC = 120 X 10–12 CL ei
2kΩ 10Ω
R2
RC =
4CL X 1010 – 1

CL X 103
CC =
RC

(c) (d)

R1 R2 R1 R2

10kΩ 10kΩ 2kΩ 2kΩ

CC
RC
20Ω
24pF
CC
RC
0.22µF
OPA604 eo OPA604 eo
ei 25Ω ei

CL CL
50 5000pF R2 5000pF
CC = CL RC =
R2 2CL X 1010 – (1 + R2/R1)

CL X 103
CC =
RC

(e) (f)

R2 R1 R2
e1
2kΩ 2kΩ 2kΩ

R1
RC
ei
20Ω
2kΩ OPA604 eo OPA604 eo
CC
RC 0.22µF
20Ω CL CL
5000pF 5000pF
CC R3 R4
0.22µF e2
R2 2kΩ 2kΩ
RC =
2CL X 1010 – (1 + R2/R1) R2
RC =
2CL X 1010 – (1 + R2/R1)
CL X 103
CC =
RC CL X 103
CC =
RC

NOTE: Design equations and component values are approximate. User adjustment is required for optimum performance.

FIGURE 3. Driving Large Capacitive Loads.

OPA604 9
SBOS019A www.ti.com
 R4

22kΩ
C3

R1 R2 R3 100pF
VIN
2.7kΩ 22kΩ 10kΩ OPA604 VO
C1 C2
3000pF 2000pF

fp = 20kHz

FIGURE 4. Three-Pole Low-Pass Filter.

R1 R5 OPA604 VO
VIN
6.04kΩ 2kΩ
R2
C3
4.02kΩ 1000pF

R2 Low-pass
1
4.02kΩ 2 3-pole Butterworth
OPA2604 f–3dB = 40kHz
1
2

OPA2604 C1
1000pF

R4
5.36kΩ

See Application Bulletin AB-026

C2 for information on GIC filters.
1000pF

FIGURE 5. Three-Pole Generalized Immittance Converter (GIC) Low-Pass Filter.

1 10kΩ 10kΩ
2
7.87kΩ OPA2604

VIN 100pF OPA604 VO

G=1
+
1
2
7.87kΩ OPA2604
100kHz Input Filter 10kΩ 10kΩ

FIGURE 6. Differential Amplifier with Low-Pass Filter.

10
OPA604
www.ti.com SBOS019A
 100Ω 10kΩ COUT
NOTE: (1) C1 ≈
2π Rf fc

RF = Internal feedback resistance = 1.5kΩ

G = 101
fC = Crossover frequency = 8MHz
(40dB)
OPA604 10

5 C1(1)
Piezoelectric PCM63
Transducer 20-bit 6
D/A
1MΩ(1)
Converter 9 OPA604 VO = ±3Vp
To low-pass
NOTE: (1) Provides input
filter.
bias current return path.

FIGURE 7. High Impedance Amplifier. FIGURE 8. Digital Audio DAC I-V Amplifier.

OPA604

A2
I2

R4
51Ω
OPA604 R3
51Ω
A1 IL = I1 + I2
I1
VIN R2

VOUT Load
R1
VOUT = VIN (1+R2/R1)

FIGURE 9. Using Two OPA604 Op Amps to Double the Output Current to a Load.

OPA604 11
SBOS019A www.ti.com
 SOUND QUALITY
The following discussion is provided, recognizing that
I1 I2
not all measured performance behavior explains or R6
800µA
correlates with listening tests by audio experts. The 500Ω 200µA
design of the OPA604 included consideration of both R1 R2 R5 R7
objective performance measurements, as well as an 75Ω 75Ω 500Ω 4kΩ
awareness of widely held theory on the success and (+)
J1 J2 J3 J4
failure of previous op amp designs.
(–)
Distortion
Rejection J5 Output
SOUND QUALITY Circuitry Stage

The sound quality of an op amp is often the crucial

selection criteria—even when a data sheet claims
R10 Q3 Q2
exceptional distortion performance. By its nature, sound 10kΩ Q1
quality is subjective. Furthermore, results of listening
tests can vary depending on application and circuit Q4
R11
configuration. Even experienced listeners in controlled 10kΩ
R3 R4 R8 R9
tests often reach different conclusions.
1kΩ 1kΩ 3kΩ 3kΩ
Many audio experts believe that the sound quality of a
high performance FET op amp is superior to that of
bipolar op amps. A possible reason for this is that
bipolar designs generate greater odd-order harmonics
THE OPA604 DESIGN
than FETs. To the human ear, odd-order harmonics
have long been identified as sounding more unpleas- The OPA604 uses FETs throughout the signal path,
ant than even-order harmonics. FETs, like vacuum including the input stage, input-stage load, and the
tubes, have a square-law I-V transfer function which is important phase-splitting section of the output stage.
more linear than the exponential transfer function of a Bipolar transistors are used where their attributes,
bipolar transistor. As a direct result of this square-law such as current capability are important, and where
characteristic, FETs produce predominantly even-or- their transfer characteristics have minimal impact.
der harmonics. Figure 10 shows the transfer function of The topology consists of a single folded-cascode gain
a bipolar transistor and FET. Fourier transformation of stage followed by a unity-gain output stage. Differen-
both transfer functions reveals the lower odd-order tial input transistors J1 and J2 are special large-geom-
harmonics of the FET amplifier stage. etry, P-channel JFETs. Input stage current is a rela-
tively high 800µA, providing high transconductance
VBE = 1kHz + DC Bias and reducing voltage noise. Laser trimming of stage
1 FFT
IC currents and careful attention to symmetry yields a
VO
nearly symmetrical slew rate of ±25V/µs.
IC log The JFET input stage holds input bias current to
V
(mA) BE (VO) approximately 50pA or roughly 3000 times lower than
common bipolar-input audio op amps. This dramati-
fO 2fO 3fO 4fO 5fO
cally reduces noise with high-impedance circuitry.
0
0 0.65 1 0 1 2 3 4 5 The drains of J1 and J2 are cascoded by Q1 and Q2,
VBE (V) Frequency (kHz)
driving the input stage loads, FETs J3 and J4. Distor-
VGS = 1kHz + DC Bias
tion reduction circuitry (patented) linearizes the open-
1
FFT loop response and increases voltage gain. The 20MHz
VGS bandwidth of the OPA604 further reduces distortion
through the user-connected feedback loop.
–ID log
VO
(mA) (VO) The output stage consists of a JFET phase-splitter
ID
loaded into high speed all-NPN output drivers. Output
fO 2fO 3fO 4fO 5fO transistors are biased by a special circuit to prevent
0 cutoff, even with full output swing into 600Ω loads.
1 0 0 1 2 3 4 5
VGS (V) Frequency (kHz)

FIGURE 10. I-V and Spectral Response of NPN and

JFET.

12
OPA604
www.ti.com SBOS019A
 PACKAGE OPTION ADDENDUM

www.ti.com 27-Feb-2024

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

OPA604AU ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 OPA Samples
604AU
OPA604AU/2K5 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 OPA Samples
604AU

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 27-Feb-2024

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 2-Nov-2023

TAPE AND REEL INFORMATION

REEL DIMENSIONS TAPE DIMENSIONS

K0 P1

B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2 Q1 Q2

Q3 Q4 Q3 Q4 User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
OPA604AU/2K5 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 2-Nov-2023

TAPE AND REEL BOX DIMENSIONS

Width (mm)
H
W

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
OPA604AU/2K5 SOIC D 8 2500 356.0 356.0 35.0

Pack Materials-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 2-Nov-2023

TUBE

T - Tube
height L - Tube length

W - Tube
width

B - Alignment groove width

*All dimensions are nominal

Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)
OPA604AU D SOIC 8 75 506.6 8 3940 4.32

Pack Materials-Page 3
 PACKAGE OUTLINE
D0008A SCALE 2.800
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A PIN 1 ID AREA
6X .050
[1.27]
8
1

.189-.197 2X
[4.81-5.00] .150
NOTE 3 [3.81]

4X (0 -15 )

4
5
8X .012-.020
B .150-.157 [0.31-0.51]
.069 MAX
[3.81-3.98] .010 [0.25] C A B [1.75]
NOTE 4

.005-.010 TYP
[0.13-0.25]

4X (0 -15 )

SEE DETAIL A
.010
[0.25]

.004-.010
0 -8 [0.11-0.25]
.016-.050
[0.41-1.27] DETAIL A
(.041) TYPICAL
[1.04]

4214825/C 02/2019

NOTES:

1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.

www.ti.com
 EXAMPLE BOARD LAYOUT
D0008A SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

8X (.061 )
[1.55]
SYMM SEE
DETAILS
1
8

8X (.024)
[0.6] SYMM

(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE:8X

SOLDER MASK SOLDER MASK

METAL METAL UNDER
OPENING OPENING SOLDER MASK

EXPOSED
METAL EXPOSED
METAL
.0028 MAX .0028 MIN
[0.07] [0.07]
ALL AROUND ALL AROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED

SOLDER MASK DETAILS

4214825/C 02/2019

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
D0008A SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

8X (.061 )
[1.55] SYMM

1
8

8X (.024)
[0.6] SYMM

(R.002 ) TYP
5 [0.05]
4
6X (.050 )
[1.27]
(.213)
[5.4]

SOLDER PASTE EXAMPLE

BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X

4214825/C 02/2019

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

www.ti.com
 IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, regulatory or other requirements.
These resources are subject to change without notice. TI grants you permission to use these resources only for development of an
application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license
is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you
will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these
resources.
TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with
such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for
TI products.
TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2024, Texas Instruments Incorporated